pmap.c revision 212627
1176771Sraj/*- 2192532Sraj * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3176771Sraj * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4176771Sraj * All rights reserved. 5176771Sraj * 6176771Sraj * Redistribution and use in source and binary forms, with or without 7176771Sraj * modification, are permitted provided that the following conditions 8176771Sraj * are met: 9176771Sraj * 1. Redistributions of source code must retain the above copyright 10176771Sraj * notice, this list of conditions and the following disclaimer. 11176771Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176771Sraj * notice, this list of conditions and the following disclaimer in the 13176771Sraj * documentation and/or other materials provided with the distribution. 14176771Sraj * 15176771Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176771Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176771Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176771Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176771Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176771Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176771Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176771Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176771Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176771Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176771Sraj * 26176771Sraj * Some hw specific parts of this pmap were derived or influenced 27176771Sraj * by NetBSD's ibm4xx pmap module. More generic code is shared with 28176771Sraj * a few other pmap modules from the FreeBSD tree. 29176771Sraj */ 30176771Sraj 31176771Sraj /* 32176771Sraj * VM layout notes: 33176771Sraj * 34176771Sraj * Kernel and user threads run within one common virtual address space 35176771Sraj * defined by AS=0. 36176771Sraj * 37176771Sraj * Virtual address space layout: 38176771Sraj * ----------------------------- 39187151Sraj * 0x0000_0000 - 0xafff_ffff : user process 40187151Sraj * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41187151Sraj * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42190701Smarcel * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43187151Sraj * 0xc100_0000 - 0xfeef_ffff : KVA 44187151Sraj * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45187151Sraj * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46187151Sraj * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47187151Sraj * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48187151Sraj * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49176771Sraj */ 50176771Sraj 51176771Sraj#include <sys/cdefs.h> 52176771Sraj__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 212627 2010-09-15 00:17:52Z grehan $"); 53176771Sraj 54176771Sraj#include <sys/types.h> 55176771Sraj#include <sys/param.h> 56176771Sraj#include <sys/malloc.h> 57187149Sraj#include <sys/ktr.h> 58176771Sraj#include <sys/proc.h> 59176771Sraj#include <sys/user.h> 60176771Sraj#include <sys/queue.h> 61176771Sraj#include <sys/systm.h> 62176771Sraj#include <sys/kernel.h> 63176771Sraj#include <sys/msgbuf.h> 64176771Sraj#include <sys/lock.h> 65176771Sraj#include <sys/mutex.h> 66192532Sraj#include <sys/smp.h> 67176771Sraj#include <sys/vmmeter.h> 68176771Sraj 69176771Sraj#include <vm/vm.h> 70176771Sraj#include <vm/vm_page.h> 71176771Sraj#include <vm/vm_kern.h> 72176771Sraj#include <vm/vm_pageout.h> 73176771Sraj#include <vm/vm_extern.h> 74176771Sraj#include <vm/vm_object.h> 75176771Sraj#include <vm/vm_param.h> 76176771Sraj#include <vm/vm_map.h> 77176771Sraj#include <vm/vm_pager.h> 78176771Sraj#include <vm/uma.h> 79176771Sraj 80176771Sraj#include <machine/cpu.h> 81176771Sraj#include <machine/pcb.h> 82192067Snwhitehorn#include <machine/platform.h> 83176771Sraj 84176771Sraj#include <machine/tlb.h> 85176771Sraj#include <machine/spr.h> 86176771Sraj#include <machine/vmparam.h> 87176771Sraj#include <machine/md_var.h> 88176771Sraj#include <machine/mmuvar.h> 89176771Sraj#include <machine/pmap.h> 90176771Sraj#include <machine/pte.h> 91176771Sraj 92176771Sraj#include "mmu_if.h" 93176771Sraj 94176771Sraj#define DEBUG 95176771Sraj#undef DEBUG 96176771Sraj 97176771Sraj#ifdef DEBUG 98176771Sraj#define debugf(fmt, args...) printf(fmt, ##args) 99176771Sraj#else 100176771Sraj#define debugf(fmt, args...) 101176771Sraj#endif 102176771Sraj 103176771Sraj#define TODO panic("%s: not implemented", __func__); 104176771Sraj 105176771Sraj#include "opt_sched.h" 106176771Sraj#ifndef SCHED_4BSD 107176771Sraj#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 108176771Sraj#endif 109176771Srajextern struct mtx sched_lock; 110176771Sraj 111190701Smarcelextern int dumpsys_minidump; 112190701Smarcel 113190701Smarcelextern unsigned char _etext[]; 114190701Smarcelextern unsigned char _end[]; 115190701Smarcel 116176771Sraj/* Kernel physical load address. */ 117176771Srajextern uint32_t kernload; 118190701Smarcelvm_offset_t kernstart; 119190701Smarcelvm_size_t kernsize; 120176771Sraj 121190701Smarcel/* Message buffer and tables. */ 122190701Smarcelstatic vm_offset_t data_start; 123190701Smarcelstatic vm_size_t data_end; 124190701Smarcel 125192067Snwhitehorn/* Phys/avail memory regions. */ 126192067Snwhitehornstatic struct mem_region *availmem_regions; 127192067Snwhitehornstatic int availmem_regions_sz; 128192067Snwhitehornstatic struct mem_region *physmem_regions; 129192067Snwhitehornstatic int physmem_regions_sz; 130176771Sraj 131176771Sraj/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 132176771Srajstatic vm_offset_t zero_page_va; 133176771Srajstatic struct mtx zero_page_mutex; 134176771Sraj 135187149Srajstatic struct mtx tlbivax_mutex; 136187149Sraj 137176771Sraj/* 138176771Sraj * Reserved KVA space for mmu_booke_zero_page_idle. This is used 139176771Sraj * by idle thred only, no lock required. 140176771Sraj */ 141176771Srajstatic vm_offset_t zero_page_idle_va; 142176771Sraj 143176771Sraj/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 144176771Srajstatic vm_offset_t copy_page_src_va; 145176771Srajstatic vm_offset_t copy_page_dst_va; 146176771Srajstatic struct mtx copy_page_mutex; 147176771Sraj 148176771Sraj/**************************************************************************/ 149176771Sraj/* PMAP */ 150176771Sraj/**************************************************************************/ 151176771Sraj 152176771Srajstatic void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 153176771Sraj vm_prot_t, boolean_t); 154176771Sraj 155176771Srajunsigned int kptbl_min; /* Index of the first kernel ptbl. */ 156176771Srajunsigned int kernel_ptbls; /* Number of KVA ptbls. */ 157176771Sraj 158176771Sraj/* 159176771Sraj * If user pmap is processed with mmu_booke_remove and the resident count 160176771Sraj * drops to 0, there are no more pages to remove, so we need not continue. 161176771Sraj */ 162176771Sraj#define PMAP_REMOVE_DONE(pmap) \ 163176771Sraj ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 164176771Sraj 165187149Srajextern void tlb_lock(uint32_t *); 166187149Srajextern void tlb_unlock(uint32_t *); 167187149Srajextern void tid_flush(tlbtid_t); 168176771Sraj 169176771Sraj/**************************************************************************/ 170176771Sraj/* TLB and TID handling */ 171176771Sraj/**************************************************************************/ 172176771Sraj 173176771Sraj/* Translation ID busy table */ 174187149Srajstatic volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 175176771Sraj 176176771Sraj/* 177187149Sraj * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 178187149Sraj * core revisions and should be read from h/w registers during early config. 179176771Sraj */ 180187149Srajuint32_t tlb0_entries; 181187149Srajuint32_t tlb0_ways; 182187149Srajuint32_t tlb0_entries_per_way; 183176771Sraj 184187149Sraj#define TLB0_ENTRIES (tlb0_entries) 185187149Sraj#define TLB0_WAYS (tlb0_ways) 186187149Sraj#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 187176771Sraj 188187149Sraj#define TLB1_ENTRIES 16 189176771Sraj 190176771Sraj/* In-ram copy of the TLB1 */ 191187149Srajstatic tlb_entry_t tlb1[TLB1_ENTRIES]; 192176771Sraj 193176771Sraj/* Next free entry in the TLB1 */ 194176771Srajstatic unsigned int tlb1_idx; 195176771Sraj 196176771Srajstatic tlbtid_t tid_alloc(struct pmap *); 197176771Sraj 198187149Srajstatic void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 199176771Sraj 200187149Srajstatic int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 201176771Srajstatic void tlb1_write_entry(unsigned int); 202176771Srajstatic int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 203176771Srajstatic vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 204176771Sraj 205176771Srajstatic vm_size_t tsize2size(unsigned int); 206176771Srajstatic unsigned int size2tsize(vm_size_t); 207176771Srajstatic unsigned int ilog2(unsigned int); 208176771Sraj 209176771Srajstatic void set_mas4_defaults(void); 210176771Sraj 211187149Srajstatic inline void tlb0_flush_entry(vm_offset_t); 212176771Srajstatic inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 213176771Sraj 214176771Sraj/**************************************************************************/ 215176771Sraj/* Page table management */ 216176771Sraj/**************************************************************************/ 217176771Sraj 218176771Sraj/* Data for the pv entry allocation mechanism */ 219176771Srajstatic uma_zone_t pvzone; 220176771Srajstatic struct vm_object pvzone_obj; 221176771Srajstatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 222176771Sraj 223176771Sraj#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 224176771Sraj 225176771Sraj#ifndef PMAP_SHPGPERPROC 226176771Sraj#define PMAP_SHPGPERPROC 200 227176771Sraj#endif 228176771Sraj 229176771Srajstatic void ptbl_init(void); 230176771Srajstatic struct ptbl_buf *ptbl_buf_alloc(void); 231176771Srajstatic void ptbl_buf_free(struct ptbl_buf *); 232176771Srajstatic void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 233176771Sraj 234187149Srajstatic pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 235176771Srajstatic void ptbl_free(mmu_t, pmap_t, unsigned int); 236176771Srajstatic void ptbl_hold(mmu_t, pmap_t, unsigned int); 237176771Srajstatic int ptbl_unhold(mmu_t, pmap_t, unsigned int); 238176771Sraj 239176771Srajstatic vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 240176771Srajstatic pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 241187149Srajstatic void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 242187149Srajstatic int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 243176771Sraj 244187149Srajstatic pv_entry_t pv_alloc(void); 245176771Srajstatic void pv_free(pv_entry_t); 246176771Srajstatic void pv_insert(pmap_t, vm_offset_t, vm_page_t); 247176771Srajstatic void pv_remove(pmap_t, vm_offset_t, vm_page_t); 248176771Sraj 249176771Sraj/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 250176771Sraj#define PTBL_BUFS (128 * 16) 251176771Sraj 252176771Srajstruct ptbl_buf { 253176771Sraj TAILQ_ENTRY(ptbl_buf) link; /* list link */ 254176771Sraj vm_offset_t kva; /* va of mapping */ 255176771Sraj}; 256176771Sraj 257176771Sraj/* ptbl free list and a lock used for access synchronization. */ 258176771Srajstatic TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 259176771Srajstatic struct mtx ptbl_buf_freelist_lock; 260176771Sraj 261176771Sraj/* Base address of kva space allocated fot ptbl bufs. */ 262176771Srajstatic vm_offset_t ptbl_buf_pool_vabase; 263176771Sraj 264176771Sraj/* Pointer to ptbl_buf structures. */ 265176771Srajstatic struct ptbl_buf *ptbl_bufs; 266176771Sraj 267192532Srajvoid pmap_bootstrap_ap(volatile uint32_t *); 268192532Sraj 269176771Sraj/* 270176771Sraj * Kernel MMU interface 271176771Sraj */ 272176771Srajstatic void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 273176771Srajstatic void mmu_booke_clear_modify(mmu_t, vm_page_t); 274176771Srajstatic void mmu_booke_clear_reference(mmu_t, vm_page_t); 275194101Srajstatic void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 276194101Sraj vm_size_t, vm_offset_t); 277176771Srajstatic void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 278176771Srajstatic void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 279176771Sraj vm_prot_t, boolean_t); 280176771Srajstatic void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 281176771Sraj vm_page_t, vm_prot_t); 282176771Srajstatic void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 283176771Sraj vm_prot_t); 284176771Srajstatic vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 285176771Srajstatic vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 286176771Sraj vm_prot_t); 287176771Srajstatic void mmu_booke_init(mmu_t); 288176771Srajstatic boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 289176771Srajstatic boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290207155Salcstatic boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 291176771Srajstatic boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 292176771Srajstatic vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 293176771Sraj int); 294208504Salcstatic int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 295208504Salc vm_paddr_t *); 296176771Srajstatic void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 297176771Sraj vm_object_t, vm_pindex_t, vm_size_t); 298176771Srajstatic boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 299176771Srajstatic void mmu_booke_page_init(mmu_t, vm_page_t); 300176771Srajstatic int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 301176771Srajstatic void mmu_booke_pinit(mmu_t, pmap_t); 302176771Srajstatic void mmu_booke_pinit0(mmu_t, pmap_t); 303176771Srajstatic void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 304176771Sraj vm_prot_t); 305176771Srajstatic void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 306176771Srajstatic void mmu_booke_qremove(mmu_t, vm_offset_t, int); 307176771Srajstatic void mmu_booke_release(mmu_t, pmap_t); 308176771Srajstatic void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 309176771Srajstatic void mmu_booke_remove_all(mmu_t, vm_page_t); 310176771Srajstatic void mmu_booke_remove_write(mmu_t, vm_page_t); 311176771Srajstatic void mmu_booke_zero_page(mmu_t, vm_page_t); 312176771Srajstatic void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 313176771Srajstatic void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 314176771Srajstatic void mmu_booke_activate(mmu_t, struct thread *); 315176771Srajstatic void mmu_booke_deactivate(mmu_t, struct thread *); 316176771Srajstatic void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 317176771Srajstatic void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 318176771Srajstatic void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 319176771Srajstatic vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 320176771Srajstatic void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 321176771Srajstatic void mmu_booke_kremove(mmu_t, vm_offset_t); 322176771Srajstatic boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 323198341Smarcelstatic void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 324198341Smarcel vm_size_t); 325190701Smarcelstatic vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 326190701Smarcel vm_size_t, vm_size_t *); 327190701Smarcelstatic void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 328190701Smarcel vm_size_t, vm_offset_t); 329190701Smarcelstatic struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 330176771Sraj 331176771Srajstatic mmu_method_t mmu_booke_methods[] = { 332176771Sraj /* pmap dispatcher interface */ 333176771Sraj MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 334176771Sraj MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 335176771Sraj MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 336176771Sraj MMUMETHOD(mmu_copy, mmu_booke_copy), 337176771Sraj MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 338176771Sraj MMUMETHOD(mmu_enter, mmu_booke_enter), 339176771Sraj MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 340176771Sraj MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 341176771Sraj MMUMETHOD(mmu_extract, mmu_booke_extract), 342176771Sraj MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 343176771Sraj MMUMETHOD(mmu_init, mmu_booke_init), 344176771Sraj MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 345176771Sraj MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 346207155Salc MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 347176771Sraj MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 348176771Sraj MMUMETHOD(mmu_map, mmu_booke_map), 349176771Sraj MMUMETHOD(mmu_mincore, mmu_booke_mincore), 350176771Sraj MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 351176771Sraj MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 352176771Sraj MMUMETHOD(mmu_page_init, mmu_booke_page_init), 353176771Sraj MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 354176771Sraj MMUMETHOD(mmu_pinit, mmu_booke_pinit), 355176771Sraj MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 356176771Sraj MMUMETHOD(mmu_protect, mmu_booke_protect), 357176771Sraj MMUMETHOD(mmu_qenter, mmu_booke_qenter), 358176771Sraj MMUMETHOD(mmu_qremove, mmu_booke_qremove), 359176771Sraj MMUMETHOD(mmu_release, mmu_booke_release), 360176771Sraj MMUMETHOD(mmu_remove, mmu_booke_remove), 361176771Sraj MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 362176771Sraj MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 363198341Smarcel MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 364176771Sraj MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 365176771Sraj MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 366176771Sraj MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 367176771Sraj MMUMETHOD(mmu_activate, mmu_booke_activate), 368176771Sraj MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 369176771Sraj 370176771Sraj /* Internal interfaces */ 371176771Sraj MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 372176771Sraj MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 373176771Sraj MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 374176771Sraj MMUMETHOD(mmu_kenter, mmu_booke_kenter), 375176771Sraj MMUMETHOD(mmu_kextract, mmu_booke_kextract), 376176771Sraj/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 377176771Sraj MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 378176771Sraj 379190701Smarcel /* dumpsys() support */ 380190701Smarcel MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 381190701Smarcel MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 382190701Smarcel MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 383190701Smarcel 384176771Sraj { 0, 0 } 385176771Sraj}; 386176771Sraj 387212627SgrehanMMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 388176771Sraj 389192532Srajstatic inline void 390192532Srajtlb_miss_lock(void) 391192532Sraj{ 392192532Sraj#ifdef SMP 393192532Sraj struct pcpu *pc; 394192532Sraj 395192532Sraj if (!smp_started) 396192532Sraj return; 397192532Sraj 398192532Sraj SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 399192532Sraj if (pc != pcpup) { 400192532Sraj 401192532Sraj CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 402192532Sraj "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 403192532Sraj 404192532Sraj KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 405192532Sraj ("tlb_miss_lock: tried to lock self")); 406192532Sraj 407192532Sraj tlb_lock(pc->pc_booke_tlb_lock); 408192532Sraj 409192532Sraj CTR1(KTR_PMAP, "%s: locked", __func__); 410192532Sraj } 411192532Sraj } 412192532Sraj#endif 413192532Sraj} 414192532Sraj 415192532Srajstatic inline void 416192532Srajtlb_miss_unlock(void) 417192532Sraj{ 418192532Sraj#ifdef SMP 419192532Sraj struct pcpu *pc; 420192532Sraj 421192532Sraj if (!smp_started) 422192532Sraj return; 423192532Sraj 424192532Sraj SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 425192532Sraj if (pc != pcpup) { 426192532Sraj CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 427192532Sraj __func__, pc->pc_cpuid); 428192532Sraj 429192532Sraj tlb_unlock(pc->pc_booke_tlb_lock); 430192532Sraj 431192532Sraj CTR1(KTR_PMAP, "%s: unlocked", __func__); 432192532Sraj } 433192532Sraj } 434192532Sraj#endif 435192532Sraj} 436192532Sraj 437176771Sraj/* Return number of entries in TLB0. */ 438176771Srajstatic __inline void 439176771Srajtlb0_get_tlbconf(void) 440176771Sraj{ 441176771Sraj uint32_t tlb0_cfg; 442176771Sraj 443176771Sraj tlb0_cfg = mfspr(SPR_TLB0CFG); 444187149Sraj tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 445187149Sraj tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 446187149Sraj tlb0_entries_per_way = tlb0_entries / tlb0_ways; 447176771Sraj} 448176771Sraj 449176771Sraj/* Initialize pool of kva ptbl buffers. */ 450176771Srajstatic void 451176771Srajptbl_init(void) 452176771Sraj{ 453176771Sraj int i; 454176771Sraj 455187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 456187151Sraj (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 457187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 458187151Sraj __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 459176771Sraj 460176771Sraj mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 461176771Sraj TAILQ_INIT(&ptbl_buf_freelist); 462176771Sraj 463176771Sraj for (i = 0; i < PTBL_BUFS; i++) { 464176771Sraj ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 465176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 466176771Sraj } 467176771Sraj} 468176771Sraj 469182362Sraj/* Get a ptbl_buf from the freelist. */ 470176771Srajstatic struct ptbl_buf * 471176771Srajptbl_buf_alloc(void) 472176771Sraj{ 473176771Sraj struct ptbl_buf *buf; 474176771Sraj 475176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 476176771Sraj buf = TAILQ_FIRST(&ptbl_buf_freelist); 477176771Sraj if (buf != NULL) 478176771Sraj TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 479176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 480176771Sraj 481187151Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 482187151Sraj 483176771Sraj return (buf); 484176771Sraj} 485176771Sraj 486176771Sraj/* Return ptbl buff to free pool. */ 487176771Srajstatic void 488176771Srajptbl_buf_free(struct ptbl_buf *buf) 489176771Sraj{ 490176771Sraj 491187149Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 492176771Sraj 493176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 494176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 495176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 496176771Sraj} 497176771Sraj 498176771Sraj/* 499187149Sraj * Search the list of allocated ptbl bufs and find on list of allocated ptbls 500176771Sraj */ 501176771Srajstatic void 502176771Srajptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 503176771Sraj{ 504176771Sraj struct ptbl_buf *pbuf; 505176771Sraj 506187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 507176771Sraj 508187149Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 509187149Sraj 510187149Sraj TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 511176771Sraj if (pbuf->kva == (vm_offset_t)ptbl) { 512176771Sraj /* Remove from pmap ptbl buf list. */ 513187149Sraj TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 514176771Sraj 515187149Sraj /* Free corresponding ptbl buf. */ 516176771Sraj ptbl_buf_free(pbuf); 517176771Sraj break; 518176771Sraj } 519176771Sraj} 520176771Sraj 521176771Sraj/* Allocate page table. */ 522187149Srajstatic pte_t * 523176771Srajptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 524176771Sraj{ 525176771Sraj vm_page_t mtbl[PTBL_PAGES]; 526176771Sraj vm_page_t m; 527176771Sraj struct ptbl_buf *pbuf; 528176771Sraj unsigned int pidx; 529187149Sraj pte_t *ptbl; 530176771Sraj int i; 531176771Sraj 532187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 533187149Sraj (pmap == kernel_pmap), pdir_idx); 534176771Sraj 535176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 536176771Sraj ("ptbl_alloc: invalid pdir_idx")); 537176771Sraj KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 538176771Sraj ("pte_alloc: valid ptbl entry exists!")); 539176771Sraj 540176771Sraj pbuf = ptbl_buf_alloc(); 541176771Sraj if (pbuf == NULL) 542176771Sraj panic("pte_alloc: couldn't alloc kernel virtual memory"); 543187149Sraj 544187149Sraj ptbl = (pte_t *)pbuf->kva; 545176771Sraj 546187149Sraj CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 547187149Sraj 548176771Sraj /* Allocate ptbl pages, this will sleep! */ 549176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 550176771Sraj pidx = (PTBL_PAGES * pdir_idx) + i; 551187149Sraj while ((m = vm_page_alloc(NULL, pidx, 552187149Sraj VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 553187149Sraj 554176771Sraj PMAP_UNLOCK(pmap); 555176771Sraj vm_page_unlock_queues(); 556176771Sraj VM_WAIT; 557176771Sraj vm_page_lock_queues(); 558176771Sraj PMAP_LOCK(pmap); 559176771Sraj } 560176771Sraj mtbl[i] = m; 561176771Sraj } 562176771Sraj 563187149Sraj /* Map allocated pages into kernel_pmap. */ 564187149Sraj mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 565176771Sraj 566176771Sraj /* Zero whole ptbl. */ 567187149Sraj bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 568176771Sraj 569176771Sraj /* Add pbuf to the pmap ptbl bufs list. */ 570187149Sraj TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 571176771Sraj 572187149Sraj return (ptbl); 573176771Sraj} 574176771Sraj 575176771Sraj/* Free ptbl pages and invalidate pdir entry. */ 576176771Srajstatic void 577176771Srajptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 578176771Sraj{ 579176771Sraj pte_t *ptbl; 580176771Sraj vm_paddr_t pa; 581176771Sraj vm_offset_t va; 582176771Sraj vm_page_t m; 583176771Sraj int i; 584176771Sraj 585187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 586187149Sraj (pmap == kernel_pmap), pdir_idx); 587176771Sraj 588176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 589176771Sraj ("ptbl_free: invalid pdir_idx")); 590176771Sraj 591176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 592176771Sraj 593187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 594187149Sraj 595176771Sraj KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 596176771Sraj 597187149Sraj /* 598187149Sraj * Invalidate the pdir entry as soon as possible, so that other CPUs 599187149Sraj * don't attempt to look up the page tables we are releasing. 600187149Sraj */ 601187149Sraj mtx_lock_spin(&tlbivax_mutex); 602192532Sraj tlb_miss_lock(); 603187149Sraj 604187149Sraj pmap->pm_pdir[pdir_idx] = NULL; 605187149Sraj 606192532Sraj tlb_miss_unlock(); 607187149Sraj mtx_unlock_spin(&tlbivax_mutex); 608187149Sraj 609176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 610176771Sraj va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 611176771Sraj pa = pte_vatopa(mmu, kernel_pmap, va); 612176771Sraj m = PHYS_TO_VM_PAGE(pa); 613176771Sraj vm_page_free_zero(m); 614176771Sraj atomic_subtract_int(&cnt.v_wire_count, 1); 615176771Sraj mmu_booke_kremove(mmu, va); 616176771Sraj } 617176771Sraj 618176771Sraj ptbl_free_pmap_ptbl(pmap, ptbl); 619176771Sraj} 620176771Sraj 621176771Sraj/* 622176771Sraj * Decrement ptbl pages hold count and attempt to free ptbl pages. 623176771Sraj * Called when removing pte entry from ptbl. 624176771Sraj * 625176771Sraj * Return 1 if ptbl pages were freed. 626176771Sraj */ 627176771Srajstatic int 628176771Srajptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 629176771Sraj{ 630176771Sraj pte_t *ptbl; 631176771Sraj vm_paddr_t pa; 632176771Sraj vm_page_t m; 633176771Sraj int i; 634176771Sraj 635187151Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 636187151Sraj (pmap == kernel_pmap), pdir_idx); 637176771Sraj 638176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 639176771Sraj ("ptbl_unhold: invalid pdir_idx")); 640176771Sraj KASSERT((pmap != kernel_pmap), 641176771Sraj ("ptbl_unhold: unholding kernel ptbl!")); 642176771Sraj 643176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 644176771Sraj 645176771Sraj //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 646176771Sraj KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 647176771Sraj ("ptbl_unhold: non kva ptbl")); 648176771Sraj 649176771Sraj /* decrement hold count */ 650176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 651187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 652187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 653176771Sraj m = PHYS_TO_VM_PAGE(pa); 654176771Sraj m->wire_count--; 655176771Sraj } 656176771Sraj 657176771Sraj /* 658176771Sraj * Free ptbl pages if there are no pte etries in this ptbl. 659187151Sraj * wire_count has the same value for all ptbl pages, so check the last 660187151Sraj * page. 661176771Sraj */ 662176771Sraj if (m->wire_count == 0) { 663176771Sraj ptbl_free(mmu, pmap, pdir_idx); 664176771Sraj 665176771Sraj //debugf("ptbl_unhold: e (freed ptbl)\n"); 666176771Sraj return (1); 667176771Sraj } 668176771Sraj 669176771Sraj return (0); 670176771Sraj} 671176771Sraj 672176771Sraj/* 673187151Sraj * Increment hold count for ptbl pages. This routine is used when a new pte 674187151Sraj * entry is being inserted into the ptbl. 675176771Sraj */ 676176771Srajstatic void 677176771Srajptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 678176771Sraj{ 679176771Sraj vm_paddr_t pa; 680176771Sraj pte_t *ptbl; 681176771Sraj vm_page_t m; 682176771Sraj int i; 683176771Sraj 684187151Sraj CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 685187151Sraj pdir_idx); 686176771Sraj 687176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 688176771Sraj ("ptbl_hold: invalid pdir_idx")); 689176771Sraj KASSERT((pmap != kernel_pmap), 690176771Sraj ("ptbl_hold: holding kernel ptbl!")); 691176771Sraj 692176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 693176771Sraj 694176771Sraj KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 695176771Sraj 696176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 697187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 698187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 699176771Sraj m = PHYS_TO_VM_PAGE(pa); 700176771Sraj m->wire_count++; 701176771Sraj } 702176771Sraj} 703176771Sraj 704176771Sraj/* Allocate pv_entry structure. */ 705176771Srajpv_entry_t 706176771Srajpv_alloc(void) 707176771Sraj{ 708176771Sraj pv_entry_t pv; 709176771Sraj 710176771Sraj pv_entry_count++; 711194123Salc if (pv_entry_count > pv_entry_high_water) 712194123Salc pagedaemon_wakeup(); 713176771Sraj pv = uma_zalloc(pvzone, M_NOWAIT); 714176771Sraj 715176771Sraj return (pv); 716176771Sraj} 717176771Sraj 718176771Sraj/* Free pv_entry structure. */ 719176771Srajstatic __inline void 720176771Srajpv_free(pv_entry_t pve) 721176771Sraj{ 722176771Sraj 723176771Sraj pv_entry_count--; 724176771Sraj uma_zfree(pvzone, pve); 725176771Sraj} 726176771Sraj 727176771Sraj 728176771Sraj/* Allocate and initialize pv_entry structure. */ 729176771Srajstatic void 730176771Srajpv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 731176771Sraj{ 732176771Sraj pv_entry_t pve; 733176771Sraj 734176771Sraj //int su = (pmap == kernel_pmap); 735176771Sraj //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 736176771Sraj // (u_int32_t)pmap, va, (u_int32_t)m); 737176771Sraj 738176771Sraj pve = pv_alloc(); 739176771Sraj if (pve == NULL) 740176771Sraj panic("pv_insert: no pv entries!"); 741176771Sraj 742176771Sraj pve->pv_pmap = pmap; 743176771Sraj pve->pv_va = va; 744176771Sraj 745176771Sraj /* add to pv_list */ 746176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 747176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 748176771Sraj 749176771Sraj TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 750176771Sraj 751176771Sraj //debugf("pv_insert: e\n"); 752176771Sraj} 753176771Sraj 754176771Sraj/* Destroy pv entry. */ 755176771Srajstatic void 756176771Srajpv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 757176771Sraj{ 758176771Sraj pv_entry_t pve; 759176771Sraj 760176771Sraj //int su = (pmap == kernel_pmap); 761176771Sraj //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 762176771Sraj 763176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 764176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 765176771Sraj 766176771Sraj /* find pv entry */ 767176771Sraj TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 768176771Sraj if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 769176771Sraj /* remove from pv_list */ 770176771Sraj TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 771176771Sraj if (TAILQ_EMPTY(&m->md.pv_list)) 772176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 773176771Sraj 774176771Sraj /* free pv entry struct */ 775176771Sraj pv_free(pve); 776176771Sraj break; 777176771Sraj } 778176771Sraj } 779176771Sraj 780176771Sraj //debugf("pv_remove: e\n"); 781176771Sraj} 782176771Sraj 783176771Sraj/* 784176771Sraj * Clean pte entry, try to free page table page if requested. 785176771Sraj * 786176771Sraj * Return 1 if ptbl pages were freed, otherwise return 0. 787176771Sraj */ 788176771Srajstatic int 789187151Srajpte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 790176771Sraj{ 791176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 792176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 793176771Sraj vm_page_t m; 794176771Sraj pte_t *ptbl; 795176771Sraj pte_t *pte; 796176771Sraj 797176771Sraj //int su = (pmap == kernel_pmap); 798176771Sraj //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 799176771Sraj // su, (u_int32_t)pmap, va, flags); 800176771Sraj 801176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 802176771Sraj KASSERT(ptbl, ("pte_remove: null ptbl")); 803176771Sraj 804176771Sraj pte = &ptbl[ptbl_idx]; 805176771Sraj 806176771Sraj if (pte == NULL || !PTE_ISVALID(pte)) 807176771Sraj return (0); 808176771Sraj 809176771Sraj if (PTE_ISWIRED(pte)) 810176771Sraj pmap->pm_stats.wired_count--; 811176771Sraj 812191445Smarcel /* Handle managed entry. */ 813191445Smarcel if (PTE_ISMANAGED(pte)) { 814191445Smarcel /* Get vm_page_t for mapped pte. */ 815191445Smarcel m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 816176771Sraj 817191445Smarcel if (PTE_ISMODIFIED(pte)) 818191445Smarcel vm_page_dirty(m); 819176771Sraj 820191445Smarcel if (PTE_ISREFERENCED(pte)) 821191445Smarcel vm_page_flag_set(m, PG_REFERENCED); 822176771Sraj 823191445Smarcel pv_remove(pmap, va, m); 824176771Sraj } 825176771Sraj 826187149Sraj mtx_lock_spin(&tlbivax_mutex); 827192532Sraj tlb_miss_lock(); 828187149Sraj 829187149Sraj tlb0_flush_entry(va); 830176771Sraj pte->flags = 0; 831176771Sraj pte->rpn = 0; 832187149Sraj 833192532Sraj tlb_miss_unlock(); 834187149Sraj mtx_unlock_spin(&tlbivax_mutex); 835187149Sraj 836176771Sraj pmap->pm_stats.resident_count--; 837176771Sraj 838176771Sraj if (flags & PTBL_UNHOLD) { 839176771Sraj //debugf("pte_remove: e (unhold)\n"); 840176771Sraj return (ptbl_unhold(mmu, pmap, pdir_idx)); 841176771Sraj } 842176771Sraj 843176771Sraj //debugf("pte_remove: e\n"); 844176771Sraj return (0); 845176771Sraj} 846176771Sraj 847176771Sraj/* 848176771Sraj * Insert PTE for a given page and virtual address. 849176771Sraj */ 850187149Srajstatic void 851187149Srajpte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 852176771Sraj{ 853176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 854176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 855187149Sraj pte_t *ptbl, *pte; 856176771Sraj 857187149Sraj CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 858187149Sraj pmap == kernel_pmap, pmap, va); 859176771Sraj 860176771Sraj /* Get the page table pointer. */ 861176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 862176771Sraj 863187149Sraj if (ptbl == NULL) { 864187149Sraj /* Allocate page table pages. */ 865187149Sraj ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 866187149Sraj } else { 867176771Sraj /* 868176771Sraj * Check if there is valid mapping for requested 869176771Sraj * va, if there is, remove it. 870176771Sraj */ 871176771Sraj pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 872176771Sraj if (PTE_ISVALID(pte)) { 873176771Sraj pte_remove(mmu, pmap, va, PTBL_HOLD); 874176771Sraj } else { 875176771Sraj /* 876176771Sraj * pte is not used, increment hold count 877176771Sraj * for ptbl pages. 878176771Sraj */ 879176771Sraj if (pmap != kernel_pmap) 880176771Sraj ptbl_hold(mmu, pmap, pdir_idx); 881176771Sraj } 882176771Sraj } 883176771Sraj 884176771Sraj /* 885187149Sraj * Insert pv_entry into pv_list for mapped page if part of managed 886187149Sraj * memory. 887176771Sraj */ 888176771Sraj if ((m->flags & PG_FICTITIOUS) == 0) { 889176771Sraj if ((m->flags & PG_UNMANAGED) == 0) { 890187149Sraj flags |= PTE_MANAGED; 891176771Sraj 892176771Sraj /* Create and insert pv entry. */ 893176771Sraj pv_insert(pmap, va, m); 894176771Sraj } 895176771Sraj } 896176771Sraj 897176771Sraj pmap->pm_stats.resident_count++; 898187149Sraj 899187149Sraj mtx_lock_spin(&tlbivax_mutex); 900192532Sraj tlb_miss_lock(); 901187149Sraj 902187149Sraj tlb0_flush_entry(va); 903187149Sraj if (pmap->pm_pdir[pdir_idx] == NULL) { 904187149Sraj /* 905187149Sraj * If we just allocated a new page table, hook it in 906187149Sraj * the pdir. 907187149Sraj */ 908187149Sraj pmap->pm_pdir[pdir_idx] = ptbl; 909187149Sraj } 910187149Sraj pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 911176771Sraj pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 912176771Sraj pte->flags |= (PTE_VALID | flags); 913176771Sraj 914192532Sraj tlb_miss_unlock(); 915187149Sraj mtx_unlock_spin(&tlbivax_mutex); 916176771Sraj} 917176771Sraj 918176771Sraj/* Return the pa for the given pmap/va. */ 919176771Srajstatic vm_paddr_t 920176771Srajpte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 921176771Sraj{ 922176771Sraj vm_paddr_t pa = 0; 923176771Sraj pte_t *pte; 924176771Sraj 925176771Sraj pte = pte_find(mmu, pmap, va); 926176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 927176771Sraj pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 928176771Sraj return (pa); 929176771Sraj} 930176771Sraj 931176771Sraj/* Get a pointer to a PTE in a page table. */ 932176771Srajstatic pte_t * 933176771Srajpte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 934176771Sraj{ 935176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 936176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 937176771Sraj 938176771Sraj KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 939176771Sraj 940176771Sraj if (pmap->pm_pdir[pdir_idx]) 941176771Sraj return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 942176771Sraj 943176771Sraj return (NULL); 944176771Sraj} 945176771Sraj 946176771Sraj/**************************************************************************/ 947176771Sraj/* PMAP related */ 948176771Sraj/**************************************************************************/ 949176771Sraj 950176771Sraj/* 951176771Sraj * This is called during e500_init, before the system is really initialized. 952176771Sraj */ 953176771Srajstatic void 954190701Smarcelmmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 955176771Sraj{ 956176771Sraj vm_offset_t phys_kernelend; 957176771Sraj struct mem_region *mp, *mp1; 958176771Sraj int cnt, i, j; 959176771Sraj u_int s, e, sz; 960176771Sraj u_int phys_avail_count; 961182198Sraj vm_size_t physsz, hwphyssz, kstack0_sz; 962193489Sraj vm_offset_t kernel_pdir, kstack0, va; 963182198Sraj vm_paddr_t kstack0_phys; 964194784Sjeff void *dpcpu; 965193489Sraj pte_t *pte; 966176771Sraj 967176771Sraj debugf("mmu_booke_bootstrap: entered\n"); 968176771Sraj 969187149Sraj /* Initialize invalidation mutex */ 970187149Sraj mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 971187149Sraj 972187149Sraj /* Read TLB0 size and associativity. */ 973187149Sraj tlb0_get_tlbconf(); 974187149Sraj 975176771Sraj /* Align kernel start and end address (kernel image). */ 976190701Smarcel kernstart = trunc_page(start); 977190701Smarcel data_start = round_page(kernelend); 978190701Smarcel kernsize = data_start - kernstart; 979176771Sraj 980190701Smarcel data_end = data_start; 981190701Smarcel 982176771Sraj /* Allocate space for the message buffer. */ 983190701Smarcel msgbufp = (struct msgbuf *)data_end; 984190701Smarcel data_end += MSGBUF_SIZE; 985187149Sraj debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 986190701Smarcel data_end); 987176771Sraj 988190701Smarcel data_end = round_page(data_end); 989176771Sraj 990194784Sjeff /* Allocate the dynamic per-cpu area. */ 991194784Sjeff dpcpu = (void *)data_end; 992194784Sjeff data_end += DPCPU_SIZE; 993194784Sjeff dpcpu_init(dpcpu, 0); 994194784Sjeff 995176771Sraj /* Allocate space for ptbl_bufs. */ 996190701Smarcel ptbl_bufs = (struct ptbl_buf *)data_end; 997190701Smarcel data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 998187149Sraj debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 999190701Smarcel data_end); 1000176771Sraj 1001190701Smarcel data_end = round_page(data_end); 1002176771Sraj 1003176771Sraj /* Allocate PTE tables for kernel KVA. */ 1004190701Smarcel kernel_pdir = data_end; 1005176771Sraj kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1006176771Sraj PDIR_SIZE - 1) / PDIR_SIZE; 1007190701Smarcel data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1008176771Sraj debugf(" kernel ptbls: %d\n", kernel_ptbls); 1009190701Smarcel debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1010176771Sraj 1011190701Smarcel debugf(" data_end: 0x%08x\n", data_end); 1012190701Smarcel if (data_end - kernstart > 0x1000000) { 1013190701Smarcel data_end = (data_end + 0x3fffff) & ~0x3fffff; 1014190701Smarcel tlb1_mapin_region(kernstart + 0x1000000, 1015190701Smarcel kernload + 0x1000000, data_end - kernstart - 0x1000000); 1016176771Sraj } else 1017190701Smarcel data_end = (data_end + 0xffffff) & ~0xffffff; 1018176771Sraj 1019190701Smarcel debugf(" updated data_end: 0x%08x\n", data_end); 1020187149Sraj 1021190701Smarcel kernsize += data_end - data_start; 1022190701Smarcel 1023182362Sraj /* 1024182362Sraj * Clear the structures - note we can only do it safely after the 1025187149Sraj * possible additional TLB1 translations are in place (above) so that 1026190701Smarcel * all range up to the currently calculated 'data_end' is covered. 1027182362Sraj */ 1028182362Sraj memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1029182362Sraj memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1030182362Sraj 1031176771Sraj /*******************************************************/ 1032176771Sraj /* Set the start and end of kva. */ 1033176771Sraj /*******************************************************/ 1034190701Smarcel virtual_avail = round_page(data_end); 1035176771Sraj virtual_end = VM_MAX_KERNEL_ADDRESS; 1036176771Sraj 1037176771Sraj /* Allocate KVA space for page zero/copy operations. */ 1038176771Sraj zero_page_va = virtual_avail; 1039176771Sraj virtual_avail += PAGE_SIZE; 1040176771Sraj zero_page_idle_va = virtual_avail; 1041176771Sraj virtual_avail += PAGE_SIZE; 1042176771Sraj copy_page_src_va = virtual_avail; 1043176771Sraj virtual_avail += PAGE_SIZE; 1044176771Sraj copy_page_dst_va = virtual_avail; 1045176771Sraj virtual_avail += PAGE_SIZE; 1046187149Sraj debugf("zero_page_va = 0x%08x\n", zero_page_va); 1047187149Sraj debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1048187149Sraj debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1049187149Sraj debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1050176771Sraj 1051176771Sraj /* Initialize page zero/copy mutexes. */ 1052176771Sraj mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1053176771Sraj mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1054176771Sraj 1055176771Sraj /* Allocate KVA space for ptbl bufs. */ 1056176771Sraj ptbl_buf_pool_vabase = virtual_avail; 1057176771Sraj virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1058187149Sraj debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1059187149Sraj ptbl_buf_pool_vabase, virtual_avail); 1060176771Sraj 1061176771Sraj /* Calculate corresponding physical addresses for the kernel region. */ 1062190701Smarcel phys_kernelend = kernload + kernsize; 1063176771Sraj debugf("kernel image and allocated data:\n"); 1064176771Sraj debugf(" kernload = 0x%08x\n", kernload); 1065190701Smarcel debugf(" kernstart = 0x%08x\n", kernstart); 1066190701Smarcel debugf(" kernsize = 0x%08x\n", kernsize); 1067176771Sraj 1068176771Sraj if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1069176771Sraj panic("mmu_booke_bootstrap: phys_avail too small"); 1070176771Sraj 1071176771Sraj /* 1072187151Sraj * Remove kernel physical address range from avail regions list. Page 1073187151Sraj * align all regions. Non-page aligned memory isn't very interesting 1074187151Sraj * to us. Also, sort the entries for ascending addresses. 1075176771Sraj */ 1076192067Snwhitehorn 1077192067Snwhitehorn /* Retrieve phys/avail mem regions */ 1078192067Snwhitehorn mem_regions(&physmem_regions, &physmem_regions_sz, 1079192067Snwhitehorn &availmem_regions, &availmem_regions_sz); 1080176771Sraj sz = 0; 1081176771Sraj cnt = availmem_regions_sz; 1082176771Sraj debugf("processing avail regions:\n"); 1083176771Sraj for (mp = availmem_regions; mp->mr_size; mp++) { 1084176771Sraj s = mp->mr_start; 1085176771Sraj e = mp->mr_start + mp->mr_size; 1086176771Sraj debugf(" %08x-%08x -> ", s, e); 1087176771Sraj /* Check whether this region holds all of the kernel. */ 1088176771Sraj if (s < kernload && e > phys_kernelend) { 1089176771Sraj availmem_regions[cnt].mr_start = phys_kernelend; 1090176771Sraj availmem_regions[cnt++].mr_size = e - phys_kernelend; 1091176771Sraj e = kernload; 1092176771Sraj } 1093176771Sraj /* Look whether this regions starts within the kernel. */ 1094176771Sraj if (s >= kernload && s < phys_kernelend) { 1095176771Sraj if (e <= phys_kernelend) 1096176771Sraj goto empty; 1097176771Sraj s = phys_kernelend; 1098176771Sraj } 1099176771Sraj /* Now look whether this region ends within the kernel. */ 1100176771Sraj if (e > kernload && e <= phys_kernelend) { 1101176771Sraj if (s >= kernload) 1102176771Sraj goto empty; 1103176771Sraj e = kernload; 1104176771Sraj } 1105176771Sraj /* Now page align the start and size of the region. */ 1106176771Sraj s = round_page(s); 1107176771Sraj e = trunc_page(e); 1108176771Sraj if (e < s) 1109176771Sraj e = s; 1110176771Sraj sz = e - s; 1111176771Sraj debugf("%08x-%08x = %x\n", s, e, sz); 1112176771Sraj 1113176771Sraj /* Check whether some memory is left here. */ 1114176771Sraj if (sz == 0) { 1115176771Sraj empty: 1116176771Sraj memmove(mp, mp + 1, 1117176771Sraj (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1118176771Sraj cnt--; 1119176771Sraj mp--; 1120176771Sraj continue; 1121176771Sraj } 1122176771Sraj 1123176771Sraj /* Do an insertion sort. */ 1124176771Sraj for (mp1 = availmem_regions; mp1 < mp; mp1++) 1125176771Sraj if (s < mp1->mr_start) 1126176771Sraj break; 1127176771Sraj if (mp1 < mp) { 1128176771Sraj memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1129176771Sraj mp1->mr_start = s; 1130176771Sraj mp1->mr_size = sz; 1131176771Sraj } else { 1132176771Sraj mp->mr_start = s; 1133176771Sraj mp->mr_size = sz; 1134176771Sraj } 1135176771Sraj } 1136176771Sraj availmem_regions_sz = cnt; 1137176771Sraj 1138176771Sraj /*******************************************************/ 1139182198Sraj /* Steal physical memory for kernel stack from the end */ 1140182198Sraj /* of the first avail region */ 1141182198Sraj /*******************************************************/ 1142182198Sraj kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1143182198Sraj kstack0_phys = availmem_regions[0].mr_start + 1144182198Sraj availmem_regions[0].mr_size; 1145182198Sraj kstack0_phys -= kstack0_sz; 1146182198Sraj availmem_regions[0].mr_size -= kstack0_sz; 1147182198Sraj 1148182198Sraj /*******************************************************/ 1149176771Sraj /* Fill in phys_avail table, based on availmem_regions */ 1150176771Sraj /*******************************************************/ 1151176771Sraj phys_avail_count = 0; 1152176771Sraj physsz = 0; 1153176771Sraj hwphyssz = 0; 1154176771Sraj TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1155176771Sraj 1156176771Sraj debugf("fill in phys_avail:\n"); 1157176771Sraj for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1158176771Sraj 1159176771Sraj debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1160176771Sraj availmem_regions[i].mr_start, 1161187151Sraj availmem_regions[i].mr_start + 1162187151Sraj availmem_regions[i].mr_size, 1163176771Sraj availmem_regions[i].mr_size); 1164176771Sraj 1165182362Sraj if (hwphyssz != 0 && 1166182362Sraj (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1167176771Sraj debugf(" hw.physmem adjust\n"); 1168176771Sraj if (physsz < hwphyssz) { 1169176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1170182362Sraj phys_avail[j + 1] = 1171182362Sraj availmem_regions[i].mr_start + 1172176771Sraj hwphyssz - physsz; 1173176771Sraj physsz = hwphyssz; 1174176771Sraj phys_avail_count++; 1175176771Sraj } 1176176771Sraj break; 1177176771Sraj } 1178176771Sraj 1179176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1180176771Sraj phys_avail[j + 1] = availmem_regions[i].mr_start + 1181176771Sraj availmem_regions[i].mr_size; 1182176771Sraj phys_avail_count++; 1183176771Sraj physsz += availmem_regions[i].mr_size; 1184176771Sraj } 1185176771Sraj physmem = btoc(physsz); 1186176771Sraj 1187176771Sraj /* Calculate the last available physical address. */ 1188176771Sraj for (i = 0; phys_avail[i + 2] != 0; i += 2) 1189176771Sraj ; 1190176771Sraj Maxmem = powerpc_btop(phys_avail[i + 1]); 1191176771Sraj 1192176771Sraj debugf("Maxmem = 0x%08lx\n", Maxmem); 1193176771Sraj debugf("phys_avail_count = %d\n", phys_avail_count); 1194187151Sraj debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1195187151Sraj physmem); 1196176771Sraj 1197176771Sraj /*******************************************************/ 1198176771Sraj /* Initialize (statically allocated) kernel pmap. */ 1199176771Sraj /*******************************************************/ 1200176771Sraj PMAP_LOCK_INIT(kernel_pmap); 1201176771Sraj kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1202176771Sraj 1203187149Sraj debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1204187149Sraj debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1205176771Sraj debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1206176771Sraj kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1207176771Sraj 1208176771Sraj /* Initialize kernel pdir */ 1209176771Sraj for (i = 0; i < kernel_ptbls; i++) 1210176771Sraj kernel_pmap->pm_pdir[kptbl_min + i] = 1211176771Sraj (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1212176771Sraj 1213187149Sraj for (i = 0; i < MAXCPU; i++) { 1214187149Sraj kernel_pmap->pm_tid[i] = TID_KERNEL; 1215187149Sraj 1216187149Sraj /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1217187149Sraj tidbusy[i][0] = kernel_pmap; 1218187149Sraj } 1219193489Sraj 1220193489Sraj /* 1221193489Sraj * Fill in PTEs covering kernel code and data. They are not required 1222193489Sraj * for address translation, as this area is covered by static TLB1 1223193489Sraj * entries, but for pte_vatopa() to work correctly with kernel area 1224193489Sraj * addresses. 1225193489Sraj */ 1226193489Sraj for (va = KERNBASE; va < data_end; va += PAGE_SIZE) { 1227193489Sraj pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1228193489Sraj pte->rpn = kernload + (va - KERNBASE); 1229193489Sraj pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1230193489Sraj PTE_VALID; 1231193489Sraj } 1232187149Sraj /* Mark kernel_pmap active on all CPUs */ 1233176771Sraj kernel_pmap->pm_active = ~0; 1234176771Sraj 1235176771Sraj /*******************************************************/ 1236176771Sraj /* Final setup */ 1237176771Sraj /*******************************************************/ 1238187149Sraj 1239182198Sraj /* Enter kstack0 into kernel map, provide guard page */ 1240182198Sraj kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1241182198Sraj thread0.td_kstack = kstack0; 1242182198Sraj thread0.td_kstack_pages = KSTACK_PAGES; 1243182198Sraj 1244182198Sraj debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1245182198Sraj debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1246182198Sraj kstack0_phys, kstack0_phys + kstack0_sz); 1247182198Sraj debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1248182198Sraj 1249182198Sraj virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1250182198Sraj for (i = 0; i < KSTACK_PAGES; i++) { 1251182198Sraj mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1252182198Sraj kstack0 += PAGE_SIZE; 1253182198Sraj kstack0_phys += PAGE_SIZE; 1254182198Sraj } 1255187149Sraj 1256187149Sraj debugf("virtual_avail = %08x\n", virtual_avail); 1257187149Sraj debugf("virtual_end = %08x\n", virtual_end); 1258182198Sraj 1259176771Sraj debugf("mmu_booke_bootstrap: exit\n"); 1260176771Sraj} 1261176771Sraj 1262192532Srajvoid 1263192532Srajpmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1264192532Sraj{ 1265192532Sraj int i; 1266192532Sraj 1267192532Sraj /* 1268192532Sraj * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1269192532Sraj * have the snapshot of its contents in the s/w tlb1[] table, so use 1270192532Sraj * these values directly to (re)program AP's TLB1 hardware. 1271192532Sraj */ 1272192532Sraj for (i = 0; i < tlb1_idx; i ++) { 1273192532Sraj /* Skip invalid entries */ 1274192532Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 1275192532Sraj continue; 1276192532Sraj 1277192532Sraj tlb1_write_entry(i); 1278192532Sraj } 1279192532Sraj 1280192532Sraj set_mas4_defaults(); 1281192532Sraj} 1282192532Sraj 1283176771Sraj/* 1284176771Sraj * Get the physical page address for the given pmap/virtual address. 1285176771Sraj */ 1286176771Srajstatic vm_paddr_t 1287176771Srajmmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1288176771Sraj{ 1289176771Sraj vm_paddr_t pa; 1290176771Sraj 1291176771Sraj PMAP_LOCK(pmap); 1292176771Sraj pa = pte_vatopa(mmu, pmap, va); 1293176771Sraj PMAP_UNLOCK(pmap); 1294176771Sraj 1295176771Sraj return (pa); 1296176771Sraj} 1297176771Sraj 1298176771Sraj/* 1299176771Sraj * Extract the physical page address associated with the given 1300176771Sraj * kernel virtual address. 1301176771Sraj */ 1302176771Srajstatic vm_paddr_t 1303176771Srajmmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1304176771Sraj{ 1305176771Sraj 1306176771Sraj return (pte_vatopa(mmu, kernel_pmap, va)); 1307176771Sraj} 1308176771Sraj 1309176771Sraj/* 1310176771Sraj * Initialize the pmap module. 1311176771Sraj * Called by vm_init, to initialize any structures that the pmap 1312176771Sraj * system needs to map virtual memory. 1313176771Sraj */ 1314176771Srajstatic void 1315176771Srajmmu_booke_init(mmu_t mmu) 1316176771Sraj{ 1317176771Sraj int shpgperproc = PMAP_SHPGPERPROC; 1318176771Sraj 1319176771Sraj /* 1320176771Sraj * Initialize the address space (zone) for the pv entries. Set a 1321176771Sraj * high water mark so that the system can recover from excessive 1322176771Sraj * numbers of pv entries. 1323176771Sraj */ 1324176771Sraj pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1325176771Sraj NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1326176771Sraj 1327176771Sraj TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1328176771Sraj pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1329176771Sraj 1330176771Sraj TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1331176771Sraj pv_entry_high_water = 9 * (pv_entry_max / 10); 1332176771Sraj 1333176771Sraj uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1334176771Sraj 1335176771Sraj /* Pre-fill pvzone with initial number of pv entries. */ 1336176771Sraj uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1337176771Sraj 1338176771Sraj /* Initialize ptbl allocation. */ 1339176771Sraj ptbl_init(); 1340176771Sraj} 1341176771Sraj 1342176771Sraj/* 1343176771Sraj * Map a list of wired pages into kernel virtual address space. This is 1344176771Sraj * intended for temporary mappings which do not need page modification or 1345176771Sraj * references recorded. Existing mappings in the region are overwritten. 1346176771Sraj */ 1347176771Srajstatic void 1348176771Srajmmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1349176771Sraj{ 1350176771Sraj vm_offset_t va; 1351176771Sraj 1352176771Sraj va = sva; 1353176771Sraj while (count-- > 0) { 1354176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1355176771Sraj va += PAGE_SIZE; 1356176771Sraj m++; 1357176771Sraj } 1358176771Sraj} 1359176771Sraj 1360176771Sraj/* 1361176771Sraj * Remove page mappings from kernel virtual address space. Intended for 1362176771Sraj * temporary mappings entered by mmu_booke_qenter. 1363176771Sraj */ 1364176771Srajstatic void 1365176771Srajmmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1366176771Sraj{ 1367176771Sraj vm_offset_t va; 1368176771Sraj 1369176771Sraj va = sva; 1370176771Sraj while (count-- > 0) { 1371176771Sraj mmu_booke_kremove(mmu, va); 1372176771Sraj va += PAGE_SIZE; 1373176771Sraj } 1374176771Sraj} 1375176771Sraj 1376176771Sraj/* 1377176771Sraj * Map a wired page into kernel virtual address space. 1378176771Sraj */ 1379176771Srajstatic void 1380176771Srajmmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1381176771Sraj{ 1382176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1383176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1384187151Sraj uint32_t flags; 1385176771Sraj pte_t *pte; 1386176771Sraj 1387187151Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1388187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1389176771Sraj 1390176771Sraj flags = 0; 1391176771Sraj flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1392187149Sraj flags |= PTE_M; 1393176771Sraj 1394176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1395176771Sraj 1396187149Sraj mtx_lock_spin(&tlbivax_mutex); 1397192532Sraj tlb_miss_lock(); 1398187149Sraj 1399176771Sraj if (PTE_ISVALID(pte)) { 1400187149Sraj 1401187149Sraj CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1402176771Sraj 1403176771Sraj /* Flush entry from TLB0 */ 1404187149Sraj tlb0_flush_entry(va); 1405176771Sraj } 1406176771Sraj 1407176771Sraj pte->rpn = pa & ~PTE_PA_MASK; 1408176771Sraj pte->flags = flags; 1409176771Sraj 1410176771Sraj //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1411176771Sraj // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1412176771Sraj // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1413176771Sraj 1414176771Sraj /* Flush the real memory from the instruction cache. */ 1415176771Sraj if ((flags & (PTE_I | PTE_G)) == 0) { 1416176771Sraj __syncicache((void *)va, PAGE_SIZE); 1417176771Sraj } 1418176771Sraj 1419192532Sraj tlb_miss_unlock(); 1420187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1421176771Sraj} 1422176771Sraj 1423176771Sraj/* 1424176771Sraj * Remove a page from kernel page table. 1425176771Sraj */ 1426176771Srajstatic void 1427176771Srajmmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1428176771Sraj{ 1429176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1430176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1431176771Sraj pte_t *pte; 1432176771Sraj 1433187149Sraj// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1434176771Sraj 1435187149Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1436187149Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1437176771Sraj ("mmu_booke_kremove: invalid va")); 1438176771Sraj 1439176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1440176771Sraj 1441176771Sraj if (!PTE_ISVALID(pte)) { 1442187149Sraj 1443187149Sraj CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1444187149Sraj 1445176771Sraj return; 1446176771Sraj } 1447176771Sraj 1448187149Sraj mtx_lock_spin(&tlbivax_mutex); 1449192532Sraj tlb_miss_lock(); 1450176771Sraj 1451187149Sraj /* Invalidate entry in TLB0, update PTE. */ 1452187149Sraj tlb0_flush_entry(va); 1453176771Sraj pte->flags = 0; 1454176771Sraj pte->rpn = 0; 1455176771Sraj 1456192532Sraj tlb_miss_unlock(); 1457187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1458176771Sraj} 1459176771Sraj 1460176771Sraj/* 1461176771Sraj * Initialize pmap associated with process 0. 1462176771Sraj */ 1463176771Srajstatic void 1464176771Srajmmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1465176771Sraj{ 1466187151Sraj 1467176771Sraj mmu_booke_pinit(mmu, pmap); 1468176771Sraj PCPU_SET(curpmap, pmap); 1469176771Sraj} 1470176771Sraj 1471176771Sraj/* 1472176771Sraj * Initialize a preallocated and zeroed pmap structure, 1473176771Sraj * such as one in a vmspace structure. 1474176771Sraj */ 1475176771Srajstatic void 1476176771Srajmmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1477176771Sraj{ 1478187149Sraj int i; 1479176771Sraj 1480187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1481187149Sraj curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1482176771Sraj 1483187149Sraj KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1484176771Sraj 1485176771Sraj PMAP_LOCK_INIT(pmap); 1486187149Sraj for (i = 0; i < MAXCPU; i++) 1487187149Sraj pmap->pm_tid[i] = TID_NONE; 1488176771Sraj pmap->pm_active = 0; 1489176771Sraj bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1490176771Sraj bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1491187149Sraj TAILQ_INIT(&pmap->pm_ptbl_list); 1492176771Sraj} 1493176771Sraj 1494176771Sraj/* 1495176771Sraj * Release any resources held by the given physical map. 1496176771Sraj * Called when a pmap initialized by mmu_booke_pinit is being released. 1497176771Sraj * Should only be called if the map contains no valid mappings. 1498176771Sraj */ 1499176771Srajstatic void 1500176771Srajmmu_booke_release(mmu_t mmu, pmap_t pmap) 1501176771Sraj{ 1502176771Sraj 1503187151Sraj KASSERT(pmap->pm_stats.resident_count == 0, 1504187151Sraj ("pmap_release: pmap resident count %ld != 0", 1505187151Sraj pmap->pm_stats.resident_count)); 1506187151Sraj 1507176771Sraj PMAP_LOCK_DESTROY(pmap); 1508176771Sraj} 1509176771Sraj 1510176771Sraj/* 1511176771Sraj * Insert the given physical page at the specified virtual address in the 1512176771Sraj * target physical map with the protection requested. If specified the page 1513176771Sraj * will be wired down. 1514176771Sraj */ 1515176771Srajstatic void 1516176771Srajmmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1517176771Sraj vm_prot_t prot, boolean_t wired) 1518176771Sraj{ 1519187151Sraj 1520176771Sraj vm_page_lock_queues(); 1521176771Sraj PMAP_LOCK(pmap); 1522176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1523176771Sraj vm_page_unlock_queues(); 1524176771Sraj PMAP_UNLOCK(pmap); 1525176771Sraj} 1526176771Sraj 1527176771Srajstatic void 1528176771Srajmmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1529176771Sraj vm_prot_t prot, boolean_t wired) 1530176771Sraj{ 1531176771Sraj pte_t *pte; 1532176771Sraj vm_paddr_t pa; 1533187151Sraj uint32_t flags; 1534176771Sraj int su, sync; 1535176771Sraj 1536176771Sraj pa = VM_PAGE_TO_PHYS(m); 1537176771Sraj su = (pmap == kernel_pmap); 1538176771Sraj sync = 0; 1539176771Sraj 1540176771Sraj //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1541176771Sraj // "pa=0x%08x prot=0x%08x wired=%d)\n", 1542176771Sraj // (u_int32_t)pmap, su, pmap->pm_tid, 1543176771Sraj // (u_int32_t)m, va, pa, prot, wired); 1544176771Sraj 1545176771Sraj if (su) { 1546187151Sraj KASSERT(((va >= virtual_avail) && 1547187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1548187151Sraj ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1549176771Sraj } else { 1550176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1551187151Sraj ("mmu_booke_enter_locked: user pmap, non user va")); 1552176771Sraj } 1553209048Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1554209048Salc (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1555208175Salc ("mmu_booke_enter_locked: page %p is not busy", m)); 1556176771Sraj 1557176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1558176771Sraj 1559176771Sraj /* 1560176771Sraj * If there is an existing mapping, and the physical address has not 1561176771Sraj * changed, must be protection or wiring change. 1562176771Sraj */ 1563176771Sraj if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1564176771Sraj (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1565187149Sraj 1566187149Sraj /* 1567187149Sraj * Before actually updating pte->flags we calculate and 1568187149Sraj * prepare its new value in a helper var. 1569187149Sraj */ 1570187149Sraj flags = pte->flags; 1571187149Sraj flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1572176771Sraj 1573176771Sraj /* Wiring change, just update stats. */ 1574176771Sraj if (wired) { 1575176771Sraj if (!PTE_ISWIRED(pte)) { 1576187149Sraj flags |= PTE_WIRED; 1577176771Sraj pmap->pm_stats.wired_count++; 1578176771Sraj } 1579176771Sraj } else { 1580176771Sraj if (PTE_ISWIRED(pte)) { 1581187149Sraj flags &= ~PTE_WIRED; 1582176771Sraj pmap->pm_stats.wired_count--; 1583176771Sraj } 1584176771Sraj } 1585176771Sraj 1586176771Sraj if (prot & VM_PROT_WRITE) { 1587176771Sraj /* Add write permissions. */ 1588187149Sraj flags |= PTE_SW; 1589176771Sraj if (!su) 1590187149Sraj flags |= PTE_UW; 1591192795Sraj 1592208846Salc if ((flags & PTE_MANAGED) != 0) 1593208846Salc vm_page_flag_set(m, PG_WRITEABLE); 1594176771Sraj } else { 1595176771Sraj /* Handle modified pages, sense modify status. */ 1596187149Sraj 1597187149Sraj /* 1598187149Sraj * The PTE_MODIFIED flag could be set by underlying 1599187149Sraj * TLB misses since we last read it (above), possibly 1600187149Sraj * other CPUs could update it so we check in the PTE 1601187149Sraj * directly rather than rely on that saved local flags 1602187149Sraj * copy. 1603187149Sraj */ 1604178626Smarcel if (PTE_ISMODIFIED(pte)) 1605178626Smarcel vm_page_dirty(m); 1606176771Sraj } 1607176771Sraj 1608176771Sraj if (prot & VM_PROT_EXECUTE) { 1609187149Sraj flags |= PTE_SX; 1610176771Sraj if (!su) 1611187149Sraj flags |= PTE_UX; 1612176771Sraj 1613187149Sraj /* 1614187149Sraj * Check existing flags for execute permissions: if we 1615187149Sraj * are turning execute permissions on, icache should 1616187149Sraj * be flushed. 1617187149Sraj */ 1618208720Salc if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1619176771Sraj sync++; 1620176771Sraj } 1621176771Sraj 1622187149Sraj flags &= ~PTE_REFERENCED; 1623187149Sraj 1624187149Sraj /* 1625187149Sraj * The new flags value is all calculated -- only now actually 1626187149Sraj * update the PTE. 1627187149Sraj */ 1628187149Sraj mtx_lock_spin(&tlbivax_mutex); 1629192532Sraj tlb_miss_lock(); 1630187149Sraj 1631187149Sraj tlb0_flush_entry(va); 1632187149Sraj pte->flags = flags; 1633187149Sraj 1634192532Sraj tlb_miss_unlock(); 1635187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1636187149Sraj 1637176771Sraj } else { 1638176771Sraj /* 1639187149Sraj * If there is an existing mapping, but it's for a different 1640176771Sraj * physical address, pte_enter() will delete the old mapping. 1641176771Sraj */ 1642176771Sraj //if ((pte != NULL) && PTE_ISVALID(pte)) 1643176771Sraj // debugf("mmu_booke_enter_locked: replace\n"); 1644176771Sraj //else 1645176771Sraj // debugf("mmu_booke_enter_locked: new\n"); 1646176771Sraj 1647176771Sraj /* Now set up the flags and install the new mapping. */ 1648176771Sraj flags = (PTE_SR | PTE_VALID); 1649187149Sraj flags |= PTE_M; 1650176771Sraj 1651176771Sraj if (!su) 1652176771Sraj flags |= PTE_UR; 1653176771Sraj 1654176771Sraj if (prot & VM_PROT_WRITE) { 1655176771Sraj flags |= PTE_SW; 1656176771Sraj if (!su) 1657176771Sraj flags |= PTE_UW; 1658192795Sraj 1659208846Salc if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1660208846Salc vm_page_flag_set(m, PG_WRITEABLE); 1661176771Sraj } 1662176771Sraj 1663176771Sraj if (prot & VM_PROT_EXECUTE) { 1664176771Sraj flags |= PTE_SX; 1665176771Sraj if (!su) 1666176771Sraj flags |= PTE_UX; 1667176771Sraj } 1668176771Sraj 1669176771Sraj /* If its wired update stats. */ 1670176771Sraj if (wired) { 1671176771Sraj pmap->pm_stats.wired_count++; 1672176771Sraj flags |= PTE_WIRED; 1673176771Sraj } 1674176771Sraj 1675176771Sraj pte_enter(mmu, pmap, m, va, flags); 1676176771Sraj 1677176771Sraj /* Flush the real memory from the instruction cache. */ 1678176771Sraj if (prot & VM_PROT_EXECUTE) 1679176771Sraj sync++; 1680176771Sraj } 1681176771Sraj 1682176771Sraj if (sync && (su || pmap == PCPU_GET(curpmap))) { 1683176771Sraj __syncicache((void *)va, PAGE_SIZE); 1684176771Sraj sync = 0; 1685176771Sraj } 1686176771Sraj} 1687176771Sraj 1688176771Sraj/* 1689176771Sraj * Maps a sequence of resident pages belonging to the same object. 1690176771Sraj * The sequence begins with the given page m_start. This page is 1691176771Sraj * mapped at the given virtual address start. Each subsequent page is 1692176771Sraj * mapped at a virtual address that is offset from start by the same 1693176771Sraj * amount as the page is offset from m_start within the object. The 1694176771Sraj * last page in the sequence is the page with the largest offset from 1695176771Sraj * m_start that can be mapped at a virtual address less than the given 1696176771Sraj * virtual address end. Not every virtual page between start and end 1697176771Sraj * is mapped; only those for which a resident page exists with the 1698176771Sraj * corresponding offset from m_start are mapped. 1699176771Sraj */ 1700176771Srajstatic void 1701176771Srajmmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1702176771Sraj vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1703176771Sraj{ 1704176771Sraj vm_page_t m; 1705176771Sraj vm_pindex_t diff, psize; 1706176771Sraj 1707176771Sraj psize = atop(end - start); 1708176771Sraj m = m_start; 1709208574Salc vm_page_lock_queues(); 1710176771Sraj PMAP_LOCK(pmap); 1711176771Sraj while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1712187151Sraj mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1713187151Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1714176771Sraj m = TAILQ_NEXT(m, listq); 1715176771Sraj } 1716208574Salc vm_page_unlock_queues(); 1717176771Sraj PMAP_UNLOCK(pmap); 1718176771Sraj} 1719176771Sraj 1720176771Srajstatic void 1721176771Srajmmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1722176771Sraj vm_prot_t prot) 1723176771Sraj{ 1724176771Sraj 1725207796Salc vm_page_lock_queues(); 1726176771Sraj PMAP_LOCK(pmap); 1727176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, 1728176771Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1729207796Salc vm_page_unlock_queues(); 1730176771Sraj PMAP_UNLOCK(pmap); 1731176771Sraj} 1732176771Sraj 1733176771Sraj/* 1734176771Sraj * Remove the given range of addresses from the specified map. 1735176771Sraj * 1736176771Sraj * It is assumed that the start and end are properly rounded to the page size. 1737176771Sraj */ 1738176771Srajstatic void 1739176771Srajmmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1740176771Sraj{ 1741176771Sraj pte_t *pte; 1742187151Sraj uint8_t hold_flag; 1743176771Sraj 1744176771Sraj int su = (pmap == kernel_pmap); 1745176771Sraj 1746176771Sraj //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1747176771Sraj // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1748176771Sraj 1749176771Sraj if (su) { 1750187151Sraj KASSERT(((va >= virtual_avail) && 1751187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1752187151Sraj ("mmu_booke_remove: kernel pmap, non kernel va")); 1753176771Sraj } else { 1754176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1755187151Sraj ("mmu_booke_remove: user pmap, non user va")); 1756176771Sraj } 1757176771Sraj 1758176771Sraj if (PMAP_REMOVE_DONE(pmap)) { 1759176771Sraj //debugf("mmu_booke_remove: e (empty)\n"); 1760176771Sraj return; 1761176771Sraj } 1762176771Sraj 1763176771Sraj hold_flag = PTBL_HOLD_FLAG(pmap); 1764176771Sraj //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1765176771Sraj 1766176771Sraj vm_page_lock_queues(); 1767176771Sraj PMAP_LOCK(pmap); 1768176771Sraj for (; va < endva; va += PAGE_SIZE) { 1769176771Sraj pte = pte_find(mmu, pmap, va); 1770187149Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 1771176771Sraj pte_remove(mmu, pmap, va, hold_flag); 1772176771Sraj } 1773176771Sraj PMAP_UNLOCK(pmap); 1774176771Sraj vm_page_unlock_queues(); 1775176771Sraj 1776176771Sraj //debugf("mmu_booke_remove: e\n"); 1777176771Sraj} 1778176771Sraj 1779176771Sraj/* 1780176771Sraj * Remove physical page from all pmaps in which it resides. 1781176771Sraj */ 1782176771Srajstatic void 1783176771Srajmmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1784176771Sraj{ 1785176771Sraj pv_entry_t pv, pvn; 1786187151Sraj uint8_t hold_flag; 1787176771Sraj 1788207796Salc vm_page_lock_queues(); 1789176771Sraj for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1790176771Sraj pvn = TAILQ_NEXT(pv, pv_link); 1791176771Sraj 1792176771Sraj PMAP_LOCK(pv->pv_pmap); 1793176771Sraj hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1794176771Sraj pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1795176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1796176771Sraj } 1797176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1798207796Salc vm_page_unlock_queues(); 1799176771Sraj} 1800176771Sraj 1801176771Sraj/* 1802176771Sraj * Map a range of physical addresses into kernel virtual address space. 1803176771Sraj */ 1804176771Srajstatic vm_offset_t 1805176771Srajmmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1806176771Sraj vm_offset_t pa_end, int prot) 1807176771Sraj{ 1808176771Sraj vm_offset_t sva = *virt; 1809176771Sraj vm_offset_t va = sva; 1810176771Sraj 1811176771Sraj //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1812176771Sraj // sva, pa_start, pa_end); 1813176771Sraj 1814176771Sraj while (pa_start < pa_end) { 1815176771Sraj mmu_booke_kenter(mmu, va, pa_start); 1816176771Sraj va += PAGE_SIZE; 1817176771Sraj pa_start += PAGE_SIZE; 1818176771Sraj } 1819176771Sraj *virt = va; 1820176771Sraj 1821176771Sraj //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1822176771Sraj return (sva); 1823176771Sraj} 1824176771Sraj 1825176771Sraj/* 1826176771Sraj * The pmap must be activated before it's address space can be accessed in any 1827176771Sraj * way. 1828176771Sraj */ 1829176771Srajstatic void 1830176771Srajmmu_booke_activate(mmu_t mmu, struct thread *td) 1831176771Sraj{ 1832176771Sraj pmap_t pmap; 1833176771Sraj 1834176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1835176771Sraj 1836187149Sraj CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1837187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1838176771Sraj 1839176771Sraj KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1840176771Sraj 1841176771Sraj mtx_lock_spin(&sched_lock); 1842176771Sraj 1843187149Sraj atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 1844176771Sraj PCPU_SET(curpmap, pmap); 1845187149Sraj 1846187149Sraj if (pmap->pm_tid[PCPU_GET(cpuid)] == TID_NONE) 1847176771Sraj tid_alloc(pmap); 1848176771Sraj 1849176771Sraj /* Load PID0 register with pmap tid value. */ 1850187149Sraj mtspr(SPR_PID0, pmap->pm_tid[PCPU_GET(cpuid)]); 1851187149Sraj __asm __volatile("isync"); 1852176771Sraj 1853176771Sraj mtx_unlock_spin(&sched_lock); 1854176771Sraj 1855187149Sraj CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1856187149Sraj pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1857176771Sraj} 1858176771Sraj 1859176771Sraj/* 1860176771Sraj * Deactivate the specified process's address space. 1861176771Sraj */ 1862176771Srajstatic void 1863176771Srajmmu_booke_deactivate(mmu_t mmu, struct thread *td) 1864176771Sraj{ 1865176771Sraj pmap_t pmap; 1866176771Sraj 1867176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1868187149Sraj 1869187149Sraj CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1870187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1871187149Sraj 1872187149Sraj atomic_clear_int(&pmap->pm_active, PCPU_GET(cpumask)); 1873176771Sraj PCPU_SET(curpmap, NULL); 1874176771Sraj} 1875176771Sraj 1876176771Sraj/* 1877176771Sraj * Copy the range specified by src_addr/len 1878176771Sraj * from the source map to the range dst_addr/len 1879176771Sraj * in the destination map. 1880176771Sraj * 1881176771Sraj * This routine is only advisory and need not do anything. 1882176771Sraj */ 1883176771Srajstatic void 1884194101Srajmmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1885194101Sraj vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1886176771Sraj{ 1887176771Sraj 1888176771Sraj} 1889176771Sraj 1890176771Sraj/* 1891176771Sraj * Set the physical protection on the specified range of this map as requested. 1892176771Sraj */ 1893176771Srajstatic void 1894176771Srajmmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1895176771Sraj vm_prot_t prot) 1896176771Sraj{ 1897176771Sraj vm_offset_t va; 1898176771Sraj vm_page_t m; 1899176771Sraj pte_t *pte; 1900176771Sraj 1901176771Sraj if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1902176771Sraj mmu_booke_remove(mmu, pmap, sva, eva); 1903176771Sraj return; 1904176771Sraj } 1905176771Sraj 1906176771Sraj if (prot & VM_PROT_WRITE) 1907176771Sraj return; 1908176771Sraj 1909176771Sraj vm_page_lock_queues(); 1910176771Sraj PMAP_LOCK(pmap); 1911176771Sraj for (va = sva; va < eva; va += PAGE_SIZE) { 1912176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1913176771Sraj if (PTE_ISVALID(pte)) { 1914176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1915176771Sraj 1916187149Sraj mtx_lock_spin(&tlbivax_mutex); 1917192532Sraj tlb_miss_lock(); 1918187149Sraj 1919176771Sraj /* Handle modified pages. */ 1920207437Salc if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1921178626Smarcel vm_page_dirty(m); 1922176771Sraj 1923187149Sraj tlb0_flush_entry(va); 1924207437Salc pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1925187149Sraj 1926192532Sraj tlb_miss_unlock(); 1927187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1928176771Sraj } 1929176771Sraj } 1930176771Sraj } 1931176771Sraj PMAP_UNLOCK(pmap); 1932176771Sraj vm_page_unlock_queues(); 1933176771Sraj} 1934176771Sraj 1935176771Sraj/* 1936176771Sraj * Clear the write and modified bits in each of the given page's mappings. 1937176771Sraj */ 1938176771Srajstatic void 1939176771Srajmmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1940176771Sraj{ 1941176771Sraj pv_entry_t pv; 1942176771Sraj pte_t *pte; 1943176771Sraj 1944208175Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1945208175Salc ("mmu_booke_remove_write: page %p is not managed", m)); 1946208175Salc 1947208175Salc /* 1948208175Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1949208175Salc * another thread while the object is locked. Thus, if PG_WRITEABLE 1950208175Salc * is clear, no page table entries need updating. 1951208175Salc */ 1952208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1953208175Salc if ((m->oflags & VPO_BUSY) == 0 && 1954176771Sraj (m->flags & PG_WRITEABLE) == 0) 1955176771Sraj return; 1956207796Salc vm_page_lock_queues(); 1957176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1958176771Sraj PMAP_LOCK(pv->pv_pmap); 1959176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1960176771Sraj if (PTE_ISVALID(pte)) { 1961176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1962176771Sraj 1963187149Sraj mtx_lock_spin(&tlbivax_mutex); 1964192532Sraj tlb_miss_lock(); 1965187149Sraj 1966176771Sraj /* Handle modified pages. */ 1967178626Smarcel if (PTE_ISMODIFIED(pte)) 1968178626Smarcel vm_page_dirty(m); 1969176771Sraj 1970176771Sraj /* Flush mapping from TLB0. */ 1971207437Salc pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1972187149Sraj 1973192532Sraj tlb_miss_unlock(); 1974187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1975176771Sraj } 1976176771Sraj } 1977176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1978176771Sraj } 1979176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1980207796Salc vm_page_unlock_queues(); 1981176771Sraj} 1982176771Sraj 1983198341Smarcelstatic void 1984198341Smarcelmmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1985176771Sraj{ 1986176771Sraj pte_t *pte; 1987198341Smarcel pmap_t pmap; 1988198341Smarcel vm_page_t m; 1989198341Smarcel vm_offset_t addr; 1990198341Smarcel vm_paddr_t pa; 1991198341Smarcel int active, valid; 1992198341Smarcel 1993198341Smarcel va = trunc_page(va); 1994198341Smarcel sz = round_page(sz); 1995176771Sraj 1996198341Smarcel vm_page_lock_queues(); 1997198341Smarcel pmap = PCPU_GET(curpmap); 1998198341Smarcel active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 1999198341Smarcel while (sz > 0) { 2000198341Smarcel PMAP_LOCK(pm); 2001198341Smarcel pte = pte_find(mmu, pm, va); 2002198341Smarcel valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2003198341Smarcel if (valid) 2004198341Smarcel pa = PTE_PA(pte); 2005198341Smarcel PMAP_UNLOCK(pm); 2006198341Smarcel if (valid) { 2007198341Smarcel if (!active) { 2008198341Smarcel /* Create a mapping in the active pmap. */ 2009198341Smarcel addr = 0; 2010198341Smarcel m = PHYS_TO_VM_PAGE(pa); 2011198341Smarcel PMAP_LOCK(pmap); 2012198341Smarcel pte_enter(mmu, pmap, m, addr, 2013198341Smarcel PTE_SR | PTE_VALID | PTE_UR); 2014198341Smarcel __syncicache((void *)addr, PAGE_SIZE); 2015198341Smarcel pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2016198341Smarcel PMAP_UNLOCK(pmap); 2017198341Smarcel } else 2018198341Smarcel __syncicache((void *)va, PAGE_SIZE); 2019198341Smarcel } 2020198341Smarcel va += PAGE_SIZE; 2021198341Smarcel sz -= PAGE_SIZE; 2022176771Sraj } 2023198341Smarcel vm_page_unlock_queues(); 2024176771Sraj} 2025176771Sraj 2026176771Sraj/* 2027176771Sraj * Atomically extract and hold the physical page with the given 2028176771Sraj * pmap and virtual address pair if that mapping permits the given 2029176771Sraj * protection. 2030176771Sraj */ 2031176771Srajstatic vm_page_t 2032176771Srajmmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2033176771Sraj vm_prot_t prot) 2034176771Sraj{ 2035176771Sraj pte_t *pte; 2036176771Sraj vm_page_t m; 2037187151Sraj uint32_t pte_wbit; 2038207410Skmacy vm_paddr_t pa; 2039207410Skmacy 2040176771Sraj m = NULL; 2041207410Skmacy pa = 0; 2042176771Sraj PMAP_LOCK(pmap); 2043207410Skmacyretry: 2044176771Sraj pte = pte_find(mmu, pmap, va); 2045176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) { 2046176771Sraj if (pmap == kernel_pmap) 2047176771Sraj pte_wbit = PTE_SW; 2048176771Sraj else 2049176771Sraj pte_wbit = PTE_UW; 2050176771Sraj 2051176771Sraj if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2052207410Skmacy if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2053207410Skmacy goto retry; 2054176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2055176771Sraj vm_page_hold(m); 2056176771Sraj } 2057176771Sraj } 2058176771Sraj 2059207410Skmacy PA_UNLOCK_COND(pa); 2060176771Sraj PMAP_UNLOCK(pmap); 2061176771Sraj return (m); 2062176771Sraj} 2063176771Sraj 2064176771Sraj/* 2065176771Sraj * Initialize a vm_page's machine-dependent fields. 2066176771Sraj */ 2067176771Srajstatic void 2068176771Srajmmu_booke_page_init(mmu_t mmu, vm_page_t m) 2069176771Sraj{ 2070176771Sraj 2071176771Sraj TAILQ_INIT(&m->md.pv_list); 2072176771Sraj} 2073176771Sraj 2074176771Sraj/* 2075176771Sraj * mmu_booke_zero_page_area zeros the specified hardware page by 2076176771Sraj * mapping it into virtual memory and using bzero to clear 2077176771Sraj * its contents. 2078176771Sraj * 2079176771Sraj * off and size must reside within a single page. 2080176771Sraj */ 2081176771Srajstatic void 2082176771Srajmmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2083176771Sraj{ 2084176771Sraj vm_offset_t va; 2085176771Sraj 2086187151Sraj /* XXX KASSERT off and size are within a single page? */ 2087176771Sraj 2088176771Sraj mtx_lock(&zero_page_mutex); 2089176771Sraj va = zero_page_va; 2090176771Sraj 2091176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2092176771Sraj bzero((caddr_t)va + off, size); 2093176771Sraj mmu_booke_kremove(mmu, va); 2094176771Sraj 2095176771Sraj mtx_unlock(&zero_page_mutex); 2096176771Sraj} 2097176771Sraj 2098176771Sraj/* 2099176771Sraj * mmu_booke_zero_page zeros the specified hardware page. 2100176771Sraj */ 2101176771Srajstatic void 2102176771Srajmmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2103176771Sraj{ 2104176771Sraj 2105176771Sraj mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2106176771Sraj} 2107176771Sraj 2108176771Sraj/* 2109176771Sraj * mmu_booke_copy_page copies the specified (machine independent) page by 2110176771Sraj * mapping the page into virtual memory and using memcopy to copy the page, 2111176771Sraj * one machine dependent page at a time. 2112176771Sraj */ 2113176771Srajstatic void 2114176771Srajmmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2115176771Sraj{ 2116176771Sraj vm_offset_t sva, dva; 2117176771Sraj 2118176771Sraj sva = copy_page_src_va; 2119176771Sraj dva = copy_page_dst_va; 2120176771Sraj 2121187149Sraj mtx_lock(©_page_mutex); 2122176771Sraj mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2123176771Sraj mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2124176771Sraj memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2125176771Sraj mmu_booke_kremove(mmu, dva); 2126176771Sraj mmu_booke_kremove(mmu, sva); 2127176771Sraj mtx_unlock(©_page_mutex); 2128176771Sraj} 2129176771Sraj 2130176771Sraj/* 2131176771Sraj * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2132176771Sraj * into virtual memory and using bzero to clear its contents. This is intended 2133176771Sraj * to be called from the vm_pagezero process only and outside of Giant. No 2134176771Sraj * lock is required. 2135176771Sraj */ 2136176771Srajstatic void 2137176771Srajmmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2138176771Sraj{ 2139176771Sraj vm_offset_t va; 2140176771Sraj 2141176771Sraj va = zero_page_idle_va; 2142176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2143176771Sraj bzero((caddr_t)va, PAGE_SIZE); 2144176771Sraj mmu_booke_kremove(mmu, va); 2145176771Sraj} 2146176771Sraj 2147176771Sraj/* 2148176771Sraj * Return whether or not the specified physical page was modified 2149176771Sraj * in any of physical maps. 2150176771Sraj */ 2151176771Srajstatic boolean_t 2152176771Srajmmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2153176771Sraj{ 2154176771Sraj pte_t *pte; 2155176771Sraj pv_entry_t pv; 2156208504Salc boolean_t rv; 2157176771Sraj 2158208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2159208504Salc ("mmu_booke_is_modified: page %p is not managed", m)); 2160208504Salc rv = FALSE; 2161176771Sraj 2162208504Salc /* 2163208504Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2164208504Salc * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2165208504Salc * is clear, no PTEs can be modified. 2166208504Salc */ 2167208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2168208504Salc if ((m->oflags & VPO_BUSY) == 0 && 2169208504Salc (m->flags & PG_WRITEABLE) == 0) 2170208504Salc return (rv); 2171208504Salc vm_page_lock_queues(); 2172176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2173176771Sraj PMAP_LOCK(pv->pv_pmap); 2174208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2175208504Salc PTE_ISVALID(pte)) { 2176208504Salc if (PTE_ISMODIFIED(pte)) 2177208504Salc rv = TRUE; 2178176771Sraj } 2179176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2180208504Salc if (rv) 2181208504Salc break; 2182176771Sraj } 2183208504Salc vm_page_unlock_queues(); 2184208504Salc return (rv); 2185176771Sraj} 2186176771Sraj 2187176771Sraj/* 2188187151Sraj * Return whether or not the specified virtual address is eligible 2189176771Sraj * for prefault. 2190176771Sraj */ 2191176771Srajstatic boolean_t 2192176771Srajmmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2193176771Sraj{ 2194176771Sraj 2195176771Sraj return (FALSE); 2196176771Sraj} 2197176771Sraj 2198176771Sraj/* 2199207155Salc * Return whether or not the specified physical page was referenced 2200207155Salc * in any physical maps. 2201207155Salc */ 2202207155Salcstatic boolean_t 2203207155Salcmmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2204207155Salc{ 2205207155Salc pte_t *pte; 2206207155Salc pv_entry_t pv; 2207207155Salc boolean_t rv; 2208207155Salc 2209208574Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2210208574Salc ("mmu_booke_is_referenced: page %p is not managed", m)); 2211207155Salc rv = FALSE; 2212208574Salc vm_page_lock_queues(); 2213207155Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2214207155Salc PMAP_LOCK(pv->pv_pmap); 2215207155Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2216208574Salc PTE_ISVALID(pte)) { 2217208574Salc if (PTE_ISREFERENCED(pte)) 2218208574Salc rv = TRUE; 2219208574Salc } 2220207155Salc PMAP_UNLOCK(pv->pv_pmap); 2221207155Salc if (rv) 2222207155Salc break; 2223207155Salc } 2224208574Salc vm_page_unlock_queues(); 2225207155Salc return (rv); 2226207155Salc} 2227207155Salc 2228207155Salc/* 2229176771Sraj * Clear the modify bits on the specified physical page. 2230176771Sraj */ 2231176771Srajstatic void 2232176771Srajmmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2233176771Sraj{ 2234176771Sraj pte_t *pte; 2235176771Sraj pv_entry_t pv; 2236176771Sraj 2237208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2238208504Salc ("mmu_booke_clear_modify: page %p is not managed", m)); 2239208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2240208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 2241208504Salc ("mmu_booke_clear_modify: page %p is busy", m)); 2242208504Salc 2243208504Salc /* 2244208504Salc * If the page is not PG_WRITEABLE, then no PTEs can be modified. 2245208504Salc * If the object containing the page is locked and the page is not 2246208504Salc * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2247208504Salc */ 2248208504Salc if ((m->flags & PG_WRITEABLE) == 0) 2249176771Sraj return; 2250208504Salc vm_page_lock_queues(); 2251176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2252176771Sraj PMAP_LOCK(pv->pv_pmap); 2253208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2254208504Salc PTE_ISVALID(pte)) { 2255187149Sraj mtx_lock_spin(&tlbivax_mutex); 2256192532Sraj tlb_miss_lock(); 2257187149Sraj 2258176771Sraj if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2259187149Sraj tlb0_flush_entry(pv->pv_va); 2260176771Sraj pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2261176771Sraj PTE_REFERENCED); 2262176771Sraj } 2263187149Sraj 2264192532Sraj tlb_miss_unlock(); 2265187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2266176771Sraj } 2267176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2268176771Sraj } 2269208504Salc vm_page_unlock_queues(); 2270176771Sraj} 2271176771Sraj 2272176771Sraj/* 2273176771Sraj * Return a count of reference bits for a page, clearing those bits. 2274176771Sraj * It is not necessary for every reference bit to be cleared, but it 2275176771Sraj * is necessary that 0 only be returned when there are truly no 2276176771Sraj * reference bits set. 2277176771Sraj * 2278176771Sraj * XXX: The exact number of bits to check and clear is a matter that 2279176771Sraj * should be tested and standardized at some point in the future for 2280176771Sraj * optimal aging of shared pages. 2281176771Sraj */ 2282176771Srajstatic int 2283176771Srajmmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2284176771Sraj{ 2285176771Sraj pte_t *pte; 2286176771Sraj pv_entry_t pv; 2287176771Sraj int count; 2288176771Sraj 2289208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2290208990Salc ("mmu_booke_ts_referenced: page %p is not managed", m)); 2291176771Sraj count = 0; 2292208990Salc vm_page_lock_queues(); 2293176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2294176771Sraj PMAP_LOCK(pv->pv_pmap); 2295208990Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2296208990Salc PTE_ISVALID(pte)) { 2297176771Sraj if (PTE_ISREFERENCED(pte)) { 2298187149Sraj mtx_lock_spin(&tlbivax_mutex); 2299192532Sraj tlb_miss_lock(); 2300187149Sraj 2301187149Sraj tlb0_flush_entry(pv->pv_va); 2302176771Sraj pte->flags &= ~PTE_REFERENCED; 2303176771Sraj 2304192532Sraj tlb_miss_unlock(); 2305187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2306187149Sraj 2307176771Sraj if (++count > 4) { 2308176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2309176771Sraj break; 2310176771Sraj } 2311176771Sraj } 2312176771Sraj } 2313176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2314176771Sraj } 2315208990Salc vm_page_unlock_queues(); 2316176771Sraj return (count); 2317176771Sraj} 2318176771Sraj 2319176771Sraj/* 2320176771Sraj * Clear the reference bit on the specified physical page. 2321176771Sraj */ 2322176771Srajstatic void 2323176771Srajmmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2324176771Sraj{ 2325176771Sraj pte_t *pte; 2326176771Sraj pv_entry_t pv; 2327176771Sraj 2328208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2329208504Salc ("mmu_booke_clear_reference: page %p is not managed", m)); 2330208504Salc vm_page_lock_queues(); 2331176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2332176771Sraj PMAP_LOCK(pv->pv_pmap); 2333208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2334208504Salc PTE_ISVALID(pte)) { 2335176771Sraj if (PTE_ISREFERENCED(pte)) { 2336187149Sraj mtx_lock_spin(&tlbivax_mutex); 2337192532Sraj tlb_miss_lock(); 2338187149Sraj 2339187149Sraj tlb0_flush_entry(pv->pv_va); 2340176771Sraj pte->flags &= ~PTE_REFERENCED; 2341187149Sraj 2342192532Sraj tlb_miss_unlock(); 2343187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2344176771Sraj } 2345176771Sraj } 2346176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2347176771Sraj } 2348208504Salc vm_page_unlock_queues(); 2349176771Sraj} 2350176771Sraj 2351176771Sraj/* 2352176771Sraj * Change wiring attribute for a map/virtual-address pair. 2353176771Sraj */ 2354176771Srajstatic void 2355176771Srajmmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2356176771Sraj{ 2357201758Smbr pte_t *pte; 2358176771Sraj 2359176771Sraj PMAP_LOCK(pmap); 2360176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2361176771Sraj if (wired) { 2362176771Sraj if (!PTE_ISWIRED(pte)) { 2363176771Sraj pte->flags |= PTE_WIRED; 2364176771Sraj pmap->pm_stats.wired_count++; 2365176771Sraj } 2366176771Sraj } else { 2367176771Sraj if (PTE_ISWIRED(pte)) { 2368176771Sraj pte->flags &= ~PTE_WIRED; 2369176771Sraj pmap->pm_stats.wired_count--; 2370176771Sraj } 2371176771Sraj } 2372176771Sraj } 2373176771Sraj PMAP_UNLOCK(pmap); 2374176771Sraj} 2375176771Sraj 2376176771Sraj/* 2377176771Sraj * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2378176771Sraj * page. This count may be changed upwards or downwards in the future; it is 2379176771Sraj * only necessary that true be returned for a small subset of pmaps for proper 2380176771Sraj * page aging. 2381176771Sraj */ 2382176771Srajstatic boolean_t 2383176771Srajmmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2384176771Sraj{ 2385176771Sraj pv_entry_t pv; 2386176771Sraj int loops; 2387208990Salc boolean_t rv; 2388176771Sraj 2389208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2390208990Salc ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2391176771Sraj loops = 0; 2392208990Salc rv = FALSE; 2393208990Salc vm_page_lock_queues(); 2394176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2395208990Salc if (pv->pv_pmap == pmap) { 2396208990Salc rv = TRUE; 2397208990Salc break; 2398208990Salc } 2399176771Sraj if (++loops >= 16) 2400176771Sraj break; 2401176771Sraj } 2402208990Salc vm_page_unlock_queues(); 2403208990Salc return (rv); 2404176771Sraj} 2405176771Sraj 2406176771Sraj/* 2407176771Sraj * Return the number of managed mappings to the given physical page that are 2408176771Sraj * wired. 2409176771Sraj */ 2410176771Srajstatic int 2411176771Srajmmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2412176771Sraj{ 2413176771Sraj pv_entry_t pv; 2414176771Sraj pte_t *pte; 2415176771Sraj int count = 0; 2416176771Sraj 2417176771Sraj if ((m->flags & PG_FICTITIOUS) != 0) 2418176771Sraj return (count); 2419207796Salc vm_page_lock_queues(); 2420176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2421176771Sraj PMAP_LOCK(pv->pv_pmap); 2422176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2423176771Sraj if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2424176771Sraj count++; 2425176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2426176771Sraj } 2427207796Salc vm_page_unlock_queues(); 2428176771Sraj return (count); 2429176771Sraj} 2430176771Sraj 2431176771Srajstatic int 2432176771Srajmmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2433176771Sraj{ 2434176771Sraj int i; 2435176771Sraj vm_offset_t va; 2436176771Sraj 2437176771Sraj /* 2438176771Sraj * This currently does not work for entries that 2439176771Sraj * overlap TLB1 entries. 2440176771Sraj */ 2441176771Sraj for (i = 0; i < tlb1_idx; i ++) { 2442176771Sraj if (tlb1_iomapped(i, pa, size, &va) == 0) 2443176771Sraj return (0); 2444176771Sraj } 2445176771Sraj 2446176771Sraj return (EFAULT); 2447176771Sraj} 2448176771Sraj 2449190701Smarcelvm_offset_t 2450190701Smarcelmmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2451190701Smarcel vm_size_t *sz) 2452190701Smarcel{ 2453190701Smarcel vm_paddr_t pa, ppa; 2454190701Smarcel vm_offset_t va; 2455190701Smarcel vm_size_t gran; 2456190701Smarcel 2457190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2458190701Smarcel if (md->md_vaddr == ~0UL) { 2459190701Smarcel /* We always map a 256MB page at 256M. */ 2460190701Smarcel gran = 256 * 1024 * 1024; 2461190701Smarcel pa = md->md_paddr + ofs; 2462190701Smarcel ppa = pa & ~(gran - 1); 2463190701Smarcel ofs = pa - ppa; 2464190701Smarcel va = gran; 2465190701Smarcel tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2466190701Smarcel if (*sz > (gran - ofs)) 2467190701Smarcel *sz = gran - ofs; 2468190701Smarcel return (va + ofs); 2469190701Smarcel } 2470190701Smarcel 2471190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2472190701Smarcel va = md->md_vaddr + ofs; 2473190701Smarcel if (va >= kernstart + kernsize) { 2474190701Smarcel gran = PAGE_SIZE - (va & PAGE_MASK); 2475190701Smarcel if (*sz > gran) 2476190701Smarcel *sz = gran; 2477190701Smarcel } 2478190701Smarcel return (va); 2479190701Smarcel} 2480190701Smarcel 2481190701Smarcelvoid 2482190701Smarcelmmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2483190701Smarcel vm_offset_t va) 2484190701Smarcel{ 2485190701Smarcel 2486190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2487190701Smarcel if (md->md_vaddr == ~0UL) { 2488190701Smarcel tlb1_idx--; 2489190701Smarcel tlb1[tlb1_idx].mas1 = 0; 2490190701Smarcel tlb1[tlb1_idx].mas2 = 0; 2491190701Smarcel tlb1[tlb1_idx].mas3 = 0; 2492190701Smarcel tlb1_write_entry(tlb1_idx); 2493190701Smarcel return; 2494190701Smarcel } 2495190701Smarcel 2496190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2497190701Smarcel /* Nothing to do... */ 2498190701Smarcel} 2499190701Smarcel 2500190701Smarcelstruct pmap_md * 2501190701Smarcelmmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2502190701Smarcel{ 2503190701Smarcel static struct pmap_md md; 2504190701Smarcel pte_t *pte; 2505190701Smarcel vm_offset_t va; 2506190701Smarcel 2507190701Smarcel if (dumpsys_minidump) { 2508190701Smarcel md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2509190701Smarcel if (prev == NULL) { 2510190701Smarcel /* 1st: kernel .data and .bss. */ 2511190701Smarcel md.md_index = 1; 2512190701Smarcel md.md_vaddr = trunc_page((uintptr_t)_etext); 2513190701Smarcel md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2514190701Smarcel return (&md); 2515190701Smarcel } 2516190701Smarcel switch (prev->md_index) { 2517190701Smarcel case 1: 2518190701Smarcel /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2519190701Smarcel md.md_index = 2; 2520190701Smarcel md.md_vaddr = data_start; 2521190701Smarcel md.md_size = data_end - data_start; 2522190701Smarcel break; 2523190701Smarcel case 2: 2524190701Smarcel /* 3rd: kernel VM. */ 2525190701Smarcel va = prev->md_vaddr + prev->md_size; 2526190701Smarcel /* Find start of next chunk (from va). */ 2527190701Smarcel while (va < virtual_end) { 2528190701Smarcel /* Don't dump the buffer cache. */ 2529190701Smarcel if (va >= kmi.buffer_sva && 2530190701Smarcel va < kmi.buffer_eva) { 2531190701Smarcel va = kmi.buffer_eva; 2532190701Smarcel continue; 2533190701Smarcel } 2534190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2535190701Smarcel if (pte != NULL && PTE_ISVALID(pte)) 2536190701Smarcel break; 2537190701Smarcel va += PAGE_SIZE; 2538190701Smarcel } 2539190701Smarcel if (va < virtual_end) { 2540190701Smarcel md.md_vaddr = va; 2541190701Smarcel va += PAGE_SIZE; 2542190701Smarcel /* Find last page in chunk. */ 2543190701Smarcel while (va < virtual_end) { 2544190701Smarcel /* Don't run into the buffer cache. */ 2545190701Smarcel if (va == kmi.buffer_sva) 2546190701Smarcel break; 2547190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2548190701Smarcel if (pte == NULL || !PTE_ISVALID(pte)) 2549190701Smarcel break; 2550190701Smarcel va += PAGE_SIZE; 2551190701Smarcel } 2552190701Smarcel md.md_size = va - md.md_vaddr; 2553190701Smarcel break; 2554190701Smarcel } 2555190701Smarcel md.md_index = 3; 2556190701Smarcel /* FALLTHROUGH */ 2557190701Smarcel default: 2558190701Smarcel return (NULL); 2559190701Smarcel } 2560190701Smarcel } else { /* minidumps */ 2561209908Sraj mem_regions(&physmem_regions, &physmem_regions_sz, 2562209908Sraj &availmem_regions, &availmem_regions_sz); 2563209908Sraj 2564190701Smarcel if (prev == NULL) { 2565190701Smarcel /* first physical chunk. */ 2566209908Sraj md.md_paddr = physmem_regions[0].mr_start; 2567209908Sraj md.md_size = physmem_regions[0].mr_size; 2568190701Smarcel md.md_vaddr = ~0UL; 2569190701Smarcel md.md_index = 1; 2570209908Sraj } else if (md.md_index < physmem_regions_sz) { 2571209908Sraj md.md_paddr = physmem_regions[md.md_index].mr_start; 2572209908Sraj md.md_size = physmem_regions[md.md_index].mr_size; 2573190701Smarcel md.md_vaddr = ~0UL; 2574190701Smarcel md.md_index++; 2575190701Smarcel } else { 2576190701Smarcel /* There's no next physical chunk. */ 2577190701Smarcel return (NULL); 2578190701Smarcel } 2579190701Smarcel } 2580190701Smarcel 2581190701Smarcel return (&md); 2582190701Smarcel} 2583190701Smarcel 2584176771Sraj/* 2585176771Sraj * Map a set of physical memory pages into the kernel virtual address space. 2586176771Sraj * Return a pointer to where it is mapped. This routine is intended to be used 2587176771Sraj * for mapping device memory, NOT real memory. 2588176771Sraj */ 2589176771Srajstatic void * 2590176771Srajmmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2591176771Sraj{ 2592184244Smarcel void *res; 2593176771Sraj uintptr_t va; 2594184244Smarcel vm_size_t sz; 2595176771Sraj 2596176771Sraj va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2597184244Smarcel res = (void *)va; 2598184244Smarcel 2599184244Smarcel do { 2600184244Smarcel sz = 1 << (ilog2(size) & ~1); 2601184244Smarcel if (bootverbose) 2602184244Smarcel printf("Wiring VA=%x to PA=%x (size=%x), " 2603184244Smarcel "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2604184244Smarcel tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2605184244Smarcel size -= sz; 2606184244Smarcel pa += sz; 2607184244Smarcel va += sz; 2608184244Smarcel } while (size > 0); 2609184244Smarcel 2610184244Smarcel return (res); 2611176771Sraj} 2612176771Sraj 2613176771Sraj/* 2614176771Sraj * 'Unmap' a range mapped by mmu_booke_mapdev(). 2615176771Sraj */ 2616176771Srajstatic void 2617176771Srajmmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2618176771Sraj{ 2619176771Sraj vm_offset_t base, offset; 2620176771Sraj 2621176771Sraj /* 2622176771Sraj * Unmap only if this is inside kernel virtual space. 2623176771Sraj */ 2624176771Sraj if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2625176771Sraj base = trunc_page(va); 2626176771Sraj offset = va & PAGE_MASK; 2627176771Sraj size = roundup(offset + size, PAGE_SIZE); 2628176771Sraj kmem_free(kernel_map, base, size); 2629176771Sraj } 2630176771Sraj} 2631176771Sraj 2632176771Sraj/* 2633187151Sraj * mmu_booke_object_init_pt preloads the ptes for a given object into the 2634187151Sraj * specified pmap. This eliminates the blast of soft faults on process startup 2635187151Sraj * and immediately after an mmap. 2636176771Sraj */ 2637176771Srajstatic void 2638176771Srajmmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2639176771Sraj vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2640176771Sraj{ 2641187151Sraj 2642176771Sraj VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2643195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2644176771Sraj ("mmu_booke_object_init_pt: non-device object")); 2645176771Sraj} 2646176771Sraj 2647176771Sraj/* 2648176771Sraj * Perform the pmap work for mincore. 2649176771Sraj */ 2650176771Srajstatic int 2651208504Salcmmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2652208504Salc vm_paddr_t *locked_pa) 2653176771Sraj{ 2654176771Sraj 2655176771Sraj TODO; 2656176771Sraj return (0); 2657176771Sraj} 2658176771Sraj 2659176771Sraj/**************************************************************************/ 2660176771Sraj/* TID handling */ 2661176771Sraj/**************************************************************************/ 2662176771Sraj 2663176771Sraj/* 2664176771Sraj * Allocate a TID. If necessary, steal one from someone else. 2665176771Sraj * The new TID is flushed from the TLB before returning. 2666176771Sraj */ 2667176771Srajstatic tlbtid_t 2668176771Srajtid_alloc(pmap_t pmap) 2669176771Sraj{ 2670176771Sraj tlbtid_t tid; 2671187149Sraj int thiscpu; 2672176771Sraj 2673187149Sraj KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2674176771Sraj 2675187149Sraj CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2676176771Sraj 2677187149Sraj thiscpu = PCPU_GET(cpuid); 2678176771Sraj 2679187149Sraj tid = PCPU_GET(tid_next); 2680187149Sraj if (tid > TID_MAX) 2681187149Sraj tid = TID_MIN; 2682187149Sraj PCPU_SET(tid_next, tid + 1); 2683176771Sraj 2684187149Sraj /* If we are stealing TID then clear the relevant pmap's field */ 2685187149Sraj if (tidbusy[thiscpu][tid] != NULL) { 2686176771Sraj 2687187149Sraj CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2688187149Sraj 2689187149Sraj tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2690176771Sraj 2691187149Sraj /* Flush all entries from TLB0 matching this TID. */ 2692187149Sraj tid_flush(tid); 2693176771Sraj } 2694176771Sraj 2695187149Sraj tidbusy[thiscpu][tid] = pmap; 2696187149Sraj pmap->pm_tid[thiscpu] = tid; 2697187149Sraj __asm __volatile("msync; isync"); 2698176771Sraj 2699187149Sraj CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2700187149Sraj PCPU_GET(tid_next)); 2701176771Sraj 2702176771Sraj return (tid); 2703176771Sraj} 2704176771Sraj 2705176771Sraj/**************************************************************************/ 2706176771Sraj/* TLB0 handling */ 2707176771Sraj/**************************************************************************/ 2708176771Sraj 2709176771Srajstatic void 2710187149Srajtlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2711187149Sraj uint32_t mas7) 2712176771Sraj{ 2713176771Sraj int as; 2714176771Sraj char desc[3]; 2715176771Sraj tlbtid_t tid; 2716176771Sraj vm_size_t size; 2717176771Sraj unsigned int tsize; 2718176771Sraj 2719176771Sraj desc[2] = '\0'; 2720176771Sraj if (mas1 & MAS1_VALID) 2721176771Sraj desc[0] = 'V'; 2722176771Sraj else 2723176771Sraj desc[0] = ' '; 2724176771Sraj 2725176771Sraj if (mas1 & MAS1_IPROT) 2726176771Sraj desc[1] = 'P'; 2727176771Sraj else 2728176771Sraj desc[1] = ' '; 2729176771Sraj 2730187149Sraj as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2731176771Sraj tid = MAS1_GETTID(mas1); 2732176771Sraj 2733176771Sraj tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2734176771Sraj size = 0; 2735176771Sraj if (tsize) 2736176771Sraj size = tsize2size(tsize); 2737176771Sraj 2738176771Sraj debugf("%3d: (%s) [AS=%d] " 2739176771Sraj "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2740176771Sraj "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2741176771Sraj i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2742176771Sraj} 2743176771Sraj 2744176771Sraj/* Convert TLB0 va and way number to tlb0[] table index. */ 2745176771Srajstatic inline unsigned int 2746176771Srajtlb0_tableidx(vm_offset_t va, unsigned int way) 2747176771Sraj{ 2748176771Sraj unsigned int idx; 2749176771Sraj 2750176771Sraj idx = (way * TLB0_ENTRIES_PER_WAY); 2751176771Sraj idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2752176771Sraj return (idx); 2753176771Sraj} 2754176771Sraj 2755176771Sraj/* 2756187149Sraj * Invalidate TLB0 entry. 2757176771Sraj */ 2758187149Srajstatic inline void 2759187149Srajtlb0_flush_entry(vm_offset_t va) 2760176771Sraj{ 2761176771Sraj 2762187149Sraj CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2763176771Sraj 2764187149Sraj mtx_assert(&tlbivax_mutex, MA_OWNED); 2765176771Sraj 2766187149Sraj __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2767187149Sraj __asm __volatile("isync; msync"); 2768187149Sraj __asm __volatile("tlbsync; msync"); 2769176771Sraj 2770187149Sraj CTR1(KTR_PMAP, "%s: e", __func__); 2771176771Sraj} 2772176771Sraj 2773176771Sraj/* Print out contents of the MAS registers for each TLB0 entry */ 2774187149Srajvoid 2775176771Srajtlb0_print_tlbentries(void) 2776176771Sraj{ 2777187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 2778176771Sraj int entryidx, way, idx; 2779176771Sraj 2780176771Sraj debugf("TLB0 entries:\n"); 2781187149Sraj for (way = 0; way < TLB0_WAYS; way ++) 2782176771Sraj for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2783176771Sraj 2784176771Sraj mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2785176771Sraj mtspr(SPR_MAS0, mas0); 2786187149Sraj __asm __volatile("isync"); 2787176771Sraj 2788176771Sraj mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2789176771Sraj mtspr(SPR_MAS2, mas2); 2790176771Sraj 2791187149Sraj __asm __volatile("isync; tlbre"); 2792176771Sraj 2793176771Sraj mas1 = mfspr(SPR_MAS1); 2794176771Sraj mas2 = mfspr(SPR_MAS2); 2795176771Sraj mas3 = mfspr(SPR_MAS3); 2796176771Sraj mas7 = mfspr(SPR_MAS7); 2797176771Sraj 2798176771Sraj idx = tlb0_tableidx(mas2, way); 2799176771Sraj tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2800176771Sraj } 2801176771Sraj} 2802176771Sraj 2803176771Sraj/**************************************************************************/ 2804176771Sraj/* TLB1 handling */ 2805176771Sraj/**************************************************************************/ 2806187149Sraj 2807176771Sraj/* 2808187149Sraj * TLB1 mapping notes: 2809187149Sraj * 2810187149Sraj * TLB1[0] CCSRBAR 2811187149Sraj * TLB1[1] Kernel text and data. 2812187149Sraj * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2813187149Sraj * windows, other devices mappings. 2814187149Sraj */ 2815187149Sraj 2816187149Sraj/* 2817176771Sraj * Write given entry to TLB1 hardware. 2818176771Sraj * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2819176771Sraj */ 2820176771Srajstatic void 2821176771Srajtlb1_write_entry(unsigned int idx) 2822176771Sraj{ 2823187151Sraj uint32_t mas0, mas7; 2824176771Sraj 2825176771Sraj //debugf("tlb1_write_entry: s\n"); 2826176771Sraj 2827176771Sraj /* Clear high order RPN bits */ 2828176771Sraj mas7 = 0; 2829176771Sraj 2830176771Sraj /* Select entry */ 2831176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2832176771Sraj //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2833176771Sraj 2834176771Sraj mtspr(SPR_MAS0, mas0); 2835187151Sraj __asm __volatile("isync"); 2836176771Sraj mtspr(SPR_MAS1, tlb1[idx].mas1); 2837187151Sraj __asm __volatile("isync"); 2838176771Sraj mtspr(SPR_MAS2, tlb1[idx].mas2); 2839187151Sraj __asm __volatile("isync"); 2840176771Sraj mtspr(SPR_MAS3, tlb1[idx].mas3); 2841187151Sraj __asm __volatile("isync"); 2842176771Sraj mtspr(SPR_MAS7, mas7); 2843187151Sraj __asm __volatile("isync; tlbwe; isync; msync"); 2844176771Sraj 2845201758Smbr //debugf("tlb1_write_entry: e\n"); 2846176771Sraj} 2847176771Sraj 2848176771Sraj/* 2849176771Sraj * Return the largest uint value log such that 2^log <= num. 2850176771Sraj */ 2851176771Srajstatic unsigned int 2852176771Srajilog2(unsigned int num) 2853176771Sraj{ 2854176771Sraj int lz; 2855176771Sraj 2856176771Sraj __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2857176771Sraj return (31 - lz); 2858176771Sraj} 2859176771Sraj 2860176771Sraj/* 2861176771Sraj * Convert TLB TSIZE value to mapped region size. 2862176771Sraj */ 2863176771Srajstatic vm_size_t 2864176771Srajtsize2size(unsigned int tsize) 2865176771Sraj{ 2866176771Sraj 2867176771Sraj /* 2868176771Sraj * size = 4^tsize KB 2869176771Sraj * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2870176771Sraj */ 2871176771Sraj 2872176771Sraj return ((1 << (2 * tsize)) * 1024); 2873176771Sraj} 2874176771Sraj 2875176771Sraj/* 2876176771Sraj * Convert region size (must be power of 4) to TLB TSIZE value. 2877176771Sraj */ 2878176771Srajstatic unsigned int 2879176771Srajsize2tsize(vm_size_t size) 2880176771Sraj{ 2881176771Sraj 2882176771Sraj return (ilog2(size) / 2 - 5); 2883176771Sraj} 2884176771Sraj 2885176771Sraj/* 2886187149Sraj * Register permanent kernel mapping in TLB1. 2887176771Sraj * 2888187149Sraj * Entries are created starting from index 0 (current free entry is 2889187149Sraj * kept in tlb1_idx) and are not supposed to be invalidated. 2890176771Sraj */ 2891187149Srajstatic int 2892187149Srajtlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2893187149Sraj uint32_t flags) 2894176771Sraj{ 2895187149Sraj uint32_t ts, tid; 2896176771Sraj int tsize; 2897187149Sraj 2898187149Sraj if (tlb1_idx >= TLB1_ENTRIES) { 2899187149Sraj printf("tlb1_set_entry: TLB1 full!\n"); 2900187149Sraj return (-1); 2901187149Sraj } 2902176771Sraj 2903176771Sraj /* Convert size to TSIZE */ 2904176771Sraj tsize = size2tsize(size); 2905176771Sraj 2906187149Sraj tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2907187149Sraj /* XXX TS is hard coded to 0 for now as we only use single address space */ 2908187149Sraj ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2909176771Sraj 2910187149Sraj /* XXX LOCK tlb1[] */ 2911176771Sraj 2912187149Sraj tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2913187149Sraj tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2914187149Sraj tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2915176771Sraj 2916187149Sraj /* Set supervisor RWX permission bits */ 2917187149Sraj tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2918176771Sraj 2919187149Sraj tlb1_write_entry(tlb1_idx++); 2920176771Sraj 2921187149Sraj /* XXX UNLOCK tlb1[] */ 2922176771Sraj 2923187149Sraj /* 2924187149Sraj * XXX in general TLB1 updates should be propagated between CPUs, 2925187149Sraj * since current design assumes to have the same TLB1 set-up on all 2926187149Sraj * cores. 2927187149Sraj */ 2928176771Sraj return (0); 2929176771Sraj} 2930176771Sraj 2931176771Srajstatic int 2932176771Srajtlb1_entry_size_cmp(const void *a, const void *b) 2933176771Sraj{ 2934176771Sraj const vm_size_t *sza; 2935176771Sraj const vm_size_t *szb; 2936176771Sraj 2937176771Sraj sza = a; 2938176771Sraj szb = b; 2939176771Sraj if (*sza > *szb) 2940176771Sraj return (-1); 2941176771Sraj else if (*sza < *szb) 2942176771Sraj return (1); 2943176771Sraj else 2944176771Sraj return (0); 2945176771Sraj} 2946176771Sraj 2947176771Sraj/* 2948187151Sraj * Map in contiguous RAM region into the TLB1 using maximum of 2949176771Sraj * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2950176771Sraj * 2951187151Sraj * If necessary round up last entry size and return total size 2952176771Sraj * used by all allocated entries. 2953176771Sraj */ 2954176771Srajvm_size_t 2955176771Srajtlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2956176771Sraj{ 2957176771Sraj vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2958176771Sraj vm_size_t mapped_size, sz, esz; 2959176771Sraj unsigned int log; 2960176771Sraj int i; 2961176771Sraj 2962187151Sraj CTR4(KTR_PMAP, "%s: region size = 0x%08x va = 0x%08x pa = 0x%08x", 2963187151Sraj __func__, size, va, pa); 2964176771Sraj 2965176771Sraj mapped_size = 0; 2966176771Sraj sz = size; 2967176771Sraj memset(entry_size, 0, sizeof(entry_size)); 2968176771Sraj 2969176771Sraj /* Calculate entry sizes. */ 2970176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2971176771Sraj 2972176771Sraj /* Largest region that is power of 4 and fits within size */ 2973187149Sraj log = ilog2(sz) / 2; 2974176771Sraj esz = 1 << (2 * log); 2975176771Sraj 2976176771Sraj /* If this is last entry cover remaining size. */ 2977176771Sraj if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2978176771Sraj while (esz < sz) 2979176771Sraj esz = esz << 2; 2980176771Sraj } 2981176771Sraj 2982176771Sraj entry_size[i] = esz; 2983176771Sraj mapped_size += esz; 2984176771Sraj if (esz < sz) 2985176771Sraj sz -= esz; 2986176771Sraj else 2987176771Sraj sz = 0; 2988176771Sraj } 2989176771Sraj 2990176771Sraj /* Sort entry sizes, required to get proper entry address alignment. */ 2991176771Sraj qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2992176771Sraj sizeof(vm_size_t), tlb1_entry_size_cmp); 2993176771Sraj 2994176771Sraj /* Load TLB1 entries. */ 2995176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2996176771Sraj esz = entry_size[i]; 2997176771Sraj if (!esz) 2998176771Sraj break; 2999187151Sraj 3000187151Sraj CTR5(KTR_PMAP, "%s: entry %d: sz = 0x%08x (va = 0x%08x " 3001187151Sraj "pa = 0x%08x)", __func__, tlb1_idx, esz, va, pa); 3002187151Sraj 3003176771Sraj tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 3004176771Sraj 3005176771Sraj va += esz; 3006176771Sraj pa += esz; 3007176771Sraj } 3008176771Sraj 3009187151Sraj CTR3(KTR_PMAP, "%s: mapped size 0x%08x (wasted space 0x%08x)", 3010187151Sraj __func__, mapped_size, mapped_size - size); 3011176771Sraj 3012176771Sraj return (mapped_size); 3013176771Sraj} 3014176771Sraj 3015176771Sraj/* 3016176771Sraj * TLB1 initialization routine, to be called after the very first 3017176771Sraj * assembler level setup done in locore.S. 3018176771Sraj */ 3019176771Srajvoid 3020176771Srajtlb1_init(vm_offset_t ccsrbar) 3021176771Sraj{ 3022176771Sraj uint32_t mas0; 3023176771Sraj 3024187151Sraj /* TLB1[1] is used to map the kernel. Save that entry. */ 3025176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 3026176771Sraj mtspr(SPR_MAS0, mas0); 3027176771Sraj __asm __volatile("isync; tlbre"); 3028176771Sraj 3029176771Sraj tlb1[1].mas1 = mfspr(SPR_MAS1); 3030176771Sraj tlb1[1].mas2 = mfspr(SPR_MAS2); 3031176771Sraj tlb1[1].mas3 = mfspr(SPR_MAS3); 3032176771Sraj 3033187149Sraj /* Map in CCSRBAR in TLB1[0] */ 3034187149Sraj tlb1_idx = 0; 3035187149Sraj tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3036187149Sraj /* 3037187149Sraj * Set the next available TLB1 entry index. Note TLB[1] is reserved 3038187149Sraj * for initial mapping of kernel text+data, which was set early in 3039187149Sraj * locore, we need to skip this [busy] entry. 3040187149Sraj */ 3041187149Sraj tlb1_idx = 2; 3042176771Sraj 3043176771Sraj /* Setup TLB miss defaults */ 3044176771Sraj set_mas4_defaults(); 3045176771Sraj} 3046176771Sraj 3047176771Sraj/* 3048176771Sraj * Setup MAS4 defaults. 3049176771Sraj * These values are loaded to MAS0-2 on a TLB miss. 3050176771Sraj */ 3051176771Srajstatic void 3052176771Srajset_mas4_defaults(void) 3053176771Sraj{ 3054187151Sraj uint32_t mas4; 3055176771Sraj 3056176771Sraj /* Defaults: TLB0, PID0, TSIZED=4K */ 3057176771Sraj mas4 = MAS4_TLBSELD0; 3058176771Sraj mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3059192532Sraj#ifdef SMP 3060192532Sraj mas4 |= MAS4_MD; 3061192532Sraj#endif 3062176771Sraj mtspr(SPR_MAS4, mas4); 3063187151Sraj __asm __volatile("isync"); 3064176771Sraj} 3065176771Sraj 3066176771Sraj/* 3067176771Sraj * Print out contents of the MAS registers for each TLB1 entry 3068176771Sraj */ 3069176771Srajvoid 3070176771Srajtlb1_print_tlbentries(void) 3071176771Sraj{ 3072187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 3073176771Sraj int i; 3074176771Sraj 3075176771Sraj debugf("TLB1 entries:\n"); 3076187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) { 3077176771Sraj 3078176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3079176771Sraj mtspr(SPR_MAS0, mas0); 3080176771Sraj 3081187149Sraj __asm __volatile("isync; tlbre"); 3082176771Sraj 3083176771Sraj mas1 = mfspr(SPR_MAS1); 3084176771Sraj mas2 = mfspr(SPR_MAS2); 3085176771Sraj mas3 = mfspr(SPR_MAS3); 3086176771Sraj mas7 = mfspr(SPR_MAS7); 3087176771Sraj 3088176771Sraj tlb_print_entry(i, mas1, mas2, mas3, mas7); 3089176771Sraj } 3090176771Sraj} 3091176771Sraj 3092176771Sraj/* 3093176771Sraj * Print out contents of the in-ram tlb1 table. 3094176771Sraj */ 3095176771Srajvoid 3096176771Srajtlb1_print_entries(void) 3097176771Sraj{ 3098176771Sraj int i; 3099176771Sraj 3100176771Sraj debugf("tlb1[] table entries:\n"); 3101187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) 3102176771Sraj tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3103176771Sraj} 3104176771Sraj 3105176771Sraj/* 3106176771Sraj * Return 0 if the physical IO range is encompassed by one of the 3107176771Sraj * the TLB1 entries, otherwise return related error code. 3108176771Sraj */ 3109176771Srajstatic int 3110176771Srajtlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3111176771Sraj{ 3112187151Sraj uint32_t prot; 3113176771Sraj vm_paddr_t pa_start; 3114176771Sraj vm_paddr_t pa_end; 3115176771Sraj unsigned int entry_tsize; 3116176771Sraj vm_size_t entry_size; 3117176771Sraj 3118176771Sraj *va = (vm_offset_t)NULL; 3119176771Sraj 3120176771Sraj /* Skip invalid entries */ 3121176771Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 3122176771Sraj return (EINVAL); 3123176771Sraj 3124176771Sraj /* 3125176771Sraj * The entry must be cache-inhibited, guarded, and r/w 3126176771Sraj * so it can function as an i/o page 3127176771Sraj */ 3128176771Sraj prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3129176771Sraj if (prot != (MAS2_I | MAS2_G)) 3130176771Sraj return (EPERM); 3131176771Sraj 3132176771Sraj prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3133176771Sraj if (prot != (MAS3_SR | MAS3_SW)) 3134176771Sraj return (EPERM); 3135176771Sraj 3136176771Sraj /* The address should be within the entry range. */ 3137176771Sraj entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3138176771Sraj KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3139176771Sraj 3140176771Sraj entry_size = tsize2size(entry_tsize); 3141176771Sraj pa_start = tlb1[i].mas3 & MAS3_RPN; 3142176771Sraj pa_end = pa_start + entry_size - 1; 3143176771Sraj 3144176771Sraj if ((pa < pa_start) || ((pa + size) > pa_end)) 3145176771Sraj return (ERANGE); 3146176771Sraj 3147176771Sraj /* Return virtual address of this mapping. */ 3148187149Sraj *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3149176771Sraj return (0); 3150176771Sraj} 3151