pmap.c revision 208574
1176771Sraj/*- 2192532Sraj * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3176771Sraj * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4176771Sraj * All rights reserved. 5176771Sraj * 6176771Sraj * Redistribution and use in source and binary forms, with or without 7176771Sraj * modification, are permitted provided that the following conditions 8176771Sraj * are met: 9176771Sraj * 1. Redistributions of source code must retain the above copyright 10176771Sraj * notice, this list of conditions and the following disclaimer. 11176771Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176771Sraj * notice, this list of conditions and the following disclaimer in the 13176771Sraj * documentation and/or other materials provided with the distribution. 14176771Sraj * 15176771Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176771Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176771Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176771Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176771Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176771Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176771Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176771Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176771Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176771Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176771Sraj * 26176771Sraj * Some hw specific parts of this pmap were derived or influenced 27176771Sraj * by NetBSD's ibm4xx pmap module. More generic code is shared with 28176771Sraj * a few other pmap modules from the FreeBSD tree. 29176771Sraj */ 30176771Sraj 31176771Sraj /* 32176771Sraj * VM layout notes: 33176771Sraj * 34176771Sraj * Kernel and user threads run within one common virtual address space 35176771Sraj * defined by AS=0. 36176771Sraj * 37176771Sraj * Virtual address space layout: 38176771Sraj * ----------------------------- 39187151Sraj * 0x0000_0000 - 0xafff_ffff : user process 40187151Sraj * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41187151Sraj * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42190701Smarcel * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43187151Sraj * 0xc100_0000 - 0xfeef_ffff : KVA 44187151Sraj * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45187151Sraj * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46187151Sraj * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47187151Sraj * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48187151Sraj * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49176771Sraj */ 50176771Sraj 51176771Sraj#include <sys/cdefs.h> 52176771Sraj__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 208574 2010-05-26 18:00:44Z alc $"); 53176771Sraj 54176771Sraj#include <sys/types.h> 55176771Sraj#include <sys/param.h> 56176771Sraj#include <sys/malloc.h> 57187149Sraj#include <sys/ktr.h> 58176771Sraj#include <sys/proc.h> 59176771Sraj#include <sys/user.h> 60176771Sraj#include <sys/queue.h> 61176771Sraj#include <sys/systm.h> 62176771Sraj#include <sys/kernel.h> 63176771Sraj#include <sys/msgbuf.h> 64176771Sraj#include <sys/lock.h> 65176771Sraj#include <sys/mutex.h> 66192532Sraj#include <sys/smp.h> 67176771Sraj#include <sys/vmmeter.h> 68176771Sraj 69176771Sraj#include <vm/vm.h> 70176771Sraj#include <vm/vm_page.h> 71176771Sraj#include <vm/vm_kern.h> 72176771Sraj#include <vm/vm_pageout.h> 73176771Sraj#include <vm/vm_extern.h> 74176771Sraj#include <vm/vm_object.h> 75176771Sraj#include <vm/vm_param.h> 76176771Sraj#include <vm/vm_map.h> 77176771Sraj#include <vm/vm_pager.h> 78176771Sraj#include <vm/uma.h> 79176771Sraj 80190701Smarcel#include <machine/bootinfo.h> 81176771Sraj#include <machine/cpu.h> 82176771Sraj#include <machine/pcb.h> 83192067Snwhitehorn#include <machine/platform.h> 84176771Sraj 85176771Sraj#include <machine/tlb.h> 86176771Sraj#include <machine/spr.h> 87176771Sraj#include <machine/vmparam.h> 88176771Sraj#include <machine/md_var.h> 89176771Sraj#include <machine/mmuvar.h> 90176771Sraj#include <machine/pmap.h> 91176771Sraj#include <machine/pte.h> 92176771Sraj 93176771Sraj#include "mmu_if.h" 94176771Sraj 95176771Sraj#define DEBUG 96176771Sraj#undef DEBUG 97176771Sraj 98176771Sraj#ifdef DEBUG 99176771Sraj#define debugf(fmt, args...) printf(fmt, ##args) 100176771Sraj#else 101176771Sraj#define debugf(fmt, args...) 102176771Sraj#endif 103176771Sraj 104176771Sraj#define TODO panic("%s: not implemented", __func__); 105176771Sraj 106176771Sraj#include "opt_sched.h" 107176771Sraj#ifndef SCHED_4BSD 108176771Sraj#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 109176771Sraj#endif 110176771Srajextern struct mtx sched_lock; 111176771Sraj 112190701Smarcelextern int dumpsys_minidump; 113190701Smarcel 114190701Smarcelextern unsigned char _etext[]; 115190701Smarcelextern unsigned char _end[]; 116190701Smarcel 117176771Sraj/* Kernel physical load address. */ 118176771Srajextern uint32_t kernload; 119190701Smarcelvm_offset_t kernstart; 120190701Smarcelvm_size_t kernsize; 121176771Sraj 122190701Smarcel/* Message buffer and tables. */ 123190701Smarcelstatic vm_offset_t data_start; 124190701Smarcelstatic vm_size_t data_end; 125190701Smarcel 126192067Snwhitehorn/* Phys/avail memory regions. */ 127192067Snwhitehornstatic struct mem_region *availmem_regions; 128192067Snwhitehornstatic int availmem_regions_sz; 129192067Snwhitehornstatic struct mem_region *physmem_regions; 130192067Snwhitehornstatic int physmem_regions_sz; 131176771Sraj 132176771Sraj/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 133176771Srajstatic vm_offset_t zero_page_va; 134176771Srajstatic struct mtx zero_page_mutex; 135176771Sraj 136187149Srajstatic struct mtx tlbivax_mutex; 137187149Sraj 138176771Sraj/* 139176771Sraj * Reserved KVA space for mmu_booke_zero_page_idle. This is used 140176771Sraj * by idle thred only, no lock required. 141176771Sraj */ 142176771Srajstatic vm_offset_t zero_page_idle_va; 143176771Sraj 144176771Sraj/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 145176771Srajstatic vm_offset_t copy_page_src_va; 146176771Srajstatic vm_offset_t copy_page_dst_va; 147176771Srajstatic struct mtx copy_page_mutex; 148176771Sraj 149176771Sraj/**************************************************************************/ 150176771Sraj/* PMAP */ 151176771Sraj/**************************************************************************/ 152176771Sraj 153176771Srajstatic void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 154176771Sraj vm_prot_t, boolean_t); 155176771Sraj 156176771Srajunsigned int kptbl_min; /* Index of the first kernel ptbl. */ 157176771Srajunsigned int kernel_ptbls; /* Number of KVA ptbls. */ 158176771Sraj 159176771Sraj/* 160176771Sraj * If user pmap is processed with mmu_booke_remove and the resident count 161176771Sraj * drops to 0, there are no more pages to remove, so we need not continue. 162176771Sraj */ 163176771Sraj#define PMAP_REMOVE_DONE(pmap) \ 164176771Sraj ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 165176771Sraj 166187149Srajextern void tlb_lock(uint32_t *); 167187149Srajextern void tlb_unlock(uint32_t *); 168187149Srajextern void tid_flush(tlbtid_t); 169176771Sraj 170176771Sraj/**************************************************************************/ 171176771Sraj/* TLB and TID handling */ 172176771Sraj/**************************************************************************/ 173176771Sraj 174176771Sraj/* Translation ID busy table */ 175187149Srajstatic volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 176176771Sraj 177176771Sraj/* 178187149Sraj * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 179187149Sraj * core revisions and should be read from h/w registers during early config. 180176771Sraj */ 181187149Srajuint32_t tlb0_entries; 182187149Srajuint32_t tlb0_ways; 183187149Srajuint32_t tlb0_entries_per_way; 184176771Sraj 185187149Sraj#define TLB0_ENTRIES (tlb0_entries) 186187149Sraj#define TLB0_WAYS (tlb0_ways) 187187149Sraj#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 188176771Sraj 189187149Sraj#define TLB1_ENTRIES 16 190176771Sraj 191176771Sraj/* In-ram copy of the TLB1 */ 192187149Srajstatic tlb_entry_t tlb1[TLB1_ENTRIES]; 193176771Sraj 194176771Sraj/* Next free entry in the TLB1 */ 195176771Srajstatic unsigned int tlb1_idx; 196176771Sraj 197176771Srajstatic tlbtid_t tid_alloc(struct pmap *); 198176771Sraj 199187149Srajstatic void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 200176771Sraj 201187149Srajstatic int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 202176771Srajstatic void tlb1_write_entry(unsigned int); 203176771Srajstatic int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 204176771Srajstatic vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 205176771Sraj 206176771Srajstatic vm_size_t tsize2size(unsigned int); 207176771Srajstatic unsigned int size2tsize(vm_size_t); 208176771Srajstatic unsigned int ilog2(unsigned int); 209176771Sraj 210176771Srajstatic void set_mas4_defaults(void); 211176771Sraj 212187149Srajstatic inline void tlb0_flush_entry(vm_offset_t); 213176771Srajstatic inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 214176771Sraj 215176771Sraj/**************************************************************************/ 216176771Sraj/* Page table management */ 217176771Sraj/**************************************************************************/ 218176771Sraj 219176771Sraj/* Data for the pv entry allocation mechanism */ 220176771Srajstatic uma_zone_t pvzone; 221176771Srajstatic struct vm_object pvzone_obj; 222176771Srajstatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 223176771Sraj 224176771Sraj#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 225176771Sraj 226176771Sraj#ifndef PMAP_SHPGPERPROC 227176771Sraj#define PMAP_SHPGPERPROC 200 228176771Sraj#endif 229176771Sraj 230176771Srajstatic void ptbl_init(void); 231176771Srajstatic struct ptbl_buf *ptbl_buf_alloc(void); 232176771Srajstatic void ptbl_buf_free(struct ptbl_buf *); 233176771Srajstatic void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 234176771Sraj 235187149Srajstatic pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 236176771Srajstatic void ptbl_free(mmu_t, pmap_t, unsigned int); 237176771Srajstatic void ptbl_hold(mmu_t, pmap_t, unsigned int); 238176771Srajstatic int ptbl_unhold(mmu_t, pmap_t, unsigned int); 239176771Sraj 240176771Srajstatic vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 241176771Srajstatic pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 242187149Srajstatic void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 243187149Srajstatic int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 244176771Sraj 245187149Srajstatic pv_entry_t pv_alloc(void); 246176771Srajstatic void pv_free(pv_entry_t); 247176771Srajstatic void pv_insert(pmap_t, vm_offset_t, vm_page_t); 248176771Srajstatic void pv_remove(pmap_t, vm_offset_t, vm_page_t); 249176771Sraj 250176771Sraj/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 251176771Sraj#define PTBL_BUFS (128 * 16) 252176771Sraj 253176771Srajstruct ptbl_buf { 254176771Sraj TAILQ_ENTRY(ptbl_buf) link; /* list link */ 255176771Sraj vm_offset_t kva; /* va of mapping */ 256176771Sraj}; 257176771Sraj 258176771Sraj/* ptbl free list and a lock used for access synchronization. */ 259176771Srajstatic TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 260176771Srajstatic struct mtx ptbl_buf_freelist_lock; 261176771Sraj 262176771Sraj/* Base address of kva space allocated fot ptbl bufs. */ 263176771Srajstatic vm_offset_t ptbl_buf_pool_vabase; 264176771Sraj 265176771Sraj/* Pointer to ptbl_buf structures. */ 266176771Srajstatic struct ptbl_buf *ptbl_bufs; 267176771Sraj 268192532Srajvoid pmap_bootstrap_ap(volatile uint32_t *); 269192532Sraj 270176771Sraj/* 271176771Sraj * Kernel MMU interface 272176771Sraj */ 273176771Srajstatic void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 274176771Srajstatic void mmu_booke_clear_modify(mmu_t, vm_page_t); 275176771Srajstatic void mmu_booke_clear_reference(mmu_t, vm_page_t); 276194101Srajstatic void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 277194101Sraj vm_size_t, vm_offset_t); 278176771Srajstatic void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 279176771Srajstatic void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 280176771Sraj vm_prot_t, boolean_t); 281176771Srajstatic void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 282176771Sraj vm_page_t, vm_prot_t); 283176771Srajstatic void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 284176771Sraj vm_prot_t); 285176771Srajstatic vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 286176771Srajstatic vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 287176771Sraj vm_prot_t); 288176771Srajstatic void mmu_booke_init(mmu_t); 289176771Srajstatic boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 290176771Srajstatic boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 291207155Salcstatic boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 292176771Srajstatic boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 293176771Srajstatic vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 294176771Sraj int); 295208504Salcstatic int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 296208504Salc vm_paddr_t *); 297176771Srajstatic void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 298176771Sraj vm_object_t, vm_pindex_t, vm_size_t); 299176771Srajstatic boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 300176771Srajstatic void mmu_booke_page_init(mmu_t, vm_page_t); 301176771Srajstatic int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 302176771Srajstatic void mmu_booke_pinit(mmu_t, pmap_t); 303176771Srajstatic void mmu_booke_pinit0(mmu_t, pmap_t); 304176771Srajstatic void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 305176771Sraj vm_prot_t); 306176771Srajstatic void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 307176771Srajstatic void mmu_booke_qremove(mmu_t, vm_offset_t, int); 308176771Srajstatic void mmu_booke_release(mmu_t, pmap_t); 309176771Srajstatic void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 310176771Srajstatic void mmu_booke_remove_all(mmu_t, vm_page_t); 311176771Srajstatic void mmu_booke_remove_write(mmu_t, vm_page_t); 312176771Srajstatic void mmu_booke_zero_page(mmu_t, vm_page_t); 313176771Srajstatic void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 314176771Srajstatic void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 315176771Srajstatic void mmu_booke_activate(mmu_t, struct thread *); 316176771Srajstatic void mmu_booke_deactivate(mmu_t, struct thread *); 317176771Srajstatic void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 318176771Srajstatic void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 319176771Srajstatic void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 320176771Srajstatic vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 321176771Srajstatic void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 322176771Srajstatic void mmu_booke_kremove(mmu_t, vm_offset_t); 323176771Srajstatic boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 324198341Smarcelstatic void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 325198341Smarcel vm_size_t); 326190701Smarcelstatic vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 327190701Smarcel vm_size_t, vm_size_t *); 328190701Smarcelstatic void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 329190701Smarcel vm_size_t, vm_offset_t); 330190701Smarcelstatic struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 331176771Sraj 332176771Srajstatic mmu_method_t mmu_booke_methods[] = { 333176771Sraj /* pmap dispatcher interface */ 334176771Sraj MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 335176771Sraj MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 336176771Sraj MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 337176771Sraj MMUMETHOD(mmu_copy, mmu_booke_copy), 338176771Sraj MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 339176771Sraj MMUMETHOD(mmu_enter, mmu_booke_enter), 340176771Sraj MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 341176771Sraj MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 342176771Sraj MMUMETHOD(mmu_extract, mmu_booke_extract), 343176771Sraj MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 344176771Sraj MMUMETHOD(mmu_init, mmu_booke_init), 345176771Sraj MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 346176771Sraj MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 347207155Salc MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 348176771Sraj MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 349176771Sraj MMUMETHOD(mmu_map, mmu_booke_map), 350176771Sraj MMUMETHOD(mmu_mincore, mmu_booke_mincore), 351176771Sraj MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 352176771Sraj MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 353176771Sraj MMUMETHOD(mmu_page_init, mmu_booke_page_init), 354176771Sraj MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 355176771Sraj MMUMETHOD(mmu_pinit, mmu_booke_pinit), 356176771Sraj MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 357176771Sraj MMUMETHOD(mmu_protect, mmu_booke_protect), 358176771Sraj MMUMETHOD(mmu_qenter, mmu_booke_qenter), 359176771Sraj MMUMETHOD(mmu_qremove, mmu_booke_qremove), 360176771Sraj MMUMETHOD(mmu_release, mmu_booke_release), 361176771Sraj MMUMETHOD(mmu_remove, mmu_booke_remove), 362176771Sraj MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 363176771Sraj MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 364198341Smarcel MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 365176771Sraj MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 366176771Sraj MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 367176771Sraj MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 368176771Sraj MMUMETHOD(mmu_activate, mmu_booke_activate), 369176771Sraj MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 370176771Sraj 371176771Sraj /* Internal interfaces */ 372176771Sraj MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 373176771Sraj MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 374176771Sraj MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 375176771Sraj MMUMETHOD(mmu_kenter, mmu_booke_kenter), 376176771Sraj MMUMETHOD(mmu_kextract, mmu_booke_kextract), 377176771Sraj/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 378176771Sraj MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 379176771Sraj 380190701Smarcel /* dumpsys() support */ 381190701Smarcel MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 382190701Smarcel MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 383190701Smarcel MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 384190701Smarcel 385176771Sraj { 0, 0 } 386176771Sraj}; 387176771Sraj 388176771Srajstatic mmu_def_t booke_mmu = { 389176771Sraj MMU_TYPE_BOOKE, 390176771Sraj mmu_booke_methods, 391176771Sraj 0 392176771Sraj}; 393176771SrajMMU_DEF(booke_mmu); 394176771Sraj 395192532Srajstatic inline void 396192532Srajtlb_miss_lock(void) 397192532Sraj{ 398192532Sraj#ifdef SMP 399192532Sraj struct pcpu *pc; 400192532Sraj 401192532Sraj if (!smp_started) 402192532Sraj return; 403192532Sraj 404192532Sraj SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 405192532Sraj if (pc != pcpup) { 406192532Sraj 407192532Sraj CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 408192532Sraj "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 409192532Sraj 410192532Sraj KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 411192532Sraj ("tlb_miss_lock: tried to lock self")); 412192532Sraj 413192532Sraj tlb_lock(pc->pc_booke_tlb_lock); 414192532Sraj 415192532Sraj CTR1(KTR_PMAP, "%s: locked", __func__); 416192532Sraj } 417192532Sraj } 418192532Sraj#endif 419192532Sraj} 420192532Sraj 421192532Srajstatic inline void 422192532Srajtlb_miss_unlock(void) 423192532Sraj{ 424192532Sraj#ifdef SMP 425192532Sraj struct pcpu *pc; 426192532Sraj 427192532Sraj if (!smp_started) 428192532Sraj return; 429192532Sraj 430192532Sraj SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 431192532Sraj if (pc != pcpup) { 432192532Sraj CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 433192532Sraj __func__, pc->pc_cpuid); 434192532Sraj 435192532Sraj tlb_unlock(pc->pc_booke_tlb_lock); 436192532Sraj 437192532Sraj CTR1(KTR_PMAP, "%s: unlocked", __func__); 438192532Sraj } 439192532Sraj } 440192532Sraj#endif 441192532Sraj} 442192532Sraj 443176771Sraj/* Return number of entries in TLB0. */ 444176771Srajstatic __inline void 445176771Srajtlb0_get_tlbconf(void) 446176771Sraj{ 447176771Sraj uint32_t tlb0_cfg; 448176771Sraj 449176771Sraj tlb0_cfg = mfspr(SPR_TLB0CFG); 450187149Sraj tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 451187149Sraj tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 452187149Sraj tlb0_entries_per_way = tlb0_entries / tlb0_ways; 453176771Sraj} 454176771Sraj 455176771Sraj/* Initialize pool of kva ptbl buffers. */ 456176771Srajstatic void 457176771Srajptbl_init(void) 458176771Sraj{ 459176771Sraj int i; 460176771Sraj 461187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 462187151Sraj (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 463187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 464187151Sraj __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 465176771Sraj 466176771Sraj mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 467176771Sraj TAILQ_INIT(&ptbl_buf_freelist); 468176771Sraj 469176771Sraj for (i = 0; i < PTBL_BUFS; i++) { 470176771Sraj ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 471176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 472176771Sraj } 473176771Sraj} 474176771Sraj 475182362Sraj/* Get a ptbl_buf from the freelist. */ 476176771Srajstatic struct ptbl_buf * 477176771Srajptbl_buf_alloc(void) 478176771Sraj{ 479176771Sraj struct ptbl_buf *buf; 480176771Sraj 481176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 482176771Sraj buf = TAILQ_FIRST(&ptbl_buf_freelist); 483176771Sraj if (buf != NULL) 484176771Sraj TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 485176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 486176771Sraj 487187151Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 488187151Sraj 489176771Sraj return (buf); 490176771Sraj} 491176771Sraj 492176771Sraj/* Return ptbl buff to free pool. */ 493176771Srajstatic void 494176771Srajptbl_buf_free(struct ptbl_buf *buf) 495176771Sraj{ 496176771Sraj 497187149Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 498176771Sraj 499176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 500176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 501176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 502176771Sraj} 503176771Sraj 504176771Sraj/* 505187149Sraj * Search the list of allocated ptbl bufs and find on list of allocated ptbls 506176771Sraj */ 507176771Srajstatic void 508176771Srajptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 509176771Sraj{ 510176771Sraj struct ptbl_buf *pbuf; 511176771Sraj 512187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 513176771Sraj 514187149Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 515187149Sraj 516187149Sraj TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 517176771Sraj if (pbuf->kva == (vm_offset_t)ptbl) { 518176771Sraj /* Remove from pmap ptbl buf list. */ 519187149Sraj TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 520176771Sraj 521187149Sraj /* Free corresponding ptbl buf. */ 522176771Sraj ptbl_buf_free(pbuf); 523176771Sraj break; 524176771Sraj } 525176771Sraj} 526176771Sraj 527176771Sraj/* Allocate page table. */ 528187149Srajstatic pte_t * 529176771Srajptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 530176771Sraj{ 531176771Sraj vm_page_t mtbl[PTBL_PAGES]; 532176771Sraj vm_page_t m; 533176771Sraj struct ptbl_buf *pbuf; 534176771Sraj unsigned int pidx; 535187149Sraj pte_t *ptbl; 536176771Sraj int i; 537176771Sraj 538187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 539187149Sraj (pmap == kernel_pmap), pdir_idx); 540176771Sraj 541176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 542176771Sraj ("ptbl_alloc: invalid pdir_idx")); 543176771Sraj KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 544176771Sraj ("pte_alloc: valid ptbl entry exists!")); 545176771Sraj 546176771Sraj pbuf = ptbl_buf_alloc(); 547176771Sraj if (pbuf == NULL) 548176771Sraj panic("pte_alloc: couldn't alloc kernel virtual memory"); 549187149Sraj 550187149Sraj ptbl = (pte_t *)pbuf->kva; 551176771Sraj 552187149Sraj CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 553187149Sraj 554176771Sraj /* Allocate ptbl pages, this will sleep! */ 555176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 556176771Sraj pidx = (PTBL_PAGES * pdir_idx) + i; 557187149Sraj while ((m = vm_page_alloc(NULL, pidx, 558187149Sraj VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 559187149Sraj 560176771Sraj PMAP_UNLOCK(pmap); 561176771Sraj vm_page_unlock_queues(); 562176771Sraj VM_WAIT; 563176771Sraj vm_page_lock_queues(); 564176771Sraj PMAP_LOCK(pmap); 565176771Sraj } 566176771Sraj mtbl[i] = m; 567176771Sraj } 568176771Sraj 569187149Sraj /* Map allocated pages into kernel_pmap. */ 570187149Sraj mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 571176771Sraj 572176771Sraj /* Zero whole ptbl. */ 573187149Sraj bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 574176771Sraj 575176771Sraj /* Add pbuf to the pmap ptbl bufs list. */ 576187149Sraj TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 577176771Sraj 578187149Sraj return (ptbl); 579176771Sraj} 580176771Sraj 581176771Sraj/* Free ptbl pages and invalidate pdir entry. */ 582176771Srajstatic void 583176771Srajptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 584176771Sraj{ 585176771Sraj pte_t *ptbl; 586176771Sraj vm_paddr_t pa; 587176771Sraj vm_offset_t va; 588176771Sraj vm_page_t m; 589176771Sraj int i; 590176771Sraj 591187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 592187149Sraj (pmap == kernel_pmap), pdir_idx); 593176771Sraj 594176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 595176771Sraj ("ptbl_free: invalid pdir_idx")); 596176771Sraj 597176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 598176771Sraj 599187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 600187149Sraj 601176771Sraj KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 602176771Sraj 603187149Sraj /* 604187149Sraj * Invalidate the pdir entry as soon as possible, so that other CPUs 605187149Sraj * don't attempt to look up the page tables we are releasing. 606187149Sraj */ 607187149Sraj mtx_lock_spin(&tlbivax_mutex); 608192532Sraj tlb_miss_lock(); 609187149Sraj 610187149Sraj pmap->pm_pdir[pdir_idx] = NULL; 611187149Sraj 612192532Sraj tlb_miss_unlock(); 613187149Sraj mtx_unlock_spin(&tlbivax_mutex); 614187149Sraj 615176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 616176771Sraj va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 617176771Sraj pa = pte_vatopa(mmu, kernel_pmap, va); 618176771Sraj m = PHYS_TO_VM_PAGE(pa); 619176771Sraj vm_page_free_zero(m); 620176771Sraj atomic_subtract_int(&cnt.v_wire_count, 1); 621176771Sraj mmu_booke_kremove(mmu, va); 622176771Sraj } 623176771Sraj 624176771Sraj ptbl_free_pmap_ptbl(pmap, ptbl); 625176771Sraj} 626176771Sraj 627176771Sraj/* 628176771Sraj * Decrement ptbl pages hold count and attempt to free ptbl pages. 629176771Sraj * Called when removing pte entry from ptbl. 630176771Sraj * 631176771Sraj * Return 1 if ptbl pages were freed. 632176771Sraj */ 633176771Srajstatic int 634176771Srajptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 635176771Sraj{ 636176771Sraj pte_t *ptbl; 637176771Sraj vm_paddr_t pa; 638176771Sraj vm_page_t m; 639176771Sraj int i; 640176771Sraj 641187151Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 642187151Sraj (pmap == kernel_pmap), pdir_idx); 643176771Sraj 644176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 645176771Sraj ("ptbl_unhold: invalid pdir_idx")); 646176771Sraj KASSERT((pmap != kernel_pmap), 647176771Sraj ("ptbl_unhold: unholding kernel ptbl!")); 648176771Sraj 649176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 650176771Sraj 651176771Sraj //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 652176771Sraj KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 653176771Sraj ("ptbl_unhold: non kva ptbl")); 654176771Sraj 655176771Sraj /* decrement hold count */ 656176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 657187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 658187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 659176771Sraj m = PHYS_TO_VM_PAGE(pa); 660176771Sraj m->wire_count--; 661176771Sraj } 662176771Sraj 663176771Sraj /* 664176771Sraj * Free ptbl pages if there are no pte etries in this ptbl. 665187151Sraj * wire_count has the same value for all ptbl pages, so check the last 666187151Sraj * page. 667176771Sraj */ 668176771Sraj if (m->wire_count == 0) { 669176771Sraj ptbl_free(mmu, pmap, pdir_idx); 670176771Sraj 671176771Sraj //debugf("ptbl_unhold: e (freed ptbl)\n"); 672176771Sraj return (1); 673176771Sraj } 674176771Sraj 675176771Sraj return (0); 676176771Sraj} 677176771Sraj 678176771Sraj/* 679187151Sraj * Increment hold count for ptbl pages. This routine is used when a new pte 680187151Sraj * entry is being inserted into the ptbl. 681176771Sraj */ 682176771Srajstatic void 683176771Srajptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 684176771Sraj{ 685176771Sraj vm_paddr_t pa; 686176771Sraj pte_t *ptbl; 687176771Sraj vm_page_t m; 688176771Sraj int i; 689176771Sraj 690187151Sraj CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 691187151Sraj pdir_idx); 692176771Sraj 693176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 694176771Sraj ("ptbl_hold: invalid pdir_idx")); 695176771Sraj KASSERT((pmap != kernel_pmap), 696176771Sraj ("ptbl_hold: holding kernel ptbl!")); 697176771Sraj 698176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 699176771Sraj 700176771Sraj KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 701176771Sraj 702176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 703187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 704187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 705176771Sraj m = PHYS_TO_VM_PAGE(pa); 706176771Sraj m->wire_count++; 707176771Sraj } 708176771Sraj} 709176771Sraj 710176771Sraj/* Allocate pv_entry structure. */ 711176771Srajpv_entry_t 712176771Srajpv_alloc(void) 713176771Sraj{ 714176771Sraj pv_entry_t pv; 715176771Sraj 716176771Sraj pv_entry_count++; 717194123Salc if (pv_entry_count > pv_entry_high_water) 718194123Salc pagedaemon_wakeup(); 719176771Sraj pv = uma_zalloc(pvzone, M_NOWAIT); 720176771Sraj 721176771Sraj return (pv); 722176771Sraj} 723176771Sraj 724176771Sraj/* Free pv_entry structure. */ 725176771Srajstatic __inline void 726176771Srajpv_free(pv_entry_t pve) 727176771Sraj{ 728176771Sraj 729176771Sraj pv_entry_count--; 730176771Sraj uma_zfree(pvzone, pve); 731176771Sraj} 732176771Sraj 733176771Sraj 734176771Sraj/* Allocate and initialize pv_entry structure. */ 735176771Srajstatic void 736176771Srajpv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 737176771Sraj{ 738176771Sraj pv_entry_t pve; 739176771Sraj 740176771Sraj //int su = (pmap == kernel_pmap); 741176771Sraj //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 742176771Sraj // (u_int32_t)pmap, va, (u_int32_t)m); 743176771Sraj 744176771Sraj pve = pv_alloc(); 745176771Sraj if (pve == NULL) 746176771Sraj panic("pv_insert: no pv entries!"); 747176771Sraj 748176771Sraj pve->pv_pmap = pmap; 749176771Sraj pve->pv_va = va; 750176771Sraj 751176771Sraj /* add to pv_list */ 752176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 753176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 754176771Sraj 755176771Sraj TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 756176771Sraj 757176771Sraj //debugf("pv_insert: e\n"); 758176771Sraj} 759176771Sraj 760176771Sraj/* Destroy pv entry. */ 761176771Srajstatic void 762176771Srajpv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 763176771Sraj{ 764176771Sraj pv_entry_t pve; 765176771Sraj 766176771Sraj //int su = (pmap == kernel_pmap); 767176771Sraj //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 768176771Sraj 769176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 770176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 771176771Sraj 772176771Sraj /* find pv entry */ 773176771Sraj TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 774176771Sraj if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 775176771Sraj /* remove from pv_list */ 776176771Sraj TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 777176771Sraj if (TAILQ_EMPTY(&m->md.pv_list)) 778176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 779176771Sraj 780176771Sraj /* free pv entry struct */ 781176771Sraj pv_free(pve); 782176771Sraj break; 783176771Sraj } 784176771Sraj } 785176771Sraj 786176771Sraj //debugf("pv_remove: e\n"); 787176771Sraj} 788176771Sraj 789176771Sraj/* 790176771Sraj * Clean pte entry, try to free page table page if requested. 791176771Sraj * 792176771Sraj * Return 1 if ptbl pages were freed, otherwise return 0. 793176771Sraj */ 794176771Srajstatic int 795187151Srajpte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 796176771Sraj{ 797176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 798176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 799176771Sraj vm_page_t m; 800176771Sraj pte_t *ptbl; 801176771Sraj pte_t *pte; 802176771Sraj 803176771Sraj //int su = (pmap == kernel_pmap); 804176771Sraj //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 805176771Sraj // su, (u_int32_t)pmap, va, flags); 806176771Sraj 807176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 808176771Sraj KASSERT(ptbl, ("pte_remove: null ptbl")); 809176771Sraj 810176771Sraj pte = &ptbl[ptbl_idx]; 811176771Sraj 812176771Sraj if (pte == NULL || !PTE_ISVALID(pte)) 813176771Sraj return (0); 814176771Sraj 815176771Sraj if (PTE_ISWIRED(pte)) 816176771Sraj pmap->pm_stats.wired_count--; 817176771Sraj 818191445Smarcel /* Handle managed entry. */ 819191445Smarcel if (PTE_ISMANAGED(pte)) { 820191445Smarcel /* Get vm_page_t for mapped pte. */ 821191445Smarcel m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 822176771Sraj 823191445Smarcel if (PTE_ISMODIFIED(pte)) 824191445Smarcel vm_page_dirty(m); 825176771Sraj 826191445Smarcel if (PTE_ISREFERENCED(pte)) 827191445Smarcel vm_page_flag_set(m, PG_REFERENCED); 828176771Sraj 829191445Smarcel pv_remove(pmap, va, m); 830176771Sraj } 831176771Sraj 832187149Sraj mtx_lock_spin(&tlbivax_mutex); 833192532Sraj tlb_miss_lock(); 834187149Sraj 835187149Sraj tlb0_flush_entry(va); 836176771Sraj pte->flags = 0; 837176771Sraj pte->rpn = 0; 838187149Sraj 839192532Sraj tlb_miss_unlock(); 840187149Sraj mtx_unlock_spin(&tlbivax_mutex); 841187149Sraj 842176771Sraj pmap->pm_stats.resident_count--; 843176771Sraj 844176771Sraj if (flags & PTBL_UNHOLD) { 845176771Sraj //debugf("pte_remove: e (unhold)\n"); 846176771Sraj return (ptbl_unhold(mmu, pmap, pdir_idx)); 847176771Sraj } 848176771Sraj 849176771Sraj //debugf("pte_remove: e\n"); 850176771Sraj return (0); 851176771Sraj} 852176771Sraj 853176771Sraj/* 854176771Sraj * Insert PTE for a given page and virtual address. 855176771Sraj */ 856187149Srajstatic void 857187149Srajpte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 858176771Sraj{ 859176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 860176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 861187149Sraj pte_t *ptbl, *pte; 862176771Sraj 863187149Sraj CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 864187149Sraj pmap == kernel_pmap, pmap, va); 865176771Sraj 866176771Sraj /* Get the page table pointer. */ 867176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 868176771Sraj 869187149Sraj if (ptbl == NULL) { 870187149Sraj /* Allocate page table pages. */ 871187149Sraj ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 872187149Sraj } else { 873176771Sraj /* 874176771Sraj * Check if there is valid mapping for requested 875176771Sraj * va, if there is, remove it. 876176771Sraj */ 877176771Sraj pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 878176771Sraj if (PTE_ISVALID(pte)) { 879176771Sraj pte_remove(mmu, pmap, va, PTBL_HOLD); 880176771Sraj } else { 881176771Sraj /* 882176771Sraj * pte is not used, increment hold count 883176771Sraj * for ptbl pages. 884176771Sraj */ 885176771Sraj if (pmap != kernel_pmap) 886176771Sraj ptbl_hold(mmu, pmap, pdir_idx); 887176771Sraj } 888176771Sraj } 889176771Sraj 890176771Sraj /* 891187149Sraj * Insert pv_entry into pv_list for mapped page if part of managed 892187149Sraj * memory. 893176771Sraj */ 894176771Sraj if ((m->flags & PG_FICTITIOUS) == 0) { 895176771Sraj if ((m->flags & PG_UNMANAGED) == 0) { 896187149Sraj flags |= PTE_MANAGED; 897176771Sraj 898176771Sraj /* Create and insert pv entry. */ 899176771Sraj pv_insert(pmap, va, m); 900176771Sraj } 901176771Sraj } 902176771Sraj 903176771Sraj pmap->pm_stats.resident_count++; 904187149Sraj 905187149Sraj mtx_lock_spin(&tlbivax_mutex); 906192532Sraj tlb_miss_lock(); 907187149Sraj 908187149Sraj tlb0_flush_entry(va); 909187149Sraj if (pmap->pm_pdir[pdir_idx] == NULL) { 910187149Sraj /* 911187149Sraj * If we just allocated a new page table, hook it in 912187149Sraj * the pdir. 913187149Sraj */ 914187149Sraj pmap->pm_pdir[pdir_idx] = ptbl; 915187149Sraj } 916187149Sraj pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 917176771Sraj pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 918176771Sraj pte->flags |= (PTE_VALID | flags); 919176771Sraj 920192532Sraj tlb_miss_unlock(); 921187149Sraj mtx_unlock_spin(&tlbivax_mutex); 922176771Sraj} 923176771Sraj 924176771Sraj/* Return the pa for the given pmap/va. */ 925176771Srajstatic vm_paddr_t 926176771Srajpte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 927176771Sraj{ 928176771Sraj vm_paddr_t pa = 0; 929176771Sraj pte_t *pte; 930176771Sraj 931176771Sraj pte = pte_find(mmu, pmap, va); 932176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 933176771Sraj pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 934176771Sraj return (pa); 935176771Sraj} 936176771Sraj 937176771Sraj/* Get a pointer to a PTE in a page table. */ 938176771Srajstatic pte_t * 939176771Srajpte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 940176771Sraj{ 941176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 942176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 943176771Sraj 944176771Sraj KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 945176771Sraj 946176771Sraj if (pmap->pm_pdir[pdir_idx]) 947176771Sraj return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 948176771Sraj 949176771Sraj return (NULL); 950176771Sraj} 951176771Sraj 952176771Sraj/**************************************************************************/ 953176771Sraj/* PMAP related */ 954176771Sraj/**************************************************************************/ 955176771Sraj 956176771Sraj/* 957176771Sraj * This is called during e500_init, before the system is really initialized. 958176771Sraj */ 959176771Srajstatic void 960190701Smarcelmmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 961176771Sraj{ 962176771Sraj vm_offset_t phys_kernelend; 963176771Sraj struct mem_region *mp, *mp1; 964176771Sraj int cnt, i, j; 965176771Sraj u_int s, e, sz; 966176771Sraj u_int phys_avail_count; 967182198Sraj vm_size_t physsz, hwphyssz, kstack0_sz; 968193489Sraj vm_offset_t kernel_pdir, kstack0, va; 969182198Sraj vm_paddr_t kstack0_phys; 970194784Sjeff void *dpcpu; 971193489Sraj pte_t *pte; 972176771Sraj 973176771Sraj debugf("mmu_booke_bootstrap: entered\n"); 974176771Sraj 975187149Sraj /* Initialize invalidation mutex */ 976187149Sraj mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 977187149Sraj 978187149Sraj /* Read TLB0 size and associativity. */ 979187149Sraj tlb0_get_tlbconf(); 980187149Sraj 981176771Sraj /* Align kernel start and end address (kernel image). */ 982190701Smarcel kernstart = trunc_page(start); 983190701Smarcel data_start = round_page(kernelend); 984190701Smarcel kernsize = data_start - kernstart; 985176771Sraj 986190701Smarcel data_end = data_start; 987190701Smarcel 988176771Sraj /* Allocate space for the message buffer. */ 989190701Smarcel msgbufp = (struct msgbuf *)data_end; 990190701Smarcel data_end += MSGBUF_SIZE; 991187149Sraj debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 992190701Smarcel data_end); 993176771Sraj 994190701Smarcel data_end = round_page(data_end); 995176771Sraj 996194784Sjeff /* Allocate the dynamic per-cpu area. */ 997194784Sjeff dpcpu = (void *)data_end; 998194784Sjeff data_end += DPCPU_SIZE; 999194784Sjeff dpcpu_init(dpcpu, 0); 1000194784Sjeff 1001176771Sraj /* Allocate space for ptbl_bufs. */ 1002190701Smarcel ptbl_bufs = (struct ptbl_buf *)data_end; 1003190701Smarcel data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1004187149Sraj debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1005190701Smarcel data_end); 1006176771Sraj 1007190701Smarcel data_end = round_page(data_end); 1008176771Sraj 1009176771Sraj /* Allocate PTE tables for kernel KVA. */ 1010190701Smarcel kernel_pdir = data_end; 1011176771Sraj kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1012176771Sraj PDIR_SIZE - 1) / PDIR_SIZE; 1013190701Smarcel data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1014176771Sraj debugf(" kernel ptbls: %d\n", kernel_ptbls); 1015190701Smarcel debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1016176771Sraj 1017190701Smarcel debugf(" data_end: 0x%08x\n", data_end); 1018190701Smarcel if (data_end - kernstart > 0x1000000) { 1019190701Smarcel data_end = (data_end + 0x3fffff) & ~0x3fffff; 1020190701Smarcel tlb1_mapin_region(kernstart + 0x1000000, 1021190701Smarcel kernload + 0x1000000, data_end - kernstart - 0x1000000); 1022176771Sraj } else 1023190701Smarcel data_end = (data_end + 0xffffff) & ~0xffffff; 1024176771Sraj 1025190701Smarcel debugf(" updated data_end: 0x%08x\n", data_end); 1026187149Sraj 1027190701Smarcel kernsize += data_end - data_start; 1028190701Smarcel 1029182362Sraj /* 1030182362Sraj * Clear the structures - note we can only do it safely after the 1031187149Sraj * possible additional TLB1 translations are in place (above) so that 1032190701Smarcel * all range up to the currently calculated 'data_end' is covered. 1033182362Sraj */ 1034182362Sraj memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1035182362Sraj memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1036182362Sraj 1037176771Sraj /*******************************************************/ 1038176771Sraj /* Set the start and end of kva. */ 1039176771Sraj /*******************************************************/ 1040190701Smarcel virtual_avail = round_page(data_end); 1041176771Sraj virtual_end = VM_MAX_KERNEL_ADDRESS; 1042176771Sraj 1043176771Sraj /* Allocate KVA space for page zero/copy operations. */ 1044176771Sraj zero_page_va = virtual_avail; 1045176771Sraj virtual_avail += PAGE_SIZE; 1046176771Sraj zero_page_idle_va = virtual_avail; 1047176771Sraj virtual_avail += PAGE_SIZE; 1048176771Sraj copy_page_src_va = virtual_avail; 1049176771Sraj virtual_avail += PAGE_SIZE; 1050176771Sraj copy_page_dst_va = virtual_avail; 1051176771Sraj virtual_avail += PAGE_SIZE; 1052187149Sraj debugf("zero_page_va = 0x%08x\n", zero_page_va); 1053187149Sraj debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1054187149Sraj debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1055187149Sraj debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1056176771Sraj 1057176771Sraj /* Initialize page zero/copy mutexes. */ 1058176771Sraj mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1059176771Sraj mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1060176771Sraj 1061176771Sraj /* Allocate KVA space for ptbl bufs. */ 1062176771Sraj ptbl_buf_pool_vabase = virtual_avail; 1063176771Sraj virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1064187149Sraj debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1065187149Sraj ptbl_buf_pool_vabase, virtual_avail); 1066176771Sraj 1067176771Sraj /* Calculate corresponding physical addresses for the kernel region. */ 1068190701Smarcel phys_kernelend = kernload + kernsize; 1069176771Sraj debugf("kernel image and allocated data:\n"); 1070176771Sraj debugf(" kernload = 0x%08x\n", kernload); 1071190701Smarcel debugf(" kernstart = 0x%08x\n", kernstart); 1072190701Smarcel debugf(" kernsize = 0x%08x\n", kernsize); 1073176771Sraj 1074176771Sraj if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1075176771Sraj panic("mmu_booke_bootstrap: phys_avail too small"); 1076176771Sraj 1077176771Sraj /* 1078187151Sraj * Remove kernel physical address range from avail regions list. Page 1079187151Sraj * align all regions. Non-page aligned memory isn't very interesting 1080187151Sraj * to us. Also, sort the entries for ascending addresses. 1081176771Sraj */ 1082192067Snwhitehorn 1083192067Snwhitehorn /* Retrieve phys/avail mem regions */ 1084192067Snwhitehorn mem_regions(&physmem_regions, &physmem_regions_sz, 1085192067Snwhitehorn &availmem_regions, &availmem_regions_sz); 1086176771Sraj sz = 0; 1087176771Sraj cnt = availmem_regions_sz; 1088176771Sraj debugf("processing avail regions:\n"); 1089176771Sraj for (mp = availmem_regions; mp->mr_size; mp++) { 1090176771Sraj s = mp->mr_start; 1091176771Sraj e = mp->mr_start + mp->mr_size; 1092176771Sraj debugf(" %08x-%08x -> ", s, e); 1093176771Sraj /* Check whether this region holds all of the kernel. */ 1094176771Sraj if (s < kernload && e > phys_kernelend) { 1095176771Sraj availmem_regions[cnt].mr_start = phys_kernelend; 1096176771Sraj availmem_regions[cnt++].mr_size = e - phys_kernelend; 1097176771Sraj e = kernload; 1098176771Sraj } 1099176771Sraj /* Look whether this regions starts within the kernel. */ 1100176771Sraj if (s >= kernload && s < phys_kernelend) { 1101176771Sraj if (e <= phys_kernelend) 1102176771Sraj goto empty; 1103176771Sraj s = phys_kernelend; 1104176771Sraj } 1105176771Sraj /* Now look whether this region ends within the kernel. */ 1106176771Sraj if (e > kernload && e <= phys_kernelend) { 1107176771Sraj if (s >= kernload) 1108176771Sraj goto empty; 1109176771Sraj e = kernload; 1110176771Sraj } 1111176771Sraj /* Now page align the start and size of the region. */ 1112176771Sraj s = round_page(s); 1113176771Sraj e = trunc_page(e); 1114176771Sraj if (e < s) 1115176771Sraj e = s; 1116176771Sraj sz = e - s; 1117176771Sraj debugf("%08x-%08x = %x\n", s, e, sz); 1118176771Sraj 1119176771Sraj /* Check whether some memory is left here. */ 1120176771Sraj if (sz == 0) { 1121176771Sraj empty: 1122176771Sraj memmove(mp, mp + 1, 1123176771Sraj (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1124176771Sraj cnt--; 1125176771Sraj mp--; 1126176771Sraj continue; 1127176771Sraj } 1128176771Sraj 1129176771Sraj /* Do an insertion sort. */ 1130176771Sraj for (mp1 = availmem_regions; mp1 < mp; mp1++) 1131176771Sraj if (s < mp1->mr_start) 1132176771Sraj break; 1133176771Sraj if (mp1 < mp) { 1134176771Sraj memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1135176771Sraj mp1->mr_start = s; 1136176771Sraj mp1->mr_size = sz; 1137176771Sraj } else { 1138176771Sraj mp->mr_start = s; 1139176771Sraj mp->mr_size = sz; 1140176771Sraj } 1141176771Sraj } 1142176771Sraj availmem_regions_sz = cnt; 1143176771Sraj 1144176771Sraj /*******************************************************/ 1145182198Sraj /* Steal physical memory for kernel stack from the end */ 1146182198Sraj /* of the first avail region */ 1147182198Sraj /*******************************************************/ 1148182198Sraj kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1149182198Sraj kstack0_phys = availmem_regions[0].mr_start + 1150182198Sraj availmem_regions[0].mr_size; 1151182198Sraj kstack0_phys -= kstack0_sz; 1152182198Sraj availmem_regions[0].mr_size -= kstack0_sz; 1153182198Sraj 1154182198Sraj /*******************************************************/ 1155176771Sraj /* Fill in phys_avail table, based on availmem_regions */ 1156176771Sraj /*******************************************************/ 1157176771Sraj phys_avail_count = 0; 1158176771Sraj physsz = 0; 1159176771Sraj hwphyssz = 0; 1160176771Sraj TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1161176771Sraj 1162176771Sraj debugf("fill in phys_avail:\n"); 1163176771Sraj for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1164176771Sraj 1165176771Sraj debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1166176771Sraj availmem_regions[i].mr_start, 1167187151Sraj availmem_regions[i].mr_start + 1168187151Sraj availmem_regions[i].mr_size, 1169176771Sraj availmem_regions[i].mr_size); 1170176771Sraj 1171182362Sraj if (hwphyssz != 0 && 1172182362Sraj (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1173176771Sraj debugf(" hw.physmem adjust\n"); 1174176771Sraj if (physsz < hwphyssz) { 1175176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1176182362Sraj phys_avail[j + 1] = 1177182362Sraj availmem_regions[i].mr_start + 1178176771Sraj hwphyssz - physsz; 1179176771Sraj physsz = hwphyssz; 1180176771Sraj phys_avail_count++; 1181176771Sraj } 1182176771Sraj break; 1183176771Sraj } 1184176771Sraj 1185176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1186176771Sraj phys_avail[j + 1] = availmem_regions[i].mr_start + 1187176771Sraj availmem_regions[i].mr_size; 1188176771Sraj phys_avail_count++; 1189176771Sraj physsz += availmem_regions[i].mr_size; 1190176771Sraj } 1191176771Sraj physmem = btoc(physsz); 1192176771Sraj 1193176771Sraj /* Calculate the last available physical address. */ 1194176771Sraj for (i = 0; phys_avail[i + 2] != 0; i += 2) 1195176771Sraj ; 1196176771Sraj Maxmem = powerpc_btop(phys_avail[i + 1]); 1197176771Sraj 1198176771Sraj debugf("Maxmem = 0x%08lx\n", Maxmem); 1199176771Sraj debugf("phys_avail_count = %d\n", phys_avail_count); 1200187151Sraj debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1201187151Sraj physmem); 1202176771Sraj 1203176771Sraj /*******************************************************/ 1204176771Sraj /* Initialize (statically allocated) kernel pmap. */ 1205176771Sraj /*******************************************************/ 1206176771Sraj PMAP_LOCK_INIT(kernel_pmap); 1207176771Sraj kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1208176771Sraj 1209187149Sraj debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1210187149Sraj debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1211176771Sraj debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1212176771Sraj kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1213176771Sraj 1214176771Sraj /* Initialize kernel pdir */ 1215176771Sraj for (i = 0; i < kernel_ptbls; i++) 1216176771Sraj kernel_pmap->pm_pdir[kptbl_min + i] = 1217176771Sraj (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1218176771Sraj 1219187149Sraj for (i = 0; i < MAXCPU; i++) { 1220187149Sraj kernel_pmap->pm_tid[i] = TID_KERNEL; 1221187149Sraj 1222187149Sraj /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1223187149Sraj tidbusy[i][0] = kernel_pmap; 1224187149Sraj } 1225193489Sraj 1226193489Sraj /* 1227193489Sraj * Fill in PTEs covering kernel code and data. They are not required 1228193489Sraj * for address translation, as this area is covered by static TLB1 1229193489Sraj * entries, but for pte_vatopa() to work correctly with kernel area 1230193489Sraj * addresses. 1231193489Sraj */ 1232193489Sraj for (va = KERNBASE; va < data_end; va += PAGE_SIZE) { 1233193489Sraj pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1234193489Sraj pte->rpn = kernload + (va - KERNBASE); 1235193489Sraj pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1236193489Sraj PTE_VALID; 1237193489Sraj } 1238187149Sraj /* Mark kernel_pmap active on all CPUs */ 1239176771Sraj kernel_pmap->pm_active = ~0; 1240176771Sraj 1241176771Sraj /*******************************************************/ 1242176771Sraj /* Final setup */ 1243176771Sraj /*******************************************************/ 1244187149Sraj 1245182198Sraj /* Enter kstack0 into kernel map, provide guard page */ 1246182198Sraj kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1247182198Sraj thread0.td_kstack = kstack0; 1248182198Sraj thread0.td_kstack_pages = KSTACK_PAGES; 1249182198Sraj 1250182198Sraj debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1251182198Sraj debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1252182198Sraj kstack0_phys, kstack0_phys + kstack0_sz); 1253182198Sraj debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1254182198Sraj 1255182198Sraj virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1256182198Sraj for (i = 0; i < KSTACK_PAGES; i++) { 1257182198Sraj mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1258182198Sraj kstack0 += PAGE_SIZE; 1259182198Sraj kstack0_phys += PAGE_SIZE; 1260182198Sraj } 1261187149Sraj 1262187149Sraj debugf("virtual_avail = %08x\n", virtual_avail); 1263187149Sraj debugf("virtual_end = %08x\n", virtual_end); 1264182198Sraj 1265176771Sraj debugf("mmu_booke_bootstrap: exit\n"); 1266176771Sraj} 1267176771Sraj 1268192532Srajvoid 1269192532Srajpmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1270192532Sraj{ 1271192532Sraj int i; 1272192532Sraj 1273192532Sraj /* 1274192532Sraj * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1275192532Sraj * have the snapshot of its contents in the s/w tlb1[] table, so use 1276192532Sraj * these values directly to (re)program AP's TLB1 hardware. 1277192532Sraj */ 1278192532Sraj for (i = 0; i < tlb1_idx; i ++) { 1279192532Sraj /* Skip invalid entries */ 1280192532Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 1281192532Sraj continue; 1282192532Sraj 1283192532Sraj tlb1_write_entry(i); 1284192532Sraj } 1285192532Sraj 1286192532Sraj set_mas4_defaults(); 1287192532Sraj} 1288192532Sraj 1289176771Sraj/* 1290176771Sraj * Get the physical page address for the given pmap/virtual address. 1291176771Sraj */ 1292176771Srajstatic vm_paddr_t 1293176771Srajmmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1294176771Sraj{ 1295176771Sraj vm_paddr_t pa; 1296176771Sraj 1297176771Sraj PMAP_LOCK(pmap); 1298176771Sraj pa = pte_vatopa(mmu, pmap, va); 1299176771Sraj PMAP_UNLOCK(pmap); 1300176771Sraj 1301176771Sraj return (pa); 1302176771Sraj} 1303176771Sraj 1304176771Sraj/* 1305176771Sraj * Extract the physical page address associated with the given 1306176771Sraj * kernel virtual address. 1307176771Sraj */ 1308176771Srajstatic vm_paddr_t 1309176771Srajmmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1310176771Sraj{ 1311176771Sraj 1312176771Sraj return (pte_vatopa(mmu, kernel_pmap, va)); 1313176771Sraj} 1314176771Sraj 1315176771Sraj/* 1316176771Sraj * Initialize the pmap module. 1317176771Sraj * Called by vm_init, to initialize any structures that the pmap 1318176771Sraj * system needs to map virtual memory. 1319176771Sraj */ 1320176771Srajstatic void 1321176771Srajmmu_booke_init(mmu_t mmu) 1322176771Sraj{ 1323176771Sraj int shpgperproc = PMAP_SHPGPERPROC; 1324176771Sraj 1325176771Sraj /* 1326176771Sraj * Initialize the address space (zone) for the pv entries. Set a 1327176771Sraj * high water mark so that the system can recover from excessive 1328176771Sraj * numbers of pv entries. 1329176771Sraj */ 1330176771Sraj pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1331176771Sraj NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1332176771Sraj 1333176771Sraj TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1334176771Sraj pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1335176771Sraj 1336176771Sraj TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1337176771Sraj pv_entry_high_water = 9 * (pv_entry_max / 10); 1338176771Sraj 1339176771Sraj uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1340176771Sraj 1341176771Sraj /* Pre-fill pvzone with initial number of pv entries. */ 1342176771Sraj uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1343176771Sraj 1344176771Sraj /* Initialize ptbl allocation. */ 1345176771Sraj ptbl_init(); 1346176771Sraj} 1347176771Sraj 1348176771Sraj/* 1349176771Sraj * Map a list of wired pages into kernel virtual address space. This is 1350176771Sraj * intended for temporary mappings which do not need page modification or 1351176771Sraj * references recorded. Existing mappings in the region are overwritten. 1352176771Sraj */ 1353176771Srajstatic void 1354176771Srajmmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1355176771Sraj{ 1356176771Sraj vm_offset_t va; 1357176771Sraj 1358176771Sraj va = sva; 1359176771Sraj while (count-- > 0) { 1360176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1361176771Sraj va += PAGE_SIZE; 1362176771Sraj m++; 1363176771Sraj } 1364176771Sraj} 1365176771Sraj 1366176771Sraj/* 1367176771Sraj * Remove page mappings from kernel virtual address space. Intended for 1368176771Sraj * temporary mappings entered by mmu_booke_qenter. 1369176771Sraj */ 1370176771Srajstatic void 1371176771Srajmmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1372176771Sraj{ 1373176771Sraj vm_offset_t va; 1374176771Sraj 1375176771Sraj va = sva; 1376176771Sraj while (count-- > 0) { 1377176771Sraj mmu_booke_kremove(mmu, va); 1378176771Sraj va += PAGE_SIZE; 1379176771Sraj } 1380176771Sraj} 1381176771Sraj 1382176771Sraj/* 1383176771Sraj * Map a wired page into kernel virtual address space. 1384176771Sraj */ 1385176771Srajstatic void 1386176771Srajmmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1387176771Sraj{ 1388176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1389176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1390187151Sraj uint32_t flags; 1391176771Sraj pte_t *pte; 1392176771Sraj 1393187151Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1394187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1395176771Sraj 1396176771Sraj flags = 0; 1397176771Sraj flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1398187149Sraj flags |= PTE_M; 1399176771Sraj 1400176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1401176771Sraj 1402187149Sraj mtx_lock_spin(&tlbivax_mutex); 1403192532Sraj tlb_miss_lock(); 1404187149Sraj 1405176771Sraj if (PTE_ISVALID(pte)) { 1406187149Sraj 1407187149Sraj CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1408176771Sraj 1409176771Sraj /* Flush entry from TLB0 */ 1410187149Sraj tlb0_flush_entry(va); 1411176771Sraj } 1412176771Sraj 1413176771Sraj pte->rpn = pa & ~PTE_PA_MASK; 1414176771Sraj pte->flags = flags; 1415176771Sraj 1416176771Sraj //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1417176771Sraj // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1418176771Sraj // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1419176771Sraj 1420176771Sraj /* Flush the real memory from the instruction cache. */ 1421176771Sraj if ((flags & (PTE_I | PTE_G)) == 0) { 1422176771Sraj __syncicache((void *)va, PAGE_SIZE); 1423176771Sraj } 1424176771Sraj 1425192532Sraj tlb_miss_unlock(); 1426187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1427176771Sraj} 1428176771Sraj 1429176771Sraj/* 1430176771Sraj * Remove a page from kernel page table. 1431176771Sraj */ 1432176771Srajstatic void 1433176771Srajmmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1434176771Sraj{ 1435176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1436176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1437176771Sraj pte_t *pte; 1438176771Sraj 1439187149Sraj// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1440176771Sraj 1441187149Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1442187149Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1443176771Sraj ("mmu_booke_kremove: invalid va")); 1444176771Sraj 1445176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1446176771Sraj 1447176771Sraj if (!PTE_ISVALID(pte)) { 1448187149Sraj 1449187149Sraj CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1450187149Sraj 1451176771Sraj return; 1452176771Sraj } 1453176771Sraj 1454187149Sraj mtx_lock_spin(&tlbivax_mutex); 1455192532Sraj tlb_miss_lock(); 1456176771Sraj 1457187149Sraj /* Invalidate entry in TLB0, update PTE. */ 1458187149Sraj tlb0_flush_entry(va); 1459176771Sraj pte->flags = 0; 1460176771Sraj pte->rpn = 0; 1461176771Sraj 1462192532Sraj tlb_miss_unlock(); 1463187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1464176771Sraj} 1465176771Sraj 1466176771Sraj/* 1467176771Sraj * Initialize pmap associated with process 0. 1468176771Sraj */ 1469176771Srajstatic void 1470176771Srajmmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1471176771Sraj{ 1472187151Sraj 1473176771Sraj mmu_booke_pinit(mmu, pmap); 1474176771Sraj PCPU_SET(curpmap, pmap); 1475176771Sraj} 1476176771Sraj 1477176771Sraj/* 1478176771Sraj * Initialize a preallocated and zeroed pmap structure, 1479176771Sraj * such as one in a vmspace structure. 1480176771Sraj */ 1481176771Srajstatic void 1482176771Srajmmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1483176771Sraj{ 1484187149Sraj int i; 1485176771Sraj 1486187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1487187149Sraj curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1488176771Sraj 1489187149Sraj KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1490176771Sraj 1491176771Sraj PMAP_LOCK_INIT(pmap); 1492187149Sraj for (i = 0; i < MAXCPU; i++) 1493187149Sraj pmap->pm_tid[i] = TID_NONE; 1494176771Sraj pmap->pm_active = 0; 1495176771Sraj bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1496176771Sraj bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1497187149Sraj TAILQ_INIT(&pmap->pm_ptbl_list); 1498176771Sraj} 1499176771Sraj 1500176771Sraj/* 1501176771Sraj * Release any resources held by the given physical map. 1502176771Sraj * Called when a pmap initialized by mmu_booke_pinit is being released. 1503176771Sraj * Should only be called if the map contains no valid mappings. 1504176771Sraj */ 1505176771Srajstatic void 1506176771Srajmmu_booke_release(mmu_t mmu, pmap_t pmap) 1507176771Sraj{ 1508176771Sraj 1509187151Sraj printf("mmu_booke_release: s\n"); 1510176771Sraj 1511187151Sraj KASSERT(pmap->pm_stats.resident_count == 0, 1512187151Sraj ("pmap_release: pmap resident count %ld != 0", 1513187151Sraj pmap->pm_stats.resident_count)); 1514187151Sraj 1515176771Sraj PMAP_LOCK_DESTROY(pmap); 1516176771Sraj} 1517176771Sraj 1518176771Sraj/* 1519176771Sraj * Insert the given physical page at the specified virtual address in the 1520176771Sraj * target physical map with the protection requested. If specified the page 1521176771Sraj * will be wired down. 1522176771Sraj */ 1523176771Srajstatic void 1524176771Srajmmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1525176771Sraj vm_prot_t prot, boolean_t wired) 1526176771Sraj{ 1527187151Sraj 1528176771Sraj vm_page_lock_queues(); 1529176771Sraj PMAP_LOCK(pmap); 1530176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1531176771Sraj vm_page_unlock_queues(); 1532176771Sraj PMAP_UNLOCK(pmap); 1533176771Sraj} 1534176771Sraj 1535176771Srajstatic void 1536176771Srajmmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1537176771Sraj vm_prot_t prot, boolean_t wired) 1538176771Sraj{ 1539176771Sraj pte_t *pte; 1540176771Sraj vm_paddr_t pa; 1541187151Sraj uint32_t flags; 1542176771Sraj int su, sync; 1543176771Sraj 1544176771Sraj pa = VM_PAGE_TO_PHYS(m); 1545176771Sraj su = (pmap == kernel_pmap); 1546176771Sraj sync = 0; 1547176771Sraj 1548176771Sraj //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1549176771Sraj // "pa=0x%08x prot=0x%08x wired=%d)\n", 1550176771Sraj // (u_int32_t)pmap, su, pmap->pm_tid, 1551176771Sraj // (u_int32_t)m, va, pa, prot, wired); 1552176771Sraj 1553176771Sraj if (su) { 1554187151Sraj KASSERT(((va >= virtual_avail) && 1555187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1556187151Sraj ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1557176771Sraj } else { 1558176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1559187151Sraj ("mmu_booke_enter_locked: user pmap, non user va")); 1560176771Sraj } 1561208175Salc KASSERT((m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1562208175Salc ("mmu_booke_enter_locked: page %p is not busy", m)); 1563176771Sraj 1564176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1565176771Sraj 1566176771Sraj /* 1567176771Sraj * If there is an existing mapping, and the physical address has not 1568176771Sraj * changed, must be protection or wiring change. 1569176771Sraj */ 1570176771Sraj if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1571176771Sraj (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1572187149Sraj 1573187149Sraj /* 1574187149Sraj * Before actually updating pte->flags we calculate and 1575187149Sraj * prepare its new value in a helper var. 1576187149Sraj */ 1577187149Sraj flags = pte->flags; 1578187149Sraj flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1579176771Sraj 1580176771Sraj /* Wiring change, just update stats. */ 1581176771Sraj if (wired) { 1582176771Sraj if (!PTE_ISWIRED(pte)) { 1583187149Sraj flags |= PTE_WIRED; 1584176771Sraj pmap->pm_stats.wired_count++; 1585176771Sraj } 1586176771Sraj } else { 1587176771Sraj if (PTE_ISWIRED(pte)) { 1588187149Sraj flags &= ~PTE_WIRED; 1589176771Sraj pmap->pm_stats.wired_count--; 1590176771Sraj } 1591176771Sraj } 1592176771Sraj 1593176771Sraj if (prot & VM_PROT_WRITE) { 1594176771Sraj /* Add write permissions. */ 1595187149Sraj flags |= PTE_SW; 1596176771Sraj if (!su) 1597187149Sraj flags |= PTE_UW; 1598192795Sraj 1599192795Sraj vm_page_flag_set(m, PG_WRITEABLE); 1600176771Sraj } else { 1601176771Sraj /* Handle modified pages, sense modify status. */ 1602187149Sraj 1603187149Sraj /* 1604187149Sraj * The PTE_MODIFIED flag could be set by underlying 1605187149Sraj * TLB misses since we last read it (above), possibly 1606187149Sraj * other CPUs could update it so we check in the PTE 1607187149Sraj * directly rather than rely on that saved local flags 1608187149Sraj * copy. 1609187149Sraj */ 1610178626Smarcel if (PTE_ISMODIFIED(pte)) 1611178626Smarcel vm_page_dirty(m); 1612176771Sraj } 1613176771Sraj 1614176771Sraj if (prot & VM_PROT_EXECUTE) { 1615187149Sraj flags |= PTE_SX; 1616176771Sraj if (!su) 1617187149Sraj flags |= PTE_UX; 1618176771Sraj 1619187149Sraj /* 1620187149Sraj * Check existing flags for execute permissions: if we 1621187149Sraj * are turning execute permissions on, icache should 1622187149Sraj * be flushed. 1623187149Sraj */ 1624176771Sraj if ((flags & (PTE_UX | PTE_SX)) == 0) 1625176771Sraj sync++; 1626176771Sraj } 1627176771Sraj 1628187149Sraj flags &= ~PTE_REFERENCED; 1629187149Sraj 1630187149Sraj /* 1631187149Sraj * The new flags value is all calculated -- only now actually 1632187149Sraj * update the PTE. 1633187149Sraj */ 1634187149Sraj mtx_lock_spin(&tlbivax_mutex); 1635192532Sraj tlb_miss_lock(); 1636187149Sraj 1637187149Sraj tlb0_flush_entry(va); 1638187149Sraj pte->flags = flags; 1639187149Sraj 1640192532Sraj tlb_miss_unlock(); 1641187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1642187149Sraj 1643176771Sraj } else { 1644176771Sraj /* 1645187149Sraj * If there is an existing mapping, but it's for a different 1646176771Sraj * physical address, pte_enter() will delete the old mapping. 1647176771Sraj */ 1648176771Sraj //if ((pte != NULL) && PTE_ISVALID(pte)) 1649176771Sraj // debugf("mmu_booke_enter_locked: replace\n"); 1650176771Sraj //else 1651176771Sraj // debugf("mmu_booke_enter_locked: new\n"); 1652176771Sraj 1653176771Sraj /* Now set up the flags and install the new mapping. */ 1654176771Sraj flags = (PTE_SR | PTE_VALID); 1655187149Sraj flags |= PTE_M; 1656176771Sraj 1657176771Sraj if (!su) 1658176771Sraj flags |= PTE_UR; 1659176771Sraj 1660176771Sraj if (prot & VM_PROT_WRITE) { 1661176771Sraj flags |= PTE_SW; 1662176771Sraj if (!su) 1663176771Sraj flags |= PTE_UW; 1664192795Sraj 1665192795Sraj vm_page_flag_set(m, PG_WRITEABLE); 1666176771Sraj } 1667176771Sraj 1668176771Sraj if (prot & VM_PROT_EXECUTE) { 1669176771Sraj flags |= PTE_SX; 1670176771Sraj if (!su) 1671176771Sraj flags |= PTE_UX; 1672176771Sraj } 1673176771Sraj 1674176771Sraj /* If its wired update stats. */ 1675176771Sraj if (wired) { 1676176771Sraj pmap->pm_stats.wired_count++; 1677176771Sraj flags |= PTE_WIRED; 1678176771Sraj } 1679176771Sraj 1680176771Sraj pte_enter(mmu, pmap, m, va, flags); 1681176771Sraj 1682176771Sraj /* Flush the real memory from the instruction cache. */ 1683176771Sraj if (prot & VM_PROT_EXECUTE) 1684176771Sraj sync++; 1685176771Sraj } 1686176771Sraj 1687176771Sraj if (sync && (su || pmap == PCPU_GET(curpmap))) { 1688176771Sraj __syncicache((void *)va, PAGE_SIZE); 1689176771Sraj sync = 0; 1690176771Sraj } 1691176771Sraj} 1692176771Sraj 1693176771Sraj/* 1694176771Sraj * Maps a sequence of resident pages belonging to the same object. 1695176771Sraj * The sequence begins with the given page m_start. This page is 1696176771Sraj * mapped at the given virtual address start. Each subsequent page is 1697176771Sraj * mapped at a virtual address that is offset from start by the same 1698176771Sraj * amount as the page is offset from m_start within the object. The 1699176771Sraj * last page in the sequence is the page with the largest offset from 1700176771Sraj * m_start that can be mapped at a virtual address less than the given 1701176771Sraj * virtual address end. Not every virtual page between start and end 1702176771Sraj * is mapped; only those for which a resident page exists with the 1703176771Sraj * corresponding offset from m_start are mapped. 1704176771Sraj */ 1705176771Srajstatic void 1706176771Srajmmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1707176771Sraj vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1708176771Sraj{ 1709176771Sraj vm_page_t m; 1710176771Sraj vm_pindex_t diff, psize; 1711176771Sraj 1712176771Sraj psize = atop(end - start); 1713176771Sraj m = m_start; 1714208574Salc vm_page_lock_queues(); 1715176771Sraj PMAP_LOCK(pmap); 1716176771Sraj while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1717187151Sraj mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1718187151Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1719176771Sraj m = TAILQ_NEXT(m, listq); 1720176771Sraj } 1721208574Salc vm_page_unlock_queues(); 1722176771Sraj PMAP_UNLOCK(pmap); 1723176771Sraj} 1724176771Sraj 1725176771Srajstatic void 1726176771Srajmmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1727176771Sraj vm_prot_t prot) 1728176771Sraj{ 1729176771Sraj 1730207796Salc vm_page_lock_queues(); 1731176771Sraj PMAP_LOCK(pmap); 1732176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, 1733176771Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1734207796Salc vm_page_unlock_queues(); 1735176771Sraj PMAP_UNLOCK(pmap); 1736176771Sraj} 1737176771Sraj 1738176771Sraj/* 1739176771Sraj * Remove the given range of addresses from the specified map. 1740176771Sraj * 1741176771Sraj * It is assumed that the start and end are properly rounded to the page size. 1742176771Sraj */ 1743176771Srajstatic void 1744176771Srajmmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1745176771Sraj{ 1746176771Sraj pte_t *pte; 1747187151Sraj uint8_t hold_flag; 1748176771Sraj 1749176771Sraj int su = (pmap == kernel_pmap); 1750176771Sraj 1751176771Sraj //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1752176771Sraj // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1753176771Sraj 1754176771Sraj if (su) { 1755187151Sraj KASSERT(((va >= virtual_avail) && 1756187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1757187151Sraj ("mmu_booke_remove: kernel pmap, non kernel va")); 1758176771Sraj } else { 1759176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1760187151Sraj ("mmu_booke_remove: user pmap, non user va")); 1761176771Sraj } 1762176771Sraj 1763176771Sraj if (PMAP_REMOVE_DONE(pmap)) { 1764176771Sraj //debugf("mmu_booke_remove: e (empty)\n"); 1765176771Sraj return; 1766176771Sraj } 1767176771Sraj 1768176771Sraj hold_flag = PTBL_HOLD_FLAG(pmap); 1769176771Sraj //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1770176771Sraj 1771176771Sraj vm_page_lock_queues(); 1772176771Sraj PMAP_LOCK(pmap); 1773176771Sraj for (; va < endva; va += PAGE_SIZE) { 1774176771Sraj pte = pte_find(mmu, pmap, va); 1775187149Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 1776176771Sraj pte_remove(mmu, pmap, va, hold_flag); 1777176771Sraj } 1778176771Sraj PMAP_UNLOCK(pmap); 1779176771Sraj vm_page_unlock_queues(); 1780176771Sraj 1781176771Sraj //debugf("mmu_booke_remove: e\n"); 1782176771Sraj} 1783176771Sraj 1784176771Sraj/* 1785176771Sraj * Remove physical page from all pmaps in which it resides. 1786176771Sraj */ 1787176771Srajstatic void 1788176771Srajmmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1789176771Sraj{ 1790176771Sraj pv_entry_t pv, pvn; 1791187151Sraj uint8_t hold_flag; 1792176771Sraj 1793207796Salc vm_page_lock_queues(); 1794176771Sraj for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1795176771Sraj pvn = TAILQ_NEXT(pv, pv_link); 1796176771Sraj 1797176771Sraj PMAP_LOCK(pv->pv_pmap); 1798176771Sraj hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1799176771Sraj pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1800176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1801176771Sraj } 1802176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1803207796Salc vm_page_unlock_queues(); 1804176771Sraj} 1805176771Sraj 1806176771Sraj/* 1807176771Sraj * Map a range of physical addresses into kernel virtual address space. 1808176771Sraj */ 1809176771Srajstatic vm_offset_t 1810176771Srajmmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1811176771Sraj vm_offset_t pa_end, int prot) 1812176771Sraj{ 1813176771Sraj vm_offset_t sva = *virt; 1814176771Sraj vm_offset_t va = sva; 1815176771Sraj 1816176771Sraj //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1817176771Sraj // sva, pa_start, pa_end); 1818176771Sraj 1819176771Sraj while (pa_start < pa_end) { 1820176771Sraj mmu_booke_kenter(mmu, va, pa_start); 1821176771Sraj va += PAGE_SIZE; 1822176771Sraj pa_start += PAGE_SIZE; 1823176771Sraj } 1824176771Sraj *virt = va; 1825176771Sraj 1826176771Sraj //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1827176771Sraj return (sva); 1828176771Sraj} 1829176771Sraj 1830176771Sraj/* 1831176771Sraj * The pmap must be activated before it's address space can be accessed in any 1832176771Sraj * way. 1833176771Sraj */ 1834176771Srajstatic void 1835176771Srajmmu_booke_activate(mmu_t mmu, struct thread *td) 1836176771Sraj{ 1837176771Sraj pmap_t pmap; 1838176771Sraj 1839176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1840176771Sraj 1841187149Sraj CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1842187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1843176771Sraj 1844176771Sraj KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1845176771Sraj 1846176771Sraj mtx_lock_spin(&sched_lock); 1847176771Sraj 1848187149Sraj atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 1849176771Sraj PCPU_SET(curpmap, pmap); 1850187149Sraj 1851187149Sraj if (pmap->pm_tid[PCPU_GET(cpuid)] == TID_NONE) 1852176771Sraj tid_alloc(pmap); 1853176771Sraj 1854176771Sraj /* Load PID0 register with pmap tid value. */ 1855187149Sraj mtspr(SPR_PID0, pmap->pm_tid[PCPU_GET(cpuid)]); 1856187149Sraj __asm __volatile("isync"); 1857176771Sraj 1858176771Sraj mtx_unlock_spin(&sched_lock); 1859176771Sraj 1860187149Sraj CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1861187149Sraj pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1862176771Sraj} 1863176771Sraj 1864176771Sraj/* 1865176771Sraj * Deactivate the specified process's address space. 1866176771Sraj */ 1867176771Srajstatic void 1868176771Srajmmu_booke_deactivate(mmu_t mmu, struct thread *td) 1869176771Sraj{ 1870176771Sraj pmap_t pmap; 1871176771Sraj 1872176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1873187149Sraj 1874187149Sraj CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1875187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1876187149Sraj 1877187149Sraj atomic_clear_int(&pmap->pm_active, PCPU_GET(cpumask)); 1878176771Sraj PCPU_SET(curpmap, NULL); 1879176771Sraj} 1880176771Sraj 1881176771Sraj/* 1882176771Sraj * Copy the range specified by src_addr/len 1883176771Sraj * from the source map to the range dst_addr/len 1884176771Sraj * in the destination map. 1885176771Sraj * 1886176771Sraj * This routine is only advisory and need not do anything. 1887176771Sraj */ 1888176771Srajstatic void 1889194101Srajmmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1890194101Sraj vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1891176771Sraj{ 1892176771Sraj 1893176771Sraj} 1894176771Sraj 1895176771Sraj/* 1896176771Sraj * Set the physical protection on the specified range of this map as requested. 1897176771Sraj */ 1898176771Srajstatic void 1899176771Srajmmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1900176771Sraj vm_prot_t prot) 1901176771Sraj{ 1902176771Sraj vm_offset_t va; 1903176771Sraj vm_page_t m; 1904176771Sraj pte_t *pte; 1905176771Sraj 1906176771Sraj if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1907176771Sraj mmu_booke_remove(mmu, pmap, sva, eva); 1908176771Sraj return; 1909176771Sraj } 1910176771Sraj 1911176771Sraj if (prot & VM_PROT_WRITE) 1912176771Sraj return; 1913176771Sraj 1914176771Sraj vm_page_lock_queues(); 1915176771Sraj PMAP_LOCK(pmap); 1916176771Sraj for (va = sva; va < eva; va += PAGE_SIZE) { 1917176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1918176771Sraj if (PTE_ISVALID(pte)) { 1919176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1920176771Sraj 1921187149Sraj mtx_lock_spin(&tlbivax_mutex); 1922192532Sraj tlb_miss_lock(); 1923187149Sraj 1924176771Sraj /* Handle modified pages. */ 1925207437Salc if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1926178626Smarcel vm_page_dirty(m); 1927176771Sraj 1928187149Sraj tlb0_flush_entry(va); 1929207437Salc pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1930187149Sraj 1931192532Sraj tlb_miss_unlock(); 1932187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1933176771Sraj } 1934176771Sraj } 1935176771Sraj } 1936176771Sraj PMAP_UNLOCK(pmap); 1937176771Sraj vm_page_unlock_queues(); 1938176771Sraj} 1939176771Sraj 1940176771Sraj/* 1941176771Sraj * Clear the write and modified bits in each of the given page's mappings. 1942176771Sraj */ 1943176771Srajstatic void 1944176771Srajmmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1945176771Sraj{ 1946176771Sraj pv_entry_t pv; 1947176771Sraj pte_t *pte; 1948176771Sraj 1949208175Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1950208175Salc ("mmu_booke_remove_write: page %p is not managed", m)); 1951208175Salc 1952208175Salc /* 1953208175Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1954208175Salc * another thread while the object is locked. Thus, if PG_WRITEABLE 1955208175Salc * is clear, no page table entries need updating. 1956208175Salc */ 1957208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1958208175Salc if ((m->oflags & VPO_BUSY) == 0 && 1959176771Sraj (m->flags & PG_WRITEABLE) == 0) 1960176771Sraj return; 1961207796Salc vm_page_lock_queues(); 1962176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1963176771Sraj PMAP_LOCK(pv->pv_pmap); 1964176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1965176771Sraj if (PTE_ISVALID(pte)) { 1966176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1967176771Sraj 1968187149Sraj mtx_lock_spin(&tlbivax_mutex); 1969192532Sraj tlb_miss_lock(); 1970187149Sraj 1971176771Sraj /* Handle modified pages. */ 1972178626Smarcel if (PTE_ISMODIFIED(pte)) 1973178626Smarcel vm_page_dirty(m); 1974176771Sraj 1975176771Sraj /* Flush mapping from TLB0. */ 1976207437Salc pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1977187149Sraj 1978192532Sraj tlb_miss_unlock(); 1979187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1980176771Sraj } 1981176771Sraj } 1982176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1983176771Sraj } 1984176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1985207796Salc vm_page_unlock_queues(); 1986176771Sraj} 1987176771Sraj 1988198341Smarcelstatic void 1989198341Smarcelmmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1990176771Sraj{ 1991176771Sraj pte_t *pte; 1992198341Smarcel pmap_t pmap; 1993198341Smarcel vm_page_t m; 1994198341Smarcel vm_offset_t addr; 1995198341Smarcel vm_paddr_t pa; 1996198341Smarcel int active, valid; 1997198341Smarcel 1998198341Smarcel va = trunc_page(va); 1999198341Smarcel sz = round_page(sz); 2000176771Sraj 2001198341Smarcel vm_page_lock_queues(); 2002198341Smarcel pmap = PCPU_GET(curpmap); 2003198341Smarcel active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2004198341Smarcel while (sz > 0) { 2005198341Smarcel PMAP_LOCK(pm); 2006198341Smarcel pte = pte_find(mmu, pm, va); 2007198341Smarcel valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2008198341Smarcel if (valid) 2009198341Smarcel pa = PTE_PA(pte); 2010198341Smarcel PMAP_UNLOCK(pm); 2011198341Smarcel if (valid) { 2012198341Smarcel if (!active) { 2013198341Smarcel /* Create a mapping in the active pmap. */ 2014198341Smarcel addr = 0; 2015198341Smarcel m = PHYS_TO_VM_PAGE(pa); 2016198341Smarcel PMAP_LOCK(pmap); 2017198341Smarcel pte_enter(mmu, pmap, m, addr, 2018198341Smarcel PTE_SR | PTE_VALID | PTE_UR); 2019198341Smarcel __syncicache((void *)addr, PAGE_SIZE); 2020198341Smarcel pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2021198341Smarcel PMAP_UNLOCK(pmap); 2022198341Smarcel } else 2023198341Smarcel __syncicache((void *)va, PAGE_SIZE); 2024198341Smarcel } 2025198341Smarcel va += PAGE_SIZE; 2026198341Smarcel sz -= PAGE_SIZE; 2027176771Sraj } 2028198341Smarcel vm_page_unlock_queues(); 2029176771Sraj} 2030176771Sraj 2031176771Sraj/* 2032176771Sraj * Atomically extract and hold the physical page with the given 2033176771Sraj * pmap and virtual address pair if that mapping permits the given 2034176771Sraj * protection. 2035176771Sraj */ 2036176771Srajstatic vm_page_t 2037176771Srajmmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2038176771Sraj vm_prot_t prot) 2039176771Sraj{ 2040176771Sraj pte_t *pte; 2041176771Sraj vm_page_t m; 2042187151Sraj uint32_t pte_wbit; 2043207410Skmacy vm_paddr_t pa; 2044207410Skmacy 2045176771Sraj m = NULL; 2046207410Skmacy pa = 0; 2047176771Sraj PMAP_LOCK(pmap); 2048207410Skmacyretry: 2049176771Sraj pte = pte_find(mmu, pmap, va); 2050176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) { 2051176771Sraj if (pmap == kernel_pmap) 2052176771Sraj pte_wbit = PTE_SW; 2053176771Sraj else 2054176771Sraj pte_wbit = PTE_UW; 2055176771Sraj 2056176771Sraj if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2057207410Skmacy if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2058207410Skmacy goto retry; 2059176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2060176771Sraj vm_page_hold(m); 2061176771Sraj } 2062176771Sraj } 2063176771Sraj 2064207410Skmacy PA_UNLOCK_COND(pa); 2065176771Sraj PMAP_UNLOCK(pmap); 2066176771Sraj return (m); 2067176771Sraj} 2068176771Sraj 2069176771Sraj/* 2070176771Sraj * Initialize a vm_page's machine-dependent fields. 2071176771Sraj */ 2072176771Srajstatic void 2073176771Srajmmu_booke_page_init(mmu_t mmu, vm_page_t m) 2074176771Sraj{ 2075176771Sraj 2076176771Sraj TAILQ_INIT(&m->md.pv_list); 2077176771Sraj} 2078176771Sraj 2079176771Sraj/* 2080176771Sraj * mmu_booke_zero_page_area zeros the specified hardware page by 2081176771Sraj * mapping it into virtual memory and using bzero to clear 2082176771Sraj * its contents. 2083176771Sraj * 2084176771Sraj * off and size must reside within a single page. 2085176771Sraj */ 2086176771Srajstatic void 2087176771Srajmmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2088176771Sraj{ 2089176771Sraj vm_offset_t va; 2090176771Sraj 2091187151Sraj /* XXX KASSERT off and size are within a single page? */ 2092176771Sraj 2093176771Sraj mtx_lock(&zero_page_mutex); 2094176771Sraj va = zero_page_va; 2095176771Sraj 2096176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2097176771Sraj bzero((caddr_t)va + off, size); 2098176771Sraj mmu_booke_kremove(mmu, va); 2099176771Sraj 2100176771Sraj mtx_unlock(&zero_page_mutex); 2101176771Sraj} 2102176771Sraj 2103176771Sraj/* 2104176771Sraj * mmu_booke_zero_page zeros the specified hardware page. 2105176771Sraj */ 2106176771Srajstatic void 2107176771Srajmmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2108176771Sraj{ 2109176771Sraj 2110176771Sraj mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2111176771Sraj} 2112176771Sraj 2113176771Sraj/* 2114176771Sraj * mmu_booke_copy_page copies the specified (machine independent) page by 2115176771Sraj * mapping the page into virtual memory and using memcopy to copy the page, 2116176771Sraj * one machine dependent page at a time. 2117176771Sraj */ 2118176771Srajstatic void 2119176771Srajmmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2120176771Sraj{ 2121176771Sraj vm_offset_t sva, dva; 2122176771Sraj 2123176771Sraj sva = copy_page_src_va; 2124176771Sraj dva = copy_page_dst_va; 2125176771Sraj 2126187149Sraj mtx_lock(©_page_mutex); 2127176771Sraj mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2128176771Sraj mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2129176771Sraj memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2130176771Sraj mmu_booke_kremove(mmu, dva); 2131176771Sraj mmu_booke_kremove(mmu, sva); 2132176771Sraj mtx_unlock(©_page_mutex); 2133176771Sraj} 2134176771Sraj 2135176771Sraj/* 2136176771Sraj * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2137176771Sraj * into virtual memory and using bzero to clear its contents. This is intended 2138176771Sraj * to be called from the vm_pagezero process only and outside of Giant. No 2139176771Sraj * lock is required. 2140176771Sraj */ 2141176771Srajstatic void 2142176771Srajmmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2143176771Sraj{ 2144176771Sraj vm_offset_t va; 2145176771Sraj 2146176771Sraj va = zero_page_idle_va; 2147176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2148176771Sraj bzero((caddr_t)va, PAGE_SIZE); 2149176771Sraj mmu_booke_kremove(mmu, va); 2150176771Sraj} 2151176771Sraj 2152176771Sraj/* 2153176771Sraj * Return whether or not the specified physical page was modified 2154176771Sraj * in any of physical maps. 2155176771Sraj */ 2156176771Srajstatic boolean_t 2157176771Srajmmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2158176771Sraj{ 2159176771Sraj pte_t *pte; 2160176771Sraj pv_entry_t pv; 2161208504Salc boolean_t rv; 2162176771Sraj 2163208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2164208504Salc ("mmu_booke_is_modified: page %p is not managed", m)); 2165208504Salc rv = FALSE; 2166176771Sraj 2167208504Salc /* 2168208504Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2169208504Salc * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2170208504Salc * is clear, no PTEs can be modified. 2171208504Salc */ 2172208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2173208504Salc if ((m->oflags & VPO_BUSY) == 0 && 2174208504Salc (m->flags & PG_WRITEABLE) == 0) 2175208504Salc return (rv); 2176208504Salc vm_page_lock_queues(); 2177176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2178176771Sraj PMAP_LOCK(pv->pv_pmap); 2179208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2180208504Salc PTE_ISVALID(pte)) { 2181208504Salc if (PTE_ISMODIFIED(pte)) 2182208504Salc rv = TRUE; 2183176771Sraj } 2184176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2185208504Salc if (rv) 2186208504Salc break; 2187176771Sraj } 2188208504Salc vm_page_unlock_queues(); 2189208504Salc return (rv); 2190176771Sraj} 2191176771Sraj 2192176771Sraj/* 2193187151Sraj * Return whether or not the specified virtual address is eligible 2194176771Sraj * for prefault. 2195176771Sraj */ 2196176771Srajstatic boolean_t 2197176771Srajmmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2198176771Sraj{ 2199176771Sraj 2200176771Sraj return (FALSE); 2201176771Sraj} 2202176771Sraj 2203176771Sraj/* 2204207155Salc * Return whether or not the specified physical page was referenced 2205207155Salc * in any physical maps. 2206207155Salc */ 2207207155Salcstatic boolean_t 2208207155Salcmmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2209207155Salc{ 2210207155Salc pte_t *pte; 2211207155Salc pv_entry_t pv; 2212207155Salc boolean_t rv; 2213207155Salc 2214208574Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2215208574Salc ("mmu_booke_is_referenced: page %p is not managed", m)); 2216207155Salc rv = FALSE; 2217208574Salc vm_page_lock_queues(); 2218207155Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2219207155Salc PMAP_LOCK(pv->pv_pmap); 2220207155Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2221208574Salc PTE_ISVALID(pte)) { 2222208574Salc if (PTE_ISREFERENCED(pte)) 2223208574Salc rv = TRUE; 2224208574Salc } 2225207155Salc PMAP_UNLOCK(pv->pv_pmap); 2226207155Salc if (rv) 2227207155Salc break; 2228207155Salc } 2229208574Salc vm_page_unlock_queues(); 2230207155Salc return (rv); 2231207155Salc} 2232207155Salc 2233207155Salc/* 2234176771Sraj * Clear the modify bits on the specified physical page. 2235176771Sraj */ 2236176771Srajstatic void 2237176771Srajmmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2238176771Sraj{ 2239176771Sraj pte_t *pte; 2240176771Sraj pv_entry_t pv; 2241176771Sraj 2242208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2243208504Salc ("mmu_booke_clear_modify: page %p is not managed", m)); 2244208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2245208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 2246208504Salc ("mmu_booke_clear_modify: page %p is busy", m)); 2247208504Salc 2248208504Salc /* 2249208504Salc * If the page is not PG_WRITEABLE, then no PTEs can be modified. 2250208504Salc * If the object containing the page is locked and the page is not 2251208504Salc * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2252208504Salc */ 2253208504Salc if ((m->flags & PG_WRITEABLE) == 0) 2254176771Sraj return; 2255208504Salc vm_page_lock_queues(); 2256176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2257176771Sraj PMAP_LOCK(pv->pv_pmap); 2258208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2259208504Salc PTE_ISVALID(pte)) { 2260187149Sraj mtx_lock_spin(&tlbivax_mutex); 2261192532Sraj tlb_miss_lock(); 2262187149Sraj 2263176771Sraj if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2264187149Sraj tlb0_flush_entry(pv->pv_va); 2265176771Sraj pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2266176771Sraj PTE_REFERENCED); 2267176771Sraj } 2268187149Sraj 2269192532Sraj tlb_miss_unlock(); 2270187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2271176771Sraj } 2272176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2273176771Sraj } 2274208504Salc vm_page_unlock_queues(); 2275176771Sraj} 2276176771Sraj 2277176771Sraj/* 2278176771Sraj * Return a count of reference bits for a page, clearing those bits. 2279176771Sraj * It is not necessary for every reference bit to be cleared, but it 2280176771Sraj * is necessary that 0 only be returned when there are truly no 2281176771Sraj * reference bits set. 2282176771Sraj * 2283176771Sraj * XXX: The exact number of bits to check and clear is a matter that 2284176771Sraj * should be tested and standardized at some point in the future for 2285176771Sraj * optimal aging of shared pages. 2286176771Sraj */ 2287176771Srajstatic int 2288176771Srajmmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2289176771Sraj{ 2290176771Sraj pte_t *pte; 2291176771Sraj pv_entry_t pv; 2292176771Sraj int count; 2293176771Sraj 2294176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2295176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2296176771Sraj return (0); 2297176771Sraj 2298176771Sraj count = 0; 2299176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2300176771Sraj PMAP_LOCK(pv->pv_pmap); 2301176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2302176771Sraj if (!PTE_ISVALID(pte)) 2303176771Sraj goto make_sure_to_unlock; 2304176771Sraj 2305176771Sraj if (PTE_ISREFERENCED(pte)) { 2306187149Sraj mtx_lock_spin(&tlbivax_mutex); 2307192532Sraj tlb_miss_lock(); 2308187149Sraj 2309187149Sraj tlb0_flush_entry(pv->pv_va); 2310176771Sraj pte->flags &= ~PTE_REFERENCED; 2311176771Sraj 2312192532Sraj tlb_miss_unlock(); 2313187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2314187149Sraj 2315176771Sraj if (++count > 4) { 2316176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2317176771Sraj break; 2318176771Sraj } 2319176771Sraj } 2320176771Sraj } 2321176771Srajmake_sure_to_unlock: 2322176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2323176771Sraj } 2324176771Sraj return (count); 2325176771Sraj} 2326176771Sraj 2327176771Sraj/* 2328176771Sraj * Clear the reference bit on the specified physical page. 2329176771Sraj */ 2330176771Srajstatic void 2331176771Srajmmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2332176771Sraj{ 2333176771Sraj pte_t *pte; 2334176771Sraj pv_entry_t pv; 2335176771Sraj 2336208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2337208504Salc ("mmu_booke_clear_reference: page %p is not managed", m)); 2338208504Salc vm_page_lock_queues(); 2339176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2340176771Sraj PMAP_LOCK(pv->pv_pmap); 2341208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2342208504Salc PTE_ISVALID(pte)) { 2343176771Sraj if (PTE_ISREFERENCED(pte)) { 2344187149Sraj mtx_lock_spin(&tlbivax_mutex); 2345192532Sraj tlb_miss_lock(); 2346187149Sraj 2347187149Sraj tlb0_flush_entry(pv->pv_va); 2348176771Sraj pte->flags &= ~PTE_REFERENCED; 2349187149Sraj 2350192532Sraj tlb_miss_unlock(); 2351187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2352176771Sraj } 2353176771Sraj } 2354176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2355176771Sraj } 2356208504Salc vm_page_unlock_queues(); 2357176771Sraj} 2358176771Sraj 2359176771Sraj/* 2360176771Sraj * Change wiring attribute for a map/virtual-address pair. 2361176771Sraj */ 2362176771Srajstatic void 2363176771Srajmmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2364176771Sraj{ 2365201758Smbr pte_t *pte; 2366176771Sraj 2367176771Sraj PMAP_LOCK(pmap); 2368176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2369176771Sraj if (wired) { 2370176771Sraj if (!PTE_ISWIRED(pte)) { 2371176771Sraj pte->flags |= PTE_WIRED; 2372176771Sraj pmap->pm_stats.wired_count++; 2373176771Sraj } 2374176771Sraj } else { 2375176771Sraj if (PTE_ISWIRED(pte)) { 2376176771Sraj pte->flags &= ~PTE_WIRED; 2377176771Sraj pmap->pm_stats.wired_count--; 2378176771Sraj } 2379176771Sraj } 2380176771Sraj } 2381176771Sraj PMAP_UNLOCK(pmap); 2382176771Sraj} 2383176771Sraj 2384176771Sraj/* 2385176771Sraj * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2386176771Sraj * page. This count may be changed upwards or downwards in the future; it is 2387176771Sraj * only necessary that true be returned for a small subset of pmaps for proper 2388176771Sraj * page aging. 2389176771Sraj */ 2390176771Srajstatic boolean_t 2391176771Srajmmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2392176771Sraj{ 2393176771Sraj pv_entry_t pv; 2394176771Sraj int loops; 2395176771Sraj 2396176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2397176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2398176771Sraj return (FALSE); 2399176771Sraj 2400176771Sraj loops = 0; 2401176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2402176771Sraj if (pv->pv_pmap == pmap) 2403176771Sraj return (TRUE); 2404176771Sraj 2405176771Sraj if (++loops >= 16) 2406176771Sraj break; 2407176771Sraj } 2408176771Sraj return (FALSE); 2409176771Sraj} 2410176771Sraj 2411176771Sraj/* 2412176771Sraj * Return the number of managed mappings to the given physical page that are 2413176771Sraj * wired. 2414176771Sraj */ 2415176771Srajstatic int 2416176771Srajmmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2417176771Sraj{ 2418176771Sraj pv_entry_t pv; 2419176771Sraj pte_t *pte; 2420176771Sraj int count = 0; 2421176771Sraj 2422176771Sraj if ((m->flags & PG_FICTITIOUS) != 0) 2423176771Sraj return (count); 2424207796Salc vm_page_lock_queues(); 2425176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2426176771Sraj PMAP_LOCK(pv->pv_pmap); 2427176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2428176771Sraj if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2429176771Sraj count++; 2430176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2431176771Sraj } 2432207796Salc vm_page_unlock_queues(); 2433176771Sraj return (count); 2434176771Sraj} 2435176771Sraj 2436176771Srajstatic int 2437176771Srajmmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2438176771Sraj{ 2439176771Sraj int i; 2440176771Sraj vm_offset_t va; 2441176771Sraj 2442176771Sraj /* 2443176771Sraj * This currently does not work for entries that 2444176771Sraj * overlap TLB1 entries. 2445176771Sraj */ 2446176771Sraj for (i = 0; i < tlb1_idx; i ++) { 2447176771Sraj if (tlb1_iomapped(i, pa, size, &va) == 0) 2448176771Sraj return (0); 2449176771Sraj } 2450176771Sraj 2451176771Sraj return (EFAULT); 2452176771Sraj} 2453176771Sraj 2454190701Smarcelvm_offset_t 2455190701Smarcelmmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2456190701Smarcel vm_size_t *sz) 2457190701Smarcel{ 2458190701Smarcel vm_paddr_t pa, ppa; 2459190701Smarcel vm_offset_t va; 2460190701Smarcel vm_size_t gran; 2461190701Smarcel 2462190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2463190701Smarcel if (md->md_vaddr == ~0UL) { 2464190701Smarcel /* We always map a 256MB page at 256M. */ 2465190701Smarcel gran = 256 * 1024 * 1024; 2466190701Smarcel pa = md->md_paddr + ofs; 2467190701Smarcel ppa = pa & ~(gran - 1); 2468190701Smarcel ofs = pa - ppa; 2469190701Smarcel va = gran; 2470190701Smarcel tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2471190701Smarcel if (*sz > (gran - ofs)) 2472190701Smarcel *sz = gran - ofs; 2473190701Smarcel return (va + ofs); 2474190701Smarcel } 2475190701Smarcel 2476190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2477190701Smarcel va = md->md_vaddr + ofs; 2478190701Smarcel if (va >= kernstart + kernsize) { 2479190701Smarcel gran = PAGE_SIZE - (va & PAGE_MASK); 2480190701Smarcel if (*sz > gran) 2481190701Smarcel *sz = gran; 2482190701Smarcel } 2483190701Smarcel return (va); 2484190701Smarcel} 2485190701Smarcel 2486190701Smarcelvoid 2487190701Smarcelmmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2488190701Smarcel vm_offset_t va) 2489190701Smarcel{ 2490190701Smarcel 2491190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2492190701Smarcel if (md->md_vaddr == ~0UL) { 2493190701Smarcel tlb1_idx--; 2494190701Smarcel tlb1[tlb1_idx].mas1 = 0; 2495190701Smarcel tlb1[tlb1_idx].mas2 = 0; 2496190701Smarcel tlb1[tlb1_idx].mas3 = 0; 2497190701Smarcel tlb1_write_entry(tlb1_idx); 2498190701Smarcel return; 2499190701Smarcel } 2500190701Smarcel 2501190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2502190701Smarcel /* Nothing to do... */ 2503190701Smarcel} 2504190701Smarcel 2505190701Smarcelstruct pmap_md * 2506190701Smarcelmmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2507190701Smarcel{ 2508190701Smarcel static struct pmap_md md; 2509190701Smarcel struct bi_mem_region *mr; 2510190701Smarcel pte_t *pte; 2511190701Smarcel vm_offset_t va; 2512190701Smarcel 2513190701Smarcel if (dumpsys_minidump) { 2514190701Smarcel md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2515190701Smarcel if (prev == NULL) { 2516190701Smarcel /* 1st: kernel .data and .bss. */ 2517190701Smarcel md.md_index = 1; 2518190701Smarcel md.md_vaddr = trunc_page((uintptr_t)_etext); 2519190701Smarcel md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2520190701Smarcel return (&md); 2521190701Smarcel } 2522190701Smarcel switch (prev->md_index) { 2523190701Smarcel case 1: 2524190701Smarcel /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2525190701Smarcel md.md_index = 2; 2526190701Smarcel md.md_vaddr = data_start; 2527190701Smarcel md.md_size = data_end - data_start; 2528190701Smarcel break; 2529190701Smarcel case 2: 2530190701Smarcel /* 3rd: kernel VM. */ 2531190701Smarcel va = prev->md_vaddr + prev->md_size; 2532190701Smarcel /* Find start of next chunk (from va). */ 2533190701Smarcel while (va < virtual_end) { 2534190701Smarcel /* Don't dump the buffer cache. */ 2535190701Smarcel if (va >= kmi.buffer_sva && 2536190701Smarcel va < kmi.buffer_eva) { 2537190701Smarcel va = kmi.buffer_eva; 2538190701Smarcel continue; 2539190701Smarcel } 2540190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2541190701Smarcel if (pte != NULL && PTE_ISVALID(pte)) 2542190701Smarcel break; 2543190701Smarcel va += PAGE_SIZE; 2544190701Smarcel } 2545190701Smarcel if (va < virtual_end) { 2546190701Smarcel md.md_vaddr = va; 2547190701Smarcel va += PAGE_SIZE; 2548190701Smarcel /* Find last page in chunk. */ 2549190701Smarcel while (va < virtual_end) { 2550190701Smarcel /* Don't run into the buffer cache. */ 2551190701Smarcel if (va == kmi.buffer_sva) 2552190701Smarcel break; 2553190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2554190701Smarcel if (pte == NULL || !PTE_ISVALID(pte)) 2555190701Smarcel break; 2556190701Smarcel va += PAGE_SIZE; 2557190701Smarcel } 2558190701Smarcel md.md_size = va - md.md_vaddr; 2559190701Smarcel break; 2560190701Smarcel } 2561190701Smarcel md.md_index = 3; 2562190701Smarcel /* FALLTHROUGH */ 2563190701Smarcel default: 2564190701Smarcel return (NULL); 2565190701Smarcel } 2566190701Smarcel } else { /* minidumps */ 2567190701Smarcel mr = bootinfo_mr(); 2568190701Smarcel if (prev == NULL) { 2569190701Smarcel /* first physical chunk. */ 2570190701Smarcel md.md_paddr = mr->mem_base; 2571190701Smarcel md.md_size = mr->mem_size; 2572190701Smarcel md.md_vaddr = ~0UL; 2573190701Smarcel md.md_index = 1; 2574190701Smarcel } else if (md.md_index < bootinfo->bi_mem_reg_no) { 2575190701Smarcel md.md_paddr = mr[md.md_index].mem_base; 2576190701Smarcel md.md_size = mr[md.md_index].mem_size; 2577190701Smarcel md.md_vaddr = ~0UL; 2578190701Smarcel md.md_index++; 2579190701Smarcel } else { 2580190701Smarcel /* There's no next physical chunk. */ 2581190701Smarcel return (NULL); 2582190701Smarcel } 2583190701Smarcel } 2584190701Smarcel 2585190701Smarcel return (&md); 2586190701Smarcel} 2587190701Smarcel 2588176771Sraj/* 2589176771Sraj * Map a set of physical memory pages into the kernel virtual address space. 2590176771Sraj * Return a pointer to where it is mapped. This routine is intended to be used 2591176771Sraj * for mapping device memory, NOT real memory. 2592176771Sraj */ 2593176771Srajstatic void * 2594176771Srajmmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2595176771Sraj{ 2596184244Smarcel void *res; 2597176771Sraj uintptr_t va; 2598184244Smarcel vm_size_t sz; 2599176771Sraj 2600176771Sraj va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2601184244Smarcel res = (void *)va; 2602184244Smarcel 2603184244Smarcel do { 2604184244Smarcel sz = 1 << (ilog2(size) & ~1); 2605184244Smarcel if (bootverbose) 2606184244Smarcel printf("Wiring VA=%x to PA=%x (size=%x), " 2607184244Smarcel "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2608184244Smarcel tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2609184244Smarcel size -= sz; 2610184244Smarcel pa += sz; 2611184244Smarcel va += sz; 2612184244Smarcel } while (size > 0); 2613184244Smarcel 2614184244Smarcel return (res); 2615176771Sraj} 2616176771Sraj 2617176771Sraj/* 2618176771Sraj * 'Unmap' a range mapped by mmu_booke_mapdev(). 2619176771Sraj */ 2620176771Srajstatic void 2621176771Srajmmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2622176771Sraj{ 2623176771Sraj vm_offset_t base, offset; 2624176771Sraj 2625176771Sraj /* 2626176771Sraj * Unmap only if this is inside kernel virtual space. 2627176771Sraj */ 2628176771Sraj if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2629176771Sraj base = trunc_page(va); 2630176771Sraj offset = va & PAGE_MASK; 2631176771Sraj size = roundup(offset + size, PAGE_SIZE); 2632176771Sraj kmem_free(kernel_map, base, size); 2633176771Sraj } 2634176771Sraj} 2635176771Sraj 2636176771Sraj/* 2637187151Sraj * mmu_booke_object_init_pt preloads the ptes for a given object into the 2638187151Sraj * specified pmap. This eliminates the blast of soft faults on process startup 2639187151Sraj * and immediately after an mmap. 2640176771Sraj */ 2641176771Srajstatic void 2642176771Srajmmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2643176771Sraj vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2644176771Sraj{ 2645187151Sraj 2646176771Sraj VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2647195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2648176771Sraj ("mmu_booke_object_init_pt: non-device object")); 2649176771Sraj} 2650176771Sraj 2651176771Sraj/* 2652176771Sraj * Perform the pmap work for mincore. 2653176771Sraj */ 2654176771Srajstatic int 2655208504Salcmmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2656208504Salc vm_paddr_t *locked_pa) 2657176771Sraj{ 2658176771Sraj 2659176771Sraj TODO; 2660176771Sraj return (0); 2661176771Sraj} 2662176771Sraj 2663176771Sraj/**************************************************************************/ 2664176771Sraj/* TID handling */ 2665176771Sraj/**************************************************************************/ 2666176771Sraj 2667176771Sraj/* 2668176771Sraj * Allocate a TID. If necessary, steal one from someone else. 2669176771Sraj * The new TID is flushed from the TLB before returning. 2670176771Sraj */ 2671176771Srajstatic tlbtid_t 2672176771Srajtid_alloc(pmap_t pmap) 2673176771Sraj{ 2674176771Sraj tlbtid_t tid; 2675187149Sraj int thiscpu; 2676176771Sraj 2677187149Sraj KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2678176771Sraj 2679187149Sraj CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2680176771Sraj 2681187149Sraj thiscpu = PCPU_GET(cpuid); 2682176771Sraj 2683187149Sraj tid = PCPU_GET(tid_next); 2684187149Sraj if (tid > TID_MAX) 2685187149Sraj tid = TID_MIN; 2686187149Sraj PCPU_SET(tid_next, tid + 1); 2687176771Sraj 2688187149Sraj /* If we are stealing TID then clear the relevant pmap's field */ 2689187149Sraj if (tidbusy[thiscpu][tid] != NULL) { 2690176771Sraj 2691187149Sraj CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2692187149Sraj 2693187149Sraj tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2694176771Sraj 2695187149Sraj /* Flush all entries from TLB0 matching this TID. */ 2696187149Sraj tid_flush(tid); 2697176771Sraj } 2698176771Sraj 2699187149Sraj tidbusy[thiscpu][tid] = pmap; 2700187149Sraj pmap->pm_tid[thiscpu] = tid; 2701187149Sraj __asm __volatile("msync; isync"); 2702176771Sraj 2703187149Sraj CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2704187149Sraj PCPU_GET(tid_next)); 2705176771Sraj 2706176771Sraj return (tid); 2707176771Sraj} 2708176771Sraj 2709176771Sraj/**************************************************************************/ 2710176771Sraj/* TLB0 handling */ 2711176771Sraj/**************************************************************************/ 2712176771Sraj 2713176771Srajstatic void 2714187149Srajtlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2715187149Sraj uint32_t mas7) 2716176771Sraj{ 2717176771Sraj int as; 2718176771Sraj char desc[3]; 2719176771Sraj tlbtid_t tid; 2720176771Sraj vm_size_t size; 2721176771Sraj unsigned int tsize; 2722176771Sraj 2723176771Sraj desc[2] = '\0'; 2724176771Sraj if (mas1 & MAS1_VALID) 2725176771Sraj desc[0] = 'V'; 2726176771Sraj else 2727176771Sraj desc[0] = ' '; 2728176771Sraj 2729176771Sraj if (mas1 & MAS1_IPROT) 2730176771Sraj desc[1] = 'P'; 2731176771Sraj else 2732176771Sraj desc[1] = ' '; 2733176771Sraj 2734187149Sraj as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2735176771Sraj tid = MAS1_GETTID(mas1); 2736176771Sraj 2737176771Sraj tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2738176771Sraj size = 0; 2739176771Sraj if (tsize) 2740176771Sraj size = tsize2size(tsize); 2741176771Sraj 2742176771Sraj debugf("%3d: (%s) [AS=%d] " 2743176771Sraj "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2744176771Sraj "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2745176771Sraj i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2746176771Sraj} 2747176771Sraj 2748176771Sraj/* Convert TLB0 va and way number to tlb0[] table index. */ 2749176771Srajstatic inline unsigned int 2750176771Srajtlb0_tableidx(vm_offset_t va, unsigned int way) 2751176771Sraj{ 2752176771Sraj unsigned int idx; 2753176771Sraj 2754176771Sraj idx = (way * TLB0_ENTRIES_PER_WAY); 2755176771Sraj idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2756176771Sraj return (idx); 2757176771Sraj} 2758176771Sraj 2759176771Sraj/* 2760187149Sraj * Invalidate TLB0 entry. 2761176771Sraj */ 2762187149Srajstatic inline void 2763187149Srajtlb0_flush_entry(vm_offset_t va) 2764176771Sraj{ 2765176771Sraj 2766187149Sraj CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2767176771Sraj 2768187149Sraj mtx_assert(&tlbivax_mutex, MA_OWNED); 2769176771Sraj 2770187149Sraj __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2771187149Sraj __asm __volatile("isync; msync"); 2772187149Sraj __asm __volatile("tlbsync; msync"); 2773176771Sraj 2774187149Sraj CTR1(KTR_PMAP, "%s: e", __func__); 2775176771Sraj} 2776176771Sraj 2777176771Sraj/* Print out contents of the MAS registers for each TLB0 entry */ 2778187149Srajvoid 2779176771Srajtlb0_print_tlbentries(void) 2780176771Sraj{ 2781187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 2782176771Sraj int entryidx, way, idx; 2783176771Sraj 2784176771Sraj debugf("TLB0 entries:\n"); 2785187149Sraj for (way = 0; way < TLB0_WAYS; way ++) 2786176771Sraj for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2787176771Sraj 2788176771Sraj mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2789176771Sraj mtspr(SPR_MAS0, mas0); 2790187149Sraj __asm __volatile("isync"); 2791176771Sraj 2792176771Sraj mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2793176771Sraj mtspr(SPR_MAS2, mas2); 2794176771Sraj 2795187149Sraj __asm __volatile("isync; tlbre"); 2796176771Sraj 2797176771Sraj mas1 = mfspr(SPR_MAS1); 2798176771Sraj mas2 = mfspr(SPR_MAS2); 2799176771Sraj mas3 = mfspr(SPR_MAS3); 2800176771Sraj mas7 = mfspr(SPR_MAS7); 2801176771Sraj 2802176771Sraj idx = tlb0_tableidx(mas2, way); 2803176771Sraj tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2804176771Sraj } 2805176771Sraj} 2806176771Sraj 2807176771Sraj/**************************************************************************/ 2808176771Sraj/* TLB1 handling */ 2809176771Sraj/**************************************************************************/ 2810187149Sraj 2811176771Sraj/* 2812187149Sraj * TLB1 mapping notes: 2813187149Sraj * 2814187149Sraj * TLB1[0] CCSRBAR 2815187149Sraj * TLB1[1] Kernel text and data. 2816187149Sraj * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2817187149Sraj * windows, other devices mappings. 2818187149Sraj */ 2819187149Sraj 2820187149Sraj/* 2821176771Sraj * Write given entry to TLB1 hardware. 2822176771Sraj * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2823176771Sraj */ 2824176771Srajstatic void 2825176771Srajtlb1_write_entry(unsigned int idx) 2826176771Sraj{ 2827187151Sraj uint32_t mas0, mas7; 2828176771Sraj 2829176771Sraj //debugf("tlb1_write_entry: s\n"); 2830176771Sraj 2831176771Sraj /* Clear high order RPN bits */ 2832176771Sraj mas7 = 0; 2833176771Sraj 2834176771Sraj /* Select entry */ 2835176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2836176771Sraj //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2837176771Sraj 2838176771Sraj mtspr(SPR_MAS0, mas0); 2839187151Sraj __asm __volatile("isync"); 2840176771Sraj mtspr(SPR_MAS1, tlb1[idx].mas1); 2841187151Sraj __asm __volatile("isync"); 2842176771Sraj mtspr(SPR_MAS2, tlb1[idx].mas2); 2843187151Sraj __asm __volatile("isync"); 2844176771Sraj mtspr(SPR_MAS3, tlb1[idx].mas3); 2845187151Sraj __asm __volatile("isync"); 2846176771Sraj mtspr(SPR_MAS7, mas7); 2847187151Sraj __asm __volatile("isync; tlbwe; isync; msync"); 2848176771Sraj 2849201758Smbr //debugf("tlb1_write_entry: e\n"); 2850176771Sraj} 2851176771Sraj 2852176771Sraj/* 2853176771Sraj * Return the largest uint value log such that 2^log <= num. 2854176771Sraj */ 2855176771Srajstatic unsigned int 2856176771Srajilog2(unsigned int num) 2857176771Sraj{ 2858176771Sraj int lz; 2859176771Sraj 2860176771Sraj __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2861176771Sraj return (31 - lz); 2862176771Sraj} 2863176771Sraj 2864176771Sraj/* 2865176771Sraj * Convert TLB TSIZE value to mapped region size. 2866176771Sraj */ 2867176771Srajstatic vm_size_t 2868176771Srajtsize2size(unsigned int tsize) 2869176771Sraj{ 2870176771Sraj 2871176771Sraj /* 2872176771Sraj * size = 4^tsize KB 2873176771Sraj * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2874176771Sraj */ 2875176771Sraj 2876176771Sraj return ((1 << (2 * tsize)) * 1024); 2877176771Sraj} 2878176771Sraj 2879176771Sraj/* 2880176771Sraj * Convert region size (must be power of 4) to TLB TSIZE value. 2881176771Sraj */ 2882176771Srajstatic unsigned int 2883176771Srajsize2tsize(vm_size_t size) 2884176771Sraj{ 2885176771Sraj 2886176771Sraj return (ilog2(size) / 2 - 5); 2887176771Sraj} 2888176771Sraj 2889176771Sraj/* 2890187149Sraj * Register permanent kernel mapping in TLB1. 2891176771Sraj * 2892187149Sraj * Entries are created starting from index 0 (current free entry is 2893187149Sraj * kept in tlb1_idx) and are not supposed to be invalidated. 2894176771Sraj */ 2895187149Srajstatic int 2896187149Srajtlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2897187149Sraj uint32_t flags) 2898176771Sraj{ 2899187149Sraj uint32_t ts, tid; 2900176771Sraj int tsize; 2901187149Sraj 2902187149Sraj if (tlb1_idx >= TLB1_ENTRIES) { 2903187149Sraj printf("tlb1_set_entry: TLB1 full!\n"); 2904187149Sraj return (-1); 2905187149Sraj } 2906176771Sraj 2907176771Sraj /* Convert size to TSIZE */ 2908176771Sraj tsize = size2tsize(size); 2909176771Sraj 2910187149Sraj tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2911187149Sraj /* XXX TS is hard coded to 0 for now as we only use single address space */ 2912187149Sraj ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2913176771Sraj 2914187149Sraj /* XXX LOCK tlb1[] */ 2915176771Sraj 2916187149Sraj tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2917187149Sraj tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2918187149Sraj tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2919176771Sraj 2920187149Sraj /* Set supervisor RWX permission bits */ 2921187149Sraj tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2922176771Sraj 2923187149Sraj tlb1_write_entry(tlb1_idx++); 2924176771Sraj 2925187149Sraj /* XXX UNLOCK tlb1[] */ 2926176771Sraj 2927187149Sraj /* 2928187149Sraj * XXX in general TLB1 updates should be propagated between CPUs, 2929187149Sraj * since current design assumes to have the same TLB1 set-up on all 2930187149Sraj * cores. 2931187149Sraj */ 2932176771Sraj return (0); 2933176771Sraj} 2934176771Sraj 2935176771Srajstatic int 2936176771Srajtlb1_entry_size_cmp(const void *a, const void *b) 2937176771Sraj{ 2938176771Sraj const vm_size_t *sza; 2939176771Sraj const vm_size_t *szb; 2940176771Sraj 2941176771Sraj sza = a; 2942176771Sraj szb = b; 2943176771Sraj if (*sza > *szb) 2944176771Sraj return (-1); 2945176771Sraj else if (*sza < *szb) 2946176771Sraj return (1); 2947176771Sraj else 2948176771Sraj return (0); 2949176771Sraj} 2950176771Sraj 2951176771Sraj/* 2952187151Sraj * Map in contiguous RAM region into the TLB1 using maximum of 2953176771Sraj * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2954176771Sraj * 2955187151Sraj * If necessary round up last entry size and return total size 2956176771Sraj * used by all allocated entries. 2957176771Sraj */ 2958176771Srajvm_size_t 2959176771Srajtlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2960176771Sraj{ 2961176771Sraj vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2962176771Sraj vm_size_t mapped_size, sz, esz; 2963176771Sraj unsigned int log; 2964176771Sraj int i; 2965176771Sraj 2966187151Sraj CTR4(KTR_PMAP, "%s: region size = 0x%08x va = 0x%08x pa = 0x%08x", 2967187151Sraj __func__, size, va, pa); 2968176771Sraj 2969176771Sraj mapped_size = 0; 2970176771Sraj sz = size; 2971176771Sraj memset(entry_size, 0, sizeof(entry_size)); 2972176771Sraj 2973176771Sraj /* Calculate entry sizes. */ 2974176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2975176771Sraj 2976176771Sraj /* Largest region that is power of 4 and fits within size */ 2977187149Sraj log = ilog2(sz) / 2; 2978176771Sraj esz = 1 << (2 * log); 2979176771Sraj 2980176771Sraj /* If this is last entry cover remaining size. */ 2981176771Sraj if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2982176771Sraj while (esz < sz) 2983176771Sraj esz = esz << 2; 2984176771Sraj } 2985176771Sraj 2986176771Sraj entry_size[i] = esz; 2987176771Sraj mapped_size += esz; 2988176771Sraj if (esz < sz) 2989176771Sraj sz -= esz; 2990176771Sraj else 2991176771Sraj sz = 0; 2992176771Sraj } 2993176771Sraj 2994176771Sraj /* Sort entry sizes, required to get proper entry address alignment. */ 2995176771Sraj qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2996176771Sraj sizeof(vm_size_t), tlb1_entry_size_cmp); 2997176771Sraj 2998176771Sraj /* Load TLB1 entries. */ 2999176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 3000176771Sraj esz = entry_size[i]; 3001176771Sraj if (!esz) 3002176771Sraj break; 3003187151Sraj 3004187151Sraj CTR5(KTR_PMAP, "%s: entry %d: sz = 0x%08x (va = 0x%08x " 3005187151Sraj "pa = 0x%08x)", __func__, tlb1_idx, esz, va, pa); 3006187151Sraj 3007176771Sraj tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 3008176771Sraj 3009176771Sraj va += esz; 3010176771Sraj pa += esz; 3011176771Sraj } 3012176771Sraj 3013187151Sraj CTR3(KTR_PMAP, "%s: mapped size 0x%08x (wasted space 0x%08x)", 3014187151Sraj __func__, mapped_size, mapped_size - size); 3015176771Sraj 3016176771Sraj return (mapped_size); 3017176771Sraj} 3018176771Sraj 3019176771Sraj/* 3020176771Sraj * TLB1 initialization routine, to be called after the very first 3021176771Sraj * assembler level setup done in locore.S. 3022176771Sraj */ 3023176771Srajvoid 3024176771Srajtlb1_init(vm_offset_t ccsrbar) 3025176771Sraj{ 3026176771Sraj uint32_t mas0; 3027176771Sraj 3028187151Sraj /* TLB1[1] is used to map the kernel. Save that entry. */ 3029176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 3030176771Sraj mtspr(SPR_MAS0, mas0); 3031176771Sraj __asm __volatile("isync; tlbre"); 3032176771Sraj 3033176771Sraj tlb1[1].mas1 = mfspr(SPR_MAS1); 3034176771Sraj tlb1[1].mas2 = mfspr(SPR_MAS2); 3035176771Sraj tlb1[1].mas3 = mfspr(SPR_MAS3); 3036176771Sraj 3037187149Sraj /* Map in CCSRBAR in TLB1[0] */ 3038187149Sraj tlb1_idx = 0; 3039187149Sraj tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3040187149Sraj /* 3041187149Sraj * Set the next available TLB1 entry index. Note TLB[1] is reserved 3042187149Sraj * for initial mapping of kernel text+data, which was set early in 3043187149Sraj * locore, we need to skip this [busy] entry. 3044187149Sraj */ 3045187149Sraj tlb1_idx = 2; 3046176771Sraj 3047176771Sraj /* Setup TLB miss defaults */ 3048176771Sraj set_mas4_defaults(); 3049176771Sraj} 3050176771Sraj 3051176771Sraj/* 3052176771Sraj * Setup MAS4 defaults. 3053176771Sraj * These values are loaded to MAS0-2 on a TLB miss. 3054176771Sraj */ 3055176771Srajstatic void 3056176771Srajset_mas4_defaults(void) 3057176771Sraj{ 3058187151Sraj uint32_t mas4; 3059176771Sraj 3060176771Sraj /* Defaults: TLB0, PID0, TSIZED=4K */ 3061176771Sraj mas4 = MAS4_TLBSELD0; 3062176771Sraj mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3063192532Sraj#ifdef SMP 3064192532Sraj mas4 |= MAS4_MD; 3065192532Sraj#endif 3066176771Sraj mtspr(SPR_MAS4, mas4); 3067187151Sraj __asm __volatile("isync"); 3068176771Sraj} 3069176771Sraj 3070176771Sraj/* 3071176771Sraj * Print out contents of the MAS registers for each TLB1 entry 3072176771Sraj */ 3073176771Srajvoid 3074176771Srajtlb1_print_tlbentries(void) 3075176771Sraj{ 3076187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 3077176771Sraj int i; 3078176771Sraj 3079176771Sraj debugf("TLB1 entries:\n"); 3080187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) { 3081176771Sraj 3082176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3083176771Sraj mtspr(SPR_MAS0, mas0); 3084176771Sraj 3085187149Sraj __asm __volatile("isync; tlbre"); 3086176771Sraj 3087176771Sraj mas1 = mfspr(SPR_MAS1); 3088176771Sraj mas2 = mfspr(SPR_MAS2); 3089176771Sraj mas3 = mfspr(SPR_MAS3); 3090176771Sraj mas7 = mfspr(SPR_MAS7); 3091176771Sraj 3092176771Sraj tlb_print_entry(i, mas1, mas2, mas3, mas7); 3093176771Sraj } 3094176771Sraj} 3095176771Sraj 3096176771Sraj/* 3097176771Sraj * Print out contents of the in-ram tlb1 table. 3098176771Sraj */ 3099176771Srajvoid 3100176771Srajtlb1_print_entries(void) 3101176771Sraj{ 3102176771Sraj int i; 3103176771Sraj 3104176771Sraj debugf("tlb1[] table entries:\n"); 3105187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) 3106176771Sraj tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3107176771Sraj} 3108176771Sraj 3109176771Sraj/* 3110176771Sraj * Return 0 if the physical IO range is encompassed by one of the 3111176771Sraj * the TLB1 entries, otherwise return related error code. 3112176771Sraj */ 3113176771Srajstatic int 3114176771Srajtlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3115176771Sraj{ 3116187151Sraj uint32_t prot; 3117176771Sraj vm_paddr_t pa_start; 3118176771Sraj vm_paddr_t pa_end; 3119176771Sraj unsigned int entry_tsize; 3120176771Sraj vm_size_t entry_size; 3121176771Sraj 3122176771Sraj *va = (vm_offset_t)NULL; 3123176771Sraj 3124176771Sraj /* Skip invalid entries */ 3125176771Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 3126176771Sraj return (EINVAL); 3127176771Sraj 3128176771Sraj /* 3129176771Sraj * The entry must be cache-inhibited, guarded, and r/w 3130176771Sraj * so it can function as an i/o page 3131176771Sraj */ 3132176771Sraj prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3133176771Sraj if (prot != (MAS2_I | MAS2_G)) 3134176771Sraj return (EPERM); 3135176771Sraj 3136176771Sraj prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3137176771Sraj if (prot != (MAS3_SR | MAS3_SW)) 3138176771Sraj return (EPERM); 3139176771Sraj 3140176771Sraj /* The address should be within the entry range. */ 3141176771Sraj entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3142176771Sraj KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3143176771Sraj 3144176771Sraj entry_size = tsize2size(entry_tsize); 3145176771Sraj pa_start = tlb1[i].mas3 & MAS3_RPN; 3146176771Sraj pa_end = pa_start + entry_size - 1; 3147176771Sraj 3148176771Sraj if ((pa < pa_start) || ((pa + size) > pa_end)) 3149176771Sraj return (ERANGE); 3150176771Sraj 3151176771Sraj /* Return virtual address of this mapping. */ 3152187149Sraj *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3153176771Sraj return (0); 3154176771Sraj} 3155