pmap.c revision 207155
1176771Sraj/*- 2192532Sraj * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3176771Sraj * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4176771Sraj * All rights reserved. 5176771Sraj * 6176771Sraj * Redistribution and use in source and binary forms, with or without 7176771Sraj * modification, are permitted provided that the following conditions 8176771Sraj * are met: 9176771Sraj * 1. Redistributions of source code must retain the above copyright 10176771Sraj * notice, this list of conditions and the following disclaimer. 11176771Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176771Sraj * notice, this list of conditions and the following disclaimer in the 13176771Sraj * documentation and/or other materials provided with the distribution. 14176771Sraj * 15176771Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176771Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176771Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176771Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176771Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176771Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176771Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176771Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176771Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176771Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176771Sraj * 26176771Sraj * Some hw specific parts of this pmap were derived or influenced 27176771Sraj * by NetBSD's ibm4xx pmap module. More generic code is shared with 28176771Sraj * a few other pmap modules from the FreeBSD tree. 29176771Sraj */ 30176771Sraj 31176771Sraj /* 32176771Sraj * VM layout notes: 33176771Sraj * 34176771Sraj * Kernel and user threads run within one common virtual address space 35176771Sraj * defined by AS=0. 36176771Sraj * 37176771Sraj * Virtual address space layout: 38176771Sraj * ----------------------------- 39187151Sraj * 0x0000_0000 - 0xafff_ffff : user process 40187151Sraj * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41187151Sraj * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42190701Smarcel * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43187151Sraj * 0xc100_0000 - 0xfeef_ffff : KVA 44187151Sraj * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45187151Sraj * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46187151Sraj * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47187151Sraj * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48187151Sraj * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49176771Sraj */ 50176771Sraj 51176771Sraj#include <sys/cdefs.h> 52176771Sraj__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 207155 2010-04-24 17:32:52Z alc $"); 53176771Sraj 54176771Sraj#include <sys/types.h> 55176771Sraj#include <sys/param.h> 56176771Sraj#include <sys/malloc.h> 57187149Sraj#include <sys/ktr.h> 58176771Sraj#include <sys/proc.h> 59176771Sraj#include <sys/user.h> 60176771Sraj#include <sys/queue.h> 61176771Sraj#include <sys/systm.h> 62176771Sraj#include <sys/kernel.h> 63176771Sraj#include <sys/msgbuf.h> 64176771Sraj#include <sys/lock.h> 65176771Sraj#include <sys/mutex.h> 66192532Sraj#include <sys/smp.h> 67176771Sraj#include <sys/vmmeter.h> 68176771Sraj 69176771Sraj#include <vm/vm.h> 70176771Sraj#include <vm/vm_page.h> 71176771Sraj#include <vm/vm_kern.h> 72176771Sraj#include <vm/vm_pageout.h> 73176771Sraj#include <vm/vm_extern.h> 74176771Sraj#include <vm/vm_object.h> 75176771Sraj#include <vm/vm_param.h> 76176771Sraj#include <vm/vm_map.h> 77176771Sraj#include <vm/vm_pager.h> 78176771Sraj#include <vm/uma.h> 79176771Sraj 80190701Smarcel#include <machine/bootinfo.h> 81176771Sraj#include <machine/cpu.h> 82176771Sraj#include <machine/pcb.h> 83192067Snwhitehorn#include <machine/platform.h> 84176771Sraj 85176771Sraj#include <machine/tlb.h> 86176771Sraj#include <machine/spr.h> 87176771Sraj#include <machine/vmparam.h> 88176771Sraj#include <machine/md_var.h> 89176771Sraj#include <machine/mmuvar.h> 90176771Sraj#include <machine/pmap.h> 91176771Sraj#include <machine/pte.h> 92176771Sraj 93176771Sraj#include "mmu_if.h" 94176771Sraj 95176771Sraj#define DEBUG 96176771Sraj#undef DEBUG 97176771Sraj 98176771Sraj#ifdef DEBUG 99176771Sraj#define debugf(fmt, args...) printf(fmt, ##args) 100176771Sraj#else 101176771Sraj#define debugf(fmt, args...) 102176771Sraj#endif 103176771Sraj 104176771Sraj#define TODO panic("%s: not implemented", __func__); 105176771Sraj 106176771Sraj#include "opt_sched.h" 107176771Sraj#ifndef SCHED_4BSD 108176771Sraj#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 109176771Sraj#endif 110176771Srajextern struct mtx sched_lock; 111176771Sraj 112190701Smarcelextern int dumpsys_minidump; 113190701Smarcel 114190701Smarcelextern unsigned char _etext[]; 115190701Smarcelextern unsigned char _end[]; 116190701Smarcel 117176771Sraj/* Kernel physical load address. */ 118176771Srajextern uint32_t kernload; 119190701Smarcelvm_offset_t kernstart; 120190701Smarcelvm_size_t kernsize; 121176771Sraj 122190701Smarcel/* Message buffer and tables. */ 123190701Smarcelstatic vm_offset_t data_start; 124190701Smarcelstatic vm_size_t data_end; 125190701Smarcel 126192067Snwhitehorn/* Phys/avail memory regions. */ 127192067Snwhitehornstatic struct mem_region *availmem_regions; 128192067Snwhitehornstatic int availmem_regions_sz; 129192067Snwhitehornstatic struct mem_region *physmem_regions; 130192067Snwhitehornstatic int physmem_regions_sz; 131176771Sraj 132176771Sraj/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 133176771Srajstatic vm_offset_t zero_page_va; 134176771Srajstatic struct mtx zero_page_mutex; 135176771Sraj 136187149Srajstatic struct mtx tlbivax_mutex; 137187149Sraj 138176771Sraj/* 139176771Sraj * Reserved KVA space for mmu_booke_zero_page_idle. This is used 140176771Sraj * by idle thred only, no lock required. 141176771Sraj */ 142176771Srajstatic vm_offset_t zero_page_idle_va; 143176771Sraj 144176771Sraj/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 145176771Srajstatic vm_offset_t copy_page_src_va; 146176771Srajstatic vm_offset_t copy_page_dst_va; 147176771Srajstatic struct mtx copy_page_mutex; 148176771Sraj 149176771Sraj/**************************************************************************/ 150176771Sraj/* PMAP */ 151176771Sraj/**************************************************************************/ 152176771Sraj 153176771Srajstatic void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 154176771Sraj vm_prot_t, boolean_t); 155176771Sraj 156176771Srajunsigned int kptbl_min; /* Index of the first kernel ptbl. */ 157176771Srajunsigned int kernel_ptbls; /* Number of KVA ptbls. */ 158176771Sraj 159176771Sraj/* 160176771Sraj * If user pmap is processed with mmu_booke_remove and the resident count 161176771Sraj * drops to 0, there are no more pages to remove, so we need not continue. 162176771Sraj */ 163176771Sraj#define PMAP_REMOVE_DONE(pmap) \ 164176771Sraj ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 165176771Sraj 166187149Srajextern void tlb_lock(uint32_t *); 167187149Srajextern void tlb_unlock(uint32_t *); 168187149Srajextern void tid_flush(tlbtid_t); 169176771Sraj 170176771Sraj/**************************************************************************/ 171176771Sraj/* TLB and TID handling */ 172176771Sraj/**************************************************************************/ 173176771Sraj 174176771Sraj/* Translation ID busy table */ 175187149Srajstatic volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 176176771Sraj 177176771Sraj/* 178187149Sraj * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 179187149Sraj * core revisions and should be read from h/w registers during early config. 180176771Sraj */ 181187149Srajuint32_t tlb0_entries; 182187149Srajuint32_t tlb0_ways; 183187149Srajuint32_t tlb0_entries_per_way; 184176771Sraj 185187149Sraj#define TLB0_ENTRIES (tlb0_entries) 186187149Sraj#define TLB0_WAYS (tlb0_ways) 187187149Sraj#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 188176771Sraj 189187149Sraj#define TLB1_ENTRIES 16 190176771Sraj 191176771Sraj/* In-ram copy of the TLB1 */ 192187149Srajstatic tlb_entry_t tlb1[TLB1_ENTRIES]; 193176771Sraj 194176771Sraj/* Next free entry in the TLB1 */ 195176771Srajstatic unsigned int tlb1_idx; 196176771Sraj 197176771Srajstatic tlbtid_t tid_alloc(struct pmap *); 198176771Sraj 199187149Srajstatic void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 200176771Sraj 201187149Srajstatic int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 202176771Srajstatic void tlb1_write_entry(unsigned int); 203176771Srajstatic int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 204176771Srajstatic vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 205176771Sraj 206176771Srajstatic vm_size_t tsize2size(unsigned int); 207176771Srajstatic unsigned int size2tsize(vm_size_t); 208176771Srajstatic unsigned int ilog2(unsigned int); 209176771Sraj 210176771Srajstatic void set_mas4_defaults(void); 211176771Sraj 212187149Srajstatic inline void tlb0_flush_entry(vm_offset_t); 213176771Srajstatic inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 214176771Sraj 215176771Sraj/**************************************************************************/ 216176771Sraj/* Page table management */ 217176771Sraj/**************************************************************************/ 218176771Sraj 219176771Sraj/* Data for the pv entry allocation mechanism */ 220176771Srajstatic uma_zone_t pvzone; 221176771Srajstatic struct vm_object pvzone_obj; 222176771Srajstatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 223176771Sraj 224176771Sraj#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 225176771Sraj 226176771Sraj#ifndef PMAP_SHPGPERPROC 227176771Sraj#define PMAP_SHPGPERPROC 200 228176771Sraj#endif 229176771Sraj 230176771Srajstatic void ptbl_init(void); 231176771Srajstatic struct ptbl_buf *ptbl_buf_alloc(void); 232176771Srajstatic void ptbl_buf_free(struct ptbl_buf *); 233176771Srajstatic void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 234176771Sraj 235187149Srajstatic pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 236176771Srajstatic void ptbl_free(mmu_t, pmap_t, unsigned int); 237176771Srajstatic void ptbl_hold(mmu_t, pmap_t, unsigned int); 238176771Srajstatic int ptbl_unhold(mmu_t, pmap_t, unsigned int); 239176771Sraj 240176771Srajstatic vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 241176771Srajstatic pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 242187149Srajstatic void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 243187149Srajstatic int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 244176771Sraj 245187149Srajstatic pv_entry_t pv_alloc(void); 246176771Srajstatic void pv_free(pv_entry_t); 247176771Srajstatic void pv_insert(pmap_t, vm_offset_t, vm_page_t); 248176771Srajstatic void pv_remove(pmap_t, vm_offset_t, vm_page_t); 249176771Sraj 250176771Sraj/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 251176771Sraj#define PTBL_BUFS (128 * 16) 252176771Sraj 253176771Srajstruct ptbl_buf { 254176771Sraj TAILQ_ENTRY(ptbl_buf) link; /* list link */ 255176771Sraj vm_offset_t kva; /* va of mapping */ 256176771Sraj}; 257176771Sraj 258176771Sraj/* ptbl free list and a lock used for access synchronization. */ 259176771Srajstatic TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 260176771Srajstatic struct mtx ptbl_buf_freelist_lock; 261176771Sraj 262176771Sraj/* Base address of kva space allocated fot ptbl bufs. */ 263176771Srajstatic vm_offset_t ptbl_buf_pool_vabase; 264176771Sraj 265176771Sraj/* Pointer to ptbl_buf structures. */ 266176771Srajstatic struct ptbl_buf *ptbl_bufs; 267176771Sraj 268192532Srajvoid pmap_bootstrap_ap(volatile uint32_t *); 269192532Sraj 270176771Sraj/* 271176771Sraj * Kernel MMU interface 272176771Sraj */ 273176771Srajstatic void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 274176771Srajstatic void mmu_booke_clear_modify(mmu_t, vm_page_t); 275176771Srajstatic void mmu_booke_clear_reference(mmu_t, vm_page_t); 276194101Srajstatic void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 277194101Sraj vm_size_t, vm_offset_t); 278176771Srajstatic void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 279176771Srajstatic void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 280176771Sraj vm_prot_t, boolean_t); 281176771Srajstatic void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 282176771Sraj vm_page_t, vm_prot_t); 283176771Srajstatic void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 284176771Sraj vm_prot_t); 285176771Srajstatic vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 286176771Srajstatic vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 287176771Sraj vm_prot_t); 288176771Srajstatic void mmu_booke_init(mmu_t); 289176771Srajstatic boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 290176771Srajstatic boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 291207155Salcstatic boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 292176771Srajstatic boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 293176771Srajstatic vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 294176771Sraj int); 295176771Srajstatic int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t); 296176771Srajstatic void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 297176771Sraj vm_object_t, vm_pindex_t, vm_size_t); 298176771Srajstatic boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 299176771Srajstatic void mmu_booke_page_init(mmu_t, vm_page_t); 300176771Srajstatic int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 301176771Srajstatic void mmu_booke_pinit(mmu_t, pmap_t); 302176771Srajstatic void mmu_booke_pinit0(mmu_t, pmap_t); 303176771Srajstatic void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 304176771Sraj vm_prot_t); 305176771Srajstatic void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 306176771Srajstatic void mmu_booke_qremove(mmu_t, vm_offset_t, int); 307176771Srajstatic void mmu_booke_release(mmu_t, pmap_t); 308176771Srajstatic void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 309176771Srajstatic void mmu_booke_remove_all(mmu_t, vm_page_t); 310176771Srajstatic void mmu_booke_remove_write(mmu_t, vm_page_t); 311176771Srajstatic void mmu_booke_zero_page(mmu_t, vm_page_t); 312176771Srajstatic void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 313176771Srajstatic void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 314176771Srajstatic void mmu_booke_activate(mmu_t, struct thread *); 315176771Srajstatic void mmu_booke_deactivate(mmu_t, struct thread *); 316176771Srajstatic void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 317176771Srajstatic void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 318176771Srajstatic void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 319176771Srajstatic vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 320176771Srajstatic void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 321176771Srajstatic void mmu_booke_kremove(mmu_t, vm_offset_t); 322176771Srajstatic boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 323198341Smarcelstatic void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 324198341Smarcel vm_size_t); 325190701Smarcelstatic vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 326190701Smarcel vm_size_t, vm_size_t *); 327190701Smarcelstatic void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 328190701Smarcel vm_size_t, vm_offset_t); 329190701Smarcelstatic struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 330176771Sraj 331176771Srajstatic mmu_method_t mmu_booke_methods[] = { 332176771Sraj /* pmap dispatcher interface */ 333176771Sraj MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 334176771Sraj MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 335176771Sraj MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 336176771Sraj MMUMETHOD(mmu_copy, mmu_booke_copy), 337176771Sraj MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 338176771Sraj MMUMETHOD(mmu_enter, mmu_booke_enter), 339176771Sraj MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 340176771Sraj MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 341176771Sraj MMUMETHOD(mmu_extract, mmu_booke_extract), 342176771Sraj MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 343176771Sraj MMUMETHOD(mmu_init, mmu_booke_init), 344176771Sraj MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 345176771Sraj MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 346207155Salc MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 347176771Sraj MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 348176771Sraj MMUMETHOD(mmu_map, mmu_booke_map), 349176771Sraj MMUMETHOD(mmu_mincore, mmu_booke_mincore), 350176771Sraj MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 351176771Sraj MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 352176771Sraj MMUMETHOD(mmu_page_init, mmu_booke_page_init), 353176771Sraj MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 354176771Sraj MMUMETHOD(mmu_pinit, mmu_booke_pinit), 355176771Sraj MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 356176771Sraj MMUMETHOD(mmu_protect, mmu_booke_protect), 357176771Sraj MMUMETHOD(mmu_qenter, mmu_booke_qenter), 358176771Sraj MMUMETHOD(mmu_qremove, mmu_booke_qremove), 359176771Sraj MMUMETHOD(mmu_release, mmu_booke_release), 360176771Sraj MMUMETHOD(mmu_remove, mmu_booke_remove), 361176771Sraj MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 362176771Sraj MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 363198341Smarcel MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 364176771Sraj MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 365176771Sraj MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 366176771Sraj MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 367176771Sraj MMUMETHOD(mmu_activate, mmu_booke_activate), 368176771Sraj MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 369176771Sraj 370176771Sraj /* Internal interfaces */ 371176771Sraj MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 372176771Sraj MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 373176771Sraj MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 374176771Sraj MMUMETHOD(mmu_kenter, mmu_booke_kenter), 375176771Sraj MMUMETHOD(mmu_kextract, mmu_booke_kextract), 376176771Sraj/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 377176771Sraj MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 378176771Sraj 379190701Smarcel /* dumpsys() support */ 380190701Smarcel MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 381190701Smarcel MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 382190701Smarcel MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 383190701Smarcel 384176771Sraj { 0, 0 } 385176771Sraj}; 386176771Sraj 387176771Srajstatic mmu_def_t booke_mmu = { 388176771Sraj MMU_TYPE_BOOKE, 389176771Sraj mmu_booke_methods, 390176771Sraj 0 391176771Sraj}; 392176771SrajMMU_DEF(booke_mmu); 393176771Sraj 394192532Srajstatic inline void 395192532Srajtlb_miss_lock(void) 396192532Sraj{ 397192532Sraj#ifdef SMP 398192532Sraj struct pcpu *pc; 399192532Sraj 400192532Sraj if (!smp_started) 401192532Sraj return; 402192532Sraj 403192532Sraj SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 404192532Sraj if (pc != pcpup) { 405192532Sraj 406192532Sraj CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 407192532Sraj "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 408192532Sraj 409192532Sraj KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 410192532Sraj ("tlb_miss_lock: tried to lock self")); 411192532Sraj 412192532Sraj tlb_lock(pc->pc_booke_tlb_lock); 413192532Sraj 414192532Sraj CTR1(KTR_PMAP, "%s: locked", __func__); 415192532Sraj } 416192532Sraj } 417192532Sraj#endif 418192532Sraj} 419192532Sraj 420192532Srajstatic inline void 421192532Srajtlb_miss_unlock(void) 422192532Sraj{ 423192532Sraj#ifdef SMP 424192532Sraj struct pcpu *pc; 425192532Sraj 426192532Sraj if (!smp_started) 427192532Sraj return; 428192532Sraj 429192532Sraj SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 430192532Sraj if (pc != pcpup) { 431192532Sraj CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 432192532Sraj __func__, pc->pc_cpuid); 433192532Sraj 434192532Sraj tlb_unlock(pc->pc_booke_tlb_lock); 435192532Sraj 436192532Sraj CTR1(KTR_PMAP, "%s: unlocked", __func__); 437192532Sraj } 438192532Sraj } 439192532Sraj#endif 440192532Sraj} 441192532Sraj 442176771Sraj/* Return number of entries in TLB0. */ 443176771Srajstatic __inline void 444176771Srajtlb0_get_tlbconf(void) 445176771Sraj{ 446176771Sraj uint32_t tlb0_cfg; 447176771Sraj 448176771Sraj tlb0_cfg = mfspr(SPR_TLB0CFG); 449187149Sraj tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 450187149Sraj tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 451187149Sraj tlb0_entries_per_way = tlb0_entries / tlb0_ways; 452176771Sraj} 453176771Sraj 454176771Sraj/* Initialize pool of kva ptbl buffers. */ 455176771Srajstatic void 456176771Srajptbl_init(void) 457176771Sraj{ 458176771Sraj int i; 459176771Sraj 460187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 461187151Sraj (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 462187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 463187151Sraj __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 464176771Sraj 465176771Sraj mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 466176771Sraj TAILQ_INIT(&ptbl_buf_freelist); 467176771Sraj 468176771Sraj for (i = 0; i < PTBL_BUFS; i++) { 469176771Sraj ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 470176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 471176771Sraj } 472176771Sraj} 473176771Sraj 474182362Sraj/* Get a ptbl_buf from the freelist. */ 475176771Srajstatic struct ptbl_buf * 476176771Srajptbl_buf_alloc(void) 477176771Sraj{ 478176771Sraj struct ptbl_buf *buf; 479176771Sraj 480176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 481176771Sraj buf = TAILQ_FIRST(&ptbl_buf_freelist); 482176771Sraj if (buf != NULL) 483176771Sraj TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 484176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 485176771Sraj 486187151Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 487187151Sraj 488176771Sraj return (buf); 489176771Sraj} 490176771Sraj 491176771Sraj/* Return ptbl buff to free pool. */ 492176771Srajstatic void 493176771Srajptbl_buf_free(struct ptbl_buf *buf) 494176771Sraj{ 495176771Sraj 496187149Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 497176771Sraj 498176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 499176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 500176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 501176771Sraj} 502176771Sraj 503176771Sraj/* 504187149Sraj * Search the list of allocated ptbl bufs and find on list of allocated ptbls 505176771Sraj */ 506176771Srajstatic void 507176771Srajptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 508176771Sraj{ 509176771Sraj struct ptbl_buf *pbuf; 510176771Sraj 511187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 512176771Sraj 513187149Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 514187149Sraj 515187149Sraj TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 516176771Sraj if (pbuf->kva == (vm_offset_t)ptbl) { 517176771Sraj /* Remove from pmap ptbl buf list. */ 518187149Sraj TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 519176771Sraj 520187149Sraj /* Free corresponding ptbl buf. */ 521176771Sraj ptbl_buf_free(pbuf); 522176771Sraj break; 523176771Sraj } 524176771Sraj} 525176771Sraj 526176771Sraj/* Allocate page table. */ 527187149Srajstatic pte_t * 528176771Srajptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 529176771Sraj{ 530176771Sraj vm_page_t mtbl[PTBL_PAGES]; 531176771Sraj vm_page_t m; 532176771Sraj struct ptbl_buf *pbuf; 533176771Sraj unsigned int pidx; 534187149Sraj pte_t *ptbl; 535176771Sraj int i; 536176771Sraj 537187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 538187149Sraj (pmap == kernel_pmap), pdir_idx); 539176771Sraj 540176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 541176771Sraj ("ptbl_alloc: invalid pdir_idx")); 542176771Sraj KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 543176771Sraj ("pte_alloc: valid ptbl entry exists!")); 544176771Sraj 545176771Sraj pbuf = ptbl_buf_alloc(); 546176771Sraj if (pbuf == NULL) 547176771Sraj panic("pte_alloc: couldn't alloc kernel virtual memory"); 548187149Sraj 549187149Sraj ptbl = (pte_t *)pbuf->kva; 550176771Sraj 551187149Sraj CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 552187149Sraj 553176771Sraj /* Allocate ptbl pages, this will sleep! */ 554176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 555176771Sraj pidx = (PTBL_PAGES * pdir_idx) + i; 556187149Sraj while ((m = vm_page_alloc(NULL, pidx, 557187149Sraj VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 558187149Sraj 559176771Sraj PMAP_UNLOCK(pmap); 560176771Sraj vm_page_unlock_queues(); 561176771Sraj VM_WAIT; 562176771Sraj vm_page_lock_queues(); 563176771Sraj PMAP_LOCK(pmap); 564176771Sraj } 565176771Sraj mtbl[i] = m; 566176771Sraj } 567176771Sraj 568187149Sraj /* Map allocated pages into kernel_pmap. */ 569187149Sraj mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 570176771Sraj 571176771Sraj /* Zero whole ptbl. */ 572187149Sraj bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 573176771Sraj 574176771Sraj /* Add pbuf to the pmap ptbl bufs list. */ 575187149Sraj TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 576176771Sraj 577187149Sraj return (ptbl); 578176771Sraj} 579176771Sraj 580176771Sraj/* Free ptbl pages and invalidate pdir entry. */ 581176771Srajstatic void 582176771Srajptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 583176771Sraj{ 584176771Sraj pte_t *ptbl; 585176771Sraj vm_paddr_t pa; 586176771Sraj vm_offset_t va; 587176771Sraj vm_page_t m; 588176771Sraj int i; 589176771Sraj 590187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 591187149Sraj (pmap == kernel_pmap), pdir_idx); 592176771Sraj 593176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 594176771Sraj ("ptbl_free: invalid pdir_idx")); 595176771Sraj 596176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 597176771Sraj 598187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 599187149Sraj 600176771Sraj KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 601176771Sraj 602187149Sraj /* 603187149Sraj * Invalidate the pdir entry as soon as possible, so that other CPUs 604187149Sraj * don't attempt to look up the page tables we are releasing. 605187149Sraj */ 606187149Sraj mtx_lock_spin(&tlbivax_mutex); 607192532Sraj tlb_miss_lock(); 608187149Sraj 609187149Sraj pmap->pm_pdir[pdir_idx] = NULL; 610187149Sraj 611192532Sraj tlb_miss_unlock(); 612187149Sraj mtx_unlock_spin(&tlbivax_mutex); 613187149Sraj 614176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 615176771Sraj va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 616176771Sraj pa = pte_vatopa(mmu, kernel_pmap, va); 617176771Sraj m = PHYS_TO_VM_PAGE(pa); 618176771Sraj vm_page_free_zero(m); 619176771Sraj atomic_subtract_int(&cnt.v_wire_count, 1); 620176771Sraj mmu_booke_kremove(mmu, va); 621176771Sraj } 622176771Sraj 623176771Sraj ptbl_free_pmap_ptbl(pmap, ptbl); 624176771Sraj} 625176771Sraj 626176771Sraj/* 627176771Sraj * Decrement ptbl pages hold count and attempt to free ptbl pages. 628176771Sraj * Called when removing pte entry from ptbl. 629176771Sraj * 630176771Sraj * Return 1 if ptbl pages were freed. 631176771Sraj */ 632176771Srajstatic int 633176771Srajptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 634176771Sraj{ 635176771Sraj pte_t *ptbl; 636176771Sraj vm_paddr_t pa; 637176771Sraj vm_page_t m; 638176771Sraj int i; 639176771Sraj 640187151Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 641187151Sraj (pmap == kernel_pmap), pdir_idx); 642176771Sraj 643176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 644176771Sraj ("ptbl_unhold: invalid pdir_idx")); 645176771Sraj KASSERT((pmap != kernel_pmap), 646176771Sraj ("ptbl_unhold: unholding kernel ptbl!")); 647176771Sraj 648176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 649176771Sraj 650176771Sraj //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 651176771Sraj KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 652176771Sraj ("ptbl_unhold: non kva ptbl")); 653176771Sraj 654176771Sraj /* decrement hold count */ 655176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 656187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 657187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 658176771Sraj m = PHYS_TO_VM_PAGE(pa); 659176771Sraj m->wire_count--; 660176771Sraj } 661176771Sraj 662176771Sraj /* 663176771Sraj * Free ptbl pages if there are no pte etries in this ptbl. 664187151Sraj * wire_count has the same value for all ptbl pages, so check the last 665187151Sraj * page. 666176771Sraj */ 667176771Sraj if (m->wire_count == 0) { 668176771Sraj ptbl_free(mmu, pmap, pdir_idx); 669176771Sraj 670176771Sraj //debugf("ptbl_unhold: e (freed ptbl)\n"); 671176771Sraj return (1); 672176771Sraj } 673176771Sraj 674176771Sraj return (0); 675176771Sraj} 676176771Sraj 677176771Sraj/* 678187151Sraj * Increment hold count for ptbl pages. This routine is used when a new pte 679187151Sraj * entry is being inserted into the ptbl. 680176771Sraj */ 681176771Srajstatic void 682176771Srajptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 683176771Sraj{ 684176771Sraj vm_paddr_t pa; 685176771Sraj pte_t *ptbl; 686176771Sraj vm_page_t m; 687176771Sraj int i; 688176771Sraj 689187151Sraj CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 690187151Sraj pdir_idx); 691176771Sraj 692176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 693176771Sraj ("ptbl_hold: invalid pdir_idx")); 694176771Sraj KASSERT((pmap != kernel_pmap), 695176771Sraj ("ptbl_hold: holding kernel ptbl!")); 696176771Sraj 697176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 698176771Sraj 699176771Sraj KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 700176771Sraj 701176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 702187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 703187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 704176771Sraj m = PHYS_TO_VM_PAGE(pa); 705176771Sraj m->wire_count++; 706176771Sraj } 707176771Sraj} 708176771Sraj 709176771Sraj/* Allocate pv_entry structure. */ 710176771Srajpv_entry_t 711176771Srajpv_alloc(void) 712176771Sraj{ 713176771Sraj pv_entry_t pv; 714176771Sraj 715176771Sraj pv_entry_count++; 716194123Salc if (pv_entry_count > pv_entry_high_water) 717194123Salc pagedaemon_wakeup(); 718176771Sraj pv = uma_zalloc(pvzone, M_NOWAIT); 719176771Sraj 720176771Sraj return (pv); 721176771Sraj} 722176771Sraj 723176771Sraj/* Free pv_entry structure. */ 724176771Srajstatic __inline void 725176771Srajpv_free(pv_entry_t pve) 726176771Sraj{ 727176771Sraj 728176771Sraj pv_entry_count--; 729176771Sraj uma_zfree(pvzone, pve); 730176771Sraj} 731176771Sraj 732176771Sraj 733176771Sraj/* Allocate and initialize pv_entry structure. */ 734176771Srajstatic void 735176771Srajpv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 736176771Sraj{ 737176771Sraj pv_entry_t pve; 738176771Sraj 739176771Sraj //int su = (pmap == kernel_pmap); 740176771Sraj //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 741176771Sraj // (u_int32_t)pmap, va, (u_int32_t)m); 742176771Sraj 743176771Sraj pve = pv_alloc(); 744176771Sraj if (pve == NULL) 745176771Sraj panic("pv_insert: no pv entries!"); 746176771Sraj 747176771Sraj pve->pv_pmap = pmap; 748176771Sraj pve->pv_va = va; 749176771Sraj 750176771Sraj /* add to pv_list */ 751176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 752176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 753176771Sraj 754176771Sraj TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 755176771Sraj 756176771Sraj //debugf("pv_insert: e\n"); 757176771Sraj} 758176771Sraj 759176771Sraj/* Destroy pv entry. */ 760176771Srajstatic void 761176771Srajpv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 762176771Sraj{ 763176771Sraj pv_entry_t pve; 764176771Sraj 765176771Sraj //int su = (pmap == kernel_pmap); 766176771Sraj //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 767176771Sraj 768176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 769176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 770176771Sraj 771176771Sraj /* find pv entry */ 772176771Sraj TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 773176771Sraj if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 774176771Sraj /* remove from pv_list */ 775176771Sraj TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 776176771Sraj if (TAILQ_EMPTY(&m->md.pv_list)) 777176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 778176771Sraj 779176771Sraj /* free pv entry struct */ 780176771Sraj pv_free(pve); 781176771Sraj break; 782176771Sraj } 783176771Sraj } 784176771Sraj 785176771Sraj //debugf("pv_remove: e\n"); 786176771Sraj} 787176771Sraj 788176771Sraj/* 789176771Sraj * Clean pte entry, try to free page table page if requested. 790176771Sraj * 791176771Sraj * Return 1 if ptbl pages were freed, otherwise return 0. 792176771Sraj */ 793176771Srajstatic int 794187151Srajpte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 795176771Sraj{ 796176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 797176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 798176771Sraj vm_page_t m; 799176771Sraj pte_t *ptbl; 800176771Sraj pte_t *pte; 801176771Sraj 802176771Sraj //int su = (pmap == kernel_pmap); 803176771Sraj //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 804176771Sraj // su, (u_int32_t)pmap, va, flags); 805176771Sraj 806176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 807176771Sraj KASSERT(ptbl, ("pte_remove: null ptbl")); 808176771Sraj 809176771Sraj pte = &ptbl[ptbl_idx]; 810176771Sraj 811176771Sraj if (pte == NULL || !PTE_ISVALID(pte)) 812176771Sraj return (0); 813176771Sraj 814176771Sraj if (PTE_ISWIRED(pte)) 815176771Sraj pmap->pm_stats.wired_count--; 816176771Sraj 817191445Smarcel /* Handle managed entry. */ 818191445Smarcel if (PTE_ISMANAGED(pte)) { 819191445Smarcel /* Get vm_page_t for mapped pte. */ 820191445Smarcel m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 821176771Sraj 822191445Smarcel if (PTE_ISMODIFIED(pte)) 823191445Smarcel vm_page_dirty(m); 824176771Sraj 825191445Smarcel if (PTE_ISREFERENCED(pte)) 826191445Smarcel vm_page_flag_set(m, PG_REFERENCED); 827176771Sraj 828191445Smarcel pv_remove(pmap, va, m); 829176771Sraj } 830176771Sraj 831187149Sraj mtx_lock_spin(&tlbivax_mutex); 832192532Sraj tlb_miss_lock(); 833187149Sraj 834187149Sraj tlb0_flush_entry(va); 835176771Sraj pte->flags = 0; 836176771Sraj pte->rpn = 0; 837187149Sraj 838192532Sraj tlb_miss_unlock(); 839187149Sraj mtx_unlock_spin(&tlbivax_mutex); 840187149Sraj 841176771Sraj pmap->pm_stats.resident_count--; 842176771Sraj 843176771Sraj if (flags & PTBL_UNHOLD) { 844176771Sraj //debugf("pte_remove: e (unhold)\n"); 845176771Sraj return (ptbl_unhold(mmu, pmap, pdir_idx)); 846176771Sraj } 847176771Sraj 848176771Sraj //debugf("pte_remove: e\n"); 849176771Sraj return (0); 850176771Sraj} 851176771Sraj 852176771Sraj/* 853176771Sraj * Insert PTE for a given page and virtual address. 854176771Sraj */ 855187149Srajstatic void 856187149Srajpte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 857176771Sraj{ 858176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 859176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 860187149Sraj pte_t *ptbl, *pte; 861176771Sraj 862187149Sraj CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 863187149Sraj pmap == kernel_pmap, pmap, va); 864176771Sraj 865176771Sraj /* Get the page table pointer. */ 866176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 867176771Sraj 868187149Sraj if (ptbl == NULL) { 869187149Sraj /* Allocate page table pages. */ 870187149Sraj ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 871187149Sraj } else { 872176771Sraj /* 873176771Sraj * Check if there is valid mapping for requested 874176771Sraj * va, if there is, remove it. 875176771Sraj */ 876176771Sraj pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 877176771Sraj if (PTE_ISVALID(pte)) { 878176771Sraj pte_remove(mmu, pmap, va, PTBL_HOLD); 879176771Sraj } else { 880176771Sraj /* 881176771Sraj * pte is not used, increment hold count 882176771Sraj * for ptbl pages. 883176771Sraj */ 884176771Sraj if (pmap != kernel_pmap) 885176771Sraj ptbl_hold(mmu, pmap, pdir_idx); 886176771Sraj } 887176771Sraj } 888176771Sraj 889176771Sraj /* 890187149Sraj * Insert pv_entry into pv_list for mapped page if part of managed 891187149Sraj * memory. 892176771Sraj */ 893176771Sraj if ((m->flags & PG_FICTITIOUS) == 0) { 894176771Sraj if ((m->flags & PG_UNMANAGED) == 0) { 895187149Sraj flags |= PTE_MANAGED; 896176771Sraj 897176771Sraj /* Create and insert pv entry. */ 898176771Sraj pv_insert(pmap, va, m); 899176771Sraj } 900176771Sraj } 901176771Sraj 902176771Sraj pmap->pm_stats.resident_count++; 903187149Sraj 904187149Sraj mtx_lock_spin(&tlbivax_mutex); 905192532Sraj tlb_miss_lock(); 906187149Sraj 907187149Sraj tlb0_flush_entry(va); 908187149Sraj if (pmap->pm_pdir[pdir_idx] == NULL) { 909187149Sraj /* 910187149Sraj * If we just allocated a new page table, hook it in 911187149Sraj * the pdir. 912187149Sraj */ 913187149Sraj pmap->pm_pdir[pdir_idx] = ptbl; 914187149Sraj } 915187149Sraj pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 916176771Sraj pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 917176771Sraj pte->flags |= (PTE_VALID | flags); 918176771Sraj 919192532Sraj tlb_miss_unlock(); 920187149Sraj mtx_unlock_spin(&tlbivax_mutex); 921176771Sraj} 922176771Sraj 923176771Sraj/* Return the pa for the given pmap/va. */ 924176771Srajstatic vm_paddr_t 925176771Srajpte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 926176771Sraj{ 927176771Sraj vm_paddr_t pa = 0; 928176771Sraj pte_t *pte; 929176771Sraj 930176771Sraj pte = pte_find(mmu, pmap, va); 931176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 932176771Sraj pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 933176771Sraj return (pa); 934176771Sraj} 935176771Sraj 936176771Sraj/* Get a pointer to a PTE in a page table. */ 937176771Srajstatic pte_t * 938176771Srajpte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 939176771Sraj{ 940176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 941176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 942176771Sraj 943176771Sraj KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 944176771Sraj 945176771Sraj if (pmap->pm_pdir[pdir_idx]) 946176771Sraj return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 947176771Sraj 948176771Sraj return (NULL); 949176771Sraj} 950176771Sraj 951176771Sraj/**************************************************************************/ 952176771Sraj/* PMAP related */ 953176771Sraj/**************************************************************************/ 954176771Sraj 955176771Sraj/* 956176771Sraj * This is called during e500_init, before the system is really initialized. 957176771Sraj */ 958176771Srajstatic void 959190701Smarcelmmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 960176771Sraj{ 961176771Sraj vm_offset_t phys_kernelend; 962176771Sraj struct mem_region *mp, *mp1; 963176771Sraj int cnt, i, j; 964176771Sraj u_int s, e, sz; 965176771Sraj u_int phys_avail_count; 966182198Sraj vm_size_t physsz, hwphyssz, kstack0_sz; 967193489Sraj vm_offset_t kernel_pdir, kstack0, va; 968182198Sraj vm_paddr_t kstack0_phys; 969194784Sjeff void *dpcpu; 970193489Sraj pte_t *pte; 971176771Sraj 972176771Sraj debugf("mmu_booke_bootstrap: entered\n"); 973176771Sraj 974187149Sraj /* Initialize invalidation mutex */ 975187149Sraj mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 976187149Sraj 977187149Sraj /* Read TLB0 size and associativity. */ 978187149Sraj tlb0_get_tlbconf(); 979187149Sraj 980176771Sraj /* Align kernel start and end address (kernel image). */ 981190701Smarcel kernstart = trunc_page(start); 982190701Smarcel data_start = round_page(kernelend); 983190701Smarcel kernsize = data_start - kernstart; 984176771Sraj 985190701Smarcel data_end = data_start; 986190701Smarcel 987176771Sraj /* Allocate space for the message buffer. */ 988190701Smarcel msgbufp = (struct msgbuf *)data_end; 989190701Smarcel data_end += MSGBUF_SIZE; 990187149Sraj debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 991190701Smarcel data_end); 992176771Sraj 993190701Smarcel data_end = round_page(data_end); 994176771Sraj 995194784Sjeff /* Allocate the dynamic per-cpu area. */ 996194784Sjeff dpcpu = (void *)data_end; 997194784Sjeff data_end += DPCPU_SIZE; 998194784Sjeff dpcpu_init(dpcpu, 0); 999194784Sjeff 1000176771Sraj /* Allocate space for ptbl_bufs. */ 1001190701Smarcel ptbl_bufs = (struct ptbl_buf *)data_end; 1002190701Smarcel data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1003187149Sraj debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1004190701Smarcel data_end); 1005176771Sraj 1006190701Smarcel data_end = round_page(data_end); 1007176771Sraj 1008176771Sraj /* Allocate PTE tables for kernel KVA. */ 1009190701Smarcel kernel_pdir = data_end; 1010176771Sraj kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1011176771Sraj PDIR_SIZE - 1) / PDIR_SIZE; 1012190701Smarcel data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1013176771Sraj debugf(" kernel ptbls: %d\n", kernel_ptbls); 1014190701Smarcel debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1015176771Sraj 1016190701Smarcel debugf(" data_end: 0x%08x\n", data_end); 1017190701Smarcel if (data_end - kernstart > 0x1000000) { 1018190701Smarcel data_end = (data_end + 0x3fffff) & ~0x3fffff; 1019190701Smarcel tlb1_mapin_region(kernstart + 0x1000000, 1020190701Smarcel kernload + 0x1000000, data_end - kernstart - 0x1000000); 1021176771Sraj } else 1022190701Smarcel data_end = (data_end + 0xffffff) & ~0xffffff; 1023176771Sraj 1024190701Smarcel debugf(" updated data_end: 0x%08x\n", data_end); 1025187149Sraj 1026190701Smarcel kernsize += data_end - data_start; 1027190701Smarcel 1028182362Sraj /* 1029182362Sraj * Clear the structures - note we can only do it safely after the 1030187149Sraj * possible additional TLB1 translations are in place (above) so that 1031190701Smarcel * all range up to the currently calculated 'data_end' is covered. 1032182362Sraj */ 1033182362Sraj memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1034182362Sraj memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1035182362Sraj 1036176771Sraj /*******************************************************/ 1037176771Sraj /* Set the start and end of kva. */ 1038176771Sraj /*******************************************************/ 1039190701Smarcel virtual_avail = round_page(data_end); 1040176771Sraj virtual_end = VM_MAX_KERNEL_ADDRESS; 1041176771Sraj 1042176771Sraj /* Allocate KVA space for page zero/copy operations. */ 1043176771Sraj zero_page_va = virtual_avail; 1044176771Sraj virtual_avail += PAGE_SIZE; 1045176771Sraj zero_page_idle_va = virtual_avail; 1046176771Sraj virtual_avail += PAGE_SIZE; 1047176771Sraj copy_page_src_va = virtual_avail; 1048176771Sraj virtual_avail += PAGE_SIZE; 1049176771Sraj copy_page_dst_va = virtual_avail; 1050176771Sraj virtual_avail += PAGE_SIZE; 1051187149Sraj debugf("zero_page_va = 0x%08x\n", zero_page_va); 1052187149Sraj debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1053187149Sraj debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1054187149Sraj debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1055176771Sraj 1056176771Sraj /* Initialize page zero/copy mutexes. */ 1057176771Sraj mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1058176771Sraj mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1059176771Sraj 1060176771Sraj /* Allocate KVA space for ptbl bufs. */ 1061176771Sraj ptbl_buf_pool_vabase = virtual_avail; 1062176771Sraj virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1063187149Sraj debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1064187149Sraj ptbl_buf_pool_vabase, virtual_avail); 1065176771Sraj 1066176771Sraj /* Calculate corresponding physical addresses for the kernel region. */ 1067190701Smarcel phys_kernelend = kernload + kernsize; 1068176771Sraj debugf("kernel image and allocated data:\n"); 1069176771Sraj debugf(" kernload = 0x%08x\n", kernload); 1070190701Smarcel debugf(" kernstart = 0x%08x\n", kernstart); 1071190701Smarcel debugf(" kernsize = 0x%08x\n", kernsize); 1072176771Sraj 1073176771Sraj if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1074176771Sraj panic("mmu_booke_bootstrap: phys_avail too small"); 1075176771Sraj 1076176771Sraj /* 1077187151Sraj * Remove kernel physical address range from avail regions list. Page 1078187151Sraj * align all regions. Non-page aligned memory isn't very interesting 1079187151Sraj * to us. Also, sort the entries for ascending addresses. 1080176771Sraj */ 1081192067Snwhitehorn 1082192067Snwhitehorn /* Retrieve phys/avail mem regions */ 1083192067Snwhitehorn mem_regions(&physmem_regions, &physmem_regions_sz, 1084192067Snwhitehorn &availmem_regions, &availmem_regions_sz); 1085176771Sraj sz = 0; 1086176771Sraj cnt = availmem_regions_sz; 1087176771Sraj debugf("processing avail regions:\n"); 1088176771Sraj for (mp = availmem_regions; mp->mr_size; mp++) { 1089176771Sraj s = mp->mr_start; 1090176771Sraj e = mp->mr_start + mp->mr_size; 1091176771Sraj debugf(" %08x-%08x -> ", s, e); 1092176771Sraj /* Check whether this region holds all of the kernel. */ 1093176771Sraj if (s < kernload && e > phys_kernelend) { 1094176771Sraj availmem_regions[cnt].mr_start = phys_kernelend; 1095176771Sraj availmem_regions[cnt++].mr_size = e - phys_kernelend; 1096176771Sraj e = kernload; 1097176771Sraj } 1098176771Sraj /* Look whether this regions starts within the kernel. */ 1099176771Sraj if (s >= kernload && s < phys_kernelend) { 1100176771Sraj if (e <= phys_kernelend) 1101176771Sraj goto empty; 1102176771Sraj s = phys_kernelend; 1103176771Sraj } 1104176771Sraj /* Now look whether this region ends within the kernel. */ 1105176771Sraj if (e > kernload && e <= phys_kernelend) { 1106176771Sraj if (s >= kernload) 1107176771Sraj goto empty; 1108176771Sraj e = kernload; 1109176771Sraj } 1110176771Sraj /* Now page align the start and size of the region. */ 1111176771Sraj s = round_page(s); 1112176771Sraj e = trunc_page(e); 1113176771Sraj if (e < s) 1114176771Sraj e = s; 1115176771Sraj sz = e - s; 1116176771Sraj debugf("%08x-%08x = %x\n", s, e, sz); 1117176771Sraj 1118176771Sraj /* Check whether some memory is left here. */ 1119176771Sraj if (sz == 0) { 1120176771Sraj empty: 1121176771Sraj memmove(mp, mp + 1, 1122176771Sraj (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1123176771Sraj cnt--; 1124176771Sraj mp--; 1125176771Sraj continue; 1126176771Sraj } 1127176771Sraj 1128176771Sraj /* Do an insertion sort. */ 1129176771Sraj for (mp1 = availmem_regions; mp1 < mp; mp1++) 1130176771Sraj if (s < mp1->mr_start) 1131176771Sraj break; 1132176771Sraj if (mp1 < mp) { 1133176771Sraj memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1134176771Sraj mp1->mr_start = s; 1135176771Sraj mp1->mr_size = sz; 1136176771Sraj } else { 1137176771Sraj mp->mr_start = s; 1138176771Sraj mp->mr_size = sz; 1139176771Sraj } 1140176771Sraj } 1141176771Sraj availmem_regions_sz = cnt; 1142176771Sraj 1143176771Sraj /*******************************************************/ 1144182198Sraj /* Steal physical memory for kernel stack from the end */ 1145182198Sraj /* of the first avail region */ 1146182198Sraj /*******************************************************/ 1147182198Sraj kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1148182198Sraj kstack0_phys = availmem_regions[0].mr_start + 1149182198Sraj availmem_regions[0].mr_size; 1150182198Sraj kstack0_phys -= kstack0_sz; 1151182198Sraj availmem_regions[0].mr_size -= kstack0_sz; 1152182198Sraj 1153182198Sraj /*******************************************************/ 1154176771Sraj /* Fill in phys_avail table, based on availmem_regions */ 1155176771Sraj /*******************************************************/ 1156176771Sraj phys_avail_count = 0; 1157176771Sraj physsz = 0; 1158176771Sraj hwphyssz = 0; 1159176771Sraj TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1160176771Sraj 1161176771Sraj debugf("fill in phys_avail:\n"); 1162176771Sraj for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1163176771Sraj 1164176771Sraj debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1165176771Sraj availmem_regions[i].mr_start, 1166187151Sraj availmem_regions[i].mr_start + 1167187151Sraj availmem_regions[i].mr_size, 1168176771Sraj availmem_regions[i].mr_size); 1169176771Sraj 1170182362Sraj if (hwphyssz != 0 && 1171182362Sraj (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1172176771Sraj debugf(" hw.physmem adjust\n"); 1173176771Sraj if (physsz < hwphyssz) { 1174176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1175182362Sraj phys_avail[j + 1] = 1176182362Sraj availmem_regions[i].mr_start + 1177176771Sraj hwphyssz - physsz; 1178176771Sraj physsz = hwphyssz; 1179176771Sraj phys_avail_count++; 1180176771Sraj } 1181176771Sraj break; 1182176771Sraj } 1183176771Sraj 1184176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1185176771Sraj phys_avail[j + 1] = availmem_regions[i].mr_start + 1186176771Sraj availmem_regions[i].mr_size; 1187176771Sraj phys_avail_count++; 1188176771Sraj physsz += availmem_regions[i].mr_size; 1189176771Sraj } 1190176771Sraj physmem = btoc(physsz); 1191176771Sraj 1192176771Sraj /* Calculate the last available physical address. */ 1193176771Sraj for (i = 0; phys_avail[i + 2] != 0; i += 2) 1194176771Sraj ; 1195176771Sraj Maxmem = powerpc_btop(phys_avail[i + 1]); 1196176771Sraj 1197176771Sraj debugf("Maxmem = 0x%08lx\n", Maxmem); 1198176771Sraj debugf("phys_avail_count = %d\n", phys_avail_count); 1199187151Sraj debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1200187151Sraj physmem); 1201176771Sraj 1202176771Sraj /*******************************************************/ 1203176771Sraj /* Initialize (statically allocated) kernel pmap. */ 1204176771Sraj /*******************************************************/ 1205176771Sraj PMAP_LOCK_INIT(kernel_pmap); 1206176771Sraj kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1207176771Sraj 1208187149Sraj debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1209187149Sraj debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1210176771Sraj debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1211176771Sraj kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1212176771Sraj 1213176771Sraj /* Initialize kernel pdir */ 1214176771Sraj for (i = 0; i < kernel_ptbls; i++) 1215176771Sraj kernel_pmap->pm_pdir[kptbl_min + i] = 1216176771Sraj (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1217176771Sraj 1218187149Sraj for (i = 0; i < MAXCPU; i++) { 1219187149Sraj kernel_pmap->pm_tid[i] = TID_KERNEL; 1220187149Sraj 1221187149Sraj /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1222187149Sraj tidbusy[i][0] = kernel_pmap; 1223187149Sraj } 1224193489Sraj 1225193489Sraj /* 1226193489Sraj * Fill in PTEs covering kernel code and data. They are not required 1227193489Sraj * for address translation, as this area is covered by static TLB1 1228193489Sraj * entries, but for pte_vatopa() to work correctly with kernel area 1229193489Sraj * addresses. 1230193489Sraj */ 1231193489Sraj for (va = KERNBASE; va < data_end; va += PAGE_SIZE) { 1232193489Sraj pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1233193489Sraj pte->rpn = kernload + (va - KERNBASE); 1234193489Sraj pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1235193489Sraj PTE_VALID; 1236193489Sraj } 1237187149Sraj /* Mark kernel_pmap active on all CPUs */ 1238176771Sraj kernel_pmap->pm_active = ~0; 1239176771Sraj 1240176771Sraj /*******************************************************/ 1241176771Sraj /* Final setup */ 1242176771Sraj /*******************************************************/ 1243187149Sraj 1244182198Sraj /* Enter kstack0 into kernel map, provide guard page */ 1245182198Sraj kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1246182198Sraj thread0.td_kstack = kstack0; 1247182198Sraj thread0.td_kstack_pages = KSTACK_PAGES; 1248182198Sraj 1249182198Sraj debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1250182198Sraj debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1251182198Sraj kstack0_phys, kstack0_phys + kstack0_sz); 1252182198Sraj debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1253182198Sraj 1254182198Sraj virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1255182198Sraj for (i = 0; i < KSTACK_PAGES; i++) { 1256182198Sraj mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1257182198Sraj kstack0 += PAGE_SIZE; 1258182198Sraj kstack0_phys += PAGE_SIZE; 1259182198Sraj } 1260187149Sraj 1261187149Sraj debugf("virtual_avail = %08x\n", virtual_avail); 1262187149Sraj debugf("virtual_end = %08x\n", virtual_end); 1263182198Sraj 1264176771Sraj debugf("mmu_booke_bootstrap: exit\n"); 1265176771Sraj} 1266176771Sraj 1267192532Srajvoid 1268192532Srajpmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1269192532Sraj{ 1270192532Sraj int i; 1271192532Sraj 1272192532Sraj /* 1273192532Sraj * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1274192532Sraj * have the snapshot of its contents in the s/w tlb1[] table, so use 1275192532Sraj * these values directly to (re)program AP's TLB1 hardware. 1276192532Sraj */ 1277192532Sraj for (i = 0; i < tlb1_idx; i ++) { 1278192532Sraj /* Skip invalid entries */ 1279192532Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 1280192532Sraj continue; 1281192532Sraj 1282192532Sraj tlb1_write_entry(i); 1283192532Sraj } 1284192532Sraj 1285192532Sraj set_mas4_defaults(); 1286192532Sraj} 1287192532Sraj 1288176771Sraj/* 1289176771Sraj * Get the physical page address for the given pmap/virtual address. 1290176771Sraj */ 1291176771Srajstatic vm_paddr_t 1292176771Srajmmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1293176771Sraj{ 1294176771Sraj vm_paddr_t pa; 1295176771Sraj 1296176771Sraj PMAP_LOCK(pmap); 1297176771Sraj pa = pte_vatopa(mmu, pmap, va); 1298176771Sraj PMAP_UNLOCK(pmap); 1299176771Sraj 1300176771Sraj return (pa); 1301176771Sraj} 1302176771Sraj 1303176771Sraj/* 1304176771Sraj * Extract the physical page address associated with the given 1305176771Sraj * kernel virtual address. 1306176771Sraj */ 1307176771Srajstatic vm_paddr_t 1308176771Srajmmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1309176771Sraj{ 1310176771Sraj 1311176771Sraj return (pte_vatopa(mmu, kernel_pmap, va)); 1312176771Sraj} 1313176771Sraj 1314176771Sraj/* 1315176771Sraj * Initialize the pmap module. 1316176771Sraj * Called by vm_init, to initialize any structures that the pmap 1317176771Sraj * system needs to map virtual memory. 1318176771Sraj */ 1319176771Srajstatic void 1320176771Srajmmu_booke_init(mmu_t mmu) 1321176771Sraj{ 1322176771Sraj int shpgperproc = PMAP_SHPGPERPROC; 1323176771Sraj 1324176771Sraj /* 1325176771Sraj * Initialize the address space (zone) for the pv entries. Set a 1326176771Sraj * high water mark so that the system can recover from excessive 1327176771Sraj * numbers of pv entries. 1328176771Sraj */ 1329176771Sraj pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1330176771Sraj NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1331176771Sraj 1332176771Sraj TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1333176771Sraj pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1334176771Sraj 1335176771Sraj TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1336176771Sraj pv_entry_high_water = 9 * (pv_entry_max / 10); 1337176771Sraj 1338176771Sraj uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1339176771Sraj 1340176771Sraj /* Pre-fill pvzone with initial number of pv entries. */ 1341176771Sraj uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1342176771Sraj 1343176771Sraj /* Initialize ptbl allocation. */ 1344176771Sraj ptbl_init(); 1345176771Sraj} 1346176771Sraj 1347176771Sraj/* 1348176771Sraj * Map a list of wired pages into kernel virtual address space. This is 1349176771Sraj * intended for temporary mappings which do not need page modification or 1350176771Sraj * references recorded. Existing mappings in the region are overwritten. 1351176771Sraj */ 1352176771Srajstatic void 1353176771Srajmmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1354176771Sraj{ 1355176771Sraj vm_offset_t va; 1356176771Sraj 1357176771Sraj va = sva; 1358176771Sraj while (count-- > 0) { 1359176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1360176771Sraj va += PAGE_SIZE; 1361176771Sraj m++; 1362176771Sraj } 1363176771Sraj} 1364176771Sraj 1365176771Sraj/* 1366176771Sraj * Remove page mappings from kernel virtual address space. Intended for 1367176771Sraj * temporary mappings entered by mmu_booke_qenter. 1368176771Sraj */ 1369176771Srajstatic void 1370176771Srajmmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1371176771Sraj{ 1372176771Sraj vm_offset_t va; 1373176771Sraj 1374176771Sraj va = sva; 1375176771Sraj while (count-- > 0) { 1376176771Sraj mmu_booke_kremove(mmu, va); 1377176771Sraj va += PAGE_SIZE; 1378176771Sraj } 1379176771Sraj} 1380176771Sraj 1381176771Sraj/* 1382176771Sraj * Map a wired page into kernel virtual address space. 1383176771Sraj */ 1384176771Srajstatic void 1385176771Srajmmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1386176771Sraj{ 1387176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1388176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1389187151Sraj uint32_t flags; 1390176771Sraj pte_t *pte; 1391176771Sraj 1392187151Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1393187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1394176771Sraj 1395176771Sraj flags = 0; 1396176771Sraj flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1397187149Sraj flags |= PTE_M; 1398176771Sraj 1399176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1400176771Sraj 1401187149Sraj mtx_lock_spin(&tlbivax_mutex); 1402192532Sraj tlb_miss_lock(); 1403187149Sraj 1404176771Sraj if (PTE_ISVALID(pte)) { 1405187149Sraj 1406187149Sraj CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1407176771Sraj 1408176771Sraj /* Flush entry from TLB0 */ 1409187149Sraj tlb0_flush_entry(va); 1410176771Sraj } 1411176771Sraj 1412176771Sraj pte->rpn = pa & ~PTE_PA_MASK; 1413176771Sraj pte->flags = flags; 1414176771Sraj 1415176771Sraj //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1416176771Sraj // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1417176771Sraj // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1418176771Sraj 1419176771Sraj /* Flush the real memory from the instruction cache. */ 1420176771Sraj if ((flags & (PTE_I | PTE_G)) == 0) { 1421176771Sraj __syncicache((void *)va, PAGE_SIZE); 1422176771Sraj } 1423176771Sraj 1424192532Sraj tlb_miss_unlock(); 1425187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1426176771Sraj} 1427176771Sraj 1428176771Sraj/* 1429176771Sraj * Remove a page from kernel page table. 1430176771Sraj */ 1431176771Srajstatic void 1432176771Srajmmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1433176771Sraj{ 1434176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1435176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1436176771Sraj pte_t *pte; 1437176771Sraj 1438187149Sraj// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1439176771Sraj 1440187149Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1441187149Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1442176771Sraj ("mmu_booke_kremove: invalid va")); 1443176771Sraj 1444176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1445176771Sraj 1446176771Sraj if (!PTE_ISVALID(pte)) { 1447187149Sraj 1448187149Sraj CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1449187149Sraj 1450176771Sraj return; 1451176771Sraj } 1452176771Sraj 1453187149Sraj mtx_lock_spin(&tlbivax_mutex); 1454192532Sraj tlb_miss_lock(); 1455176771Sraj 1456187149Sraj /* Invalidate entry in TLB0, update PTE. */ 1457187149Sraj tlb0_flush_entry(va); 1458176771Sraj pte->flags = 0; 1459176771Sraj pte->rpn = 0; 1460176771Sraj 1461192532Sraj tlb_miss_unlock(); 1462187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1463176771Sraj} 1464176771Sraj 1465176771Sraj/* 1466176771Sraj * Initialize pmap associated with process 0. 1467176771Sraj */ 1468176771Srajstatic void 1469176771Srajmmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1470176771Sraj{ 1471187151Sraj 1472176771Sraj mmu_booke_pinit(mmu, pmap); 1473176771Sraj PCPU_SET(curpmap, pmap); 1474176771Sraj} 1475176771Sraj 1476176771Sraj/* 1477176771Sraj * Initialize a preallocated and zeroed pmap structure, 1478176771Sraj * such as one in a vmspace structure. 1479176771Sraj */ 1480176771Srajstatic void 1481176771Srajmmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1482176771Sraj{ 1483187149Sraj int i; 1484176771Sraj 1485187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1486187149Sraj curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1487176771Sraj 1488187149Sraj KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1489176771Sraj 1490176771Sraj PMAP_LOCK_INIT(pmap); 1491187149Sraj for (i = 0; i < MAXCPU; i++) 1492187149Sraj pmap->pm_tid[i] = TID_NONE; 1493176771Sraj pmap->pm_active = 0; 1494176771Sraj bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1495176771Sraj bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1496187149Sraj TAILQ_INIT(&pmap->pm_ptbl_list); 1497176771Sraj} 1498176771Sraj 1499176771Sraj/* 1500176771Sraj * Release any resources held by the given physical map. 1501176771Sraj * Called when a pmap initialized by mmu_booke_pinit is being released. 1502176771Sraj * Should only be called if the map contains no valid mappings. 1503176771Sraj */ 1504176771Srajstatic void 1505176771Srajmmu_booke_release(mmu_t mmu, pmap_t pmap) 1506176771Sraj{ 1507176771Sraj 1508187151Sraj printf("mmu_booke_release: s\n"); 1509176771Sraj 1510187151Sraj KASSERT(pmap->pm_stats.resident_count == 0, 1511187151Sraj ("pmap_release: pmap resident count %ld != 0", 1512187151Sraj pmap->pm_stats.resident_count)); 1513187151Sraj 1514176771Sraj PMAP_LOCK_DESTROY(pmap); 1515176771Sraj} 1516176771Sraj 1517176771Sraj/* 1518176771Sraj * Insert the given physical page at the specified virtual address in the 1519176771Sraj * target physical map with the protection requested. If specified the page 1520176771Sraj * will be wired down. 1521176771Sraj */ 1522176771Srajstatic void 1523176771Srajmmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1524176771Sraj vm_prot_t prot, boolean_t wired) 1525176771Sraj{ 1526187151Sraj 1527176771Sraj vm_page_lock_queues(); 1528176771Sraj PMAP_LOCK(pmap); 1529176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1530176771Sraj vm_page_unlock_queues(); 1531176771Sraj PMAP_UNLOCK(pmap); 1532176771Sraj} 1533176771Sraj 1534176771Srajstatic void 1535176771Srajmmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1536176771Sraj vm_prot_t prot, boolean_t wired) 1537176771Sraj{ 1538176771Sraj pte_t *pte; 1539176771Sraj vm_paddr_t pa; 1540187151Sraj uint32_t flags; 1541176771Sraj int su, sync; 1542176771Sraj 1543176771Sraj pa = VM_PAGE_TO_PHYS(m); 1544176771Sraj su = (pmap == kernel_pmap); 1545176771Sraj sync = 0; 1546176771Sraj 1547176771Sraj //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1548176771Sraj // "pa=0x%08x prot=0x%08x wired=%d)\n", 1549176771Sraj // (u_int32_t)pmap, su, pmap->pm_tid, 1550176771Sraj // (u_int32_t)m, va, pa, prot, wired); 1551176771Sraj 1552176771Sraj if (su) { 1553187151Sraj KASSERT(((va >= virtual_avail) && 1554187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1555187151Sraj ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1556176771Sraj } else { 1557176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1558187151Sraj ("mmu_booke_enter_locked: user pmap, non user va")); 1559176771Sraj } 1560176771Sraj 1561176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1562176771Sraj 1563176771Sraj /* 1564176771Sraj * If there is an existing mapping, and the physical address has not 1565176771Sraj * changed, must be protection or wiring change. 1566176771Sraj */ 1567176771Sraj if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1568176771Sraj (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1569187149Sraj 1570187149Sraj /* 1571187149Sraj * Before actually updating pte->flags we calculate and 1572187149Sraj * prepare its new value in a helper var. 1573187149Sraj */ 1574187149Sraj flags = pte->flags; 1575187149Sraj flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1576176771Sraj 1577176771Sraj /* Wiring change, just update stats. */ 1578176771Sraj if (wired) { 1579176771Sraj if (!PTE_ISWIRED(pte)) { 1580187149Sraj flags |= PTE_WIRED; 1581176771Sraj pmap->pm_stats.wired_count++; 1582176771Sraj } 1583176771Sraj } else { 1584176771Sraj if (PTE_ISWIRED(pte)) { 1585187149Sraj flags &= ~PTE_WIRED; 1586176771Sraj pmap->pm_stats.wired_count--; 1587176771Sraj } 1588176771Sraj } 1589176771Sraj 1590176771Sraj if (prot & VM_PROT_WRITE) { 1591176771Sraj /* Add write permissions. */ 1592187149Sraj flags |= PTE_SW; 1593176771Sraj if (!su) 1594187149Sraj flags |= PTE_UW; 1595192795Sraj 1596192795Sraj vm_page_flag_set(m, PG_WRITEABLE); 1597176771Sraj } else { 1598176771Sraj /* Handle modified pages, sense modify status. */ 1599187149Sraj 1600187149Sraj /* 1601187149Sraj * The PTE_MODIFIED flag could be set by underlying 1602187149Sraj * TLB misses since we last read it (above), possibly 1603187149Sraj * other CPUs could update it so we check in the PTE 1604187149Sraj * directly rather than rely on that saved local flags 1605187149Sraj * copy. 1606187149Sraj */ 1607178626Smarcel if (PTE_ISMODIFIED(pte)) 1608178626Smarcel vm_page_dirty(m); 1609176771Sraj } 1610176771Sraj 1611176771Sraj if (prot & VM_PROT_EXECUTE) { 1612187149Sraj flags |= PTE_SX; 1613176771Sraj if (!su) 1614187149Sraj flags |= PTE_UX; 1615176771Sraj 1616187149Sraj /* 1617187149Sraj * Check existing flags for execute permissions: if we 1618187149Sraj * are turning execute permissions on, icache should 1619187149Sraj * be flushed. 1620187149Sraj */ 1621176771Sraj if ((flags & (PTE_UX | PTE_SX)) == 0) 1622176771Sraj sync++; 1623176771Sraj } 1624176771Sraj 1625187149Sraj flags &= ~PTE_REFERENCED; 1626187149Sraj 1627187149Sraj /* 1628187149Sraj * The new flags value is all calculated -- only now actually 1629187149Sraj * update the PTE. 1630187149Sraj */ 1631187149Sraj mtx_lock_spin(&tlbivax_mutex); 1632192532Sraj tlb_miss_lock(); 1633187149Sraj 1634187149Sraj tlb0_flush_entry(va); 1635187149Sraj pte->flags = flags; 1636187149Sraj 1637192532Sraj tlb_miss_unlock(); 1638187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1639187149Sraj 1640176771Sraj } else { 1641176771Sraj /* 1642187149Sraj * If there is an existing mapping, but it's for a different 1643176771Sraj * physical address, pte_enter() will delete the old mapping. 1644176771Sraj */ 1645176771Sraj //if ((pte != NULL) && PTE_ISVALID(pte)) 1646176771Sraj // debugf("mmu_booke_enter_locked: replace\n"); 1647176771Sraj //else 1648176771Sraj // debugf("mmu_booke_enter_locked: new\n"); 1649176771Sraj 1650176771Sraj /* Now set up the flags and install the new mapping. */ 1651176771Sraj flags = (PTE_SR | PTE_VALID); 1652187149Sraj flags |= PTE_M; 1653176771Sraj 1654176771Sraj if (!su) 1655176771Sraj flags |= PTE_UR; 1656176771Sraj 1657176771Sraj if (prot & VM_PROT_WRITE) { 1658176771Sraj flags |= PTE_SW; 1659176771Sraj if (!su) 1660176771Sraj flags |= PTE_UW; 1661192795Sraj 1662192795Sraj vm_page_flag_set(m, PG_WRITEABLE); 1663176771Sraj } 1664176771Sraj 1665176771Sraj if (prot & VM_PROT_EXECUTE) { 1666176771Sraj flags |= PTE_SX; 1667176771Sraj if (!su) 1668176771Sraj flags |= PTE_UX; 1669176771Sraj } 1670176771Sraj 1671176771Sraj /* If its wired update stats. */ 1672176771Sraj if (wired) { 1673176771Sraj pmap->pm_stats.wired_count++; 1674176771Sraj flags |= PTE_WIRED; 1675176771Sraj } 1676176771Sraj 1677176771Sraj pte_enter(mmu, pmap, m, va, flags); 1678176771Sraj 1679176771Sraj /* Flush the real memory from the instruction cache. */ 1680176771Sraj if (prot & VM_PROT_EXECUTE) 1681176771Sraj sync++; 1682176771Sraj } 1683176771Sraj 1684176771Sraj if (sync && (su || pmap == PCPU_GET(curpmap))) { 1685176771Sraj __syncicache((void *)va, PAGE_SIZE); 1686176771Sraj sync = 0; 1687176771Sraj } 1688176771Sraj} 1689176771Sraj 1690176771Sraj/* 1691176771Sraj * Maps a sequence of resident pages belonging to the same object. 1692176771Sraj * The sequence begins with the given page m_start. This page is 1693176771Sraj * mapped at the given virtual address start. Each subsequent page is 1694176771Sraj * mapped at a virtual address that is offset from start by the same 1695176771Sraj * amount as the page is offset from m_start within the object. The 1696176771Sraj * last page in the sequence is the page with the largest offset from 1697176771Sraj * m_start that can be mapped at a virtual address less than the given 1698176771Sraj * virtual address end. Not every virtual page between start and end 1699176771Sraj * is mapped; only those for which a resident page exists with the 1700176771Sraj * corresponding offset from m_start are mapped. 1701176771Sraj */ 1702176771Srajstatic void 1703176771Srajmmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1704176771Sraj vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1705176771Sraj{ 1706176771Sraj vm_page_t m; 1707176771Sraj vm_pindex_t diff, psize; 1708176771Sraj 1709176771Sraj psize = atop(end - start); 1710176771Sraj m = m_start; 1711176771Sraj PMAP_LOCK(pmap); 1712176771Sraj while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1713187151Sraj mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1714187151Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1715176771Sraj m = TAILQ_NEXT(m, listq); 1716176771Sraj } 1717176771Sraj PMAP_UNLOCK(pmap); 1718176771Sraj} 1719176771Sraj 1720176771Srajstatic void 1721176771Srajmmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1722176771Sraj vm_prot_t prot) 1723176771Sraj{ 1724176771Sraj 1725176771Sraj PMAP_LOCK(pmap); 1726176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, 1727176771Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1728176771Sraj PMAP_UNLOCK(pmap); 1729176771Sraj} 1730176771Sraj 1731176771Sraj/* 1732176771Sraj * Remove the given range of addresses from the specified map. 1733176771Sraj * 1734176771Sraj * It is assumed that the start and end are properly rounded to the page size. 1735176771Sraj */ 1736176771Srajstatic void 1737176771Srajmmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1738176771Sraj{ 1739176771Sraj pte_t *pte; 1740187151Sraj uint8_t hold_flag; 1741176771Sraj 1742176771Sraj int su = (pmap == kernel_pmap); 1743176771Sraj 1744176771Sraj //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1745176771Sraj // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1746176771Sraj 1747176771Sraj if (su) { 1748187151Sraj KASSERT(((va >= virtual_avail) && 1749187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1750187151Sraj ("mmu_booke_remove: kernel pmap, non kernel va")); 1751176771Sraj } else { 1752176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1753187151Sraj ("mmu_booke_remove: user pmap, non user va")); 1754176771Sraj } 1755176771Sraj 1756176771Sraj if (PMAP_REMOVE_DONE(pmap)) { 1757176771Sraj //debugf("mmu_booke_remove: e (empty)\n"); 1758176771Sraj return; 1759176771Sraj } 1760176771Sraj 1761176771Sraj hold_flag = PTBL_HOLD_FLAG(pmap); 1762176771Sraj //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1763176771Sraj 1764176771Sraj vm_page_lock_queues(); 1765176771Sraj PMAP_LOCK(pmap); 1766176771Sraj for (; va < endva; va += PAGE_SIZE) { 1767176771Sraj pte = pte_find(mmu, pmap, va); 1768187149Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 1769176771Sraj pte_remove(mmu, pmap, va, hold_flag); 1770176771Sraj } 1771176771Sraj PMAP_UNLOCK(pmap); 1772176771Sraj vm_page_unlock_queues(); 1773176771Sraj 1774176771Sraj //debugf("mmu_booke_remove: e\n"); 1775176771Sraj} 1776176771Sraj 1777176771Sraj/* 1778176771Sraj * Remove physical page from all pmaps in which it resides. 1779176771Sraj */ 1780176771Srajstatic void 1781176771Srajmmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1782176771Sraj{ 1783176771Sraj pv_entry_t pv, pvn; 1784187151Sraj uint8_t hold_flag; 1785176771Sraj 1786176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1787176771Sraj 1788176771Sraj for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1789176771Sraj pvn = TAILQ_NEXT(pv, pv_link); 1790176771Sraj 1791176771Sraj PMAP_LOCK(pv->pv_pmap); 1792176771Sraj hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1793176771Sraj pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1794176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1795176771Sraj } 1796176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1797176771Sraj} 1798176771Sraj 1799176771Sraj/* 1800176771Sraj * Map a range of physical addresses into kernel virtual address space. 1801176771Sraj */ 1802176771Srajstatic vm_offset_t 1803176771Srajmmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1804176771Sraj vm_offset_t pa_end, int prot) 1805176771Sraj{ 1806176771Sraj vm_offset_t sva = *virt; 1807176771Sraj vm_offset_t va = sva; 1808176771Sraj 1809176771Sraj //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1810176771Sraj // sva, pa_start, pa_end); 1811176771Sraj 1812176771Sraj while (pa_start < pa_end) { 1813176771Sraj mmu_booke_kenter(mmu, va, pa_start); 1814176771Sraj va += PAGE_SIZE; 1815176771Sraj pa_start += PAGE_SIZE; 1816176771Sraj } 1817176771Sraj *virt = va; 1818176771Sraj 1819176771Sraj //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1820176771Sraj return (sva); 1821176771Sraj} 1822176771Sraj 1823176771Sraj/* 1824176771Sraj * The pmap must be activated before it's address space can be accessed in any 1825176771Sraj * way. 1826176771Sraj */ 1827176771Srajstatic void 1828176771Srajmmu_booke_activate(mmu_t mmu, struct thread *td) 1829176771Sraj{ 1830176771Sraj pmap_t pmap; 1831176771Sraj 1832176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1833176771Sraj 1834187149Sraj CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1835187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1836176771Sraj 1837176771Sraj KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1838176771Sraj 1839176771Sraj mtx_lock_spin(&sched_lock); 1840176771Sraj 1841187149Sraj atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 1842176771Sraj PCPU_SET(curpmap, pmap); 1843187149Sraj 1844187149Sraj if (pmap->pm_tid[PCPU_GET(cpuid)] == TID_NONE) 1845176771Sraj tid_alloc(pmap); 1846176771Sraj 1847176771Sraj /* Load PID0 register with pmap tid value. */ 1848187149Sraj mtspr(SPR_PID0, pmap->pm_tid[PCPU_GET(cpuid)]); 1849187149Sraj __asm __volatile("isync"); 1850176771Sraj 1851176771Sraj mtx_unlock_spin(&sched_lock); 1852176771Sraj 1853187149Sraj CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1854187149Sraj pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1855176771Sraj} 1856176771Sraj 1857176771Sraj/* 1858176771Sraj * Deactivate the specified process's address space. 1859176771Sraj */ 1860176771Srajstatic void 1861176771Srajmmu_booke_deactivate(mmu_t mmu, struct thread *td) 1862176771Sraj{ 1863176771Sraj pmap_t pmap; 1864176771Sraj 1865176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1866187149Sraj 1867187149Sraj CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1868187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1869187149Sraj 1870187149Sraj atomic_clear_int(&pmap->pm_active, PCPU_GET(cpumask)); 1871176771Sraj PCPU_SET(curpmap, NULL); 1872176771Sraj} 1873176771Sraj 1874176771Sraj/* 1875176771Sraj * Copy the range specified by src_addr/len 1876176771Sraj * from the source map to the range dst_addr/len 1877176771Sraj * in the destination map. 1878176771Sraj * 1879176771Sraj * This routine is only advisory and need not do anything. 1880176771Sraj */ 1881176771Srajstatic void 1882194101Srajmmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1883194101Sraj vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1884176771Sraj{ 1885176771Sraj 1886176771Sraj} 1887176771Sraj 1888176771Sraj/* 1889176771Sraj * Set the physical protection on the specified range of this map as requested. 1890176771Sraj */ 1891176771Srajstatic void 1892176771Srajmmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1893176771Sraj vm_prot_t prot) 1894176771Sraj{ 1895176771Sraj vm_offset_t va; 1896176771Sraj vm_page_t m; 1897176771Sraj pte_t *pte; 1898176771Sraj 1899176771Sraj if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1900176771Sraj mmu_booke_remove(mmu, pmap, sva, eva); 1901176771Sraj return; 1902176771Sraj } 1903176771Sraj 1904176771Sraj if (prot & VM_PROT_WRITE) 1905176771Sraj return; 1906176771Sraj 1907176771Sraj vm_page_lock_queues(); 1908176771Sraj PMAP_LOCK(pmap); 1909176771Sraj for (va = sva; va < eva; va += PAGE_SIZE) { 1910176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1911176771Sraj if (PTE_ISVALID(pte)) { 1912176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1913176771Sraj 1914187149Sraj mtx_lock_spin(&tlbivax_mutex); 1915192532Sraj tlb_miss_lock(); 1916187149Sraj 1917176771Sraj /* Handle modified pages. */ 1918178626Smarcel if (PTE_ISMODIFIED(pte)) 1919178626Smarcel vm_page_dirty(m); 1920176771Sraj 1921176771Sraj /* Referenced pages. */ 1922176771Sraj if (PTE_ISREFERENCED(pte)) 1923176771Sraj vm_page_flag_set(m, PG_REFERENCED); 1924176771Sraj 1925187149Sraj tlb0_flush_entry(va); 1926176771Sraj pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1927176771Sraj PTE_REFERENCED); 1928187149Sraj 1929192532Sraj tlb_miss_unlock(); 1930187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1931176771Sraj } 1932176771Sraj } 1933176771Sraj } 1934176771Sraj PMAP_UNLOCK(pmap); 1935176771Sraj vm_page_unlock_queues(); 1936176771Sraj} 1937176771Sraj 1938176771Sraj/* 1939176771Sraj * Clear the write and modified bits in each of the given page's mappings. 1940176771Sraj */ 1941176771Srajstatic void 1942176771Srajmmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1943176771Sraj{ 1944176771Sraj pv_entry_t pv; 1945176771Sraj pte_t *pte; 1946176771Sraj 1947176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1948176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1949176771Sraj (m->flags & PG_WRITEABLE) == 0) 1950176771Sraj return; 1951176771Sraj 1952176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1953176771Sraj PMAP_LOCK(pv->pv_pmap); 1954176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1955176771Sraj if (PTE_ISVALID(pte)) { 1956176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1957176771Sraj 1958187149Sraj mtx_lock_spin(&tlbivax_mutex); 1959192532Sraj tlb_miss_lock(); 1960187149Sraj 1961176771Sraj /* Handle modified pages. */ 1962178626Smarcel if (PTE_ISMODIFIED(pte)) 1963178626Smarcel vm_page_dirty(m); 1964176771Sraj 1965176771Sraj /* Referenced pages. */ 1966176771Sraj if (PTE_ISREFERENCED(pte)) 1967176771Sraj vm_page_flag_set(m, PG_REFERENCED); 1968176771Sraj 1969176771Sraj /* Flush mapping from TLB0. */ 1970176771Sraj pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1971176771Sraj PTE_REFERENCED); 1972187149Sraj 1973192532Sraj tlb_miss_unlock(); 1974187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1975176771Sraj } 1976176771Sraj } 1977176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1978176771Sraj } 1979176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1980176771Sraj} 1981176771Sraj 1982198341Smarcelstatic void 1983198341Smarcelmmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1984176771Sraj{ 1985176771Sraj pte_t *pte; 1986198341Smarcel pmap_t pmap; 1987198341Smarcel vm_page_t m; 1988198341Smarcel vm_offset_t addr; 1989198341Smarcel vm_paddr_t pa; 1990198341Smarcel int active, valid; 1991198341Smarcel 1992198341Smarcel va = trunc_page(va); 1993198341Smarcel sz = round_page(sz); 1994176771Sraj 1995198341Smarcel vm_page_lock_queues(); 1996198341Smarcel pmap = PCPU_GET(curpmap); 1997198341Smarcel active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 1998198341Smarcel while (sz > 0) { 1999198341Smarcel PMAP_LOCK(pm); 2000198341Smarcel pte = pte_find(mmu, pm, va); 2001198341Smarcel valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2002198341Smarcel if (valid) 2003198341Smarcel pa = PTE_PA(pte); 2004198341Smarcel PMAP_UNLOCK(pm); 2005198341Smarcel if (valid) { 2006198341Smarcel if (!active) { 2007198341Smarcel /* Create a mapping in the active pmap. */ 2008198341Smarcel addr = 0; 2009198341Smarcel m = PHYS_TO_VM_PAGE(pa); 2010198341Smarcel PMAP_LOCK(pmap); 2011198341Smarcel pte_enter(mmu, pmap, m, addr, 2012198341Smarcel PTE_SR | PTE_VALID | PTE_UR); 2013198341Smarcel __syncicache((void *)addr, PAGE_SIZE); 2014198341Smarcel pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2015198341Smarcel PMAP_UNLOCK(pmap); 2016198341Smarcel } else 2017198341Smarcel __syncicache((void *)va, PAGE_SIZE); 2018198341Smarcel } 2019198341Smarcel va += PAGE_SIZE; 2020198341Smarcel sz -= PAGE_SIZE; 2021176771Sraj } 2022198341Smarcel vm_page_unlock_queues(); 2023176771Sraj} 2024176771Sraj 2025176771Sraj/* 2026176771Sraj * Atomically extract and hold the physical page with the given 2027176771Sraj * pmap and virtual address pair if that mapping permits the given 2028176771Sraj * protection. 2029176771Sraj */ 2030176771Srajstatic vm_page_t 2031176771Srajmmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2032176771Sraj vm_prot_t prot) 2033176771Sraj{ 2034176771Sraj pte_t *pte; 2035176771Sraj vm_page_t m; 2036187151Sraj uint32_t pte_wbit; 2037176771Sraj 2038176771Sraj m = NULL; 2039176771Sraj vm_page_lock_queues(); 2040176771Sraj PMAP_LOCK(pmap); 2041187151Sraj 2042176771Sraj pte = pte_find(mmu, pmap, va); 2043176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) { 2044176771Sraj if (pmap == kernel_pmap) 2045176771Sraj pte_wbit = PTE_SW; 2046176771Sraj else 2047176771Sraj pte_wbit = PTE_UW; 2048176771Sraj 2049176771Sraj if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2050176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2051176771Sraj vm_page_hold(m); 2052176771Sraj } 2053176771Sraj } 2054176771Sraj 2055176771Sraj vm_page_unlock_queues(); 2056176771Sraj PMAP_UNLOCK(pmap); 2057176771Sraj return (m); 2058176771Sraj} 2059176771Sraj 2060176771Sraj/* 2061176771Sraj * Initialize a vm_page's machine-dependent fields. 2062176771Sraj */ 2063176771Srajstatic void 2064176771Srajmmu_booke_page_init(mmu_t mmu, vm_page_t m) 2065176771Sraj{ 2066176771Sraj 2067176771Sraj TAILQ_INIT(&m->md.pv_list); 2068176771Sraj} 2069176771Sraj 2070176771Sraj/* 2071176771Sraj * mmu_booke_zero_page_area zeros the specified hardware page by 2072176771Sraj * mapping it into virtual memory and using bzero to clear 2073176771Sraj * its contents. 2074176771Sraj * 2075176771Sraj * off and size must reside within a single page. 2076176771Sraj */ 2077176771Srajstatic void 2078176771Srajmmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2079176771Sraj{ 2080176771Sraj vm_offset_t va; 2081176771Sraj 2082187151Sraj /* XXX KASSERT off and size are within a single page? */ 2083176771Sraj 2084176771Sraj mtx_lock(&zero_page_mutex); 2085176771Sraj va = zero_page_va; 2086176771Sraj 2087176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2088176771Sraj bzero((caddr_t)va + off, size); 2089176771Sraj mmu_booke_kremove(mmu, va); 2090176771Sraj 2091176771Sraj mtx_unlock(&zero_page_mutex); 2092176771Sraj} 2093176771Sraj 2094176771Sraj/* 2095176771Sraj * mmu_booke_zero_page zeros the specified hardware page. 2096176771Sraj */ 2097176771Srajstatic void 2098176771Srajmmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2099176771Sraj{ 2100176771Sraj 2101176771Sraj mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2102176771Sraj} 2103176771Sraj 2104176771Sraj/* 2105176771Sraj * mmu_booke_copy_page copies the specified (machine independent) page by 2106176771Sraj * mapping the page into virtual memory and using memcopy to copy the page, 2107176771Sraj * one machine dependent page at a time. 2108176771Sraj */ 2109176771Srajstatic void 2110176771Srajmmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2111176771Sraj{ 2112176771Sraj vm_offset_t sva, dva; 2113176771Sraj 2114176771Sraj sva = copy_page_src_va; 2115176771Sraj dva = copy_page_dst_va; 2116176771Sraj 2117187149Sraj mtx_lock(©_page_mutex); 2118176771Sraj mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2119176771Sraj mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2120176771Sraj memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2121176771Sraj mmu_booke_kremove(mmu, dva); 2122176771Sraj mmu_booke_kremove(mmu, sva); 2123176771Sraj mtx_unlock(©_page_mutex); 2124176771Sraj} 2125176771Sraj 2126176771Sraj/* 2127176771Sraj * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2128176771Sraj * into virtual memory and using bzero to clear its contents. This is intended 2129176771Sraj * to be called from the vm_pagezero process only and outside of Giant. No 2130176771Sraj * lock is required. 2131176771Sraj */ 2132176771Srajstatic void 2133176771Srajmmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2134176771Sraj{ 2135176771Sraj vm_offset_t va; 2136176771Sraj 2137176771Sraj va = zero_page_idle_va; 2138176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2139176771Sraj bzero((caddr_t)va, PAGE_SIZE); 2140176771Sraj mmu_booke_kremove(mmu, va); 2141176771Sraj} 2142176771Sraj 2143176771Sraj/* 2144176771Sraj * Return whether or not the specified physical page was modified 2145176771Sraj * in any of physical maps. 2146176771Sraj */ 2147176771Srajstatic boolean_t 2148176771Srajmmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2149176771Sraj{ 2150176771Sraj pte_t *pte; 2151176771Sraj pv_entry_t pv; 2152176771Sraj 2153176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2154176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2155176771Sraj return (FALSE); 2156176771Sraj 2157176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2158176771Sraj PMAP_LOCK(pv->pv_pmap); 2159176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2160176771Sraj if (!PTE_ISVALID(pte)) 2161176771Sraj goto make_sure_to_unlock; 2162176771Sraj 2163176771Sraj if (PTE_ISMODIFIED(pte)) { 2164176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2165176771Sraj return (TRUE); 2166176771Sraj } 2167176771Sraj } 2168176771Srajmake_sure_to_unlock: 2169176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2170176771Sraj } 2171176771Sraj return (FALSE); 2172176771Sraj} 2173176771Sraj 2174176771Sraj/* 2175187151Sraj * Return whether or not the specified virtual address is eligible 2176176771Sraj * for prefault. 2177176771Sraj */ 2178176771Srajstatic boolean_t 2179176771Srajmmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2180176771Sraj{ 2181176771Sraj 2182176771Sraj return (FALSE); 2183176771Sraj} 2184176771Sraj 2185176771Sraj/* 2186207155Salc * Return whether or not the specified physical page was referenced 2187207155Salc * in any physical maps. 2188207155Salc */ 2189207155Salcstatic boolean_t 2190207155Salcmmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2191207155Salc{ 2192207155Salc pte_t *pte; 2193207155Salc pv_entry_t pv; 2194207155Salc boolean_t rv; 2195207155Salc 2196207155Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2197207155Salc rv = FALSE; 2198207155Salc if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2199207155Salc return (rv); 2200207155Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2201207155Salc PMAP_LOCK(pv->pv_pmap); 2202207155Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2203207155Salc PTE_ISVALID(pte)) 2204207155Salc rv = PTE_ISREFERENCED(pte) ? TRUE : FALSE; 2205207155Salc PMAP_UNLOCK(pv->pv_pmap); 2206207155Salc if (rv) 2207207155Salc break; 2208207155Salc } 2209207155Salc return (rv); 2210207155Salc} 2211207155Salc 2212207155Salc/* 2213176771Sraj * Clear the modify bits on the specified physical page. 2214176771Sraj */ 2215176771Srajstatic void 2216176771Srajmmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2217176771Sraj{ 2218176771Sraj pte_t *pte; 2219176771Sraj pv_entry_t pv; 2220176771Sraj 2221176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2222176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2223176771Sraj return; 2224176771Sraj 2225176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2226176771Sraj PMAP_LOCK(pv->pv_pmap); 2227176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2228176771Sraj if (!PTE_ISVALID(pte)) 2229176771Sraj goto make_sure_to_unlock; 2230176771Sraj 2231187149Sraj mtx_lock_spin(&tlbivax_mutex); 2232192532Sraj tlb_miss_lock(); 2233187149Sraj 2234176771Sraj if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2235187149Sraj tlb0_flush_entry(pv->pv_va); 2236176771Sraj pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2237176771Sraj PTE_REFERENCED); 2238176771Sraj } 2239187149Sraj 2240192532Sraj tlb_miss_unlock(); 2241187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2242176771Sraj } 2243176771Srajmake_sure_to_unlock: 2244176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2245176771Sraj } 2246176771Sraj} 2247176771Sraj 2248176771Sraj/* 2249176771Sraj * Return a count of reference bits for a page, clearing those bits. 2250176771Sraj * It is not necessary for every reference bit to be cleared, but it 2251176771Sraj * is necessary that 0 only be returned when there are truly no 2252176771Sraj * reference bits set. 2253176771Sraj * 2254176771Sraj * XXX: The exact number of bits to check and clear is a matter that 2255176771Sraj * should be tested and standardized at some point in the future for 2256176771Sraj * optimal aging of shared pages. 2257176771Sraj */ 2258176771Srajstatic int 2259176771Srajmmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2260176771Sraj{ 2261176771Sraj pte_t *pte; 2262176771Sraj pv_entry_t pv; 2263176771Sraj int count; 2264176771Sraj 2265176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2266176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2267176771Sraj return (0); 2268176771Sraj 2269176771Sraj count = 0; 2270176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2271176771Sraj PMAP_LOCK(pv->pv_pmap); 2272176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2273176771Sraj if (!PTE_ISVALID(pte)) 2274176771Sraj goto make_sure_to_unlock; 2275176771Sraj 2276176771Sraj if (PTE_ISREFERENCED(pte)) { 2277187149Sraj mtx_lock_spin(&tlbivax_mutex); 2278192532Sraj tlb_miss_lock(); 2279187149Sraj 2280187149Sraj tlb0_flush_entry(pv->pv_va); 2281176771Sraj pte->flags &= ~PTE_REFERENCED; 2282176771Sraj 2283192532Sraj tlb_miss_unlock(); 2284187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2285187149Sraj 2286176771Sraj if (++count > 4) { 2287176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2288176771Sraj break; 2289176771Sraj } 2290176771Sraj } 2291176771Sraj } 2292176771Srajmake_sure_to_unlock: 2293176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2294176771Sraj } 2295176771Sraj return (count); 2296176771Sraj} 2297176771Sraj 2298176771Sraj/* 2299176771Sraj * Clear the reference bit on the specified physical page. 2300176771Sraj */ 2301176771Srajstatic void 2302176771Srajmmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2303176771Sraj{ 2304176771Sraj pte_t *pte; 2305176771Sraj pv_entry_t pv; 2306176771Sraj 2307176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2308176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2309176771Sraj return; 2310176771Sraj 2311176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2312176771Sraj PMAP_LOCK(pv->pv_pmap); 2313176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2314176771Sraj if (!PTE_ISVALID(pte)) 2315176771Sraj goto make_sure_to_unlock; 2316176771Sraj 2317176771Sraj if (PTE_ISREFERENCED(pte)) { 2318187149Sraj mtx_lock_spin(&tlbivax_mutex); 2319192532Sraj tlb_miss_lock(); 2320187149Sraj 2321187149Sraj tlb0_flush_entry(pv->pv_va); 2322176771Sraj pte->flags &= ~PTE_REFERENCED; 2323187149Sraj 2324192532Sraj tlb_miss_unlock(); 2325187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2326176771Sraj } 2327176771Sraj } 2328176771Srajmake_sure_to_unlock: 2329176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2330176771Sraj } 2331176771Sraj} 2332176771Sraj 2333176771Sraj/* 2334176771Sraj * Change wiring attribute for a map/virtual-address pair. 2335176771Sraj */ 2336176771Srajstatic void 2337176771Srajmmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2338176771Sraj{ 2339201758Smbr pte_t *pte; 2340176771Sraj 2341176771Sraj PMAP_LOCK(pmap); 2342176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2343176771Sraj if (wired) { 2344176771Sraj if (!PTE_ISWIRED(pte)) { 2345176771Sraj pte->flags |= PTE_WIRED; 2346176771Sraj pmap->pm_stats.wired_count++; 2347176771Sraj } 2348176771Sraj } else { 2349176771Sraj if (PTE_ISWIRED(pte)) { 2350176771Sraj pte->flags &= ~PTE_WIRED; 2351176771Sraj pmap->pm_stats.wired_count--; 2352176771Sraj } 2353176771Sraj } 2354176771Sraj } 2355176771Sraj PMAP_UNLOCK(pmap); 2356176771Sraj} 2357176771Sraj 2358176771Sraj/* 2359176771Sraj * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2360176771Sraj * page. This count may be changed upwards or downwards in the future; it is 2361176771Sraj * only necessary that true be returned for a small subset of pmaps for proper 2362176771Sraj * page aging. 2363176771Sraj */ 2364176771Srajstatic boolean_t 2365176771Srajmmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2366176771Sraj{ 2367176771Sraj pv_entry_t pv; 2368176771Sraj int loops; 2369176771Sraj 2370176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2371176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2372176771Sraj return (FALSE); 2373176771Sraj 2374176771Sraj loops = 0; 2375176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2376176771Sraj if (pv->pv_pmap == pmap) 2377176771Sraj return (TRUE); 2378176771Sraj 2379176771Sraj if (++loops >= 16) 2380176771Sraj break; 2381176771Sraj } 2382176771Sraj return (FALSE); 2383176771Sraj} 2384176771Sraj 2385176771Sraj/* 2386176771Sraj * Return the number of managed mappings to the given physical page that are 2387176771Sraj * wired. 2388176771Sraj */ 2389176771Srajstatic int 2390176771Srajmmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2391176771Sraj{ 2392176771Sraj pv_entry_t pv; 2393176771Sraj pte_t *pte; 2394176771Sraj int count = 0; 2395176771Sraj 2396176771Sraj if ((m->flags & PG_FICTITIOUS) != 0) 2397176771Sraj return (count); 2398176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2399176771Sraj 2400176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2401176771Sraj PMAP_LOCK(pv->pv_pmap); 2402176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2403176771Sraj if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2404176771Sraj count++; 2405176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2406176771Sraj } 2407176771Sraj 2408176771Sraj return (count); 2409176771Sraj} 2410176771Sraj 2411176771Srajstatic int 2412176771Srajmmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2413176771Sraj{ 2414176771Sraj int i; 2415176771Sraj vm_offset_t va; 2416176771Sraj 2417176771Sraj /* 2418176771Sraj * This currently does not work for entries that 2419176771Sraj * overlap TLB1 entries. 2420176771Sraj */ 2421176771Sraj for (i = 0; i < tlb1_idx; i ++) { 2422176771Sraj if (tlb1_iomapped(i, pa, size, &va) == 0) 2423176771Sraj return (0); 2424176771Sraj } 2425176771Sraj 2426176771Sraj return (EFAULT); 2427176771Sraj} 2428176771Sraj 2429190701Smarcelvm_offset_t 2430190701Smarcelmmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2431190701Smarcel vm_size_t *sz) 2432190701Smarcel{ 2433190701Smarcel vm_paddr_t pa, ppa; 2434190701Smarcel vm_offset_t va; 2435190701Smarcel vm_size_t gran; 2436190701Smarcel 2437190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2438190701Smarcel if (md->md_vaddr == ~0UL) { 2439190701Smarcel /* We always map a 256MB page at 256M. */ 2440190701Smarcel gran = 256 * 1024 * 1024; 2441190701Smarcel pa = md->md_paddr + ofs; 2442190701Smarcel ppa = pa & ~(gran - 1); 2443190701Smarcel ofs = pa - ppa; 2444190701Smarcel va = gran; 2445190701Smarcel tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2446190701Smarcel if (*sz > (gran - ofs)) 2447190701Smarcel *sz = gran - ofs; 2448190701Smarcel return (va + ofs); 2449190701Smarcel } 2450190701Smarcel 2451190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2452190701Smarcel va = md->md_vaddr + ofs; 2453190701Smarcel if (va >= kernstart + kernsize) { 2454190701Smarcel gran = PAGE_SIZE - (va & PAGE_MASK); 2455190701Smarcel if (*sz > gran) 2456190701Smarcel *sz = gran; 2457190701Smarcel } 2458190701Smarcel return (va); 2459190701Smarcel} 2460190701Smarcel 2461190701Smarcelvoid 2462190701Smarcelmmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2463190701Smarcel vm_offset_t va) 2464190701Smarcel{ 2465190701Smarcel 2466190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2467190701Smarcel if (md->md_vaddr == ~0UL) { 2468190701Smarcel tlb1_idx--; 2469190701Smarcel tlb1[tlb1_idx].mas1 = 0; 2470190701Smarcel tlb1[tlb1_idx].mas2 = 0; 2471190701Smarcel tlb1[tlb1_idx].mas3 = 0; 2472190701Smarcel tlb1_write_entry(tlb1_idx); 2473190701Smarcel return; 2474190701Smarcel } 2475190701Smarcel 2476190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2477190701Smarcel /* Nothing to do... */ 2478190701Smarcel} 2479190701Smarcel 2480190701Smarcelstruct pmap_md * 2481190701Smarcelmmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2482190701Smarcel{ 2483190701Smarcel static struct pmap_md md; 2484190701Smarcel struct bi_mem_region *mr; 2485190701Smarcel pte_t *pte; 2486190701Smarcel vm_offset_t va; 2487190701Smarcel 2488190701Smarcel if (dumpsys_minidump) { 2489190701Smarcel md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2490190701Smarcel if (prev == NULL) { 2491190701Smarcel /* 1st: kernel .data and .bss. */ 2492190701Smarcel md.md_index = 1; 2493190701Smarcel md.md_vaddr = trunc_page((uintptr_t)_etext); 2494190701Smarcel md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2495190701Smarcel return (&md); 2496190701Smarcel } 2497190701Smarcel switch (prev->md_index) { 2498190701Smarcel case 1: 2499190701Smarcel /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2500190701Smarcel md.md_index = 2; 2501190701Smarcel md.md_vaddr = data_start; 2502190701Smarcel md.md_size = data_end - data_start; 2503190701Smarcel break; 2504190701Smarcel case 2: 2505190701Smarcel /* 3rd: kernel VM. */ 2506190701Smarcel va = prev->md_vaddr + prev->md_size; 2507190701Smarcel /* Find start of next chunk (from va). */ 2508190701Smarcel while (va < virtual_end) { 2509190701Smarcel /* Don't dump the buffer cache. */ 2510190701Smarcel if (va >= kmi.buffer_sva && 2511190701Smarcel va < kmi.buffer_eva) { 2512190701Smarcel va = kmi.buffer_eva; 2513190701Smarcel continue; 2514190701Smarcel } 2515190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2516190701Smarcel if (pte != NULL && PTE_ISVALID(pte)) 2517190701Smarcel break; 2518190701Smarcel va += PAGE_SIZE; 2519190701Smarcel } 2520190701Smarcel if (va < virtual_end) { 2521190701Smarcel md.md_vaddr = va; 2522190701Smarcel va += PAGE_SIZE; 2523190701Smarcel /* Find last page in chunk. */ 2524190701Smarcel while (va < virtual_end) { 2525190701Smarcel /* Don't run into the buffer cache. */ 2526190701Smarcel if (va == kmi.buffer_sva) 2527190701Smarcel break; 2528190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2529190701Smarcel if (pte == NULL || !PTE_ISVALID(pte)) 2530190701Smarcel break; 2531190701Smarcel va += PAGE_SIZE; 2532190701Smarcel } 2533190701Smarcel md.md_size = va - md.md_vaddr; 2534190701Smarcel break; 2535190701Smarcel } 2536190701Smarcel md.md_index = 3; 2537190701Smarcel /* FALLTHROUGH */ 2538190701Smarcel default: 2539190701Smarcel return (NULL); 2540190701Smarcel } 2541190701Smarcel } else { /* minidumps */ 2542190701Smarcel mr = bootinfo_mr(); 2543190701Smarcel if (prev == NULL) { 2544190701Smarcel /* first physical chunk. */ 2545190701Smarcel md.md_paddr = mr->mem_base; 2546190701Smarcel md.md_size = mr->mem_size; 2547190701Smarcel md.md_vaddr = ~0UL; 2548190701Smarcel md.md_index = 1; 2549190701Smarcel } else if (md.md_index < bootinfo->bi_mem_reg_no) { 2550190701Smarcel md.md_paddr = mr[md.md_index].mem_base; 2551190701Smarcel md.md_size = mr[md.md_index].mem_size; 2552190701Smarcel md.md_vaddr = ~0UL; 2553190701Smarcel md.md_index++; 2554190701Smarcel } else { 2555190701Smarcel /* There's no next physical chunk. */ 2556190701Smarcel return (NULL); 2557190701Smarcel } 2558190701Smarcel } 2559190701Smarcel 2560190701Smarcel return (&md); 2561190701Smarcel} 2562190701Smarcel 2563176771Sraj/* 2564176771Sraj * Map a set of physical memory pages into the kernel virtual address space. 2565176771Sraj * Return a pointer to where it is mapped. This routine is intended to be used 2566176771Sraj * for mapping device memory, NOT real memory. 2567176771Sraj */ 2568176771Srajstatic void * 2569176771Srajmmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2570176771Sraj{ 2571184244Smarcel void *res; 2572176771Sraj uintptr_t va; 2573184244Smarcel vm_size_t sz; 2574176771Sraj 2575176771Sraj va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2576184244Smarcel res = (void *)va; 2577184244Smarcel 2578184244Smarcel do { 2579184244Smarcel sz = 1 << (ilog2(size) & ~1); 2580184244Smarcel if (bootverbose) 2581184244Smarcel printf("Wiring VA=%x to PA=%x (size=%x), " 2582184244Smarcel "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2583184244Smarcel tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2584184244Smarcel size -= sz; 2585184244Smarcel pa += sz; 2586184244Smarcel va += sz; 2587184244Smarcel } while (size > 0); 2588184244Smarcel 2589184244Smarcel return (res); 2590176771Sraj} 2591176771Sraj 2592176771Sraj/* 2593176771Sraj * 'Unmap' a range mapped by mmu_booke_mapdev(). 2594176771Sraj */ 2595176771Srajstatic void 2596176771Srajmmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2597176771Sraj{ 2598176771Sraj vm_offset_t base, offset; 2599176771Sraj 2600176771Sraj /* 2601176771Sraj * Unmap only if this is inside kernel virtual space. 2602176771Sraj */ 2603176771Sraj if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2604176771Sraj base = trunc_page(va); 2605176771Sraj offset = va & PAGE_MASK; 2606176771Sraj size = roundup(offset + size, PAGE_SIZE); 2607176771Sraj kmem_free(kernel_map, base, size); 2608176771Sraj } 2609176771Sraj} 2610176771Sraj 2611176771Sraj/* 2612187151Sraj * mmu_booke_object_init_pt preloads the ptes for a given object into the 2613187151Sraj * specified pmap. This eliminates the blast of soft faults on process startup 2614187151Sraj * and immediately after an mmap. 2615176771Sraj */ 2616176771Srajstatic void 2617176771Srajmmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2618176771Sraj vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2619176771Sraj{ 2620187151Sraj 2621176771Sraj VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2622195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2623176771Sraj ("mmu_booke_object_init_pt: non-device object")); 2624176771Sraj} 2625176771Sraj 2626176771Sraj/* 2627176771Sraj * Perform the pmap work for mincore. 2628176771Sraj */ 2629176771Srajstatic int 2630176771Srajmmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2631176771Sraj{ 2632176771Sraj 2633176771Sraj TODO; 2634176771Sraj return (0); 2635176771Sraj} 2636176771Sraj 2637176771Sraj/**************************************************************************/ 2638176771Sraj/* TID handling */ 2639176771Sraj/**************************************************************************/ 2640176771Sraj 2641176771Sraj/* 2642176771Sraj * Allocate a TID. If necessary, steal one from someone else. 2643176771Sraj * The new TID is flushed from the TLB before returning. 2644176771Sraj */ 2645176771Srajstatic tlbtid_t 2646176771Srajtid_alloc(pmap_t pmap) 2647176771Sraj{ 2648176771Sraj tlbtid_t tid; 2649187149Sraj int thiscpu; 2650176771Sraj 2651187149Sraj KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2652176771Sraj 2653187149Sraj CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2654176771Sraj 2655187149Sraj thiscpu = PCPU_GET(cpuid); 2656176771Sraj 2657187149Sraj tid = PCPU_GET(tid_next); 2658187149Sraj if (tid > TID_MAX) 2659187149Sraj tid = TID_MIN; 2660187149Sraj PCPU_SET(tid_next, tid + 1); 2661176771Sraj 2662187149Sraj /* If we are stealing TID then clear the relevant pmap's field */ 2663187149Sraj if (tidbusy[thiscpu][tid] != NULL) { 2664176771Sraj 2665187149Sraj CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2666187149Sraj 2667187149Sraj tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2668176771Sraj 2669187149Sraj /* Flush all entries from TLB0 matching this TID. */ 2670187149Sraj tid_flush(tid); 2671176771Sraj } 2672176771Sraj 2673187149Sraj tidbusy[thiscpu][tid] = pmap; 2674187149Sraj pmap->pm_tid[thiscpu] = tid; 2675187149Sraj __asm __volatile("msync; isync"); 2676176771Sraj 2677187149Sraj CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2678187149Sraj PCPU_GET(tid_next)); 2679176771Sraj 2680176771Sraj return (tid); 2681176771Sraj} 2682176771Sraj 2683176771Sraj/**************************************************************************/ 2684176771Sraj/* TLB0 handling */ 2685176771Sraj/**************************************************************************/ 2686176771Sraj 2687176771Srajstatic void 2688187149Srajtlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2689187149Sraj uint32_t mas7) 2690176771Sraj{ 2691176771Sraj int as; 2692176771Sraj char desc[3]; 2693176771Sraj tlbtid_t tid; 2694176771Sraj vm_size_t size; 2695176771Sraj unsigned int tsize; 2696176771Sraj 2697176771Sraj desc[2] = '\0'; 2698176771Sraj if (mas1 & MAS1_VALID) 2699176771Sraj desc[0] = 'V'; 2700176771Sraj else 2701176771Sraj desc[0] = ' '; 2702176771Sraj 2703176771Sraj if (mas1 & MAS1_IPROT) 2704176771Sraj desc[1] = 'P'; 2705176771Sraj else 2706176771Sraj desc[1] = ' '; 2707176771Sraj 2708187149Sraj as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2709176771Sraj tid = MAS1_GETTID(mas1); 2710176771Sraj 2711176771Sraj tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2712176771Sraj size = 0; 2713176771Sraj if (tsize) 2714176771Sraj size = tsize2size(tsize); 2715176771Sraj 2716176771Sraj debugf("%3d: (%s) [AS=%d] " 2717176771Sraj "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2718176771Sraj "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2719176771Sraj i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2720176771Sraj} 2721176771Sraj 2722176771Sraj/* Convert TLB0 va and way number to tlb0[] table index. */ 2723176771Srajstatic inline unsigned int 2724176771Srajtlb0_tableidx(vm_offset_t va, unsigned int way) 2725176771Sraj{ 2726176771Sraj unsigned int idx; 2727176771Sraj 2728176771Sraj idx = (way * TLB0_ENTRIES_PER_WAY); 2729176771Sraj idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2730176771Sraj return (idx); 2731176771Sraj} 2732176771Sraj 2733176771Sraj/* 2734187149Sraj * Invalidate TLB0 entry. 2735176771Sraj */ 2736187149Srajstatic inline void 2737187149Srajtlb0_flush_entry(vm_offset_t va) 2738176771Sraj{ 2739176771Sraj 2740187149Sraj CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2741176771Sraj 2742187149Sraj mtx_assert(&tlbivax_mutex, MA_OWNED); 2743176771Sraj 2744187149Sraj __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2745187149Sraj __asm __volatile("isync; msync"); 2746187149Sraj __asm __volatile("tlbsync; msync"); 2747176771Sraj 2748187149Sraj CTR1(KTR_PMAP, "%s: e", __func__); 2749176771Sraj} 2750176771Sraj 2751176771Sraj/* Print out contents of the MAS registers for each TLB0 entry */ 2752187149Srajvoid 2753176771Srajtlb0_print_tlbentries(void) 2754176771Sraj{ 2755187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 2756176771Sraj int entryidx, way, idx; 2757176771Sraj 2758176771Sraj debugf("TLB0 entries:\n"); 2759187149Sraj for (way = 0; way < TLB0_WAYS; way ++) 2760176771Sraj for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2761176771Sraj 2762176771Sraj mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2763176771Sraj mtspr(SPR_MAS0, mas0); 2764187149Sraj __asm __volatile("isync"); 2765176771Sraj 2766176771Sraj mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2767176771Sraj mtspr(SPR_MAS2, mas2); 2768176771Sraj 2769187149Sraj __asm __volatile("isync; tlbre"); 2770176771Sraj 2771176771Sraj mas1 = mfspr(SPR_MAS1); 2772176771Sraj mas2 = mfspr(SPR_MAS2); 2773176771Sraj mas3 = mfspr(SPR_MAS3); 2774176771Sraj mas7 = mfspr(SPR_MAS7); 2775176771Sraj 2776176771Sraj idx = tlb0_tableidx(mas2, way); 2777176771Sraj tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2778176771Sraj } 2779176771Sraj} 2780176771Sraj 2781176771Sraj/**************************************************************************/ 2782176771Sraj/* TLB1 handling */ 2783176771Sraj/**************************************************************************/ 2784187149Sraj 2785176771Sraj/* 2786187149Sraj * TLB1 mapping notes: 2787187149Sraj * 2788187149Sraj * TLB1[0] CCSRBAR 2789187149Sraj * TLB1[1] Kernel text and data. 2790187149Sraj * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2791187149Sraj * windows, other devices mappings. 2792187149Sraj */ 2793187149Sraj 2794187149Sraj/* 2795176771Sraj * Write given entry to TLB1 hardware. 2796176771Sraj * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2797176771Sraj */ 2798176771Srajstatic void 2799176771Srajtlb1_write_entry(unsigned int idx) 2800176771Sraj{ 2801187151Sraj uint32_t mas0, mas7; 2802176771Sraj 2803176771Sraj //debugf("tlb1_write_entry: s\n"); 2804176771Sraj 2805176771Sraj /* Clear high order RPN bits */ 2806176771Sraj mas7 = 0; 2807176771Sraj 2808176771Sraj /* Select entry */ 2809176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2810176771Sraj //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2811176771Sraj 2812176771Sraj mtspr(SPR_MAS0, mas0); 2813187151Sraj __asm __volatile("isync"); 2814176771Sraj mtspr(SPR_MAS1, tlb1[idx].mas1); 2815187151Sraj __asm __volatile("isync"); 2816176771Sraj mtspr(SPR_MAS2, tlb1[idx].mas2); 2817187151Sraj __asm __volatile("isync"); 2818176771Sraj mtspr(SPR_MAS3, tlb1[idx].mas3); 2819187151Sraj __asm __volatile("isync"); 2820176771Sraj mtspr(SPR_MAS7, mas7); 2821187151Sraj __asm __volatile("isync; tlbwe; isync; msync"); 2822176771Sraj 2823201758Smbr //debugf("tlb1_write_entry: e\n"); 2824176771Sraj} 2825176771Sraj 2826176771Sraj/* 2827176771Sraj * Return the largest uint value log such that 2^log <= num. 2828176771Sraj */ 2829176771Srajstatic unsigned int 2830176771Srajilog2(unsigned int num) 2831176771Sraj{ 2832176771Sraj int lz; 2833176771Sraj 2834176771Sraj __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2835176771Sraj return (31 - lz); 2836176771Sraj} 2837176771Sraj 2838176771Sraj/* 2839176771Sraj * Convert TLB TSIZE value to mapped region size. 2840176771Sraj */ 2841176771Srajstatic vm_size_t 2842176771Srajtsize2size(unsigned int tsize) 2843176771Sraj{ 2844176771Sraj 2845176771Sraj /* 2846176771Sraj * size = 4^tsize KB 2847176771Sraj * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2848176771Sraj */ 2849176771Sraj 2850176771Sraj return ((1 << (2 * tsize)) * 1024); 2851176771Sraj} 2852176771Sraj 2853176771Sraj/* 2854176771Sraj * Convert region size (must be power of 4) to TLB TSIZE value. 2855176771Sraj */ 2856176771Srajstatic unsigned int 2857176771Srajsize2tsize(vm_size_t size) 2858176771Sraj{ 2859176771Sraj 2860176771Sraj return (ilog2(size) / 2 - 5); 2861176771Sraj} 2862176771Sraj 2863176771Sraj/* 2864187149Sraj * Register permanent kernel mapping in TLB1. 2865176771Sraj * 2866187149Sraj * Entries are created starting from index 0 (current free entry is 2867187149Sraj * kept in tlb1_idx) and are not supposed to be invalidated. 2868176771Sraj */ 2869187149Srajstatic int 2870187149Srajtlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2871187149Sraj uint32_t flags) 2872176771Sraj{ 2873187149Sraj uint32_t ts, tid; 2874176771Sraj int tsize; 2875187149Sraj 2876187149Sraj if (tlb1_idx >= TLB1_ENTRIES) { 2877187149Sraj printf("tlb1_set_entry: TLB1 full!\n"); 2878187149Sraj return (-1); 2879187149Sraj } 2880176771Sraj 2881176771Sraj /* Convert size to TSIZE */ 2882176771Sraj tsize = size2tsize(size); 2883176771Sraj 2884187149Sraj tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2885187149Sraj /* XXX TS is hard coded to 0 for now as we only use single address space */ 2886187149Sraj ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2887176771Sraj 2888187149Sraj /* XXX LOCK tlb1[] */ 2889176771Sraj 2890187149Sraj tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2891187149Sraj tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2892187149Sraj tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2893176771Sraj 2894187149Sraj /* Set supervisor RWX permission bits */ 2895187149Sraj tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2896176771Sraj 2897187149Sraj tlb1_write_entry(tlb1_idx++); 2898176771Sraj 2899187149Sraj /* XXX UNLOCK tlb1[] */ 2900176771Sraj 2901187149Sraj /* 2902187149Sraj * XXX in general TLB1 updates should be propagated between CPUs, 2903187149Sraj * since current design assumes to have the same TLB1 set-up on all 2904187149Sraj * cores. 2905187149Sraj */ 2906176771Sraj return (0); 2907176771Sraj} 2908176771Sraj 2909176771Srajstatic int 2910176771Srajtlb1_entry_size_cmp(const void *a, const void *b) 2911176771Sraj{ 2912176771Sraj const vm_size_t *sza; 2913176771Sraj const vm_size_t *szb; 2914176771Sraj 2915176771Sraj sza = a; 2916176771Sraj szb = b; 2917176771Sraj if (*sza > *szb) 2918176771Sraj return (-1); 2919176771Sraj else if (*sza < *szb) 2920176771Sraj return (1); 2921176771Sraj else 2922176771Sraj return (0); 2923176771Sraj} 2924176771Sraj 2925176771Sraj/* 2926187151Sraj * Map in contiguous RAM region into the TLB1 using maximum of 2927176771Sraj * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2928176771Sraj * 2929187151Sraj * If necessary round up last entry size and return total size 2930176771Sraj * used by all allocated entries. 2931176771Sraj */ 2932176771Srajvm_size_t 2933176771Srajtlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2934176771Sraj{ 2935176771Sraj vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2936176771Sraj vm_size_t mapped_size, sz, esz; 2937176771Sraj unsigned int log; 2938176771Sraj int i; 2939176771Sraj 2940187151Sraj CTR4(KTR_PMAP, "%s: region size = 0x%08x va = 0x%08x pa = 0x%08x", 2941187151Sraj __func__, size, va, pa); 2942176771Sraj 2943176771Sraj mapped_size = 0; 2944176771Sraj sz = size; 2945176771Sraj memset(entry_size, 0, sizeof(entry_size)); 2946176771Sraj 2947176771Sraj /* Calculate entry sizes. */ 2948176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2949176771Sraj 2950176771Sraj /* Largest region that is power of 4 and fits within size */ 2951187149Sraj log = ilog2(sz) / 2; 2952176771Sraj esz = 1 << (2 * log); 2953176771Sraj 2954176771Sraj /* If this is last entry cover remaining size. */ 2955176771Sraj if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2956176771Sraj while (esz < sz) 2957176771Sraj esz = esz << 2; 2958176771Sraj } 2959176771Sraj 2960176771Sraj entry_size[i] = esz; 2961176771Sraj mapped_size += esz; 2962176771Sraj if (esz < sz) 2963176771Sraj sz -= esz; 2964176771Sraj else 2965176771Sraj sz = 0; 2966176771Sraj } 2967176771Sraj 2968176771Sraj /* Sort entry sizes, required to get proper entry address alignment. */ 2969176771Sraj qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2970176771Sraj sizeof(vm_size_t), tlb1_entry_size_cmp); 2971176771Sraj 2972176771Sraj /* Load TLB1 entries. */ 2973176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2974176771Sraj esz = entry_size[i]; 2975176771Sraj if (!esz) 2976176771Sraj break; 2977187151Sraj 2978187151Sraj CTR5(KTR_PMAP, "%s: entry %d: sz = 0x%08x (va = 0x%08x " 2979187151Sraj "pa = 0x%08x)", __func__, tlb1_idx, esz, va, pa); 2980187151Sraj 2981176771Sraj tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 2982176771Sraj 2983176771Sraj va += esz; 2984176771Sraj pa += esz; 2985176771Sraj } 2986176771Sraj 2987187151Sraj CTR3(KTR_PMAP, "%s: mapped size 0x%08x (wasted space 0x%08x)", 2988187151Sraj __func__, mapped_size, mapped_size - size); 2989176771Sraj 2990176771Sraj return (mapped_size); 2991176771Sraj} 2992176771Sraj 2993176771Sraj/* 2994176771Sraj * TLB1 initialization routine, to be called after the very first 2995176771Sraj * assembler level setup done in locore.S. 2996176771Sraj */ 2997176771Srajvoid 2998176771Srajtlb1_init(vm_offset_t ccsrbar) 2999176771Sraj{ 3000176771Sraj uint32_t mas0; 3001176771Sraj 3002187151Sraj /* TLB1[1] is used to map the kernel. Save that entry. */ 3003176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 3004176771Sraj mtspr(SPR_MAS0, mas0); 3005176771Sraj __asm __volatile("isync; tlbre"); 3006176771Sraj 3007176771Sraj tlb1[1].mas1 = mfspr(SPR_MAS1); 3008176771Sraj tlb1[1].mas2 = mfspr(SPR_MAS2); 3009176771Sraj tlb1[1].mas3 = mfspr(SPR_MAS3); 3010176771Sraj 3011187149Sraj /* Map in CCSRBAR in TLB1[0] */ 3012187149Sraj tlb1_idx = 0; 3013187149Sraj tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3014187149Sraj /* 3015187149Sraj * Set the next available TLB1 entry index. Note TLB[1] is reserved 3016187149Sraj * for initial mapping of kernel text+data, which was set early in 3017187149Sraj * locore, we need to skip this [busy] entry. 3018187149Sraj */ 3019187149Sraj tlb1_idx = 2; 3020176771Sraj 3021176771Sraj /* Setup TLB miss defaults */ 3022176771Sraj set_mas4_defaults(); 3023176771Sraj} 3024176771Sraj 3025176771Sraj/* 3026176771Sraj * Setup MAS4 defaults. 3027176771Sraj * These values are loaded to MAS0-2 on a TLB miss. 3028176771Sraj */ 3029176771Srajstatic void 3030176771Srajset_mas4_defaults(void) 3031176771Sraj{ 3032187151Sraj uint32_t mas4; 3033176771Sraj 3034176771Sraj /* Defaults: TLB0, PID0, TSIZED=4K */ 3035176771Sraj mas4 = MAS4_TLBSELD0; 3036176771Sraj mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3037192532Sraj#ifdef SMP 3038192532Sraj mas4 |= MAS4_MD; 3039192532Sraj#endif 3040176771Sraj mtspr(SPR_MAS4, mas4); 3041187151Sraj __asm __volatile("isync"); 3042176771Sraj} 3043176771Sraj 3044176771Sraj/* 3045176771Sraj * Print out contents of the MAS registers for each TLB1 entry 3046176771Sraj */ 3047176771Srajvoid 3048176771Srajtlb1_print_tlbentries(void) 3049176771Sraj{ 3050187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 3051176771Sraj int i; 3052176771Sraj 3053176771Sraj debugf("TLB1 entries:\n"); 3054187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) { 3055176771Sraj 3056176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3057176771Sraj mtspr(SPR_MAS0, mas0); 3058176771Sraj 3059187149Sraj __asm __volatile("isync; tlbre"); 3060176771Sraj 3061176771Sraj mas1 = mfspr(SPR_MAS1); 3062176771Sraj mas2 = mfspr(SPR_MAS2); 3063176771Sraj mas3 = mfspr(SPR_MAS3); 3064176771Sraj mas7 = mfspr(SPR_MAS7); 3065176771Sraj 3066176771Sraj tlb_print_entry(i, mas1, mas2, mas3, mas7); 3067176771Sraj } 3068176771Sraj} 3069176771Sraj 3070176771Sraj/* 3071176771Sraj * Print out contents of the in-ram tlb1 table. 3072176771Sraj */ 3073176771Srajvoid 3074176771Srajtlb1_print_entries(void) 3075176771Sraj{ 3076176771Sraj int i; 3077176771Sraj 3078176771Sraj debugf("tlb1[] table entries:\n"); 3079187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) 3080176771Sraj tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3081176771Sraj} 3082176771Sraj 3083176771Sraj/* 3084176771Sraj * Return 0 if the physical IO range is encompassed by one of the 3085176771Sraj * the TLB1 entries, otherwise return related error code. 3086176771Sraj */ 3087176771Srajstatic int 3088176771Srajtlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3089176771Sraj{ 3090187151Sraj uint32_t prot; 3091176771Sraj vm_paddr_t pa_start; 3092176771Sraj vm_paddr_t pa_end; 3093176771Sraj unsigned int entry_tsize; 3094176771Sraj vm_size_t entry_size; 3095176771Sraj 3096176771Sraj *va = (vm_offset_t)NULL; 3097176771Sraj 3098176771Sraj /* Skip invalid entries */ 3099176771Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 3100176771Sraj return (EINVAL); 3101176771Sraj 3102176771Sraj /* 3103176771Sraj * The entry must be cache-inhibited, guarded, and r/w 3104176771Sraj * so it can function as an i/o page 3105176771Sraj */ 3106176771Sraj prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3107176771Sraj if (prot != (MAS2_I | MAS2_G)) 3108176771Sraj return (EPERM); 3109176771Sraj 3110176771Sraj prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3111176771Sraj if (prot != (MAS3_SR | MAS3_SW)) 3112176771Sraj return (EPERM); 3113176771Sraj 3114176771Sraj /* The address should be within the entry range. */ 3115176771Sraj entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3116176771Sraj KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3117176771Sraj 3118176771Sraj entry_size = tsize2size(entry_tsize); 3119176771Sraj pa_start = tlb1[i].mas3 & MAS3_RPN; 3120176771Sraj pa_end = pa_start + entry_size - 1; 3121176771Sraj 3122176771Sraj if ((pa < pa_start) || ((pa + size) > pa_end)) 3123176771Sraj return (ERANGE); 3124176771Sraj 3125176771Sraj /* Return virtual address of this mapping. */ 3126187149Sraj *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3127176771Sraj return (0); 3128176771Sraj} 3129