pmap.c revision 192795
1176771Sraj/*- 2192532Sraj * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3176771Sraj * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4176771Sraj * All rights reserved. 5176771Sraj * 6176771Sraj * Redistribution and use in source and binary forms, with or without 7176771Sraj * modification, are permitted provided that the following conditions 8176771Sraj * are met: 9176771Sraj * 1. Redistributions of source code must retain the above copyright 10176771Sraj * notice, this list of conditions and the following disclaimer. 11176771Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176771Sraj * notice, this list of conditions and the following disclaimer in the 13176771Sraj * documentation and/or other materials provided with the distribution. 14176771Sraj * 15176771Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176771Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176771Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176771Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176771Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176771Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176771Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176771Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176771Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176771Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176771Sraj * 26176771Sraj * Some hw specific parts of this pmap were derived or influenced 27176771Sraj * by NetBSD's ibm4xx pmap module. More generic code is shared with 28176771Sraj * a few other pmap modules from the FreeBSD tree. 29176771Sraj */ 30176771Sraj 31176771Sraj /* 32176771Sraj * VM layout notes: 33176771Sraj * 34176771Sraj * Kernel and user threads run within one common virtual address space 35176771Sraj * defined by AS=0. 36176771Sraj * 37176771Sraj * Virtual address space layout: 38176771Sraj * ----------------------------- 39187151Sraj * 0x0000_0000 - 0xafff_ffff : user process 40187151Sraj * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41187151Sraj * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42190701Smarcel * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43187151Sraj * 0xc100_0000 - 0xfeef_ffff : KVA 44187151Sraj * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45187151Sraj * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46187151Sraj * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47187151Sraj * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48187151Sraj * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49176771Sraj */ 50176771Sraj 51176771Sraj#include <sys/cdefs.h> 52176771Sraj__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 192795 2009-05-26 06:24:50Z raj $"); 53176771Sraj 54176771Sraj#include <sys/types.h> 55176771Sraj#include <sys/param.h> 56176771Sraj#include <sys/malloc.h> 57187149Sraj#include <sys/ktr.h> 58176771Sraj#include <sys/proc.h> 59176771Sraj#include <sys/user.h> 60176771Sraj#include <sys/queue.h> 61176771Sraj#include <sys/systm.h> 62176771Sraj#include <sys/kernel.h> 63176771Sraj#include <sys/msgbuf.h> 64176771Sraj#include <sys/lock.h> 65176771Sraj#include <sys/mutex.h> 66192532Sraj#include <sys/smp.h> 67176771Sraj#include <sys/vmmeter.h> 68176771Sraj 69176771Sraj#include <vm/vm.h> 70176771Sraj#include <vm/vm_page.h> 71176771Sraj#include <vm/vm_kern.h> 72176771Sraj#include <vm/vm_pageout.h> 73176771Sraj#include <vm/vm_extern.h> 74176771Sraj#include <vm/vm_object.h> 75176771Sraj#include <vm/vm_param.h> 76176771Sraj#include <vm/vm_map.h> 77176771Sraj#include <vm/vm_pager.h> 78176771Sraj#include <vm/uma.h> 79176771Sraj 80190701Smarcel#include <machine/bootinfo.h> 81176771Sraj#include <machine/cpu.h> 82176771Sraj#include <machine/pcb.h> 83192067Snwhitehorn#include <machine/platform.h> 84176771Sraj 85176771Sraj#include <machine/tlb.h> 86176771Sraj#include <machine/spr.h> 87176771Sraj#include <machine/vmparam.h> 88176771Sraj#include <machine/md_var.h> 89176771Sraj#include <machine/mmuvar.h> 90176771Sraj#include <machine/pmap.h> 91176771Sraj#include <machine/pte.h> 92176771Sraj 93176771Sraj#include "mmu_if.h" 94176771Sraj 95176771Sraj#define DEBUG 96176771Sraj#undef DEBUG 97176771Sraj 98176771Sraj#ifdef DEBUG 99176771Sraj#define debugf(fmt, args...) printf(fmt, ##args) 100176771Sraj#else 101176771Sraj#define debugf(fmt, args...) 102176771Sraj#endif 103176771Sraj 104176771Sraj#define TODO panic("%s: not implemented", __func__); 105176771Sraj 106176771Sraj#include "opt_sched.h" 107176771Sraj#ifndef SCHED_4BSD 108176771Sraj#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 109176771Sraj#endif 110176771Srajextern struct mtx sched_lock; 111176771Sraj 112190701Smarcelextern int dumpsys_minidump; 113190701Smarcel 114190701Smarcelextern unsigned char _etext[]; 115190701Smarcelextern unsigned char _end[]; 116190701Smarcel 117176771Sraj/* Kernel physical load address. */ 118176771Srajextern uint32_t kernload; 119190701Smarcelvm_offset_t kernstart; 120190701Smarcelvm_size_t kernsize; 121176771Sraj 122190701Smarcel/* Message buffer and tables. */ 123190701Smarcelstatic vm_offset_t data_start; 124190701Smarcelstatic vm_size_t data_end; 125190701Smarcel 126192067Snwhitehorn/* Phys/avail memory regions. */ 127192067Snwhitehornstatic struct mem_region *availmem_regions; 128192067Snwhitehornstatic int availmem_regions_sz; 129192067Snwhitehornstatic struct mem_region *physmem_regions; 130192067Snwhitehornstatic int physmem_regions_sz; 131176771Sraj 132176771Sraj/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 133176771Srajstatic vm_offset_t zero_page_va; 134176771Srajstatic struct mtx zero_page_mutex; 135176771Sraj 136187149Srajstatic struct mtx tlbivax_mutex; 137187149Sraj 138176771Sraj/* 139176771Sraj * Reserved KVA space for mmu_booke_zero_page_idle. This is used 140176771Sraj * by idle thred only, no lock required. 141176771Sraj */ 142176771Srajstatic vm_offset_t zero_page_idle_va; 143176771Sraj 144176771Sraj/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 145176771Srajstatic vm_offset_t copy_page_src_va; 146176771Srajstatic vm_offset_t copy_page_dst_va; 147176771Srajstatic struct mtx copy_page_mutex; 148176771Sraj 149176771Sraj/**************************************************************************/ 150176771Sraj/* PMAP */ 151176771Sraj/**************************************************************************/ 152176771Sraj 153176771Srajstatic void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 154176771Sraj vm_prot_t, boolean_t); 155176771Sraj 156176771Srajunsigned int kptbl_min; /* Index of the first kernel ptbl. */ 157176771Srajunsigned int kernel_ptbls; /* Number of KVA ptbls. */ 158176771Sraj 159176771Srajstatic int pagedaemon_waken; 160176771Sraj 161176771Sraj/* 162176771Sraj * If user pmap is processed with mmu_booke_remove and the resident count 163176771Sraj * drops to 0, there are no more pages to remove, so we need not continue. 164176771Sraj */ 165176771Sraj#define PMAP_REMOVE_DONE(pmap) \ 166176771Sraj ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 167176771Sraj 168187149Srajextern void tlb_lock(uint32_t *); 169187149Srajextern void tlb_unlock(uint32_t *); 170187149Srajextern void tid_flush(tlbtid_t); 171176771Sraj 172176771Sraj/**************************************************************************/ 173176771Sraj/* TLB and TID handling */ 174176771Sraj/**************************************************************************/ 175176771Sraj 176176771Sraj/* Translation ID busy table */ 177187149Srajstatic volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 178176771Sraj 179176771Sraj/* 180187149Sraj * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 181187149Sraj * core revisions and should be read from h/w registers during early config. 182176771Sraj */ 183187149Srajuint32_t tlb0_entries; 184187149Srajuint32_t tlb0_ways; 185187149Srajuint32_t tlb0_entries_per_way; 186176771Sraj 187187149Sraj#define TLB0_ENTRIES (tlb0_entries) 188187149Sraj#define TLB0_WAYS (tlb0_ways) 189187149Sraj#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 190176771Sraj 191187149Sraj#define TLB1_ENTRIES 16 192176771Sraj 193176771Sraj/* In-ram copy of the TLB1 */ 194187149Srajstatic tlb_entry_t tlb1[TLB1_ENTRIES]; 195176771Sraj 196176771Sraj/* Next free entry in the TLB1 */ 197176771Srajstatic unsigned int tlb1_idx; 198176771Sraj 199176771Srajstatic tlbtid_t tid_alloc(struct pmap *); 200176771Sraj 201187149Srajstatic void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 202176771Sraj 203187149Srajstatic int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 204176771Srajstatic void tlb1_write_entry(unsigned int); 205176771Srajstatic int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 206176771Srajstatic vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 207176771Sraj 208176771Srajstatic vm_size_t tsize2size(unsigned int); 209176771Srajstatic unsigned int size2tsize(vm_size_t); 210176771Srajstatic unsigned int ilog2(unsigned int); 211176771Sraj 212176771Srajstatic void set_mas4_defaults(void); 213176771Sraj 214187149Srajstatic inline void tlb0_flush_entry(vm_offset_t); 215176771Srajstatic inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 216176771Sraj 217176771Sraj/**************************************************************************/ 218176771Sraj/* Page table management */ 219176771Sraj/**************************************************************************/ 220176771Sraj 221176771Sraj/* Data for the pv entry allocation mechanism */ 222176771Srajstatic uma_zone_t pvzone; 223176771Srajstatic struct vm_object pvzone_obj; 224176771Srajstatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 225176771Sraj 226176771Sraj#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 227176771Sraj 228176771Sraj#ifndef PMAP_SHPGPERPROC 229176771Sraj#define PMAP_SHPGPERPROC 200 230176771Sraj#endif 231176771Sraj 232176771Srajstatic void ptbl_init(void); 233176771Srajstatic struct ptbl_buf *ptbl_buf_alloc(void); 234176771Srajstatic void ptbl_buf_free(struct ptbl_buf *); 235176771Srajstatic void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 236176771Sraj 237187149Srajstatic pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 238176771Srajstatic void ptbl_free(mmu_t, pmap_t, unsigned int); 239176771Srajstatic void ptbl_hold(mmu_t, pmap_t, unsigned int); 240176771Srajstatic int ptbl_unhold(mmu_t, pmap_t, unsigned int); 241176771Sraj 242176771Srajstatic vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 243176771Srajstatic pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 244187149Srajstatic void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 245187149Srajstatic int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 246176771Sraj 247187149Srajstatic pv_entry_t pv_alloc(void); 248176771Srajstatic void pv_free(pv_entry_t); 249176771Srajstatic void pv_insert(pmap_t, vm_offset_t, vm_page_t); 250176771Srajstatic void pv_remove(pmap_t, vm_offset_t, vm_page_t); 251176771Sraj 252176771Sraj/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 253176771Sraj#define PTBL_BUFS (128 * 16) 254176771Sraj 255176771Srajstruct ptbl_buf { 256176771Sraj TAILQ_ENTRY(ptbl_buf) link; /* list link */ 257176771Sraj vm_offset_t kva; /* va of mapping */ 258176771Sraj}; 259176771Sraj 260176771Sraj/* ptbl free list and a lock used for access synchronization. */ 261176771Srajstatic TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 262176771Srajstatic struct mtx ptbl_buf_freelist_lock; 263176771Sraj 264176771Sraj/* Base address of kva space allocated fot ptbl bufs. */ 265176771Srajstatic vm_offset_t ptbl_buf_pool_vabase; 266176771Sraj 267176771Sraj/* Pointer to ptbl_buf structures. */ 268176771Srajstatic struct ptbl_buf *ptbl_bufs; 269176771Sraj 270192532Srajvoid pmap_bootstrap_ap(volatile uint32_t *); 271192532Sraj 272176771Sraj/* 273176771Sraj * Kernel MMU interface 274176771Sraj */ 275176771Srajstatic void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 276176771Srajstatic void mmu_booke_clear_modify(mmu_t, vm_page_t); 277176771Srajstatic void mmu_booke_clear_reference(mmu_t, vm_page_t); 278176771Srajstatic void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t, vm_size_t, 279176771Sraj vm_offset_t); 280176771Srajstatic void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 281176771Srajstatic void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 282176771Sraj vm_prot_t, boolean_t); 283176771Srajstatic void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 284176771Sraj vm_page_t, vm_prot_t); 285176771Srajstatic void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 286176771Sraj vm_prot_t); 287176771Srajstatic vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 288176771Srajstatic vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 289176771Sraj vm_prot_t); 290176771Srajstatic void mmu_booke_init(mmu_t); 291176771Srajstatic boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 292176771Srajstatic boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 293176771Srajstatic boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 294176771Srajstatic vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 295176771Sraj int); 296176771Srajstatic int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t); 297176771Srajstatic void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 298176771Sraj vm_object_t, vm_pindex_t, vm_size_t); 299176771Srajstatic boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 300176771Srajstatic void mmu_booke_page_init(mmu_t, vm_page_t); 301176771Srajstatic int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 302176771Srajstatic void mmu_booke_pinit(mmu_t, pmap_t); 303176771Srajstatic void mmu_booke_pinit0(mmu_t, pmap_t); 304176771Srajstatic void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 305176771Sraj vm_prot_t); 306176771Srajstatic void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 307176771Srajstatic void mmu_booke_qremove(mmu_t, vm_offset_t, int); 308176771Srajstatic void mmu_booke_release(mmu_t, pmap_t); 309176771Srajstatic void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 310176771Srajstatic void mmu_booke_remove_all(mmu_t, vm_page_t); 311176771Srajstatic void mmu_booke_remove_write(mmu_t, vm_page_t); 312176771Srajstatic void mmu_booke_zero_page(mmu_t, vm_page_t); 313176771Srajstatic void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 314176771Srajstatic void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 315176771Srajstatic void mmu_booke_activate(mmu_t, struct thread *); 316176771Srajstatic void mmu_booke_deactivate(mmu_t, struct thread *); 317176771Srajstatic void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 318176771Srajstatic void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 319176771Srajstatic void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 320176771Srajstatic vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 321176771Srajstatic void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 322176771Srajstatic void mmu_booke_kremove(mmu_t, vm_offset_t); 323176771Srajstatic boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 324176771Srajstatic boolean_t mmu_booke_page_executable(mmu_t, vm_page_t); 325190701Smarcelstatic vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 326190701Smarcel vm_size_t, vm_size_t *); 327190701Smarcelstatic void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 328190701Smarcel vm_size_t, vm_offset_t); 329190701Smarcelstatic struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 330176771Sraj 331176771Srajstatic mmu_method_t mmu_booke_methods[] = { 332176771Sraj /* pmap dispatcher interface */ 333176771Sraj MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 334176771Sraj MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 335176771Sraj MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 336176771Sraj MMUMETHOD(mmu_copy, mmu_booke_copy), 337176771Sraj MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 338176771Sraj MMUMETHOD(mmu_enter, mmu_booke_enter), 339176771Sraj MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 340176771Sraj MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 341176771Sraj MMUMETHOD(mmu_extract, mmu_booke_extract), 342176771Sraj MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 343176771Sraj MMUMETHOD(mmu_init, mmu_booke_init), 344176771Sraj MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 345176771Sraj MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 346176771Sraj MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 347176771Sraj MMUMETHOD(mmu_map, mmu_booke_map), 348176771Sraj MMUMETHOD(mmu_mincore, mmu_booke_mincore), 349176771Sraj MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 350176771Sraj MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 351176771Sraj MMUMETHOD(mmu_page_init, mmu_booke_page_init), 352176771Sraj MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 353176771Sraj MMUMETHOD(mmu_pinit, mmu_booke_pinit), 354176771Sraj MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 355176771Sraj MMUMETHOD(mmu_protect, mmu_booke_protect), 356176771Sraj MMUMETHOD(mmu_qenter, mmu_booke_qenter), 357176771Sraj MMUMETHOD(mmu_qremove, mmu_booke_qremove), 358176771Sraj MMUMETHOD(mmu_release, mmu_booke_release), 359176771Sraj MMUMETHOD(mmu_remove, mmu_booke_remove), 360176771Sraj MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 361176771Sraj MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 362176771Sraj MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 363176771Sraj MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 364176771Sraj MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 365176771Sraj MMUMETHOD(mmu_activate, mmu_booke_activate), 366176771Sraj MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 367176771Sraj 368176771Sraj /* Internal interfaces */ 369176771Sraj MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 370176771Sraj MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 371176771Sraj MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 372176771Sraj MMUMETHOD(mmu_kenter, mmu_booke_kenter), 373176771Sraj MMUMETHOD(mmu_kextract, mmu_booke_kextract), 374176771Sraj/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 375176771Sraj MMUMETHOD(mmu_page_executable, mmu_booke_page_executable), 376176771Sraj MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 377176771Sraj 378190701Smarcel /* dumpsys() support */ 379190701Smarcel MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 380190701Smarcel MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 381190701Smarcel MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 382190701Smarcel 383176771Sraj { 0, 0 } 384176771Sraj}; 385176771Sraj 386176771Srajstatic mmu_def_t booke_mmu = { 387176771Sraj MMU_TYPE_BOOKE, 388176771Sraj mmu_booke_methods, 389176771Sraj 0 390176771Sraj}; 391176771SrajMMU_DEF(booke_mmu); 392176771Sraj 393192532Srajstatic inline void 394192532Srajtlb_miss_lock(void) 395192532Sraj{ 396192532Sraj#ifdef SMP 397192532Sraj struct pcpu *pc; 398192532Sraj 399192532Sraj if (!smp_started) 400192532Sraj return; 401192532Sraj 402192532Sraj SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 403192532Sraj if (pc != pcpup) { 404192532Sraj 405192532Sraj CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 406192532Sraj "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 407192532Sraj 408192532Sraj KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 409192532Sraj ("tlb_miss_lock: tried to lock self")); 410192532Sraj 411192532Sraj tlb_lock(pc->pc_booke_tlb_lock); 412192532Sraj 413192532Sraj CTR1(KTR_PMAP, "%s: locked", __func__); 414192532Sraj } 415192532Sraj } 416192532Sraj#endif 417192532Sraj} 418192532Sraj 419192532Srajstatic inline void 420192532Srajtlb_miss_unlock(void) 421192532Sraj{ 422192532Sraj#ifdef SMP 423192532Sraj struct pcpu *pc; 424192532Sraj 425192532Sraj if (!smp_started) 426192532Sraj return; 427192532Sraj 428192532Sraj SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 429192532Sraj if (pc != pcpup) { 430192532Sraj CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 431192532Sraj __func__, pc->pc_cpuid); 432192532Sraj 433192532Sraj tlb_unlock(pc->pc_booke_tlb_lock); 434192532Sraj 435192532Sraj CTR1(KTR_PMAP, "%s: unlocked", __func__); 436192532Sraj } 437192532Sraj } 438192532Sraj#endif 439192532Sraj} 440192532Sraj 441176771Sraj/* Return number of entries in TLB0. */ 442176771Srajstatic __inline void 443176771Srajtlb0_get_tlbconf(void) 444176771Sraj{ 445176771Sraj uint32_t tlb0_cfg; 446176771Sraj 447176771Sraj tlb0_cfg = mfspr(SPR_TLB0CFG); 448187149Sraj tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 449187149Sraj tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 450187149Sraj tlb0_entries_per_way = tlb0_entries / tlb0_ways; 451176771Sraj} 452176771Sraj 453176771Sraj/* Initialize pool of kva ptbl buffers. */ 454176771Srajstatic void 455176771Srajptbl_init(void) 456176771Sraj{ 457176771Sraj int i; 458176771Sraj 459187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 460187151Sraj (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 461187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 462187151Sraj __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 463176771Sraj 464176771Sraj mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 465176771Sraj TAILQ_INIT(&ptbl_buf_freelist); 466176771Sraj 467176771Sraj for (i = 0; i < PTBL_BUFS; i++) { 468176771Sraj ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 469176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 470176771Sraj } 471176771Sraj} 472176771Sraj 473182362Sraj/* Get a ptbl_buf from the freelist. */ 474176771Srajstatic struct ptbl_buf * 475176771Srajptbl_buf_alloc(void) 476176771Sraj{ 477176771Sraj struct ptbl_buf *buf; 478176771Sraj 479176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 480176771Sraj buf = TAILQ_FIRST(&ptbl_buf_freelist); 481176771Sraj if (buf != NULL) 482176771Sraj TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 483176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 484176771Sraj 485187151Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 486187151Sraj 487176771Sraj return (buf); 488176771Sraj} 489176771Sraj 490176771Sraj/* Return ptbl buff to free pool. */ 491176771Srajstatic void 492176771Srajptbl_buf_free(struct ptbl_buf *buf) 493176771Sraj{ 494176771Sraj 495187149Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 496176771Sraj 497176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 498176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 499176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 500176771Sraj} 501176771Sraj 502176771Sraj/* 503187149Sraj * Search the list of allocated ptbl bufs and find on list of allocated ptbls 504176771Sraj */ 505176771Srajstatic void 506176771Srajptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 507176771Sraj{ 508176771Sraj struct ptbl_buf *pbuf; 509176771Sraj 510187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 511176771Sraj 512187149Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 513187149Sraj 514187149Sraj TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 515176771Sraj if (pbuf->kva == (vm_offset_t)ptbl) { 516176771Sraj /* Remove from pmap ptbl buf list. */ 517187149Sraj TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 518176771Sraj 519187149Sraj /* Free corresponding ptbl buf. */ 520176771Sraj ptbl_buf_free(pbuf); 521176771Sraj break; 522176771Sraj } 523176771Sraj} 524176771Sraj 525176771Sraj/* Allocate page table. */ 526187149Srajstatic pte_t * 527176771Srajptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 528176771Sraj{ 529176771Sraj vm_page_t mtbl[PTBL_PAGES]; 530176771Sraj vm_page_t m; 531176771Sraj struct ptbl_buf *pbuf; 532176771Sraj unsigned int pidx; 533187149Sraj pte_t *ptbl; 534176771Sraj int i; 535176771Sraj 536187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 537187149Sraj (pmap == kernel_pmap), pdir_idx); 538176771Sraj 539176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 540176771Sraj ("ptbl_alloc: invalid pdir_idx")); 541176771Sraj KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 542176771Sraj ("pte_alloc: valid ptbl entry exists!")); 543176771Sraj 544176771Sraj pbuf = ptbl_buf_alloc(); 545176771Sraj if (pbuf == NULL) 546176771Sraj panic("pte_alloc: couldn't alloc kernel virtual memory"); 547187149Sraj 548187149Sraj ptbl = (pte_t *)pbuf->kva; 549176771Sraj 550187149Sraj CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 551187149Sraj 552176771Sraj /* Allocate ptbl pages, this will sleep! */ 553176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 554176771Sraj pidx = (PTBL_PAGES * pdir_idx) + i; 555187149Sraj while ((m = vm_page_alloc(NULL, pidx, 556187149Sraj VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 557187149Sraj 558176771Sraj PMAP_UNLOCK(pmap); 559176771Sraj vm_page_unlock_queues(); 560176771Sraj VM_WAIT; 561176771Sraj vm_page_lock_queues(); 562176771Sraj PMAP_LOCK(pmap); 563176771Sraj } 564176771Sraj mtbl[i] = m; 565176771Sraj } 566176771Sraj 567187149Sraj /* Map allocated pages into kernel_pmap. */ 568187149Sraj mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 569176771Sraj 570176771Sraj /* Zero whole ptbl. */ 571187149Sraj bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 572176771Sraj 573176771Sraj /* Add pbuf to the pmap ptbl bufs list. */ 574187149Sraj TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 575176771Sraj 576187149Sraj return (ptbl); 577176771Sraj} 578176771Sraj 579176771Sraj/* Free ptbl pages and invalidate pdir entry. */ 580176771Srajstatic void 581176771Srajptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 582176771Sraj{ 583176771Sraj pte_t *ptbl; 584176771Sraj vm_paddr_t pa; 585176771Sraj vm_offset_t va; 586176771Sraj vm_page_t m; 587176771Sraj int i; 588176771Sraj 589187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 590187149Sraj (pmap == kernel_pmap), pdir_idx); 591176771Sraj 592176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 593176771Sraj ("ptbl_free: invalid pdir_idx")); 594176771Sraj 595176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 596176771Sraj 597187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 598187149Sraj 599176771Sraj KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 600176771Sraj 601187149Sraj /* 602187149Sraj * Invalidate the pdir entry as soon as possible, so that other CPUs 603187149Sraj * don't attempt to look up the page tables we are releasing. 604187149Sraj */ 605187149Sraj mtx_lock_spin(&tlbivax_mutex); 606192532Sraj tlb_miss_lock(); 607187149Sraj 608187149Sraj pmap->pm_pdir[pdir_idx] = NULL; 609187149Sraj 610192532Sraj tlb_miss_unlock(); 611187149Sraj mtx_unlock_spin(&tlbivax_mutex); 612187149Sraj 613176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 614176771Sraj va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 615176771Sraj pa = pte_vatopa(mmu, kernel_pmap, va); 616176771Sraj m = PHYS_TO_VM_PAGE(pa); 617176771Sraj vm_page_free_zero(m); 618176771Sraj atomic_subtract_int(&cnt.v_wire_count, 1); 619176771Sraj mmu_booke_kremove(mmu, va); 620176771Sraj } 621176771Sraj 622176771Sraj ptbl_free_pmap_ptbl(pmap, ptbl); 623176771Sraj} 624176771Sraj 625176771Sraj/* 626176771Sraj * Decrement ptbl pages hold count and attempt to free ptbl pages. 627176771Sraj * Called when removing pte entry from ptbl. 628176771Sraj * 629176771Sraj * Return 1 if ptbl pages were freed. 630176771Sraj */ 631176771Srajstatic int 632176771Srajptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 633176771Sraj{ 634176771Sraj pte_t *ptbl; 635176771Sraj vm_paddr_t pa; 636176771Sraj vm_page_t m; 637176771Sraj int i; 638176771Sraj 639187151Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 640187151Sraj (pmap == kernel_pmap), pdir_idx); 641176771Sraj 642176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 643176771Sraj ("ptbl_unhold: invalid pdir_idx")); 644176771Sraj KASSERT((pmap != kernel_pmap), 645176771Sraj ("ptbl_unhold: unholding kernel ptbl!")); 646176771Sraj 647176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 648176771Sraj 649176771Sraj //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 650176771Sraj KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 651176771Sraj ("ptbl_unhold: non kva ptbl")); 652176771Sraj 653176771Sraj /* decrement hold count */ 654176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 655187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 656187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 657176771Sraj m = PHYS_TO_VM_PAGE(pa); 658176771Sraj m->wire_count--; 659176771Sraj } 660176771Sraj 661176771Sraj /* 662176771Sraj * Free ptbl pages if there are no pte etries in this ptbl. 663187151Sraj * wire_count has the same value for all ptbl pages, so check the last 664187151Sraj * page. 665176771Sraj */ 666176771Sraj if (m->wire_count == 0) { 667176771Sraj ptbl_free(mmu, pmap, pdir_idx); 668176771Sraj 669176771Sraj //debugf("ptbl_unhold: e (freed ptbl)\n"); 670176771Sraj return (1); 671176771Sraj } 672176771Sraj 673176771Sraj return (0); 674176771Sraj} 675176771Sraj 676176771Sraj/* 677187151Sraj * Increment hold count for ptbl pages. This routine is used when a new pte 678187151Sraj * entry is being inserted into the ptbl. 679176771Sraj */ 680176771Srajstatic void 681176771Srajptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 682176771Sraj{ 683176771Sraj vm_paddr_t pa; 684176771Sraj pte_t *ptbl; 685176771Sraj vm_page_t m; 686176771Sraj int i; 687176771Sraj 688187151Sraj CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 689187151Sraj pdir_idx); 690176771Sraj 691176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 692176771Sraj ("ptbl_hold: invalid pdir_idx")); 693176771Sraj KASSERT((pmap != kernel_pmap), 694176771Sraj ("ptbl_hold: holding kernel ptbl!")); 695176771Sraj 696176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 697176771Sraj 698176771Sraj KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 699176771Sraj 700176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 701187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 702187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 703176771Sraj m = PHYS_TO_VM_PAGE(pa); 704176771Sraj m->wire_count++; 705176771Sraj } 706176771Sraj} 707176771Sraj 708176771Sraj/* Allocate pv_entry structure. */ 709176771Srajpv_entry_t 710176771Srajpv_alloc(void) 711176771Sraj{ 712176771Sraj pv_entry_t pv; 713176771Sraj 714176771Sraj pv_entry_count++; 715187151Sraj if ((pv_entry_count > pv_entry_high_water) && 716187151Sraj (pagedaemon_waken == 0)) { 717176771Sraj pagedaemon_waken = 1; 718187151Sraj wakeup(&vm_pages_needed); 719176771Sraj } 720176771Sraj pv = uma_zalloc(pvzone, M_NOWAIT); 721176771Sraj 722176771Sraj return (pv); 723176771Sraj} 724176771Sraj 725176771Sraj/* Free pv_entry structure. */ 726176771Srajstatic __inline void 727176771Srajpv_free(pv_entry_t pve) 728176771Sraj{ 729176771Sraj 730176771Sraj pv_entry_count--; 731176771Sraj uma_zfree(pvzone, pve); 732176771Sraj} 733176771Sraj 734176771Sraj 735176771Sraj/* Allocate and initialize pv_entry structure. */ 736176771Srajstatic void 737176771Srajpv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 738176771Sraj{ 739176771Sraj pv_entry_t pve; 740176771Sraj 741176771Sraj //int su = (pmap == kernel_pmap); 742176771Sraj //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 743176771Sraj // (u_int32_t)pmap, va, (u_int32_t)m); 744176771Sraj 745176771Sraj pve = pv_alloc(); 746176771Sraj if (pve == NULL) 747176771Sraj panic("pv_insert: no pv entries!"); 748176771Sraj 749176771Sraj pve->pv_pmap = pmap; 750176771Sraj pve->pv_va = va; 751176771Sraj 752176771Sraj /* add to pv_list */ 753176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 754176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 755176771Sraj 756176771Sraj TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 757176771Sraj 758176771Sraj //debugf("pv_insert: e\n"); 759176771Sraj} 760176771Sraj 761176771Sraj/* Destroy pv entry. */ 762176771Srajstatic void 763176771Srajpv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 764176771Sraj{ 765176771Sraj pv_entry_t pve; 766176771Sraj 767176771Sraj //int su = (pmap == kernel_pmap); 768176771Sraj //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 769176771Sraj 770176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 771176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 772176771Sraj 773176771Sraj /* find pv entry */ 774176771Sraj TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 775176771Sraj if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 776176771Sraj /* remove from pv_list */ 777176771Sraj TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 778176771Sraj if (TAILQ_EMPTY(&m->md.pv_list)) 779176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 780176771Sraj 781176771Sraj /* free pv entry struct */ 782176771Sraj pv_free(pve); 783176771Sraj break; 784176771Sraj } 785176771Sraj } 786176771Sraj 787176771Sraj //debugf("pv_remove: e\n"); 788176771Sraj} 789176771Sraj 790176771Sraj/* 791176771Sraj * Clean pte entry, try to free page table page if requested. 792176771Sraj * 793176771Sraj * Return 1 if ptbl pages were freed, otherwise return 0. 794176771Sraj */ 795176771Srajstatic int 796187151Srajpte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 797176771Sraj{ 798176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 799176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 800176771Sraj vm_page_t m; 801176771Sraj pte_t *ptbl; 802176771Sraj pte_t *pte; 803176771Sraj 804176771Sraj //int su = (pmap == kernel_pmap); 805176771Sraj //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 806176771Sraj // su, (u_int32_t)pmap, va, flags); 807176771Sraj 808176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 809176771Sraj KASSERT(ptbl, ("pte_remove: null ptbl")); 810176771Sraj 811176771Sraj pte = &ptbl[ptbl_idx]; 812176771Sraj 813176771Sraj if (pte == NULL || !PTE_ISVALID(pte)) 814176771Sraj return (0); 815176771Sraj 816176771Sraj if (PTE_ISWIRED(pte)) 817176771Sraj pmap->pm_stats.wired_count--; 818176771Sraj 819191445Smarcel /* Handle managed entry. */ 820191445Smarcel if (PTE_ISMANAGED(pte)) { 821191445Smarcel /* Get vm_page_t for mapped pte. */ 822191445Smarcel m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 823176771Sraj 824191445Smarcel if (PTE_ISMODIFIED(pte)) 825191445Smarcel vm_page_dirty(m); 826176771Sraj 827191445Smarcel if (PTE_ISREFERENCED(pte)) 828191445Smarcel vm_page_flag_set(m, PG_REFERENCED); 829176771Sraj 830191445Smarcel pv_remove(pmap, va, m); 831176771Sraj } 832176771Sraj 833187149Sraj mtx_lock_spin(&tlbivax_mutex); 834192532Sraj tlb_miss_lock(); 835187149Sraj 836187149Sraj tlb0_flush_entry(va); 837176771Sraj pte->flags = 0; 838176771Sraj pte->rpn = 0; 839187149Sraj 840192532Sraj tlb_miss_unlock(); 841187149Sraj mtx_unlock_spin(&tlbivax_mutex); 842187149Sraj 843176771Sraj pmap->pm_stats.resident_count--; 844176771Sraj 845176771Sraj if (flags & PTBL_UNHOLD) { 846176771Sraj //debugf("pte_remove: e (unhold)\n"); 847176771Sraj return (ptbl_unhold(mmu, pmap, pdir_idx)); 848176771Sraj } 849176771Sraj 850176771Sraj //debugf("pte_remove: e\n"); 851176771Sraj return (0); 852176771Sraj} 853176771Sraj 854176771Sraj/* 855176771Sraj * Insert PTE for a given page and virtual address. 856176771Sraj */ 857187149Srajstatic void 858187149Srajpte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 859176771Sraj{ 860176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 861176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 862187149Sraj pte_t *ptbl, *pte; 863176771Sraj 864187149Sraj CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 865187149Sraj pmap == kernel_pmap, pmap, va); 866176771Sraj 867176771Sraj /* Get the page table pointer. */ 868176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 869176771Sraj 870187149Sraj if (ptbl == NULL) { 871187149Sraj /* Allocate page table pages. */ 872187149Sraj ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 873187149Sraj } else { 874176771Sraj /* 875176771Sraj * Check if there is valid mapping for requested 876176771Sraj * va, if there is, remove it. 877176771Sraj */ 878176771Sraj pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 879176771Sraj if (PTE_ISVALID(pte)) { 880176771Sraj pte_remove(mmu, pmap, va, PTBL_HOLD); 881176771Sraj } else { 882176771Sraj /* 883176771Sraj * pte is not used, increment hold count 884176771Sraj * for ptbl pages. 885176771Sraj */ 886176771Sraj if (pmap != kernel_pmap) 887176771Sraj ptbl_hold(mmu, pmap, pdir_idx); 888176771Sraj } 889176771Sraj } 890176771Sraj 891176771Sraj /* 892187149Sraj * Insert pv_entry into pv_list for mapped page if part of managed 893187149Sraj * memory. 894176771Sraj */ 895176771Sraj if ((m->flags & PG_FICTITIOUS) == 0) { 896176771Sraj if ((m->flags & PG_UNMANAGED) == 0) { 897187149Sraj flags |= PTE_MANAGED; 898176771Sraj 899176771Sraj /* Create and insert pv entry. */ 900176771Sraj pv_insert(pmap, va, m); 901176771Sraj } 902176771Sraj } 903176771Sraj 904176771Sraj pmap->pm_stats.resident_count++; 905187149Sraj 906187149Sraj mtx_lock_spin(&tlbivax_mutex); 907192532Sraj tlb_miss_lock(); 908187149Sraj 909187149Sraj tlb0_flush_entry(va); 910187149Sraj if (pmap->pm_pdir[pdir_idx] == NULL) { 911187149Sraj /* 912187149Sraj * If we just allocated a new page table, hook it in 913187149Sraj * the pdir. 914187149Sraj */ 915187149Sraj pmap->pm_pdir[pdir_idx] = ptbl; 916187149Sraj } 917187149Sraj pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 918176771Sraj pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 919176771Sraj pte->flags |= (PTE_VALID | flags); 920176771Sraj 921192532Sraj tlb_miss_unlock(); 922187149Sraj mtx_unlock_spin(&tlbivax_mutex); 923176771Sraj} 924176771Sraj 925176771Sraj/* Return the pa for the given pmap/va. */ 926176771Srajstatic vm_paddr_t 927176771Srajpte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 928176771Sraj{ 929176771Sraj vm_paddr_t pa = 0; 930176771Sraj pte_t *pte; 931176771Sraj 932176771Sraj pte = pte_find(mmu, pmap, va); 933176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 934176771Sraj pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 935176771Sraj return (pa); 936176771Sraj} 937176771Sraj 938176771Sraj/* Get a pointer to a PTE in a page table. */ 939176771Srajstatic pte_t * 940176771Srajpte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 941176771Sraj{ 942176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 943176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 944176771Sraj 945176771Sraj KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 946176771Sraj 947176771Sraj if (pmap->pm_pdir[pdir_idx]) 948176771Sraj return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 949176771Sraj 950176771Sraj return (NULL); 951176771Sraj} 952176771Sraj 953176771Sraj/**************************************************************************/ 954176771Sraj/* PMAP related */ 955176771Sraj/**************************************************************************/ 956176771Sraj 957176771Sraj/* 958176771Sraj * This is called during e500_init, before the system is really initialized. 959176771Sraj */ 960176771Srajstatic void 961190701Smarcelmmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 962176771Sraj{ 963176771Sraj vm_offset_t phys_kernelend; 964176771Sraj struct mem_region *mp, *mp1; 965176771Sraj int cnt, i, j; 966176771Sraj u_int s, e, sz; 967176771Sraj u_int phys_avail_count; 968182198Sraj vm_size_t physsz, hwphyssz, kstack0_sz; 969182198Sraj vm_offset_t kernel_pdir, kstack0; 970182198Sraj vm_paddr_t kstack0_phys; 971176771Sraj 972176771Sraj debugf("mmu_booke_bootstrap: entered\n"); 973176771Sraj 974187149Sraj /* Initialize invalidation mutex */ 975187149Sraj mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 976187149Sraj 977187149Sraj /* Read TLB0 size and associativity. */ 978187149Sraj tlb0_get_tlbconf(); 979187149Sraj 980176771Sraj /* Align kernel start and end address (kernel image). */ 981190701Smarcel kernstart = trunc_page(start); 982190701Smarcel data_start = round_page(kernelend); 983190701Smarcel kernsize = data_start - kernstart; 984176771Sraj 985190701Smarcel data_end = data_start; 986190701Smarcel 987176771Sraj /* Allocate space for the message buffer. */ 988190701Smarcel msgbufp = (struct msgbuf *)data_end; 989190701Smarcel data_end += MSGBUF_SIZE; 990187149Sraj debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 991190701Smarcel data_end); 992176771Sraj 993190701Smarcel data_end = round_page(data_end); 994176771Sraj 995176771Sraj /* Allocate space for ptbl_bufs. */ 996190701Smarcel ptbl_bufs = (struct ptbl_buf *)data_end; 997190701Smarcel data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 998187149Sraj debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 999190701Smarcel data_end); 1000176771Sraj 1001190701Smarcel data_end = round_page(data_end); 1002176771Sraj 1003176771Sraj /* Allocate PTE tables for kernel KVA. */ 1004190701Smarcel kernel_pdir = data_end; 1005176771Sraj kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1006176771Sraj PDIR_SIZE - 1) / PDIR_SIZE; 1007190701Smarcel data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1008176771Sraj debugf(" kernel ptbls: %d\n", kernel_ptbls); 1009190701Smarcel debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1010176771Sraj 1011190701Smarcel debugf(" data_end: 0x%08x\n", data_end); 1012190701Smarcel if (data_end - kernstart > 0x1000000) { 1013190701Smarcel data_end = (data_end + 0x3fffff) & ~0x3fffff; 1014190701Smarcel tlb1_mapin_region(kernstart + 0x1000000, 1015190701Smarcel kernload + 0x1000000, data_end - kernstart - 0x1000000); 1016176771Sraj } else 1017190701Smarcel data_end = (data_end + 0xffffff) & ~0xffffff; 1018176771Sraj 1019190701Smarcel debugf(" updated data_end: 0x%08x\n", data_end); 1020187149Sraj 1021190701Smarcel kernsize += data_end - data_start; 1022190701Smarcel 1023182362Sraj /* 1024182362Sraj * Clear the structures - note we can only do it safely after the 1025187149Sraj * possible additional TLB1 translations are in place (above) so that 1026190701Smarcel * all range up to the currently calculated 'data_end' is covered. 1027182362Sraj */ 1028182362Sraj memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1029182362Sraj memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1030182362Sraj 1031176771Sraj /*******************************************************/ 1032176771Sraj /* Set the start and end of kva. */ 1033176771Sraj /*******************************************************/ 1034190701Smarcel virtual_avail = round_page(data_end); 1035176771Sraj virtual_end = VM_MAX_KERNEL_ADDRESS; 1036176771Sraj 1037176771Sraj /* Allocate KVA space for page zero/copy operations. */ 1038176771Sraj zero_page_va = virtual_avail; 1039176771Sraj virtual_avail += PAGE_SIZE; 1040176771Sraj zero_page_idle_va = virtual_avail; 1041176771Sraj virtual_avail += PAGE_SIZE; 1042176771Sraj copy_page_src_va = virtual_avail; 1043176771Sraj virtual_avail += PAGE_SIZE; 1044176771Sraj copy_page_dst_va = virtual_avail; 1045176771Sraj virtual_avail += PAGE_SIZE; 1046187149Sraj debugf("zero_page_va = 0x%08x\n", zero_page_va); 1047187149Sraj debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1048187149Sraj debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1049187149Sraj debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1050176771Sraj 1051176771Sraj /* Initialize page zero/copy mutexes. */ 1052176771Sraj mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1053176771Sraj mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1054176771Sraj 1055176771Sraj /* Allocate KVA space for ptbl bufs. */ 1056176771Sraj ptbl_buf_pool_vabase = virtual_avail; 1057176771Sraj virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1058187149Sraj debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1059187149Sraj ptbl_buf_pool_vabase, virtual_avail); 1060176771Sraj 1061176771Sraj /* Calculate corresponding physical addresses for the kernel region. */ 1062190701Smarcel phys_kernelend = kernload + kernsize; 1063176771Sraj debugf("kernel image and allocated data:\n"); 1064176771Sraj debugf(" kernload = 0x%08x\n", kernload); 1065190701Smarcel debugf(" kernstart = 0x%08x\n", kernstart); 1066190701Smarcel debugf(" kernsize = 0x%08x\n", kernsize); 1067176771Sraj 1068176771Sraj if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1069176771Sraj panic("mmu_booke_bootstrap: phys_avail too small"); 1070176771Sraj 1071176771Sraj /* 1072187151Sraj * Remove kernel physical address range from avail regions list. Page 1073187151Sraj * align all regions. Non-page aligned memory isn't very interesting 1074187151Sraj * to us. Also, sort the entries for ascending addresses. 1075176771Sraj */ 1076192067Snwhitehorn 1077192067Snwhitehorn /* Retrieve phys/avail mem regions */ 1078192067Snwhitehorn mem_regions(&physmem_regions, &physmem_regions_sz, 1079192067Snwhitehorn &availmem_regions, &availmem_regions_sz); 1080176771Sraj sz = 0; 1081176771Sraj cnt = availmem_regions_sz; 1082176771Sraj debugf("processing avail regions:\n"); 1083176771Sraj for (mp = availmem_regions; mp->mr_size; mp++) { 1084176771Sraj s = mp->mr_start; 1085176771Sraj e = mp->mr_start + mp->mr_size; 1086176771Sraj debugf(" %08x-%08x -> ", s, e); 1087176771Sraj /* Check whether this region holds all of the kernel. */ 1088176771Sraj if (s < kernload && e > phys_kernelend) { 1089176771Sraj availmem_regions[cnt].mr_start = phys_kernelend; 1090176771Sraj availmem_regions[cnt++].mr_size = e - phys_kernelend; 1091176771Sraj e = kernload; 1092176771Sraj } 1093176771Sraj /* Look whether this regions starts within the kernel. */ 1094176771Sraj if (s >= kernload && s < phys_kernelend) { 1095176771Sraj if (e <= phys_kernelend) 1096176771Sraj goto empty; 1097176771Sraj s = phys_kernelend; 1098176771Sraj } 1099176771Sraj /* Now look whether this region ends within the kernel. */ 1100176771Sraj if (e > kernload && e <= phys_kernelend) { 1101176771Sraj if (s >= kernload) 1102176771Sraj goto empty; 1103176771Sraj e = kernload; 1104176771Sraj } 1105176771Sraj /* Now page align the start and size of the region. */ 1106176771Sraj s = round_page(s); 1107176771Sraj e = trunc_page(e); 1108176771Sraj if (e < s) 1109176771Sraj e = s; 1110176771Sraj sz = e - s; 1111176771Sraj debugf("%08x-%08x = %x\n", s, e, sz); 1112176771Sraj 1113176771Sraj /* Check whether some memory is left here. */ 1114176771Sraj if (sz == 0) { 1115176771Sraj empty: 1116176771Sraj memmove(mp, mp + 1, 1117176771Sraj (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1118176771Sraj cnt--; 1119176771Sraj mp--; 1120176771Sraj continue; 1121176771Sraj } 1122176771Sraj 1123176771Sraj /* Do an insertion sort. */ 1124176771Sraj for (mp1 = availmem_regions; mp1 < mp; mp1++) 1125176771Sraj if (s < mp1->mr_start) 1126176771Sraj break; 1127176771Sraj if (mp1 < mp) { 1128176771Sraj memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1129176771Sraj mp1->mr_start = s; 1130176771Sraj mp1->mr_size = sz; 1131176771Sraj } else { 1132176771Sraj mp->mr_start = s; 1133176771Sraj mp->mr_size = sz; 1134176771Sraj } 1135176771Sraj } 1136176771Sraj availmem_regions_sz = cnt; 1137176771Sraj 1138176771Sraj /*******************************************************/ 1139182198Sraj /* Steal physical memory for kernel stack from the end */ 1140182198Sraj /* of the first avail region */ 1141182198Sraj /*******************************************************/ 1142182198Sraj kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1143182198Sraj kstack0_phys = availmem_regions[0].mr_start + 1144182198Sraj availmem_regions[0].mr_size; 1145182198Sraj kstack0_phys -= kstack0_sz; 1146182198Sraj availmem_regions[0].mr_size -= kstack0_sz; 1147182198Sraj 1148182198Sraj /*******************************************************/ 1149176771Sraj /* Fill in phys_avail table, based on availmem_regions */ 1150176771Sraj /*******************************************************/ 1151176771Sraj phys_avail_count = 0; 1152176771Sraj physsz = 0; 1153176771Sraj hwphyssz = 0; 1154176771Sraj TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1155176771Sraj 1156176771Sraj debugf("fill in phys_avail:\n"); 1157176771Sraj for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1158176771Sraj 1159176771Sraj debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1160176771Sraj availmem_regions[i].mr_start, 1161187151Sraj availmem_regions[i].mr_start + 1162187151Sraj availmem_regions[i].mr_size, 1163176771Sraj availmem_regions[i].mr_size); 1164176771Sraj 1165182362Sraj if (hwphyssz != 0 && 1166182362Sraj (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1167176771Sraj debugf(" hw.physmem adjust\n"); 1168176771Sraj if (physsz < hwphyssz) { 1169176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1170182362Sraj phys_avail[j + 1] = 1171182362Sraj availmem_regions[i].mr_start + 1172176771Sraj hwphyssz - physsz; 1173176771Sraj physsz = hwphyssz; 1174176771Sraj phys_avail_count++; 1175176771Sraj } 1176176771Sraj break; 1177176771Sraj } 1178176771Sraj 1179176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1180176771Sraj phys_avail[j + 1] = availmem_regions[i].mr_start + 1181176771Sraj availmem_regions[i].mr_size; 1182176771Sraj phys_avail_count++; 1183176771Sraj physsz += availmem_regions[i].mr_size; 1184176771Sraj } 1185176771Sraj physmem = btoc(physsz); 1186176771Sraj 1187176771Sraj /* Calculate the last available physical address. */ 1188176771Sraj for (i = 0; phys_avail[i + 2] != 0; i += 2) 1189176771Sraj ; 1190176771Sraj Maxmem = powerpc_btop(phys_avail[i + 1]); 1191176771Sraj 1192176771Sraj debugf("Maxmem = 0x%08lx\n", Maxmem); 1193176771Sraj debugf("phys_avail_count = %d\n", phys_avail_count); 1194187151Sraj debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1195187151Sraj physmem); 1196176771Sraj 1197176771Sraj /*******************************************************/ 1198176771Sraj /* Initialize (statically allocated) kernel pmap. */ 1199176771Sraj /*******************************************************/ 1200176771Sraj PMAP_LOCK_INIT(kernel_pmap); 1201176771Sraj kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1202176771Sraj 1203187149Sraj debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1204187149Sraj debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1205176771Sraj debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1206176771Sraj kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1207176771Sraj 1208176771Sraj /* Initialize kernel pdir */ 1209176771Sraj for (i = 0; i < kernel_ptbls; i++) 1210176771Sraj kernel_pmap->pm_pdir[kptbl_min + i] = 1211176771Sraj (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1212176771Sraj 1213187149Sraj for (i = 0; i < MAXCPU; i++) { 1214187149Sraj kernel_pmap->pm_tid[i] = TID_KERNEL; 1215187149Sraj 1216187149Sraj /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1217187149Sraj tidbusy[i][0] = kernel_pmap; 1218187149Sraj } 1219187149Sraj /* Mark kernel_pmap active on all CPUs */ 1220176771Sraj kernel_pmap->pm_active = ~0; 1221176771Sraj 1222176771Sraj /*******************************************************/ 1223176771Sraj /* Final setup */ 1224176771Sraj /*******************************************************/ 1225187149Sraj 1226182198Sraj /* Enter kstack0 into kernel map, provide guard page */ 1227182198Sraj kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1228182198Sraj thread0.td_kstack = kstack0; 1229182198Sraj thread0.td_kstack_pages = KSTACK_PAGES; 1230182198Sraj 1231182198Sraj debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1232182198Sraj debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1233182198Sraj kstack0_phys, kstack0_phys + kstack0_sz); 1234182198Sraj debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1235182198Sraj 1236182198Sraj virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1237182198Sraj for (i = 0; i < KSTACK_PAGES; i++) { 1238182198Sraj mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1239182198Sraj kstack0 += PAGE_SIZE; 1240182198Sraj kstack0_phys += PAGE_SIZE; 1241182198Sraj } 1242187149Sraj 1243187149Sraj debugf("virtual_avail = %08x\n", virtual_avail); 1244187149Sraj debugf("virtual_end = %08x\n", virtual_end); 1245182198Sraj 1246176771Sraj debugf("mmu_booke_bootstrap: exit\n"); 1247176771Sraj} 1248176771Sraj 1249192532Srajvoid 1250192532Srajpmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1251192532Sraj{ 1252192532Sraj int i; 1253192532Sraj 1254192532Sraj /* 1255192532Sraj * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1256192532Sraj * have the snapshot of its contents in the s/w tlb1[] table, so use 1257192532Sraj * these values directly to (re)program AP's TLB1 hardware. 1258192532Sraj */ 1259192532Sraj for (i = 0; i < tlb1_idx; i ++) { 1260192532Sraj /* Skip invalid entries */ 1261192532Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 1262192532Sraj continue; 1263192532Sraj 1264192532Sraj tlb1_write_entry(i); 1265192532Sraj } 1266192532Sraj 1267192532Sraj set_mas4_defaults(); 1268192532Sraj} 1269192532Sraj 1270176771Sraj/* 1271176771Sraj * Get the physical page address for the given pmap/virtual address. 1272176771Sraj */ 1273176771Srajstatic vm_paddr_t 1274176771Srajmmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1275176771Sraj{ 1276176771Sraj vm_paddr_t pa; 1277176771Sraj 1278176771Sraj PMAP_LOCK(pmap); 1279176771Sraj pa = pte_vatopa(mmu, pmap, va); 1280176771Sraj PMAP_UNLOCK(pmap); 1281176771Sraj 1282176771Sraj return (pa); 1283176771Sraj} 1284176771Sraj 1285176771Sraj/* 1286176771Sraj * Extract the physical page address associated with the given 1287176771Sraj * kernel virtual address. 1288176771Sraj */ 1289176771Srajstatic vm_paddr_t 1290176771Srajmmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1291176771Sraj{ 1292176771Sraj 1293176771Sraj return (pte_vatopa(mmu, kernel_pmap, va)); 1294176771Sraj} 1295176771Sraj 1296176771Sraj/* 1297176771Sraj * Initialize the pmap module. 1298176771Sraj * Called by vm_init, to initialize any structures that the pmap 1299176771Sraj * system needs to map virtual memory. 1300176771Sraj */ 1301176771Srajstatic void 1302176771Srajmmu_booke_init(mmu_t mmu) 1303176771Sraj{ 1304176771Sraj int shpgperproc = PMAP_SHPGPERPROC; 1305176771Sraj 1306176771Sraj /* 1307176771Sraj * Initialize the address space (zone) for the pv entries. Set a 1308176771Sraj * high water mark so that the system can recover from excessive 1309176771Sraj * numbers of pv entries. 1310176771Sraj */ 1311176771Sraj pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1312176771Sraj NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1313176771Sraj 1314176771Sraj TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1315176771Sraj pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1316176771Sraj 1317176771Sraj TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1318176771Sraj pv_entry_high_water = 9 * (pv_entry_max / 10); 1319176771Sraj 1320176771Sraj uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1321176771Sraj 1322176771Sraj /* Pre-fill pvzone with initial number of pv entries. */ 1323176771Sraj uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1324176771Sraj 1325176771Sraj /* Initialize ptbl allocation. */ 1326176771Sraj ptbl_init(); 1327176771Sraj} 1328176771Sraj 1329176771Sraj/* 1330176771Sraj * Map a list of wired pages into kernel virtual address space. This is 1331176771Sraj * intended for temporary mappings which do not need page modification or 1332176771Sraj * references recorded. Existing mappings in the region are overwritten. 1333176771Sraj */ 1334176771Srajstatic void 1335176771Srajmmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1336176771Sraj{ 1337176771Sraj vm_offset_t va; 1338176771Sraj 1339176771Sraj va = sva; 1340176771Sraj while (count-- > 0) { 1341176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1342176771Sraj va += PAGE_SIZE; 1343176771Sraj m++; 1344176771Sraj } 1345176771Sraj} 1346176771Sraj 1347176771Sraj/* 1348176771Sraj * Remove page mappings from kernel virtual address space. Intended for 1349176771Sraj * temporary mappings entered by mmu_booke_qenter. 1350176771Sraj */ 1351176771Srajstatic void 1352176771Srajmmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1353176771Sraj{ 1354176771Sraj vm_offset_t va; 1355176771Sraj 1356176771Sraj va = sva; 1357176771Sraj while (count-- > 0) { 1358176771Sraj mmu_booke_kremove(mmu, va); 1359176771Sraj va += PAGE_SIZE; 1360176771Sraj } 1361176771Sraj} 1362176771Sraj 1363176771Sraj/* 1364176771Sraj * Map a wired page into kernel virtual address space. 1365176771Sraj */ 1366176771Srajstatic void 1367176771Srajmmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1368176771Sraj{ 1369176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1370176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1371187151Sraj uint32_t flags; 1372176771Sraj pte_t *pte; 1373176771Sraj 1374187151Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1375187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1376176771Sraj 1377176771Sraj flags = 0; 1378176771Sraj flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1379187149Sraj flags |= PTE_M; 1380176771Sraj 1381176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1382176771Sraj 1383187149Sraj mtx_lock_spin(&tlbivax_mutex); 1384192532Sraj tlb_miss_lock(); 1385187149Sraj 1386176771Sraj if (PTE_ISVALID(pte)) { 1387187149Sraj 1388187149Sraj CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1389176771Sraj 1390176771Sraj /* Flush entry from TLB0 */ 1391187149Sraj tlb0_flush_entry(va); 1392176771Sraj } 1393176771Sraj 1394176771Sraj pte->rpn = pa & ~PTE_PA_MASK; 1395176771Sraj pte->flags = flags; 1396176771Sraj 1397176771Sraj //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1398176771Sraj // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1399176771Sraj // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1400176771Sraj 1401176771Sraj /* Flush the real memory from the instruction cache. */ 1402176771Sraj if ((flags & (PTE_I | PTE_G)) == 0) { 1403176771Sraj __syncicache((void *)va, PAGE_SIZE); 1404176771Sraj } 1405176771Sraj 1406192532Sraj tlb_miss_unlock(); 1407187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1408176771Sraj} 1409176771Sraj 1410176771Sraj/* 1411176771Sraj * Remove a page from kernel page table. 1412176771Sraj */ 1413176771Srajstatic void 1414176771Srajmmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1415176771Sraj{ 1416176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1417176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1418176771Sraj pte_t *pte; 1419176771Sraj 1420187149Sraj// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1421176771Sraj 1422187149Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1423187149Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1424176771Sraj ("mmu_booke_kremove: invalid va")); 1425176771Sraj 1426176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1427176771Sraj 1428176771Sraj if (!PTE_ISVALID(pte)) { 1429187149Sraj 1430187149Sraj CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1431187149Sraj 1432176771Sraj return; 1433176771Sraj } 1434176771Sraj 1435187149Sraj mtx_lock_spin(&tlbivax_mutex); 1436192532Sraj tlb_miss_lock(); 1437176771Sraj 1438187149Sraj /* Invalidate entry in TLB0, update PTE. */ 1439187149Sraj tlb0_flush_entry(va); 1440176771Sraj pte->flags = 0; 1441176771Sraj pte->rpn = 0; 1442176771Sraj 1443192532Sraj tlb_miss_unlock(); 1444187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1445176771Sraj} 1446176771Sraj 1447176771Sraj/* 1448176771Sraj * Initialize pmap associated with process 0. 1449176771Sraj */ 1450176771Srajstatic void 1451176771Srajmmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1452176771Sraj{ 1453187151Sraj 1454176771Sraj mmu_booke_pinit(mmu, pmap); 1455176771Sraj PCPU_SET(curpmap, pmap); 1456176771Sraj} 1457176771Sraj 1458176771Sraj/* 1459176771Sraj * Initialize a preallocated and zeroed pmap structure, 1460176771Sraj * such as one in a vmspace structure. 1461176771Sraj */ 1462176771Srajstatic void 1463176771Srajmmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1464176771Sraj{ 1465187149Sraj int i; 1466176771Sraj 1467187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1468187149Sraj curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1469176771Sraj 1470187149Sraj KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1471176771Sraj 1472176771Sraj PMAP_LOCK_INIT(pmap); 1473187149Sraj for (i = 0; i < MAXCPU; i++) 1474187149Sraj pmap->pm_tid[i] = TID_NONE; 1475176771Sraj pmap->pm_active = 0; 1476176771Sraj bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1477176771Sraj bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1478187149Sraj TAILQ_INIT(&pmap->pm_ptbl_list); 1479176771Sraj} 1480176771Sraj 1481176771Sraj/* 1482176771Sraj * Release any resources held by the given physical map. 1483176771Sraj * Called when a pmap initialized by mmu_booke_pinit is being released. 1484176771Sraj * Should only be called if the map contains no valid mappings. 1485176771Sraj */ 1486176771Srajstatic void 1487176771Srajmmu_booke_release(mmu_t mmu, pmap_t pmap) 1488176771Sraj{ 1489176771Sraj 1490187151Sraj printf("mmu_booke_release: s\n"); 1491176771Sraj 1492187151Sraj KASSERT(pmap->pm_stats.resident_count == 0, 1493187151Sraj ("pmap_release: pmap resident count %ld != 0", 1494187151Sraj pmap->pm_stats.resident_count)); 1495187151Sraj 1496176771Sraj PMAP_LOCK_DESTROY(pmap); 1497176771Sraj} 1498176771Sraj 1499176771Sraj/* 1500176771Sraj * Insert the given physical page at the specified virtual address in the 1501176771Sraj * target physical map with the protection requested. If specified the page 1502176771Sraj * will be wired down. 1503176771Sraj */ 1504176771Srajstatic void 1505176771Srajmmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1506176771Sraj vm_prot_t prot, boolean_t wired) 1507176771Sraj{ 1508187151Sraj 1509176771Sraj vm_page_lock_queues(); 1510176771Sraj PMAP_LOCK(pmap); 1511176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1512176771Sraj vm_page_unlock_queues(); 1513176771Sraj PMAP_UNLOCK(pmap); 1514176771Sraj} 1515176771Sraj 1516176771Srajstatic void 1517176771Srajmmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1518176771Sraj vm_prot_t prot, boolean_t wired) 1519176771Sraj{ 1520176771Sraj pte_t *pte; 1521176771Sraj vm_paddr_t pa; 1522187151Sraj uint32_t flags; 1523176771Sraj int su, sync; 1524176771Sraj 1525176771Sraj pa = VM_PAGE_TO_PHYS(m); 1526176771Sraj su = (pmap == kernel_pmap); 1527176771Sraj sync = 0; 1528176771Sraj 1529176771Sraj //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1530176771Sraj // "pa=0x%08x prot=0x%08x wired=%d)\n", 1531176771Sraj // (u_int32_t)pmap, su, pmap->pm_tid, 1532176771Sraj // (u_int32_t)m, va, pa, prot, wired); 1533176771Sraj 1534176771Sraj if (su) { 1535187151Sraj KASSERT(((va >= virtual_avail) && 1536187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1537187151Sraj ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1538176771Sraj } else { 1539176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1540187151Sraj ("mmu_booke_enter_locked: user pmap, non user va")); 1541176771Sraj } 1542176771Sraj 1543176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1544176771Sraj 1545176771Sraj /* 1546176771Sraj * If there is an existing mapping, and the physical address has not 1547176771Sraj * changed, must be protection or wiring change. 1548176771Sraj */ 1549176771Sraj if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1550176771Sraj (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1551187149Sraj 1552187149Sraj /* 1553187149Sraj * Before actually updating pte->flags we calculate and 1554187149Sraj * prepare its new value in a helper var. 1555187149Sraj */ 1556187149Sraj flags = pte->flags; 1557187149Sraj flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1558176771Sraj 1559176771Sraj /* Wiring change, just update stats. */ 1560176771Sraj if (wired) { 1561176771Sraj if (!PTE_ISWIRED(pte)) { 1562187149Sraj flags |= PTE_WIRED; 1563176771Sraj pmap->pm_stats.wired_count++; 1564176771Sraj } 1565176771Sraj } else { 1566176771Sraj if (PTE_ISWIRED(pte)) { 1567187149Sraj flags &= ~PTE_WIRED; 1568176771Sraj pmap->pm_stats.wired_count--; 1569176771Sraj } 1570176771Sraj } 1571176771Sraj 1572176771Sraj if (prot & VM_PROT_WRITE) { 1573176771Sraj /* Add write permissions. */ 1574187149Sraj flags |= PTE_SW; 1575176771Sraj if (!su) 1576187149Sraj flags |= PTE_UW; 1577192795Sraj 1578192795Sraj vm_page_flag_set(m, PG_WRITEABLE); 1579176771Sraj } else { 1580176771Sraj /* Handle modified pages, sense modify status. */ 1581187149Sraj 1582187149Sraj /* 1583187149Sraj * The PTE_MODIFIED flag could be set by underlying 1584187149Sraj * TLB misses since we last read it (above), possibly 1585187149Sraj * other CPUs could update it so we check in the PTE 1586187149Sraj * directly rather than rely on that saved local flags 1587187149Sraj * copy. 1588187149Sraj */ 1589178626Smarcel if (PTE_ISMODIFIED(pte)) 1590178626Smarcel vm_page_dirty(m); 1591176771Sraj } 1592176771Sraj 1593176771Sraj if (prot & VM_PROT_EXECUTE) { 1594187149Sraj flags |= PTE_SX; 1595176771Sraj if (!su) 1596187149Sraj flags |= PTE_UX; 1597176771Sraj 1598187149Sraj /* 1599187149Sraj * Check existing flags for execute permissions: if we 1600187149Sraj * are turning execute permissions on, icache should 1601187149Sraj * be flushed. 1602187149Sraj */ 1603176771Sraj if ((flags & (PTE_UX | PTE_SX)) == 0) 1604176771Sraj sync++; 1605176771Sraj } 1606176771Sraj 1607187149Sraj flags &= ~PTE_REFERENCED; 1608187149Sraj 1609187149Sraj /* 1610187149Sraj * The new flags value is all calculated -- only now actually 1611187149Sraj * update the PTE. 1612187149Sraj */ 1613187149Sraj mtx_lock_spin(&tlbivax_mutex); 1614192532Sraj tlb_miss_lock(); 1615187149Sraj 1616187149Sraj tlb0_flush_entry(va); 1617187149Sraj pte->flags = flags; 1618187149Sraj 1619192532Sraj tlb_miss_unlock(); 1620187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1621187149Sraj 1622176771Sraj } else { 1623176771Sraj /* 1624187149Sraj * If there is an existing mapping, but it's for a different 1625176771Sraj * physical address, pte_enter() will delete the old mapping. 1626176771Sraj */ 1627176771Sraj //if ((pte != NULL) && PTE_ISVALID(pte)) 1628176771Sraj // debugf("mmu_booke_enter_locked: replace\n"); 1629176771Sraj //else 1630176771Sraj // debugf("mmu_booke_enter_locked: new\n"); 1631176771Sraj 1632176771Sraj /* Now set up the flags and install the new mapping. */ 1633176771Sraj flags = (PTE_SR | PTE_VALID); 1634187149Sraj flags |= PTE_M; 1635176771Sraj 1636176771Sraj if (!su) 1637176771Sraj flags |= PTE_UR; 1638176771Sraj 1639176771Sraj if (prot & VM_PROT_WRITE) { 1640176771Sraj flags |= PTE_SW; 1641176771Sraj if (!su) 1642176771Sraj flags |= PTE_UW; 1643192795Sraj 1644192795Sraj vm_page_flag_set(m, PG_WRITEABLE); 1645176771Sraj } 1646176771Sraj 1647176771Sraj if (prot & VM_PROT_EXECUTE) { 1648176771Sraj flags |= PTE_SX; 1649176771Sraj if (!su) 1650176771Sraj flags |= PTE_UX; 1651176771Sraj } 1652176771Sraj 1653176771Sraj /* If its wired update stats. */ 1654176771Sraj if (wired) { 1655176771Sraj pmap->pm_stats.wired_count++; 1656176771Sraj flags |= PTE_WIRED; 1657176771Sraj } 1658176771Sraj 1659176771Sraj pte_enter(mmu, pmap, m, va, flags); 1660176771Sraj 1661176771Sraj /* Flush the real memory from the instruction cache. */ 1662176771Sraj if (prot & VM_PROT_EXECUTE) 1663176771Sraj sync++; 1664176771Sraj } 1665176771Sraj 1666176771Sraj if (sync && (su || pmap == PCPU_GET(curpmap))) { 1667176771Sraj __syncicache((void *)va, PAGE_SIZE); 1668176771Sraj sync = 0; 1669176771Sraj } 1670176771Sraj 1671176771Sraj if (sync) { 1672176771Sraj /* Create a temporary mapping. */ 1673176771Sraj pmap = PCPU_GET(curpmap); 1674176771Sraj 1675176771Sraj va = 0; 1676176771Sraj pte = pte_find(mmu, pmap, va); 1677176771Sraj KASSERT(pte == NULL, ("%s:%d", __func__, __LINE__)); 1678176771Sraj 1679187149Sraj flags = PTE_SR | PTE_VALID | PTE_UR | PTE_M; 1680187149Sraj 1681176771Sraj pte_enter(mmu, pmap, m, va, flags); 1682176771Sraj __syncicache((void *)va, PAGE_SIZE); 1683176771Sraj pte_remove(mmu, pmap, va, PTBL_UNHOLD); 1684176771Sraj } 1685176771Sraj} 1686176771Sraj 1687176771Sraj/* 1688176771Sraj * Maps a sequence of resident pages belonging to the same object. 1689176771Sraj * The sequence begins with the given page m_start. This page is 1690176771Sraj * mapped at the given virtual address start. Each subsequent page is 1691176771Sraj * mapped at a virtual address that is offset from start by the same 1692176771Sraj * amount as the page is offset from m_start within the object. The 1693176771Sraj * last page in the sequence is the page with the largest offset from 1694176771Sraj * m_start that can be mapped at a virtual address less than the given 1695176771Sraj * virtual address end. Not every virtual page between start and end 1696176771Sraj * is mapped; only those for which a resident page exists with the 1697176771Sraj * corresponding offset from m_start are mapped. 1698176771Sraj */ 1699176771Srajstatic void 1700176771Srajmmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1701176771Sraj vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1702176771Sraj{ 1703176771Sraj vm_page_t m; 1704176771Sraj vm_pindex_t diff, psize; 1705176771Sraj 1706176771Sraj psize = atop(end - start); 1707176771Sraj m = m_start; 1708176771Sraj PMAP_LOCK(pmap); 1709176771Sraj while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1710187151Sraj mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1711187151Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1712176771Sraj m = TAILQ_NEXT(m, listq); 1713176771Sraj } 1714176771Sraj PMAP_UNLOCK(pmap); 1715176771Sraj} 1716176771Sraj 1717176771Srajstatic void 1718176771Srajmmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1719176771Sraj vm_prot_t prot) 1720176771Sraj{ 1721176771Sraj 1722176771Sraj PMAP_LOCK(pmap); 1723176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, 1724176771Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1725176771Sraj PMAP_UNLOCK(pmap); 1726176771Sraj} 1727176771Sraj 1728176771Sraj/* 1729176771Sraj * Remove the given range of addresses from the specified map. 1730176771Sraj * 1731176771Sraj * It is assumed that the start and end are properly rounded to the page size. 1732176771Sraj */ 1733176771Srajstatic void 1734176771Srajmmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1735176771Sraj{ 1736176771Sraj pte_t *pte; 1737187151Sraj uint8_t hold_flag; 1738176771Sraj 1739176771Sraj int su = (pmap == kernel_pmap); 1740176771Sraj 1741176771Sraj //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1742176771Sraj // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1743176771Sraj 1744176771Sraj if (su) { 1745187151Sraj KASSERT(((va >= virtual_avail) && 1746187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1747187151Sraj ("mmu_booke_remove: kernel pmap, non kernel va")); 1748176771Sraj } else { 1749176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1750187151Sraj ("mmu_booke_remove: user pmap, non user va")); 1751176771Sraj } 1752176771Sraj 1753176771Sraj if (PMAP_REMOVE_DONE(pmap)) { 1754176771Sraj //debugf("mmu_booke_remove: e (empty)\n"); 1755176771Sraj return; 1756176771Sraj } 1757176771Sraj 1758176771Sraj hold_flag = PTBL_HOLD_FLAG(pmap); 1759176771Sraj //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1760176771Sraj 1761176771Sraj vm_page_lock_queues(); 1762176771Sraj PMAP_LOCK(pmap); 1763176771Sraj for (; va < endva; va += PAGE_SIZE) { 1764176771Sraj pte = pte_find(mmu, pmap, va); 1765187149Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 1766176771Sraj pte_remove(mmu, pmap, va, hold_flag); 1767176771Sraj } 1768176771Sraj PMAP_UNLOCK(pmap); 1769176771Sraj vm_page_unlock_queues(); 1770176771Sraj 1771176771Sraj //debugf("mmu_booke_remove: e\n"); 1772176771Sraj} 1773176771Sraj 1774176771Sraj/* 1775176771Sraj * Remove physical page from all pmaps in which it resides. 1776176771Sraj */ 1777176771Srajstatic void 1778176771Srajmmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1779176771Sraj{ 1780176771Sraj pv_entry_t pv, pvn; 1781187151Sraj uint8_t hold_flag; 1782176771Sraj 1783176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1784176771Sraj 1785176771Sraj for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1786176771Sraj pvn = TAILQ_NEXT(pv, pv_link); 1787176771Sraj 1788176771Sraj PMAP_LOCK(pv->pv_pmap); 1789176771Sraj hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1790176771Sraj pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1791176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1792176771Sraj } 1793176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1794176771Sraj} 1795176771Sraj 1796176771Sraj/* 1797176771Sraj * Map a range of physical addresses into kernel virtual address space. 1798176771Sraj */ 1799176771Srajstatic vm_offset_t 1800176771Srajmmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1801176771Sraj vm_offset_t pa_end, int prot) 1802176771Sraj{ 1803176771Sraj vm_offset_t sva = *virt; 1804176771Sraj vm_offset_t va = sva; 1805176771Sraj 1806176771Sraj //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1807176771Sraj // sva, pa_start, pa_end); 1808176771Sraj 1809176771Sraj while (pa_start < pa_end) { 1810176771Sraj mmu_booke_kenter(mmu, va, pa_start); 1811176771Sraj va += PAGE_SIZE; 1812176771Sraj pa_start += PAGE_SIZE; 1813176771Sraj } 1814176771Sraj *virt = va; 1815176771Sraj 1816176771Sraj //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1817176771Sraj return (sva); 1818176771Sraj} 1819176771Sraj 1820176771Sraj/* 1821176771Sraj * The pmap must be activated before it's address space can be accessed in any 1822176771Sraj * way. 1823176771Sraj */ 1824176771Srajstatic void 1825176771Srajmmu_booke_activate(mmu_t mmu, struct thread *td) 1826176771Sraj{ 1827176771Sraj pmap_t pmap; 1828176771Sraj 1829176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1830176771Sraj 1831187149Sraj CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1832187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1833176771Sraj 1834176771Sraj KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1835176771Sraj 1836176771Sraj mtx_lock_spin(&sched_lock); 1837176771Sraj 1838187149Sraj atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 1839176771Sraj PCPU_SET(curpmap, pmap); 1840187149Sraj 1841187149Sraj if (pmap->pm_tid[PCPU_GET(cpuid)] == TID_NONE) 1842176771Sraj tid_alloc(pmap); 1843176771Sraj 1844176771Sraj /* Load PID0 register with pmap tid value. */ 1845187149Sraj mtspr(SPR_PID0, pmap->pm_tid[PCPU_GET(cpuid)]); 1846187149Sraj __asm __volatile("isync"); 1847176771Sraj 1848176771Sraj mtx_unlock_spin(&sched_lock); 1849176771Sraj 1850187149Sraj CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1851187149Sraj pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1852176771Sraj} 1853176771Sraj 1854176771Sraj/* 1855176771Sraj * Deactivate the specified process's address space. 1856176771Sraj */ 1857176771Srajstatic void 1858176771Srajmmu_booke_deactivate(mmu_t mmu, struct thread *td) 1859176771Sraj{ 1860176771Sraj pmap_t pmap; 1861176771Sraj 1862176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1863187149Sraj 1864187149Sraj CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1865187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1866187149Sraj 1867187149Sraj atomic_clear_int(&pmap->pm_active, PCPU_GET(cpumask)); 1868176771Sraj PCPU_SET(curpmap, NULL); 1869176771Sraj} 1870176771Sraj 1871176771Sraj/* 1872176771Sraj * Copy the range specified by src_addr/len 1873176771Sraj * from the source map to the range dst_addr/len 1874176771Sraj * in the destination map. 1875176771Sraj * 1876176771Sraj * This routine is only advisory and need not do anything. 1877176771Sraj */ 1878176771Srajstatic void 1879176771Srajmmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 1880176771Sraj vm_size_t len, vm_offset_t src_addr) 1881176771Sraj{ 1882176771Sraj 1883176771Sraj} 1884176771Sraj 1885176771Sraj/* 1886176771Sraj * Set the physical protection on the specified range of this map as requested. 1887176771Sraj */ 1888176771Srajstatic void 1889176771Srajmmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1890176771Sraj vm_prot_t prot) 1891176771Sraj{ 1892176771Sraj vm_offset_t va; 1893176771Sraj vm_page_t m; 1894176771Sraj pte_t *pte; 1895176771Sraj 1896176771Sraj if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1897176771Sraj mmu_booke_remove(mmu, pmap, sva, eva); 1898176771Sraj return; 1899176771Sraj } 1900176771Sraj 1901176771Sraj if (prot & VM_PROT_WRITE) 1902176771Sraj return; 1903176771Sraj 1904176771Sraj vm_page_lock_queues(); 1905176771Sraj PMAP_LOCK(pmap); 1906176771Sraj for (va = sva; va < eva; va += PAGE_SIZE) { 1907176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1908176771Sraj if (PTE_ISVALID(pte)) { 1909176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1910176771Sraj 1911187149Sraj mtx_lock_spin(&tlbivax_mutex); 1912192532Sraj tlb_miss_lock(); 1913187149Sraj 1914176771Sraj /* Handle modified pages. */ 1915178626Smarcel if (PTE_ISMODIFIED(pte)) 1916178626Smarcel vm_page_dirty(m); 1917176771Sraj 1918176771Sraj /* Referenced pages. */ 1919176771Sraj if (PTE_ISREFERENCED(pte)) 1920176771Sraj vm_page_flag_set(m, PG_REFERENCED); 1921176771Sraj 1922187149Sraj tlb0_flush_entry(va); 1923176771Sraj pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1924176771Sraj PTE_REFERENCED); 1925187149Sraj 1926192532Sraj tlb_miss_unlock(); 1927187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1928176771Sraj } 1929176771Sraj } 1930176771Sraj } 1931176771Sraj PMAP_UNLOCK(pmap); 1932176771Sraj vm_page_unlock_queues(); 1933176771Sraj} 1934176771Sraj 1935176771Sraj/* 1936176771Sraj * Clear the write and modified bits in each of the given page's mappings. 1937176771Sraj */ 1938176771Srajstatic void 1939176771Srajmmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1940176771Sraj{ 1941176771Sraj pv_entry_t pv; 1942176771Sraj pte_t *pte; 1943176771Sraj 1944176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1945176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1946176771Sraj (m->flags & PG_WRITEABLE) == 0) 1947176771Sraj return; 1948176771Sraj 1949176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1950176771Sraj PMAP_LOCK(pv->pv_pmap); 1951176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1952176771Sraj if (PTE_ISVALID(pte)) { 1953176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1954176771Sraj 1955187149Sraj mtx_lock_spin(&tlbivax_mutex); 1956192532Sraj tlb_miss_lock(); 1957187149Sraj 1958176771Sraj /* Handle modified pages. */ 1959178626Smarcel if (PTE_ISMODIFIED(pte)) 1960178626Smarcel vm_page_dirty(m); 1961176771Sraj 1962176771Sraj /* Referenced pages. */ 1963176771Sraj if (PTE_ISREFERENCED(pte)) 1964176771Sraj vm_page_flag_set(m, PG_REFERENCED); 1965176771Sraj 1966176771Sraj /* Flush mapping from TLB0. */ 1967176771Sraj pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1968176771Sraj PTE_REFERENCED); 1969187149Sraj 1970192532Sraj tlb_miss_unlock(); 1971187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1972176771Sraj } 1973176771Sraj } 1974176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1975176771Sraj } 1976176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1977176771Sraj} 1978176771Sraj 1979176771Srajstatic boolean_t 1980176771Srajmmu_booke_page_executable(mmu_t mmu, vm_page_t m) 1981176771Sraj{ 1982176771Sraj pv_entry_t pv; 1983176771Sraj pte_t *pte; 1984176771Sraj boolean_t executable; 1985176771Sraj 1986176771Sraj executable = FALSE; 1987176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1988176771Sraj PMAP_LOCK(pv->pv_pmap); 1989176771Sraj pte = pte_find(mmu, pv->pv_pmap, pv->pv_va); 1990176771Sraj if (pte != NULL && PTE_ISVALID(pte) && (pte->flags & PTE_UX)) 1991176771Sraj executable = TRUE; 1992176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1993176771Sraj if (executable) 1994176771Sraj break; 1995176771Sraj } 1996176771Sraj 1997176771Sraj return (executable); 1998176771Sraj} 1999176771Sraj 2000176771Sraj/* 2001176771Sraj * Atomically extract and hold the physical page with the given 2002176771Sraj * pmap and virtual address pair if that mapping permits the given 2003176771Sraj * protection. 2004176771Sraj */ 2005176771Srajstatic vm_page_t 2006176771Srajmmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2007176771Sraj vm_prot_t prot) 2008176771Sraj{ 2009176771Sraj pte_t *pte; 2010176771Sraj vm_page_t m; 2011187151Sraj uint32_t pte_wbit; 2012176771Sraj 2013176771Sraj m = NULL; 2014176771Sraj vm_page_lock_queues(); 2015176771Sraj PMAP_LOCK(pmap); 2016187151Sraj 2017176771Sraj pte = pte_find(mmu, pmap, va); 2018176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) { 2019176771Sraj if (pmap == kernel_pmap) 2020176771Sraj pte_wbit = PTE_SW; 2021176771Sraj else 2022176771Sraj pte_wbit = PTE_UW; 2023176771Sraj 2024176771Sraj if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2025176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2026176771Sraj vm_page_hold(m); 2027176771Sraj } 2028176771Sraj } 2029176771Sraj 2030176771Sraj vm_page_unlock_queues(); 2031176771Sraj PMAP_UNLOCK(pmap); 2032176771Sraj return (m); 2033176771Sraj} 2034176771Sraj 2035176771Sraj/* 2036176771Sraj * Initialize a vm_page's machine-dependent fields. 2037176771Sraj */ 2038176771Srajstatic void 2039176771Srajmmu_booke_page_init(mmu_t mmu, vm_page_t m) 2040176771Sraj{ 2041176771Sraj 2042176771Sraj TAILQ_INIT(&m->md.pv_list); 2043176771Sraj} 2044176771Sraj 2045176771Sraj/* 2046176771Sraj * mmu_booke_zero_page_area zeros the specified hardware page by 2047176771Sraj * mapping it into virtual memory and using bzero to clear 2048176771Sraj * its contents. 2049176771Sraj * 2050176771Sraj * off and size must reside within a single page. 2051176771Sraj */ 2052176771Srajstatic void 2053176771Srajmmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2054176771Sraj{ 2055176771Sraj vm_offset_t va; 2056176771Sraj 2057187151Sraj /* XXX KASSERT off and size are within a single page? */ 2058176771Sraj 2059176771Sraj mtx_lock(&zero_page_mutex); 2060176771Sraj va = zero_page_va; 2061176771Sraj 2062176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2063176771Sraj bzero((caddr_t)va + off, size); 2064176771Sraj mmu_booke_kremove(mmu, va); 2065176771Sraj 2066176771Sraj mtx_unlock(&zero_page_mutex); 2067176771Sraj} 2068176771Sraj 2069176771Sraj/* 2070176771Sraj * mmu_booke_zero_page zeros the specified hardware page. 2071176771Sraj */ 2072176771Srajstatic void 2073176771Srajmmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2074176771Sraj{ 2075176771Sraj 2076176771Sraj mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2077176771Sraj} 2078176771Sraj 2079176771Sraj/* 2080176771Sraj * mmu_booke_copy_page copies the specified (machine independent) page by 2081176771Sraj * mapping the page into virtual memory and using memcopy to copy the page, 2082176771Sraj * one machine dependent page at a time. 2083176771Sraj */ 2084176771Srajstatic void 2085176771Srajmmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2086176771Sraj{ 2087176771Sraj vm_offset_t sva, dva; 2088176771Sraj 2089176771Sraj sva = copy_page_src_va; 2090176771Sraj dva = copy_page_dst_va; 2091176771Sraj 2092187149Sraj mtx_lock(©_page_mutex); 2093176771Sraj mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2094176771Sraj mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2095176771Sraj memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2096176771Sraj mmu_booke_kremove(mmu, dva); 2097176771Sraj mmu_booke_kremove(mmu, sva); 2098176771Sraj mtx_unlock(©_page_mutex); 2099176771Sraj} 2100176771Sraj 2101176771Sraj/* 2102176771Sraj * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2103176771Sraj * into virtual memory and using bzero to clear its contents. This is intended 2104176771Sraj * to be called from the vm_pagezero process only and outside of Giant. No 2105176771Sraj * lock is required. 2106176771Sraj */ 2107176771Srajstatic void 2108176771Srajmmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2109176771Sraj{ 2110176771Sraj vm_offset_t va; 2111176771Sraj 2112176771Sraj va = zero_page_idle_va; 2113176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2114176771Sraj bzero((caddr_t)va, PAGE_SIZE); 2115176771Sraj mmu_booke_kremove(mmu, va); 2116176771Sraj} 2117176771Sraj 2118176771Sraj/* 2119176771Sraj * Return whether or not the specified physical page was modified 2120176771Sraj * in any of physical maps. 2121176771Sraj */ 2122176771Srajstatic boolean_t 2123176771Srajmmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2124176771Sraj{ 2125176771Sraj pte_t *pte; 2126176771Sraj pv_entry_t pv; 2127176771Sraj 2128176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2129176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2130176771Sraj return (FALSE); 2131176771Sraj 2132176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2133176771Sraj PMAP_LOCK(pv->pv_pmap); 2134176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2135176771Sraj if (!PTE_ISVALID(pte)) 2136176771Sraj goto make_sure_to_unlock; 2137176771Sraj 2138176771Sraj if (PTE_ISMODIFIED(pte)) { 2139176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2140176771Sraj return (TRUE); 2141176771Sraj } 2142176771Sraj } 2143176771Srajmake_sure_to_unlock: 2144176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2145176771Sraj } 2146176771Sraj return (FALSE); 2147176771Sraj} 2148176771Sraj 2149176771Sraj/* 2150187151Sraj * Return whether or not the specified virtual address is eligible 2151176771Sraj * for prefault. 2152176771Sraj */ 2153176771Srajstatic boolean_t 2154176771Srajmmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2155176771Sraj{ 2156176771Sraj 2157176771Sraj return (FALSE); 2158176771Sraj} 2159176771Sraj 2160176771Sraj/* 2161176771Sraj * Clear the modify bits on the specified physical page. 2162176771Sraj */ 2163176771Srajstatic void 2164176771Srajmmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2165176771Sraj{ 2166176771Sraj pte_t *pte; 2167176771Sraj pv_entry_t pv; 2168176771Sraj 2169176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2170176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2171176771Sraj return; 2172176771Sraj 2173176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2174176771Sraj PMAP_LOCK(pv->pv_pmap); 2175176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2176176771Sraj if (!PTE_ISVALID(pte)) 2177176771Sraj goto make_sure_to_unlock; 2178176771Sraj 2179187149Sraj mtx_lock_spin(&tlbivax_mutex); 2180192532Sraj tlb_miss_lock(); 2181187149Sraj 2182176771Sraj if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2183187149Sraj tlb0_flush_entry(pv->pv_va); 2184176771Sraj pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2185176771Sraj PTE_REFERENCED); 2186176771Sraj } 2187187149Sraj 2188192532Sraj tlb_miss_unlock(); 2189187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2190176771Sraj } 2191176771Srajmake_sure_to_unlock: 2192176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2193176771Sraj } 2194176771Sraj} 2195176771Sraj 2196176771Sraj/* 2197176771Sraj * Return a count of reference bits for a page, clearing those bits. 2198176771Sraj * It is not necessary for every reference bit to be cleared, but it 2199176771Sraj * is necessary that 0 only be returned when there are truly no 2200176771Sraj * reference bits set. 2201176771Sraj * 2202176771Sraj * XXX: The exact number of bits to check and clear is a matter that 2203176771Sraj * should be tested and standardized at some point in the future for 2204176771Sraj * optimal aging of shared pages. 2205176771Sraj */ 2206176771Srajstatic int 2207176771Srajmmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2208176771Sraj{ 2209176771Sraj pte_t *pte; 2210176771Sraj pv_entry_t pv; 2211176771Sraj int count; 2212176771Sraj 2213176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2214176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2215176771Sraj return (0); 2216176771Sraj 2217176771Sraj count = 0; 2218176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2219176771Sraj PMAP_LOCK(pv->pv_pmap); 2220176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2221176771Sraj if (!PTE_ISVALID(pte)) 2222176771Sraj goto make_sure_to_unlock; 2223176771Sraj 2224176771Sraj if (PTE_ISREFERENCED(pte)) { 2225187149Sraj mtx_lock_spin(&tlbivax_mutex); 2226192532Sraj tlb_miss_lock(); 2227187149Sraj 2228187149Sraj tlb0_flush_entry(pv->pv_va); 2229176771Sraj pte->flags &= ~PTE_REFERENCED; 2230176771Sraj 2231192532Sraj tlb_miss_unlock(); 2232187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2233187149Sraj 2234176771Sraj if (++count > 4) { 2235176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2236176771Sraj break; 2237176771Sraj } 2238176771Sraj } 2239176771Sraj } 2240176771Srajmake_sure_to_unlock: 2241176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2242176771Sraj } 2243176771Sraj return (count); 2244176771Sraj} 2245176771Sraj 2246176771Sraj/* 2247176771Sraj * Clear the reference bit on the specified physical page. 2248176771Sraj */ 2249176771Srajstatic void 2250176771Srajmmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2251176771Sraj{ 2252176771Sraj pte_t *pte; 2253176771Sraj pv_entry_t pv; 2254176771Sraj 2255176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2256176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2257176771Sraj return; 2258176771Sraj 2259176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2260176771Sraj PMAP_LOCK(pv->pv_pmap); 2261176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2262176771Sraj if (!PTE_ISVALID(pte)) 2263176771Sraj goto make_sure_to_unlock; 2264176771Sraj 2265176771Sraj if (PTE_ISREFERENCED(pte)) { 2266187149Sraj mtx_lock_spin(&tlbivax_mutex); 2267192532Sraj tlb_miss_lock(); 2268187149Sraj 2269187149Sraj tlb0_flush_entry(pv->pv_va); 2270176771Sraj pte->flags &= ~PTE_REFERENCED; 2271187149Sraj 2272192532Sraj tlb_miss_unlock(); 2273187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2274176771Sraj } 2275176771Sraj } 2276176771Srajmake_sure_to_unlock: 2277176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2278176771Sraj } 2279176771Sraj} 2280176771Sraj 2281176771Sraj/* 2282176771Sraj * Change wiring attribute for a map/virtual-address pair. 2283176771Sraj */ 2284176771Srajstatic void 2285176771Srajmmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2286176771Sraj{ 2287176771Sraj pte_t *pte;; 2288176771Sraj 2289176771Sraj PMAP_LOCK(pmap); 2290176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2291176771Sraj if (wired) { 2292176771Sraj if (!PTE_ISWIRED(pte)) { 2293176771Sraj pte->flags |= PTE_WIRED; 2294176771Sraj pmap->pm_stats.wired_count++; 2295176771Sraj } 2296176771Sraj } else { 2297176771Sraj if (PTE_ISWIRED(pte)) { 2298176771Sraj pte->flags &= ~PTE_WIRED; 2299176771Sraj pmap->pm_stats.wired_count--; 2300176771Sraj } 2301176771Sraj } 2302176771Sraj } 2303176771Sraj PMAP_UNLOCK(pmap); 2304176771Sraj} 2305176771Sraj 2306176771Sraj/* 2307176771Sraj * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2308176771Sraj * page. This count may be changed upwards or downwards in the future; it is 2309176771Sraj * only necessary that true be returned for a small subset of pmaps for proper 2310176771Sraj * page aging. 2311176771Sraj */ 2312176771Srajstatic boolean_t 2313176771Srajmmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2314176771Sraj{ 2315176771Sraj pv_entry_t pv; 2316176771Sraj int loops; 2317176771Sraj 2318176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2319176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2320176771Sraj return (FALSE); 2321176771Sraj 2322176771Sraj loops = 0; 2323176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2324176771Sraj if (pv->pv_pmap == pmap) 2325176771Sraj return (TRUE); 2326176771Sraj 2327176771Sraj if (++loops >= 16) 2328176771Sraj break; 2329176771Sraj } 2330176771Sraj return (FALSE); 2331176771Sraj} 2332176771Sraj 2333176771Sraj/* 2334176771Sraj * Return the number of managed mappings to the given physical page that are 2335176771Sraj * wired. 2336176771Sraj */ 2337176771Srajstatic int 2338176771Srajmmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2339176771Sraj{ 2340176771Sraj pv_entry_t pv; 2341176771Sraj pte_t *pte; 2342176771Sraj int count = 0; 2343176771Sraj 2344176771Sraj if ((m->flags & PG_FICTITIOUS) != 0) 2345176771Sraj return (count); 2346176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2347176771Sraj 2348176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2349176771Sraj PMAP_LOCK(pv->pv_pmap); 2350176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2351176771Sraj if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2352176771Sraj count++; 2353176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2354176771Sraj } 2355176771Sraj 2356176771Sraj return (count); 2357176771Sraj} 2358176771Sraj 2359176771Srajstatic int 2360176771Srajmmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2361176771Sraj{ 2362176771Sraj int i; 2363176771Sraj vm_offset_t va; 2364176771Sraj 2365176771Sraj /* 2366176771Sraj * This currently does not work for entries that 2367176771Sraj * overlap TLB1 entries. 2368176771Sraj */ 2369176771Sraj for (i = 0; i < tlb1_idx; i ++) { 2370176771Sraj if (tlb1_iomapped(i, pa, size, &va) == 0) 2371176771Sraj return (0); 2372176771Sraj } 2373176771Sraj 2374176771Sraj return (EFAULT); 2375176771Sraj} 2376176771Sraj 2377190701Smarcelvm_offset_t 2378190701Smarcelmmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2379190701Smarcel vm_size_t *sz) 2380190701Smarcel{ 2381190701Smarcel vm_paddr_t pa, ppa; 2382190701Smarcel vm_offset_t va; 2383190701Smarcel vm_size_t gran; 2384190701Smarcel 2385190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2386190701Smarcel if (md->md_vaddr == ~0UL) { 2387190701Smarcel /* We always map a 256MB page at 256M. */ 2388190701Smarcel gran = 256 * 1024 * 1024; 2389190701Smarcel pa = md->md_paddr + ofs; 2390190701Smarcel ppa = pa & ~(gran - 1); 2391190701Smarcel ofs = pa - ppa; 2392190701Smarcel va = gran; 2393190701Smarcel tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2394190701Smarcel if (*sz > (gran - ofs)) 2395190701Smarcel *sz = gran - ofs; 2396190701Smarcel return (va + ofs); 2397190701Smarcel } 2398190701Smarcel 2399190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2400190701Smarcel va = md->md_vaddr + ofs; 2401190701Smarcel if (va >= kernstart + kernsize) { 2402190701Smarcel gran = PAGE_SIZE - (va & PAGE_MASK); 2403190701Smarcel if (*sz > gran) 2404190701Smarcel *sz = gran; 2405190701Smarcel } 2406190701Smarcel return (va); 2407190701Smarcel} 2408190701Smarcel 2409190701Smarcelvoid 2410190701Smarcelmmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2411190701Smarcel vm_offset_t va) 2412190701Smarcel{ 2413190701Smarcel 2414190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2415190701Smarcel if (md->md_vaddr == ~0UL) { 2416190701Smarcel tlb1_idx--; 2417190701Smarcel tlb1[tlb1_idx].mas1 = 0; 2418190701Smarcel tlb1[tlb1_idx].mas2 = 0; 2419190701Smarcel tlb1[tlb1_idx].mas3 = 0; 2420190701Smarcel tlb1_write_entry(tlb1_idx); 2421190701Smarcel return; 2422190701Smarcel } 2423190701Smarcel 2424190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2425190701Smarcel /* Nothing to do... */ 2426190701Smarcel} 2427190701Smarcel 2428190701Smarcelstruct pmap_md * 2429190701Smarcelmmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2430190701Smarcel{ 2431190701Smarcel static struct pmap_md md; 2432190701Smarcel struct bi_mem_region *mr; 2433190701Smarcel pte_t *pte; 2434190701Smarcel vm_offset_t va; 2435190701Smarcel 2436190701Smarcel if (dumpsys_minidump) { 2437190701Smarcel md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2438190701Smarcel if (prev == NULL) { 2439190701Smarcel /* 1st: kernel .data and .bss. */ 2440190701Smarcel md.md_index = 1; 2441190701Smarcel md.md_vaddr = trunc_page((uintptr_t)_etext); 2442190701Smarcel md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2443190701Smarcel return (&md); 2444190701Smarcel } 2445190701Smarcel switch (prev->md_index) { 2446190701Smarcel case 1: 2447190701Smarcel /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2448190701Smarcel md.md_index = 2; 2449190701Smarcel md.md_vaddr = data_start; 2450190701Smarcel md.md_size = data_end - data_start; 2451190701Smarcel break; 2452190701Smarcel case 2: 2453190701Smarcel /* 3rd: kernel VM. */ 2454190701Smarcel va = prev->md_vaddr + prev->md_size; 2455190701Smarcel /* Find start of next chunk (from va). */ 2456190701Smarcel while (va < virtual_end) { 2457190701Smarcel /* Don't dump the buffer cache. */ 2458190701Smarcel if (va >= kmi.buffer_sva && 2459190701Smarcel va < kmi.buffer_eva) { 2460190701Smarcel va = kmi.buffer_eva; 2461190701Smarcel continue; 2462190701Smarcel } 2463190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2464190701Smarcel if (pte != NULL && PTE_ISVALID(pte)) 2465190701Smarcel break; 2466190701Smarcel va += PAGE_SIZE; 2467190701Smarcel } 2468190701Smarcel if (va < virtual_end) { 2469190701Smarcel md.md_vaddr = va; 2470190701Smarcel va += PAGE_SIZE; 2471190701Smarcel /* Find last page in chunk. */ 2472190701Smarcel while (va < virtual_end) { 2473190701Smarcel /* Don't run into the buffer cache. */ 2474190701Smarcel if (va == kmi.buffer_sva) 2475190701Smarcel break; 2476190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2477190701Smarcel if (pte == NULL || !PTE_ISVALID(pte)) 2478190701Smarcel break; 2479190701Smarcel va += PAGE_SIZE; 2480190701Smarcel } 2481190701Smarcel md.md_size = va - md.md_vaddr; 2482190701Smarcel break; 2483190701Smarcel } 2484190701Smarcel md.md_index = 3; 2485190701Smarcel /* FALLTHROUGH */ 2486190701Smarcel default: 2487190701Smarcel return (NULL); 2488190701Smarcel } 2489190701Smarcel } else { /* minidumps */ 2490190701Smarcel mr = bootinfo_mr(); 2491190701Smarcel if (prev == NULL) { 2492190701Smarcel /* first physical chunk. */ 2493190701Smarcel md.md_paddr = mr->mem_base; 2494190701Smarcel md.md_size = mr->mem_size; 2495190701Smarcel md.md_vaddr = ~0UL; 2496190701Smarcel md.md_index = 1; 2497190701Smarcel } else if (md.md_index < bootinfo->bi_mem_reg_no) { 2498190701Smarcel md.md_paddr = mr[md.md_index].mem_base; 2499190701Smarcel md.md_size = mr[md.md_index].mem_size; 2500190701Smarcel md.md_vaddr = ~0UL; 2501190701Smarcel md.md_index++; 2502190701Smarcel } else { 2503190701Smarcel /* There's no next physical chunk. */ 2504190701Smarcel return (NULL); 2505190701Smarcel } 2506190701Smarcel } 2507190701Smarcel 2508190701Smarcel return (&md); 2509190701Smarcel} 2510190701Smarcel 2511176771Sraj/* 2512176771Sraj * Map a set of physical memory pages into the kernel virtual address space. 2513176771Sraj * Return a pointer to where it is mapped. This routine is intended to be used 2514176771Sraj * for mapping device memory, NOT real memory. 2515176771Sraj */ 2516176771Srajstatic void * 2517176771Srajmmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2518176771Sraj{ 2519184244Smarcel void *res; 2520176771Sraj uintptr_t va; 2521184244Smarcel vm_size_t sz; 2522176771Sraj 2523176771Sraj va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2524184244Smarcel res = (void *)va; 2525184244Smarcel 2526184244Smarcel do { 2527184244Smarcel sz = 1 << (ilog2(size) & ~1); 2528184244Smarcel if (bootverbose) 2529184244Smarcel printf("Wiring VA=%x to PA=%x (size=%x), " 2530184244Smarcel "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2531184244Smarcel tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2532184244Smarcel size -= sz; 2533184244Smarcel pa += sz; 2534184244Smarcel va += sz; 2535184244Smarcel } while (size > 0); 2536184244Smarcel 2537184244Smarcel return (res); 2538176771Sraj} 2539176771Sraj 2540176771Sraj/* 2541176771Sraj * 'Unmap' a range mapped by mmu_booke_mapdev(). 2542176771Sraj */ 2543176771Srajstatic void 2544176771Srajmmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2545176771Sraj{ 2546176771Sraj vm_offset_t base, offset; 2547176771Sraj 2548176771Sraj /* 2549176771Sraj * Unmap only if this is inside kernel virtual space. 2550176771Sraj */ 2551176771Sraj if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2552176771Sraj base = trunc_page(va); 2553176771Sraj offset = va & PAGE_MASK; 2554176771Sraj size = roundup(offset + size, PAGE_SIZE); 2555176771Sraj kmem_free(kernel_map, base, size); 2556176771Sraj } 2557176771Sraj} 2558176771Sraj 2559176771Sraj/* 2560187151Sraj * mmu_booke_object_init_pt preloads the ptes for a given object into the 2561187151Sraj * specified pmap. This eliminates the blast of soft faults on process startup 2562187151Sraj * and immediately after an mmap. 2563176771Sraj */ 2564176771Srajstatic void 2565176771Srajmmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2566176771Sraj vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2567176771Sraj{ 2568187151Sraj 2569176771Sraj VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2570176771Sraj KASSERT(object->type == OBJT_DEVICE, 2571176771Sraj ("mmu_booke_object_init_pt: non-device object")); 2572176771Sraj} 2573176771Sraj 2574176771Sraj/* 2575176771Sraj * Perform the pmap work for mincore. 2576176771Sraj */ 2577176771Srajstatic int 2578176771Srajmmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2579176771Sraj{ 2580176771Sraj 2581176771Sraj TODO; 2582176771Sraj return (0); 2583176771Sraj} 2584176771Sraj 2585176771Sraj/**************************************************************************/ 2586176771Sraj/* TID handling */ 2587176771Sraj/**************************************************************************/ 2588176771Sraj 2589176771Sraj/* 2590176771Sraj * Allocate a TID. If necessary, steal one from someone else. 2591176771Sraj * The new TID is flushed from the TLB before returning. 2592176771Sraj */ 2593176771Srajstatic tlbtid_t 2594176771Srajtid_alloc(pmap_t pmap) 2595176771Sraj{ 2596176771Sraj tlbtid_t tid; 2597187149Sraj int thiscpu; 2598176771Sraj 2599187149Sraj KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2600176771Sraj 2601187149Sraj CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2602176771Sraj 2603187149Sraj thiscpu = PCPU_GET(cpuid); 2604176771Sraj 2605187149Sraj tid = PCPU_GET(tid_next); 2606187149Sraj if (tid > TID_MAX) 2607187149Sraj tid = TID_MIN; 2608187149Sraj PCPU_SET(tid_next, tid + 1); 2609176771Sraj 2610187149Sraj /* If we are stealing TID then clear the relevant pmap's field */ 2611187149Sraj if (tidbusy[thiscpu][tid] != NULL) { 2612176771Sraj 2613187149Sraj CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2614187149Sraj 2615187149Sraj tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2616176771Sraj 2617187149Sraj /* Flush all entries from TLB0 matching this TID. */ 2618187149Sraj tid_flush(tid); 2619176771Sraj } 2620176771Sraj 2621187149Sraj tidbusy[thiscpu][tid] = pmap; 2622187149Sraj pmap->pm_tid[thiscpu] = tid; 2623187149Sraj __asm __volatile("msync; isync"); 2624176771Sraj 2625187149Sraj CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2626187149Sraj PCPU_GET(tid_next)); 2627176771Sraj 2628176771Sraj return (tid); 2629176771Sraj} 2630176771Sraj 2631176771Sraj/**************************************************************************/ 2632176771Sraj/* TLB0 handling */ 2633176771Sraj/**************************************************************************/ 2634176771Sraj 2635176771Srajstatic void 2636187149Srajtlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2637187149Sraj uint32_t mas7) 2638176771Sraj{ 2639176771Sraj int as; 2640176771Sraj char desc[3]; 2641176771Sraj tlbtid_t tid; 2642176771Sraj vm_size_t size; 2643176771Sraj unsigned int tsize; 2644176771Sraj 2645176771Sraj desc[2] = '\0'; 2646176771Sraj if (mas1 & MAS1_VALID) 2647176771Sraj desc[0] = 'V'; 2648176771Sraj else 2649176771Sraj desc[0] = ' '; 2650176771Sraj 2651176771Sraj if (mas1 & MAS1_IPROT) 2652176771Sraj desc[1] = 'P'; 2653176771Sraj else 2654176771Sraj desc[1] = ' '; 2655176771Sraj 2656187149Sraj as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2657176771Sraj tid = MAS1_GETTID(mas1); 2658176771Sraj 2659176771Sraj tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2660176771Sraj size = 0; 2661176771Sraj if (tsize) 2662176771Sraj size = tsize2size(tsize); 2663176771Sraj 2664176771Sraj debugf("%3d: (%s) [AS=%d] " 2665176771Sraj "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2666176771Sraj "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2667176771Sraj i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2668176771Sraj} 2669176771Sraj 2670176771Sraj/* Convert TLB0 va and way number to tlb0[] table index. */ 2671176771Srajstatic inline unsigned int 2672176771Srajtlb0_tableidx(vm_offset_t va, unsigned int way) 2673176771Sraj{ 2674176771Sraj unsigned int idx; 2675176771Sraj 2676176771Sraj idx = (way * TLB0_ENTRIES_PER_WAY); 2677176771Sraj idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2678176771Sraj return (idx); 2679176771Sraj} 2680176771Sraj 2681176771Sraj/* 2682187149Sraj * Invalidate TLB0 entry. 2683176771Sraj */ 2684187149Srajstatic inline void 2685187149Srajtlb0_flush_entry(vm_offset_t va) 2686176771Sraj{ 2687176771Sraj 2688187149Sraj CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2689176771Sraj 2690187149Sraj mtx_assert(&tlbivax_mutex, MA_OWNED); 2691176771Sraj 2692187149Sraj __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2693187149Sraj __asm __volatile("isync; msync"); 2694187149Sraj __asm __volatile("tlbsync; msync"); 2695176771Sraj 2696187149Sraj CTR1(KTR_PMAP, "%s: e", __func__); 2697176771Sraj} 2698176771Sraj 2699176771Sraj/* Print out contents of the MAS registers for each TLB0 entry */ 2700187149Srajvoid 2701176771Srajtlb0_print_tlbentries(void) 2702176771Sraj{ 2703187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 2704176771Sraj int entryidx, way, idx; 2705176771Sraj 2706176771Sraj debugf("TLB0 entries:\n"); 2707187149Sraj for (way = 0; way < TLB0_WAYS; way ++) 2708176771Sraj for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2709176771Sraj 2710176771Sraj mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2711176771Sraj mtspr(SPR_MAS0, mas0); 2712187149Sraj __asm __volatile("isync"); 2713176771Sraj 2714176771Sraj mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2715176771Sraj mtspr(SPR_MAS2, mas2); 2716176771Sraj 2717187149Sraj __asm __volatile("isync; tlbre"); 2718176771Sraj 2719176771Sraj mas1 = mfspr(SPR_MAS1); 2720176771Sraj mas2 = mfspr(SPR_MAS2); 2721176771Sraj mas3 = mfspr(SPR_MAS3); 2722176771Sraj mas7 = mfspr(SPR_MAS7); 2723176771Sraj 2724176771Sraj idx = tlb0_tableidx(mas2, way); 2725176771Sraj tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2726176771Sraj } 2727176771Sraj} 2728176771Sraj 2729176771Sraj/**************************************************************************/ 2730176771Sraj/* TLB1 handling */ 2731176771Sraj/**************************************************************************/ 2732187149Sraj 2733176771Sraj/* 2734187149Sraj * TLB1 mapping notes: 2735187149Sraj * 2736187149Sraj * TLB1[0] CCSRBAR 2737187149Sraj * TLB1[1] Kernel text and data. 2738187149Sraj * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2739187149Sraj * windows, other devices mappings. 2740187149Sraj */ 2741187149Sraj 2742187149Sraj/* 2743176771Sraj * Write given entry to TLB1 hardware. 2744176771Sraj * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2745176771Sraj */ 2746176771Srajstatic void 2747176771Srajtlb1_write_entry(unsigned int idx) 2748176771Sraj{ 2749187151Sraj uint32_t mas0, mas7; 2750176771Sraj 2751176771Sraj //debugf("tlb1_write_entry: s\n"); 2752176771Sraj 2753176771Sraj /* Clear high order RPN bits */ 2754176771Sraj mas7 = 0; 2755176771Sraj 2756176771Sraj /* Select entry */ 2757176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2758176771Sraj //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2759176771Sraj 2760176771Sraj mtspr(SPR_MAS0, mas0); 2761187151Sraj __asm __volatile("isync"); 2762176771Sraj mtspr(SPR_MAS1, tlb1[idx].mas1); 2763187151Sraj __asm __volatile("isync"); 2764176771Sraj mtspr(SPR_MAS2, tlb1[idx].mas2); 2765187151Sraj __asm __volatile("isync"); 2766176771Sraj mtspr(SPR_MAS3, tlb1[idx].mas3); 2767187151Sraj __asm __volatile("isync"); 2768176771Sraj mtspr(SPR_MAS7, mas7); 2769187151Sraj __asm __volatile("isync; tlbwe; isync; msync"); 2770176771Sraj 2771176771Sraj //debugf("tlb1_write_entry: e\n");; 2772176771Sraj} 2773176771Sraj 2774176771Sraj/* 2775176771Sraj * Return the largest uint value log such that 2^log <= num. 2776176771Sraj */ 2777176771Srajstatic unsigned int 2778176771Srajilog2(unsigned int num) 2779176771Sraj{ 2780176771Sraj int lz; 2781176771Sraj 2782176771Sraj __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2783176771Sraj return (31 - lz); 2784176771Sraj} 2785176771Sraj 2786176771Sraj/* 2787176771Sraj * Convert TLB TSIZE value to mapped region size. 2788176771Sraj */ 2789176771Srajstatic vm_size_t 2790176771Srajtsize2size(unsigned int tsize) 2791176771Sraj{ 2792176771Sraj 2793176771Sraj /* 2794176771Sraj * size = 4^tsize KB 2795176771Sraj * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2796176771Sraj */ 2797176771Sraj 2798176771Sraj return ((1 << (2 * tsize)) * 1024); 2799176771Sraj} 2800176771Sraj 2801176771Sraj/* 2802176771Sraj * Convert region size (must be power of 4) to TLB TSIZE value. 2803176771Sraj */ 2804176771Srajstatic unsigned int 2805176771Srajsize2tsize(vm_size_t size) 2806176771Sraj{ 2807176771Sraj 2808176771Sraj return (ilog2(size) / 2 - 5); 2809176771Sraj} 2810176771Sraj 2811176771Sraj/* 2812187149Sraj * Register permanent kernel mapping in TLB1. 2813176771Sraj * 2814187149Sraj * Entries are created starting from index 0 (current free entry is 2815187149Sraj * kept in tlb1_idx) and are not supposed to be invalidated. 2816176771Sraj */ 2817187149Srajstatic int 2818187149Srajtlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2819187149Sraj uint32_t flags) 2820176771Sraj{ 2821187149Sraj uint32_t ts, tid; 2822176771Sraj int tsize; 2823187149Sraj 2824187149Sraj if (tlb1_idx >= TLB1_ENTRIES) { 2825187149Sraj printf("tlb1_set_entry: TLB1 full!\n"); 2826187149Sraj return (-1); 2827187149Sraj } 2828176771Sraj 2829176771Sraj /* Convert size to TSIZE */ 2830176771Sraj tsize = size2tsize(size); 2831176771Sraj 2832187149Sraj tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2833187149Sraj /* XXX TS is hard coded to 0 for now as we only use single address space */ 2834187149Sraj ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2835176771Sraj 2836187149Sraj /* XXX LOCK tlb1[] */ 2837176771Sraj 2838187149Sraj tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2839187149Sraj tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2840187149Sraj tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2841176771Sraj 2842187149Sraj /* Set supervisor RWX permission bits */ 2843187149Sraj tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2844176771Sraj 2845187149Sraj tlb1_write_entry(tlb1_idx++); 2846176771Sraj 2847187149Sraj /* XXX UNLOCK tlb1[] */ 2848176771Sraj 2849187149Sraj /* 2850187149Sraj * XXX in general TLB1 updates should be propagated between CPUs, 2851187149Sraj * since current design assumes to have the same TLB1 set-up on all 2852187149Sraj * cores. 2853187149Sraj */ 2854176771Sraj return (0); 2855176771Sraj} 2856176771Sraj 2857176771Srajstatic int 2858176771Srajtlb1_entry_size_cmp(const void *a, const void *b) 2859176771Sraj{ 2860176771Sraj const vm_size_t *sza; 2861176771Sraj const vm_size_t *szb; 2862176771Sraj 2863176771Sraj sza = a; 2864176771Sraj szb = b; 2865176771Sraj if (*sza > *szb) 2866176771Sraj return (-1); 2867176771Sraj else if (*sza < *szb) 2868176771Sraj return (1); 2869176771Sraj else 2870176771Sraj return (0); 2871176771Sraj} 2872176771Sraj 2873176771Sraj/* 2874187151Sraj * Map in contiguous RAM region into the TLB1 using maximum of 2875176771Sraj * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2876176771Sraj * 2877187151Sraj * If necessary round up last entry size and return total size 2878176771Sraj * used by all allocated entries. 2879176771Sraj */ 2880176771Srajvm_size_t 2881176771Srajtlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2882176771Sraj{ 2883176771Sraj vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2884176771Sraj vm_size_t mapped_size, sz, esz; 2885176771Sraj unsigned int log; 2886176771Sraj int i; 2887176771Sraj 2888187151Sraj CTR4(KTR_PMAP, "%s: region size = 0x%08x va = 0x%08x pa = 0x%08x", 2889187151Sraj __func__, size, va, pa); 2890176771Sraj 2891176771Sraj mapped_size = 0; 2892176771Sraj sz = size; 2893176771Sraj memset(entry_size, 0, sizeof(entry_size)); 2894176771Sraj 2895176771Sraj /* Calculate entry sizes. */ 2896176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2897176771Sraj 2898176771Sraj /* Largest region that is power of 4 and fits within size */ 2899187149Sraj log = ilog2(sz) / 2; 2900176771Sraj esz = 1 << (2 * log); 2901176771Sraj 2902176771Sraj /* If this is last entry cover remaining size. */ 2903176771Sraj if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2904176771Sraj while (esz < sz) 2905176771Sraj esz = esz << 2; 2906176771Sraj } 2907176771Sraj 2908176771Sraj entry_size[i] = esz; 2909176771Sraj mapped_size += esz; 2910176771Sraj if (esz < sz) 2911176771Sraj sz -= esz; 2912176771Sraj else 2913176771Sraj sz = 0; 2914176771Sraj } 2915176771Sraj 2916176771Sraj /* Sort entry sizes, required to get proper entry address alignment. */ 2917176771Sraj qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2918176771Sraj sizeof(vm_size_t), tlb1_entry_size_cmp); 2919176771Sraj 2920176771Sraj /* Load TLB1 entries. */ 2921176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2922176771Sraj esz = entry_size[i]; 2923176771Sraj if (!esz) 2924176771Sraj break; 2925187151Sraj 2926187151Sraj CTR5(KTR_PMAP, "%s: entry %d: sz = 0x%08x (va = 0x%08x " 2927187151Sraj "pa = 0x%08x)", __func__, tlb1_idx, esz, va, pa); 2928187151Sraj 2929176771Sraj tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 2930176771Sraj 2931176771Sraj va += esz; 2932176771Sraj pa += esz; 2933176771Sraj } 2934176771Sraj 2935187151Sraj CTR3(KTR_PMAP, "%s: mapped size 0x%08x (wasted space 0x%08x)", 2936187151Sraj __func__, mapped_size, mapped_size - size); 2937176771Sraj 2938176771Sraj return (mapped_size); 2939176771Sraj} 2940176771Sraj 2941176771Sraj/* 2942176771Sraj * TLB1 initialization routine, to be called after the very first 2943176771Sraj * assembler level setup done in locore.S. 2944176771Sraj */ 2945176771Srajvoid 2946176771Srajtlb1_init(vm_offset_t ccsrbar) 2947176771Sraj{ 2948176771Sraj uint32_t mas0; 2949176771Sraj 2950187151Sraj /* TLB1[1] is used to map the kernel. Save that entry. */ 2951176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 2952176771Sraj mtspr(SPR_MAS0, mas0); 2953176771Sraj __asm __volatile("isync; tlbre"); 2954176771Sraj 2955176771Sraj tlb1[1].mas1 = mfspr(SPR_MAS1); 2956176771Sraj tlb1[1].mas2 = mfspr(SPR_MAS2); 2957176771Sraj tlb1[1].mas3 = mfspr(SPR_MAS3); 2958176771Sraj 2959187149Sraj /* Map in CCSRBAR in TLB1[0] */ 2960187149Sraj tlb1_idx = 0; 2961187149Sraj tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 2962187149Sraj /* 2963187149Sraj * Set the next available TLB1 entry index. Note TLB[1] is reserved 2964187149Sraj * for initial mapping of kernel text+data, which was set early in 2965187149Sraj * locore, we need to skip this [busy] entry. 2966187149Sraj */ 2967187149Sraj tlb1_idx = 2; 2968176771Sraj 2969176771Sraj /* Setup TLB miss defaults */ 2970176771Sraj set_mas4_defaults(); 2971176771Sraj} 2972176771Sraj 2973176771Sraj/* 2974176771Sraj * Setup MAS4 defaults. 2975176771Sraj * These values are loaded to MAS0-2 on a TLB miss. 2976176771Sraj */ 2977176771Srajstatic void 2978176771Srajset_mas4_defaults(void) 2979176771Sraj{ 2980187151Sraj uint32_t mas4; 2981176771Sraj 2982176771Sraj /* Defaults: TLB0, PID0, TSIZED=4K */ 2983176771Sraj mas4 = MAS4_TLBSELD0; 2984176771Sraj mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 2985192532Sraj#ifdef SMP 2986192532Sraj mas4 |= MAS4_MD; 2987192532Sraj#endif 2988176771Sraj mtspr(SPR_MAS4, mas4); 2989187151Sraj __asm __volatile("isync"); 2990176771Sraj} 2991176771Sraj 2992176771Sraj/* 2993176771Sraj * Print out contents of the MAS registers for each TLB1 entry 2994176771Sraj */ 2995176771Srajvoid 2996176771Srajtlb1_print_tlbentries(void) 2997176771Sraj{ 2998187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 2999176771Sraj int i; 3000176771Sraj 3001176771Sraj debugf("TLB1 entries:\n"); 3002187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) { 3003176771Sraj 3004176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3005176771Sraj mtspr(SPR_MAS0, mas0); 3006176771Sraj 3007187149Sraj __asm __volatile("isync; tlbre"); 3008176771Sraj 3009176771Sraj mas1 = mfspr(SPR_MAS1); 3010176771Sraj mas2 = mfspr(SPR_MAS2); 3011176771Sraj mas3 = mfspr(SPR_MAS3); 3012176771Sraj mas7 = mfspr(SPR_MAS7); 3013176771Sraj 3014176771Sraj tlb_print_entry(i, mas1, mas2, mas3, mas7); 3015176771Sraj } 3016176771Sraj} 3017176771Sraj 3018176771Sraj/* 3019176771Sraj * Print out contents of the in-ram tlb1 table. 3020176771Sraj */ 3021176771Srajvoid 3022176771Srajtlb1_print_entries(void) 3023176771Sraj{ 3024176771Sraj int i; 3025176771Sraj 3026176771Sraj debugf("tlb1[] table entries:\n"); 3027187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) 3028176771Sraj tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3029176771Sraj} 3030176771Sraj 3031176771Sraj/* 3032176771Sraj * Return 0 if the physical IO range is encompassed by one of the 3033176771Sraj * the TLB1 entries, otherwise return related error code. 3034176771Sraj */ 3035176771Srajstatic int 3036176771Srajtlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3037176771Sraj{ 3038187151Sraj uint32_t prot; 3039176771Sraj vm_paddr_t pa_start; 3040176771Sraj vm_paddr_t pa_end; 3041176771Sraj unsigned int entry_tsize; 3042176771Sraj vm_size_t entry_size; 3043176771Sraj 3044176771Sraj *va = (vm_offset_t)NULL; 3045176771Sraj 3046176771Sraj /* Skip invalid entries */ 3047176771Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 3048176771Sraj return (EINVAL); 3049176771Sraj 3050176771Sraj /* 3051176771Sraj * The entry must be cache-inhibited, guarded, and r/w 3052176771Sraj * so it can function as an i/o page 3053176771Sraj */ 3054176771Sraj prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3055176771Sraj if (prot != (MAS2_I | MAS2_G)) 3056176771Sraj return (EPERM); 3057176771Sraj 3058176771Sraj prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3059176771Sraj if (prot != (MAS3_SR | MAS3_SW)) 3060176771Sraj return (EPERM); 3061176771Sraj 3062176771Sraj /* The address should be within the entry range. */ 3063176771Sraj entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3064176771Sraj KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3065176771Sraj 3066176771Sraj entry_size = tsize2size(entry_tsize); 3067176771Sraj pa_start = tlb1[i].mas3 & MAS3_RPN; 3068176771Sraj pa_end = pa_start + entry_size - 1; 3069176771Sraj 3070176771Sraj if ((pa < pa_start) || ((pa + size) > pa_end)) 3071176771Sraj return (ERANGE); 3072176771Sraj 3073176771Sraj /* Return virtual address of this mapping. */ 3074187149Sraj *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3075176771Sraj return (0); 3076176771Sraj} 3077