pmap.c revision 182198
1/*- 2 * Copyright (C) 2007 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Some hw specific parts of this pmap were derived or influenced 29 * by NetBSD's ibm4xx pmap module. More generic code is shared with 30 * a few other pmap modules from the FreeBSD tree. 31 */ 32 33 /* 34 * VM layout notes: 35 * 36 * Kernel and user threads run within one common virtual address space 37 * defined by AS=0. 38 * 39 * Virtual address space layout: 40 * ----------------------------- 41 * 0x0000_0000 - 0xbfff_efff : user process 42 * 0xc000_0000 - 0xc1ff_ffff : kernel reserved 43 * 0xc000_0000 - kernelend : kernel code &data 44 * 0xc1ff_c000 - 0xc200_0000 : kstack0 45 * 0xc200_0000 - 0xffef_ffff : KVA 46 * 0xc200_0000 - 0xc200_3fff : reserved for page zero/copy 47 * 0xc200_4000 - ptbl buf end: reserved for ptbl bufs 48 * ptbl buf end- 0xffef_ffff : actual free KVA space 49 * 0xfff0_0000 - 0xffff_ffff : I/O devices region 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 182198 2008-08-26 17:07:37Z raj $"); 54 55#include <sys/types.h> 56#include <sys/param.h> 57#include <sys/malloc.h> 58#include <sys/proc.h> 59#include <sys/user.h> 60#include <sys/queue.h> 61#include <sys/systm.h> 62#include <sys/kernel.h> 63#include <sys/msgbuf.h> 64#include <sys/lock.h> 65#include <sys/mutex.h> 66#include <sys/vmmeter.h> 67 68#include <vm/vm.h> 69#include <vm/vm_page.h> 70#include <vm/vm_kern.h> 71#include <vm/vm_pageout.h> 72#include <vm/vm_extern.h> 73#include <vm/vm_object.h> 74#include <vm/vm_param.h> 75#include <vm/vm_map.h> 76#include <vm/vm_pager.h> 77#include <vm/uma.h> 78 79#include <machine/cpu.h> 80#include <machine/pcb.h> 81#include <machine/powerpc.h> 82 83#include <machine/tlb.h> 84#include <machine/spr.h> 85#include <machine/vmparam.h> 86#include <machine/md_var.h> 87#include <machine/mmuvar.h> 88#include <machine/pmap.h> 89#include <machine/pte.h> 90 91#include "mmu_if.h" 92 93#define DEBUG 94#undef DEBUG 95 96#ifdef DEBUG 97#define debugf(fmt, args...) printf(fmt, ##args) 98#else 99#define debugf(fmt, args...) 100#endif 101 102#define TODO panic("%s: not implemented", __func__); 103#define memmove(d, s, l) bcopy(s, d, l) 104 105#include "opt_sched.h" 106#ifndef SCHED_4BSD 107#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 108#endif 109extern struct mtx sched_lock; 110 111/* Kernel physical load address. */ 112extern uint32_t kernload; 113 114struct mem_region availmem_regions[MEM_REGIONS]; 115int availmem_regions_sz; 116 117/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 118static vm_offset_t zero_page_va; 119static struct mtx zero_page_mutex; 120 121/* 122 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 123 * by idle thred only, no lock required. 124 */ 125static vm_offset_t zero_page_idle_va; 126 127/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 128static vm_offset_t copy_page_src_va; 129static vm_offset_t copy_page_dst_va; 130static struct mtx copy_page_mutex; 131 132/**************************************************************************/ 133/* PMAP */ 134/**************************************************************************/ 135 136static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 137 vm_prot_t, boolean_t); 138 139unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 140unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 141 142static int pagedaemon_waken; 143 144/* 145 * If user pmap is processed with mmu_booke_remove and the resident count 146 * drops to 0, there are no more pages to remove, so we need not continue. 147 */ 148#define PMAP_REMOVE_DONE(pmap) \ 149 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 150 151extern void load_pid0(tlbtid_t); 152 153/**************************************************************************/ 154/* TLB and TID handling */ 155/**************************************************************************/ 156 157/* Translation ID busy table */ 158static volatile pmap_t tidbusy[TID_MAX + 1]; 159 160/* 161 * Actual maximum number of TLB0 entries. 162 * This number differs between e500 core revisions. 163 */ 164u_int32_t tlb0_size; 165u_int32_t tlb0_nways; 166u_int32_t tlb0_nentries_per_way; 167 168#define TLB0_SIZE (tlb0_size) 169#define TLB0_NWAYS (tlb0_nways) 170#define TLB0_ENTRIES_PER_WAY (tlb0_nentries_per_way) 171 172/* Pointer to kernel tlb0 table, allocated in mmu_booke_bootstrap() */ 173tlb_entry_t *tlb0; 174 175/* 176 * Spinlock to assure proper locking between threads and 177 * between tlb miss handler and kernel. 178 */ 179static struct mtx tlb0_mutex; 180 181#define TLB1_SIZE 16 182 183/* In-ram copy of the TLB1 */ 184static tlb_entry_t tlb1[TLB1_SIZE]; 185 186/* Next free entry in the TLB1 */ 187static unsigned int tlb1_idx; 188 189static tlbtid_t tid_alloc(struct pmap *); 190static void tid_flush(tlbtid_t); 191 192extern void tlb1_inval_va(vm_offset_t); 193extern void tlb0_inval_va(vm_offset_t); 194 195static void tlb_print_entry(int, u_int32_t, u_int32_t, u_int32_t, u_int32_t); 196 197static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, u_int32_t); 198static void __tlb1_set_entry(unsigned int, vm_offset_t, vm_offset_t, 199 vm_size_t, u_int32_t, unsigned int, unsigned int); 200static void tlb1_write_entry(unsigned int); 201static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 202static vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 203 204static vm_size_t tsize2size(unsigned int); 205static unsigned int size2tsize(vm_size_t); 206static unsigned int ilog2(unsigned int); 207 208static void set_mas4_defaults(void); 209 210static void tlb0_inval_entry(vm_offset_t, unsigned int); 211static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 212static void tlb0_write_entry(unsigned int, unsigned int); 213static void tlb0_flush_entry(pmap_t, vm_offset_t); 214static void tlb0_init(void); 215 216/**************************************************************************/ 217/* Page table management */ 218/**************************************************************************/ 219 220/* Data for the pv entry allocation mechanism */ 221static uma_zone_t pvzone; 222static struct vm_object pvzone_obj; 223static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224 225#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226 227#ifndef PMAP_SHPGPERPROC 228#define PMAP_SHPGPERPROC 200 229#endif 230 231static void ptbl_init(void); 232static struct ptbl_buf *ptbl_buf_alloc(void); 233static void ptbl_buf_free(struct ptbl_buf *); 234static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235 236static void ptbl_alloc(mmu_t, pmap_t, unsigned int); 237static void ptbl_free(mmu_t, pmap_t, unsigned int); 238static void ptbl_hold(mmu_t, pmap_t, unsigned int); 239static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240 241static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, u_int32_t); 244static int pte_remove(mmu_t, pmap_t, vm_offset_t, u_int8_t); 245 246pv_entry_t pv_alloc(void); 247static void pv_free(pv_entry_t); 248static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 249static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 250 251/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 252#define PTBL_BUFS (128 * 16) 253 254struct ptbl_buf { 255 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 256 vm_offset_t kva; /* va of mapping */ 257}; 258 259/* ptbl free list and a lock used for access synchronization. */ 260static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 261static struct mtx ptbl_buf_freelist_lock; 262 263/* Base address of kva space allocated fot ptbl bufs. */ 264static vm_offset_t ptbl_buf_pool_vabase; 265 266/* Pointer to ptbl_buf structures. */ 267static struct ptbl_buf *ptbl_bufs; 268 269/* 270 * Kernel MMU interface 271 */ 272static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 273static void mmu_booke_clear_modify(mmu_t, vm_page_t); 274static void mmu_booke_clear_reference(mmu_t, vm_page_t); 275static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t, vm_size_t, 276 vm_offset_t); 277static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 278static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 279 vm_prot_t, boolean_t); 280static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 281 vm_page_t, vm_prot_t); 282static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 285static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 286 vm_prot_t); 287static void mmu_booke_init(mmu_t); 288static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 289static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 291static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 292 int); 293static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t); 294static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 295 vm_object_t, vm_pindex_t, vm_size_t); 296static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 297static void mmu_booke_page_init(mmu_t, vm_page_t); 298static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 299static void mmu_booke_pinit(mmu_t, pmap_t); 300static void mmu_booke_pinit0(mmu_t, pmap_t); 301static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 302 vm_prot_t); 303static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 304static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 305static void mmu_booke_release(mmu_t, pmap_t); 306static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307static void mmu_booke_remove_all(mmu_t, vm_page_t); 308static void mmu_booke_remove_write(mmu_t, vm_page_t); 309static void mmu_booke_zero_page(mmu_t, vm_page_t); 310static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 311static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 312static void mmu_booke_activate(mmu_t, struct thread *); 313static void mmu_booke_deactivate(mmu_t, struct thread *); 314static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 315static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 316static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 317static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 318static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 319static void mmu_booke_kremove(mmu_t, vm_offset_t); 320static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 321static boolean_t mmu_booke_page_executable(mmu_t, vm_page_t); 322 323static mmu_method_t mmu_booke_methods[] = { 324 /* pmap dispatcher interface */ 325 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 326 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 327 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 328 MMUMETHOD(mmu_copy, mmu_booke_copy), 329 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 330 MMUMETHOD(mmu_enter, mmu_booke_enter), 331 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 332 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 333 MMUMETHOD(mmu_extract, mmu_booke_extract), 334 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 335 MMUMETHOD(mmu_init, mmu_booke_init), 336 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 337 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 338 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 339 MMUMETHOD(mmu_map, mmu_booke_map), 340 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 341 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 342 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 343 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 344 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 345 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 346 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 347 MMUMETHOD(mmu_protect, mmu_booke_protect), 348 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 349 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 350 MMUMETHOD(mmu_release, mmu_booke_release), 351 MMUMETHOD(mmu_remove, mmu_booke_remove), 352 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 353 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 354 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 355 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 356 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 357 MMUMETHOD(mmu_activate, mmu_booke_activate), 358 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 359 360 /* Internal interfaces */ 361 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 362 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 363 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 364 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 365 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 366/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 367 MMUMETHOD(mmu_page_executable, mmu_booke_page_executable), 368 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 369 370 { 0, 0 } 371}; 372 373static mmu_def_t booke_mmu = { 374 MMU_TYPE_BOOKE, 375 mmu_booke_methods, 376 0 377}; 378MMU_DEF(booke_mmu); 379 380/* Return number of entries in TLB0. */ 381static __inline void 382tlb0_get_tlbconf(void) 383{ 384 uint32_t tlb0_cfg; 385 386 tlb0_cfg = mfspr(SPR_TLB0CFG); 387 tlb0_size = tlb0_cfg & TLBCFG_NENTRY_MASK; 388 tlb0_nways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 389 tlb0_nentries_per_way = tlb0_size/tlb0_nways; 390} 391 392/* Initialize pool of kva ptbl buffers. */ 393static void 394ptbl_init(void) 395{ 396 int i; 397 398 //debugf("ptbl_init: s (ptbl_bufs = 0x%08x size 0x%08x)\n", 399 // (u_int32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 400 //debugf("ptbl_init: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)\n", 401 // ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 402 403 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 404 TAILQ_INIT(&ptbl_buf_freelist); 405 406 for (i = 0; i < PTBL_BUFS; i++) { 407 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 408 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 409 } 410 411 //debugf("ptbl_init: e\n"); 412} 413 414/* Get an sf_buf from the freelist. */ 415static struct ptbl_buf * 416ptbl_buf_alloc(void) 417{ 418 struct ptbl_buf *buf; 419 420 //debugf("ptbl_buf_alloc: s\n"); 421 422 mtx_lock(&ptbl_buf_freelist_lock); 423 buf = TAILQ_FIRST(&ptbl_buf_freelist); 424 if (buf != NULL) 425 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 426 mtx_unlock(&ptbl_buf_freelist_lock); 427 428 //debugf("ptbl_buf_alloc: e (buf = 0x%08x)\n", (u_int32_t)buf); 429 return (buf); 430} 431 432/* Return ptbl buff to free pool. */ 433static void 434ptbl_buf_free(struct ptbl_buf *buf) 435{ 436 437 //debugf("ptbl_buf_free: s (buf = 0x%08x)\n", (u_int32_t)buf); 438 439 mtx_lock(&ptbl_buf_freelist_lock); 440 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 441 mtx_unlock(&ptbl_buf_freelist_lock); 442 443 //debugf("ptbl_buf_free: e\n"); 444} 445 446/* 447 * Search the list of allocated ptbl bufs and find 448 * on list of allocated ptbls 449 */ 450static void 451ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 452{ 453 struct ptbl_buf *pbuf; 454 455 //debugf("ptbl_free_pmap_ptbl: s (pmap = 0x%08x ptbl = 0x%08x)\n", 456 // (u_int32_t)pmap, (u_int32_t)ptbl); 457 458 TAILQ_FOREACH(pbuf, &pmap->ptbl_list, link) { 459 if (pbuf->kva == (vm_offset_t)ptbl) { 460 /* Remove from pmap ptbl buf list. */ 461 TAILQ_REMOVE(&pmap->ptbl_list, pbuf, link); 462 463 /* Free correspondig ptbl buf. */ 464 ptbl_buf_free(pbuf); 465 466 break; 467 } 468 } 469 470 //debugf("ptbl_free_pmap_ptbl: e\n"); 471} 472 473/* Allocate page table. */ 474static void 475ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 476{ 477 vm_page_t mtbl[PTBL_PAGES]; 478 vm_page_t m; 479 struct ptbl_buf *pbuf; 480 unsigned int pidx; 481 int i; 482 483 //int su = (pmap == kernel_pmap); 484 //debugf("ptbl_alloc: s (pmap = 0x%08x su = %d pdir_idx = %d)\n", (u_int32_t)pmap, su, pdir_idx); 485 486 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 487 ("ptbl_alloc: invalid pdir_idx")); 488 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 489 ("pte_alloc: valid ptbl entry exists!")); 490 491 pbuf = ptbl_buf_alloc(); 492 if (pbuf == NULL) 493 panic("pte_alloc: couldn't alloc kernel virtual memory"); 494 pmap->pm_pdir[pdir_idx] = (pte_t *)pbuf->kva; 495 //debugf("ptbl_alloc: kva = 0x%08x\n", (u_int32_t)pmap->pm_pdir[pdir_idx]); 496 497 /* Allocate ptbl pages, this will sleep! */ 498 for (i = 0; i < PTBL_PAGES; i++) { 499 pidx = (PTBL_PAGES * pdir_idx) + i; 500 while ((m = vm_page_alloc(NULL, pidx, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 501 PMAP_UNLOCK(pmap); 502 vm_page_unlock_queues(); 503 VM_WAIT; 504 vm_page_lock_queues(); 505 PMAP_LOCK(pmap); 506 } 507 mtbl[i] = m; 508 } 509 510 /* Map in allocated pages into kernel_pmap. */ 511 mmu_booke_qenter(mmu, (vm_offset_t)pmap->pm_pdir[pdir_idx], mtbl, PTBL_PAGES); 512 513 /* Zero whole ptbl. */ 514 bzero((caddr_t)pmap->pm_pdir[pdir_idx], PTBL_PAGES * PAGE_SIZE); 515 516 /* Add pbuf to the pmap ptbl bufs list. */ 517 TAILQ_INSERT_TAIL(&pmap->ptbl_list, pbuf, link); 518 519 //debugf("ptbl_alloc: e\n"); 520} 521 522/* Free ptbl pages and invalidate pdir entry. */ 523static void 524ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 525{ 526 pte_t *ptbl; 527 vm_paddr_t pa; 528 vm_offset_t va; 529 vm_page_t m; 530 int i; 531 532 //int su = (pmap == kernel_pmap); 533 //debugf("ptbl_free: s (pmap = 0x%08x su = %d pdir_idx = %d)\n", (u_int32_t)pmap, su, pdir_idx); 534 535 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 536 ("ptbl_free: invalid pdir_idx")); 537 538 ptbl = pmap->pm_pdir[pdir_idx]; 539 540 //debugf("ptbl_free: ptbl = 0x%08x\n", (u_int32_t)ptbl); 541 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 542 543 for (i = 0; i < PTBL_PAGES; i++) { 544 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 545 pa = pte_vatopa(mmu, kernel_pmap, va); 546 m = PHYS_TO_VM_PAGE(pa); 547 vm_page_free_zero(m); 548 atomic_subtract_int(&cnt.v_wire_count, 1); 549 mmu_booke_kremove(mmu, va); 550 } 551 552 ptbl_free_pmap_ptbl(pmap, ptbl); 553 pmap->pm_pdir[pdir_idx] = NULL; 554 555 //debugf("ptbl_free: e\n"); 556} 557 558/* 559 * Decrement ptbl pages hold count and attempt to free ptbl pages. 560 * Called when removing pte entry from ptbl. 561 * 562 * Return 1 if ptbl pages were freed. 563 */ 564static int 565ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 566{ 567 pte_t *ptbl; 568 vm_paddr_t pa; 569 vm_page_t m; 570 int i; 571 572 //int su = (pmap == kernel_pmap); 573 //debugf("ptbl_unhold: s (pmap = %08x su = %d pdir_idx = %d)\n", 574 // (u_int32_t)pmap, su, pdir_idx); 575 576 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 577 ("ptbl_unhold: invalid pdir_idx")); 578 KASSERT((pmap != kernel_pmap), 579 ("ptbl_unhold: unholding kernel ptbl!")); 580 581 ptbl = pmap->pm_pdir[pdir_idx]; 582 583 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 584 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 585 ("ptbl_unhold: non kva ptbl")); 586 587 /* decrement hold count */ 588 for (i = 0; i < PTBL_PAGES; i++) { 589 pa = pte_vatopa(mmu, kernel_pmap, (vm_offset_t)ptbl + (i * PAGE_SIZE)); 590 m = PHYS_TO_VM_PAGE(pa); 591 m->wire_count--; 592 } 593 594 /* 595 * Free ptbl pages if there are no pte etries in this ptbl. 596 * wire_count has the same value for all ptbl pages, so check 597 * the last page. 598 */ 599 if (m->wire_count == 0) { 600 ptbl_free(mmu, pmap, pdir_idx); 601 602 //debugf("ptbl_unhold: e (freed ptbl)\n"); 603 return (1); 604 } 605 606 //debugf("ptbl_unhold: e\n"); 607 return (0); 608} 609 610/* 611 * Increment hold count for ptbl pages. This routine is used when 612 * new pte entry is being inserted into ptbl. 613 */ 614static void 615ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 616{ 617 vm_paddr_t pa; 618 pte_t *ptbl; 619 vm_page_t m; 620 int i; 621 622 //debugf("ptbl_hold: s (pmap = 0x%08x pdir_idx = %d)\n", (u_int32_t)pmap, pdir_idx); 623 624 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 625 ("ptbl_hold: invalid pdir_idx")); 626 KASSERT((pmap != kernel_pmap), 627 ("ptbl_hold: holding kernel ptbl!")); 628 629 ptbl = pmap->pm_pdir[pdir_idx]; 630 631 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 632 633 for (i = 0; i < PTBL_PAGES; i++) { 634 pa = pte_vatopa(mmu, kernel_pmap, (vm_offset_t)ptbl + (i * PAGE_SIZE)); 635 m = PHYS_TO_VM_PAGE(pa); 636 m->wire_count++; 637 } 638 639 //debugf("ptbl_hold: e\n"); 640} 641 642/* Allocate pv_entry structure. */ 643pv_entry_t 644pv_alloc(void) 645{ 646 pv_entry_t pv; 647 648 debugf("pv_alloc: s\n"); 649 650 pv_entry_count++; 651 if ((pv_entry_count > pv_entry_high_water) && (pagedaemon_waken == 0)) { 652 pagedaemon_waken = 1; 653 wakeup (&vm_pages_needed); 654 } 655 pv = uma_zalloc(pvzone, M_NOWAIT); 656 657 debugf("pv_alloc: e\n"); 658 return (pv); 659} 660 661/* Free pv_entry structure. */ 662static __inline void 663pv_free(pv_entry_t pve) 664{ 665 //debugf("pv_free: s\n"); 666 667 pv_entry_count--; 668 uma_zfree(pvzone, pve); 669 670 //debugf("pv_free: e\n"); 671} 672 673 674/* Allocate and initialize pv_entry structure. */ 675static void 676pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 677{ 678 pv_entry_t pve; 679 680 //int su = (pmap == kernel_pmap); 681 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 682 // (u_int32_t)pmap, va, (u_int32_t)m); 683 684 pve = pv_alloc(); 685 if (pve == NULL) 686 panic("pv_insert: no pv entries!"); 687 688 pve->pv_pmap = pmap; 689 pve->pv_va = va; 690 691 /* add to pv_list */ 692 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 693 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 694 695 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 696 697 //debugf("pv_insert: e\n"); 698} 699 700/* Destroy pv entry. */ 701static void 702pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 703{ 704 pv_entry_t pve; 705 706 //int su = (pmap == kernel_pmap); 707 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 708 709 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 710 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 711 712 /* find pv entry */ 713 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 714 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 715 /* remove from pv_list */ 716 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 717 if (TAILQ_EMPTY(&m->md.pv_list)) 718 vm_page_flag_clear(m, PG_WRITEABLE); 719 720 /* free pv entry struct */ 721 pv_free(pve); 722 723 break; 724 } 725 } 726 727 //debugf("pv_remove: e\n"); 728} 729 730/* 731 * Clean pte entry, try to free page table page if requested. 732 * 733 * Return 1 if ptbl pages were freed, otherwise return 0. 734 */ 735static int 736pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags) 737{ 738 unsigned int pdir_idx = PDIR_IDX(va); 739 unsigned int ptbl_idx = PTBL_IDX(va); 740 vm_page_t m; 741 pte_t *ptbl; 742 pte_t *pte; 743 744 //int su = (pmap == kernel_pmap); 745 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 746 // su, (u_int32_t)pmap, va, flags); 747 748 ptbl = pmap->pm_pdir[pdir_idx]; 749 KASSERT(ptbl, ("pte_remove: null ptbl")); 750 751 pte = &ptbl[ptbl_idx]; 752 753 if (pte == NULL || !PTE_ISVALID(pte)) 754 return (0); 755 756 /* Get vm_page_t for mapped pte. */ 757 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 758 759 if (PTE_ISWIRED(pte)) 760 pmap->pm_stats.wired_count--; 761 762 if (!PTE_ISFAKE(pte)) { 763 /* Handle managed entry. */ 764 if (PTE_ISMANAGED(pte)) { 765 766 /* Handle modified pages. */ 767 if (PTE_ISMODIFIED(pte)) 768 vm_page_dirty(m); 769 770 /* Referenced pages. */ 771 if (PTE_ISREFERENCED(pte)) 772 vm_page_flag_set(m, PG_REFERENCED); 773 774 /* Remove pv_entry from pv_list. */ 775 pv_remove(pmap, va, m); 776 } 777 } 778 779 pte->flags = 0; 780 pte->rpn = 0; 781 pmap->pm_stats.resident_count--; 782 783 if (flags & PTBL_UNHOLD) { 784 //debugf("pte_remove: e (unhold)\n"); 785 return (ptbl_unhold(mmu, pmap, pdir_idx)); 786 } 787 788 //debugf("pte_remove: e\n"); 789 return (0); 790} 791 792/* 793 * Insert PTE for a given page and virtual address. 794 */ 795void 796pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, u_int32_t flags) 797{ 798 unsigned int pdir_idx = PDIR_IDX(va); 799 unsigned int ptbl_idx = PTBL_IDX(va); 800 pte_t *ptbl; 801 pte_t *pte; 802 803 //int su = (pmap == kernel_pmap); 804 //debugf("pte_enter: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 805 806 /* Get the page table pointer. */ 807 ptbl = pmap->pm_pdir[pdir_idx]; 808 809 if (ptbl) { 810 /* 811 * Check if there is valid mapping for requested 812 * va, if there is, remove it. 813 */ 814 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 815 if (PTE_ISVALID(pte)) { 816 pte_remove(mmu, pmap, va, PTBL_HOLD); 817 } else { 818 /* 819 * pte is not used, increment hold count 820 * for ptbl pages. 821 */ 822 if (pmap != kernel_pmap) 823 ptbl_hold(mmu, pmap, pdir_idx); 824 } 825 } else { 826 /* Allocate page table pages. */ 827 ptbl_alloc(mmu, pmap, pdir_idx); 828 } 829 830 /* Flush entry from TLB. */ 831 tlb0_flush_entry(pmap, va); 832 833 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 834 835 /* 836 * Insert pv_entry into pv_list for mapped page 837 * if part of managed memory. 838 */ 839 if ((m->flags & PG_FICTITIOUS) == 0) { 840 if ((m->flags & PG_UNMANAGED) == 0) { 841 pte->flags |= PTE_MANAGED; 842 843 /* Create and insert pv entry. */ 844 pv_insert(pmap, va, m); 845 } 846 } else { 847 pte->flags |= PTE_FAKE; 848 } 849 850 pmap->pm_stats.resident_count++; 851 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 852 pte->flags |= (PTE_VALID | flags); 853 854 //debugf("pte_enter: e\n"); 855} 856 857/* Return the pa for the given pmap/va. */ 858static vm_paddr_t 859pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 860{ 861 vm_paddr_t pa = 0; 862 pte_t *pte; 863 864 pte = pte_find(mmu, pmap, va); 865 if ((pte != NULL) && PTE_ISVALID(pte)) 866 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 867 return (pa); 868} 869 870/* Get a pointer to a PTE in a page table. */ 871static pte_t * 872pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 873{ 874 unsigned int pdir_idx = PDIR_IDX(va); 875 unsigned int ptbl_idx = PTBL_IDX(va); 876 877 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 878 879 if (pmap->pm_pdir[pdir_idx]) 880 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 881 882 return (NULL); 883} 884 885/**************************************************************************/ 886/* PMAP related */ 887/**************************************************************************/ 888 889/* 890 * This is called during e500_init, before the system is really initialized. 891 */ 892static void 893mmu_booke_bootstrap(mmu_t mmu, vm_offset_t kernelstart, vm_offset_t kernelend) 894{ 895 vm_offset_t phys_kernelend; 896 struct mem_region *mp, *mp1; 897 int cnt, i, j; 898 u_int s, e, sz; 899 u_int phys_avail_count; 900 vm_size_t physsz, hwphyssz, kstack0_sz; 901 vm_offset_t kernel_pdir, kstack0; 902 vm_paddr_t kstack0_phys; 903 904 debugf("mmu_booke_bootstrap: entered\n"); 905 906 /* Align kernel start and end address (kernel image). */ 907 kernelstart = trunc_page(kernelstart); 908 kernelend = round_page(kernelend); 909 910 /* Allocate space for the message buffer. */ 911 msgbufp = (struct msgbuf *)kernelend; 912 kernelend += MSGBUF_SIZE; 913 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (u_int32_t)msgbufp, 914 kernelend); 915 916 kernelend = round_page(kernelend); 917 918 /* Allocate space for tlb0 table. */ 919 tlb0_get_tlbconf(); /* Read TLB0 size and associativity. */ 920 tlb0 = (tlb_entry_t *)kernelend; 921 kernelend += sizeof(tlb_entry_t) * tlb0_size; 922 memset((void *)tlb0, 0, sizeof(tlb_entry_t) * tlb0_size); 923 debugf(" tlb0 at 0x%08x end = 0x%08x\n", (u_int32_t)tlb0, kernelend); 924 925 kernelend = round_page(kernelend); 926 927 /* Allocate space for ptbl_bufs. */ 928 ptbl_bufs = (struct ptbl_buf *)kernelend; 929 kernelend += sizeof(struct ptbl_buf) * PTBL_BUFS; 930 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 931 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (u_int32_t)ptbl_bufs, 932 kernelend); 933 934 kernelend = round_page(kernelend); 935 936 /* Allocate PTE tables for kernel KVA. */ 937 kernel_pdir = kernelend; 938 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 939 PDIR_SIZE - 1) / PDIR_SIZE; 940 kernelend += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 941 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 942 debugf(" kernel ptbls: %d\n", kernel_ptbls); 943 debugf(" kernel pdir at 0x%08x\n", kernel_pdir); 944 945 if (kernelend - kernelstart > 0x1000000) { 946 kernelend = (kernelend + 0x3fffff) & ~0x3fffff; 947 tlb1_mapin_region(kernelstart + 0x1000000, 948 kernload + 0x1000000, kernelend - kernelstart - 0x1000000); 949 } else 950 kernelend = (kernelend + 0xffffff) & ~0xffffff; 951 952 /*******************************************************/ 953 /* Set the start and end of kva. */ 954 /*******************************************************/ 955 virtual_avail = kernelend; 956 virtual_end = VM_MAX_KERNEL_ADDRESS; 957 958 /* Allocate KVA space for page zero/copy operations. */ 959 zero_page_va = virtual_avail; 960 virtual_avail += PAGE_SIZE; 961 zero_page_idle_va = virtual_avail; 962 virtual_avail += PAGE_SIZE; 963 copy_page_src_va = virtual_avail; 964 virtual_avail += PAGE_SIZE; 965 copy_page_dst_va = virtual_avail; 966 virtual_avail += PAGE_SIZE; 967 968 /* Initialize page zero/copy mutexes. */ 969 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 970 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 971 972 /* Initialize tlb0 table mutex. */ 973 mtx_init(&tlb0_mutex, "tlb0", NULL, MTX_SPIN | MTX_RECURSE); 974 975 /* Allocate KVA space for ptbl bufs. */ 976 ptbl_buf_pool_vabase = virtual_avail; 977 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 978 979 debugf("ptbl_buf_pool_vabase = 0x%08x\n", ptbl_buf_pool_vabase); 980 debugf("virtual_avail = %08x\n", virtual_avail); 981 debugf("virtual_end = %08x\n", virtual_end); 982 983 /* Calculate corresponding physical addresses for the kernel region. */ 984 phys_kernelend = kernload + (kernelend - kernelstart); 985 986 debugf("kernel image and allocated data:\n"); 987 debugf(" kernload = 0x%08x\n", kernload); 988 debugf(" kernelstart = 0x%08x\n", kernelstart); 989 debugf(" kernelend = 0x%08x\n", kernelend); 990 debugf(" kernel size = 0x%08x\n", kernelend - kernelstart); 991 992 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 993 panic("mmu_booke_bootstrap: phys_avail too small"); 994 995 /* 996 * Removed kernel physical address range from avail 997 * regions list. Page align all regions. 998 * Non-page aligned memory isn't very interesting to us. 999 * Also, sort the entries for ascending addresses. 1000 */ 1001 sz = 0; 1002 cnt = availmem_regions_sz; 1003 debugf("processing avail regions:\n"); 1004 for (mp = availmem_regions; mp->mr_size; mp++) { 1005 s = mp->mr_start; 1006 e = mp->mr_start + mp->mr_size; 1007 debugf(" %08x-%08x -> ", s, e); 1008 /* Check whether this region holds all of the kernel. */ 1009 if (s < kernload && e > phys_kernelend) { 1010 availmem_regions[cnt].mr_start = phys_kernelend; 1011 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1012 e = kernload; 1013 } 1014 /* Look whether this regions starts within the kernel. */ 1015 if (s >= kernload && s < phys_kernelend) { 1016 if (e <= phys_kernelend) 1017 goto empty; 1018 s = phys_kernelend; 1019 } 1020 /* Now look whether this region ends within the kernel. */ 1021 if (e > kernload && e <= phys_kernelend) { 1022 if (s >= kernload) 1023 goto empty; 1024 e = kernload; 1025 } 1026 /* Now page align the start and size of the region. */ 1027 s = round_page(s); 1028 e = trunc_page(e); 1029 if (e < s) 1030 e = s; 1031 sz = e - s; 1032 debugf("%08x-%08x = %x\n", s, e, sz); 1033 1034 /* Check whether some memory is left here. */ 1035 if (sz == 0) { 1036 empty: 1037 memmove(mp, mp + 1, 1038 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1039 cnt--; 1040 mp--; 1041 continue; 1042 } 1043 1044 /* Do an insertion sort. */ 1045 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1046 if (s < mp1->mr_start) 1047 break; 1048 if (mp1 < mp) { 1049 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1050 mp1->mr_start = s; 1051 mp1->mr_size = sz; 1052 } else { 1053 mp->mr_start = s; 1054 mp->mr_size = sz; 1055 } 1056 } 1057 availmem_regions_sz = cnt; 1058 1059 /*******************************************************/ 1060 /* Steal physical memory for kernel stack from the end */ 1061 /* of the first avail region */ 1062 /*******************************************************/ 1063 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1064 kstack0_phys = availmem_regions[0].mr_start + 1065 availmem_regions[0].mr_size; 1066 kstack0_phys -= kstack0_sz; 1067 availmem_regions[0].mr_size -= kstack0_sz; 1068 1069 /*******************************************************/ 1070 /* Fill in phys_avail table, based on availmem_regions */ 1071 /*******************************************************/ 1072 phys_avail_count = 0; 1073 physsz = 0; 1074 hwphyssz = 0; 1075 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1076 1077 debugf("fill in phys_avail:\n"); 1078 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1079 1080 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1081 availmem_regions[i].mr_start, 1082 availmem_regions[i].mr_start + availmem_regions[i].mr_size, 1083 availmem_regions[i].mr_size); 1084 1085 if (hwphyssz != 0 && (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1086 debugf(" hw.physmem adjust\n"); 1087 if (physsz < hwphyssz) { 1088 phys_avail[j] = availmem_regions[i].mr_start; 1089 phys_avail[j + 1] = availmem_regions[i].mr_start + 1090 hwphyssz - physsz; 1091 physsz = hwphyssz; 1092 phys_avail_count++; 1093 } 1094 break; 1095 } 1096 1097 phys_avail[j] = availmem_regions[i].mr_start; 1098 phys_avail[j + 1] = availmem_regions[i].mr_start + 1099 availmem_regions[i].mr_size; 1100 phys_avail_count++; 1101 physsz += availmem_regions[i].mr_size; 1102 } 1103 physmem = btoc(physsz); 1104 1105 /* Calculate the last available physical address. */ 1106 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1107 ; 1108 Maxmem = powerpc_btop(phys_avail[i + 1]); 1109 1110 debugf("Maxmem = 0x%08lx\n", Maxmem); 1111 debugf("phys_avail_count = %d\n", phys_avail_count); 1112 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, physmem); 1113 1114 /*******************************************************/ 1115 /* Initialize (statically allocated) kernel pmap. */ 1116 /*******************************************************/ 1117 PMAP_LOCK_INIT(kernel_pmap); 1118 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1119 1120 debugf("kernel_pmap = 0x%08x\n", (u_int32_t)kernel_pmap); 1121 debugf("kptbl_min = %d, kernel_kptbls = %d\n", kptbl_min, kernel_ptbls); 1122 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1123 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1124 1125 /* Initialize kernel pdir */ 1126 for (i = 0; i < kernel_ptbls; i++) 1127 kernel_pmap->pm_pdir[kptbl_min + i] = 1128 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1129 1130 kernel_pmap->pm_tid = KERNEL_TID; 1131 kernel_pmap->pm_active = ~0; 1132 1133 /* Initialize tidbusy with kenel_pmap entry. */ 1134 tidbusy[0] = kernel_pmap; 1135 1136 /*******************************************************/ 1137 /* Final setup */ 1138 /*******************************************************/ 1139 /* Enter kstack0 into kernel map, provide guard page */ 1140 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1141 thread0.td_kstack = kstack0; 1142 thread0.td_kstack_pages = KSTACK_PAGES; 1143 1144 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1145 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1146 kstack0_phys, kstack0_phys + kstack0_sz); 1147 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1148 1149 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1150 for (i = 0; i < KSTACK_PAGES; i++) { 1151 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1152 kstack0 += PAGE_SIZE; 1153 kstack0_phys += PAGE_SIZE; 1154 } 1155 1156 /* Initialize TLB0 handling. */ 1157 tlb0_init(); 1158 1159 debugf("mmu_booke_bootstrap: exit\n"); 1160} 1161 1162/* 1163 * Get the physical page address for the given pmap/virtual address. 1164 */ 1165static vm_paddr_t 1166mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1167{ 1168 vm_paddr_t pa; 1169 1170 PMAP_LOCK(pmap); 1171 pa = pte_vatopa(mmu, pmap, va); 1172 PMAP_UNLOCK(pmap); 1173 1174 return (pa); 1175} 1176 1177/* 1178 * Extract the physical page address associated with the given 1179 * kernel virtual address. 1180 */ 1181static vm_paddr_t 1182mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1183{ 1184 1185 return (pte_vatopa(mmu, kernel_pmap, va)); 1186} 1187 1188/* 1189 * Initialize the pmap module. 1190 * Called by vm_init, to initialize any structures that the pmap 1191 * system needs to map virtual memory. 1192 */ 1193static void 1194mmu_booke_init(mmu_t mmu) 1195{ 1196 int shpgperproc = PMAP_SHPGPERPROC; 1197 1198 //debugf("mmu_booke_init: s\n"); 1199 1200 /* 1201 * Initialize the address space (zone) for the pv entries. Set a 1202 * high water mark so that the system can recover from excessive 1203 * numbers of pv entries. 1204 */ 1205 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1206 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1207 1208 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1209 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1210 1211 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1212 pv_entry_high_water = 9 * (pv_entry_max / 10); 1213 1214 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1215 1216 /* Pre-fill pvzone with initial number of pv entries. */ 1217 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1218 1219 /* Initialize ptbl allocation. */ 1220 ptbl_init(); 1221 1222 //debugf("mmu_booke_init: e\n"); 1223} 1224 1225/* 1226 * Map a list of wired pages into kernel virtual address space. This is 1227 * intended for temporary mappings which do not need page modification or 1228 * references recorded. Existing mappings in the region are overwritten. 1229 */ 1230static void 1231mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1232{ 1233 vm_offset_t va; 1234 1235 //debugf("mmu_booke_qenter: s (sva = 0x%08x count = %d)\n", sva, count); 1236 1237 va = sva; 1238 while (count-- > 0) { 1239 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1240 va += PAGE_SIZE; 1241 m++; 1242 } 1243 1244 //debugf("mmu_booke_qenter: e\n"); 1245} 1246 1247/* 1248 * Remove page mappings from kernel virtual address space. Intended for 1249 * temporary mappings entered by mmu_booke_qenter. 1250 */ 1251static void 1252mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1253{ 1254 vm_offset_t va; 1255 1256 //debugf("mmu_booke_qremove: s (sva = 0x%08x count = %d)\n", sva, count); 1257 1258 va = sva; 1259 while (count-- > 0) { 1260 mmu_booke_kremove(mmu, va); 1261 va += PAGE_SIZE; 1262 } 1263 1264 //debugf("mmu_booke_qremove: e\n"); 1265} 1266 1267/* 1268 * Map a wired page into kernel virtual address space. 1269 */ 1270static void 1271mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1272{ 1273 unsigned int pdir_idx = PDIR_IDX(va); 1274 unsigned int ptbl_idx = PTBL_IDX(va); 1275 u_int32_t flags; 1276 pte_t *pte; 1277 1278 //debugf("mmu_booke_kenter: s (pdir_idx = %d ptbl_idx = %d va=0x%08x pa=0x%08x)\n", 1279 // pdir_idx, ptbl_idx, va, pa); 1280 1281 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)), 1282 ("mmu_booke_kenter: invalid va")); 1283 1284#if 0 1285 /* assume IO mapping, set I, G bits */ 1286 flags = (PTE_G | PTE_I | PTE_FAKE); 1287 1288 /* if mapping is within system memory, do not set I, G bits */ 1289 for (i = 0; i < totalmem_regions_sz; i++) { 1290 if ((pa >= totalmem_regions[i].mr_start) && 1291 (pa < (totalmem_regions[i].mr_start + 1292 totalmem_regions[i].mr_size))) { 1293 flags &= ~(PTE_I | PTE_G | PTE_FAKE); 1294 break; 1295 } 1296 } 1297#else 1298 flags = 0; 1299#endif 1300 1301 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1302 1303 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1304 1305 if (PTE_ISVALID(pte)) { 1306 //debugf("mmu_booke_kenter: replacing entry!\n"); 1307 1308 /* Flush entry from TLB0 */ 1309 tlb0_flush_entry(kernel_pmap, va); 1310 } 1311 1312 pte->rpn = pa & ~PTE_PA_MASK; 1313 pte->flags = flags; 1314 1315 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1316 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1317 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1318 1319 /* Flush the real memory from the instruction cache. */ 1320 if ((flags & (PTE_I | PTE_G)) == 0) { 1321 __syncicache((void *)va, PAGE_SIZE); 1322 } 1323 1324 //debugf("mmu_booke_kenter: e\n"); 1325} 1326 1327/* 1328 * Remove a page from kernel page table. 1329 */ 1330static void 1331mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1332{ 1333 unsigned int pdir_idx = PDIR_IDX(va); 1334 unsigned int ptbl_idx = PTBL_IDX(va); 1335 pte_t *pte; 1336 1337 //debugf("mmu_booke_kremove: s (va = 0x%08x)\n", va); 1338 1339 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)), 1340 ("mmu_booke_kremove: invalid va")); 1341 1342 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1343 1344 if (!PTE_ISVALID(pte)) { 1345 //debugf("mmu_booke_kremove: e (invalid pte)\n"); 1346 return; 1347 } 1348 1349 /* Invalidate entry in TLB0. */ 1350 tlb0_flush_entry(kernel_pmap, va); 1351 1352 pte->flags = 0; 1353 pte->rpn = 0; 1354 1355 //debugf("mmu_booke_kremove: e\n"); 1356} 1357 1358/* 1359 * Initialize pmap associated with process 0. 1360 */ 1361static void 1362mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1363{ 1364 //debugf("mmu_booke_pinit0: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 1365 mmu_booke_pinit(mmu, pmap); 1366 PCPU_SET(curpmap, pmap); 1367 //debugf("mmu_booke_pinit0: e\n"); 1368} 1369 1370/* 1371 * Initialize a preallocated and zeroed pmap structure, 1372 * such as one in a vmspace structure. 1373 */ 1374static void 1375mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1376{ 1377 1378 //struct thread *td; 1379 //struct proc *p; 1380 1381 //td = PCPU_GET(curthread); 1382 //p = td->td_proc; 1383 //debugf("mmu_booke_pinit: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 1384 //printf("mmu_booke_pinit: proc %d '%s'\n", p->p_pid, p->p_comm); 1385 1386 KASSERT((pmap != kernel_pmap), ("mmu_booke_pinit: initializing kernel_pmap")); 1387 1388 PMAP_LOCK_INIT(pmap); 1389 pmap->pm_tid = 0; 1390 pmap->pm_active = 0; 1391 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1392 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1393 1394 TAILQ_INIT(&pmap->ptbl_list); 1395 1396 //debugf("mmu_booke_pinit: e\n"); 1397} 1398 1399/* 1400 * Release any resources held by the given physical map. 1401 * Called when a pmap initialized by mmu_booke_pinit is being released. 1402 * Should only be called if the map contains no valid mappings. 1403 */ 1404static void 1405mmu_booke_release(mmu_t mmu, pmap_t pmap) 1406{ 1407 1408 //debugf("mmu_booke_release: s\n"); 1409 1410 PMAP_LOCK_DESTROY(pmap); 1411 1412 //debugf("mmu_booke_release: e\n"); 1413} 1414 1415#if 0 1416/* Not needed, kernel page tables are statically allocated. */ 1417void 1418mmu_booke_growkernel(vm_offset_t maxkvaddr) 1419{ 1420} 1421#endif 1422 1423/* 1424 * Insert the given physical page at the specified virtual address in the 1425 * target physical map with the protection requested. If specified the page 1426 * will be wired down. 1427 */ 1428static void 1429mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1430 vm_prot_t prot, boolean_t wired) 1431{ 1432 vm_page_lock_queues(); 1433 PMAP_LOCK(pmap); 1434 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1435 vm_page_unlock_queues(); 1436 PMAP_UNLOCK(pmap); 1437} 1438 1439static void 1440mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1441 vm_prot_t prot, boolean_t wired) 1442{ 1443 pte_t *pte; 1444 vm_paddr_t pa; 1445 u_int32_t flags; 1446 int su, sync; 1447 1448 pa = VM_PAGE_TO_PHYS(m); 1449 su = (pmap == kernel_pmap); 1450 sync = 0; 1451 1452 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1453 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1454 // (u_int32_t)pmap, su, pmap->pm_tid, 1455 // (u_int32_t)m, va, pa, prot, wired); 1456 1457 if (su) { 1458 KASSERT(((va >= virtual_avail) && (va <= VM_MAX_KERNEL_ADDRESS)), 1459 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1460 } else { 1461 KASSERT((va <= VM_MAXUSER_ADDRESS), 1462 ("mmu_booke_enter_locked: user pmap, non user va")); 1463 } 1464 1465 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1466 1467 /* 1468 * If there is an existing mapping, and the physical address has not 1469 * changed, must be protection or wiring change. 1470 */ 1471 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1472 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1473 1474 //debugf("mmu_booke_enter_locked: update\n"); 1475 1476 /* Wiring change, just update stats. */ 1477 if (wired) { 1478 if (!PTE_ISWIRED(pte)) { 1479 pte->flags |= PTE_WIRED; 1480 pmap->pm_stats.wired_count++; 1481 } 1482 } else { 1483 if (PTE_ISWIRED(pte)) { 1484 pte->flags &= ~PTE_WIRED; 1485 pmap->pm_stats.wired_count--; 1486 } 1487 } 1488 1489 /* Save the old bits and clear the ones we're interested in. */ 1490 flags = pte->flags; 1491 pte->flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1492 1493 if (prot & VM_PROT_WRITE) { 1494 /* Add write permissions. */ 1495 pte->flags |= PTE_SW; 1496 if (!su) 1497 pte->flags |= PTE_UW; 1498 } else { 1499 /* Handle modified pages, sense modify status. */ 1500 if (PTE_ISMODIFIED(pte)) 1501 vm_page_dirty(m); 1502 } 1503 1504 /* If we're turning on execute permissions, flush the icache. */ 1505 if (prot & VM_PROT_EXECUTE) { 1506 pte->flags |= PTE_SX; 1507 if (!su) 1508 pte->flags |= PTE_UX; 1509 1510 if ((flags & (PTE_UX | PTE_SX)) == 0) 1511 sync++; 1512 } 1513 1514 /* Flush the old mapping from TLB0. */ 1515 pte->flags &= ~PTE_REFERENCED; 1516 tlb0_flush_entry(pmap, va); 1517 } else { 1518 /* 1519 * If there is an existing mapping, but its for a different 1520 * physical address, pte_enter() will delete the old mapping. 1521 */ 1522 //if ((pte != NULL) && PTE_ISVALID(pte)) 1523 // debugf("mmu_booke_enter_locked: replace\n"); 1524 //else 1525 // debugf("mmu_booke_enter_locked: new\n"); 1526 1527 /* Now set up the flags and install the new mapping. */ 1528 flags = (PTE_SR | PTE_VALID); 1529 1530 if (!su) 1531 flags |= PTE_UR; 1532 1533 if (prot & VM_PROT_WRITE) { 1534 flags |= PTE_SW; 1535 if (!su) 1536 flags |= PTE_UW; 1537 } 1538 1539 if (prot & VM_PROT_EXECUTE) { 1540 flags |= PTE_SX; 1541 if (!su) 1542 flags |= PTE_UX; 1543 } 1544 1545 /* If its wired update stats. */ 1546 if (wired) { 1547 pmap->pm_stats.wired_count++; 1548 flags |= PTE_WIRED; 1549 } 1550 1551 pte_enter(mmu, pmap, m, va, flags); 1552 1553 /* Flush the real memory from the instruction cache. */ 1554 if (prot & VM_PROT_EXECUTE) 1555 sync++; 1556 } 1557 1558 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1559 __syncicache((void *)va, PAGE_SIZE); 1560 sync = 0; 1561 } 1562 1563 if (sync) { 1564 /* Create a temporary mapping. */ 1565 pmap = PCPU_GET(curpmap); 1566 1567 va = 0; 1568 pte = pte_find(mmu, pmap, va); 1569 KASSERT(pte == NULL, ("%s:%d", __func__, __LINE__)); 1570 1571 flags = PTE_SR | PTE_VALID | PTE_UR; 1572 pte_enter(mmu, pmap, m, va, flags); 1573 __syncicache((void *)va, PAGE_SIZE); 1574 pte_remove(mmu, pmap, va, PTBL_UNHOLD); 1575 } 1576 1577 //debugf("mmu_booke_enter_locked: e\n"); 1578} 1579 1580/* 1581 * Maps a sequence of resident pages belonging to the same object. 1582 * The sequence begins with the given page m_start. This page is 1583 * mapped at the given virtual address start. Each subsequent page is 1584 * mapped at a virtual address that is offset from start by the same 1585 * amount as the page is offset from m_start within the object. The 1586 * last page in the sequence is the page with the largest offset from 1587 * m_start that can be mapped at a virtual address less than the given 1588 * virtual address end. Not every virtual page between start and end 1589 * is mapped; only those for which a resident page exists with the 1590 * corresponding offset from m_start are mapped. 1591 */ 1592static void 1593mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1594 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1595{ 1596 vm_page_t m; 1597 vm_pindex_t diff, psize; 1598 1599 psize = atop(end - start); 1600 m = m_start; 1601 PMAP_LOCK(pmap); 1602 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1603 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, prot & 1604 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1605 m = TAILQ_NEXT(m, listq); 1606 } 1607 PMAP_UNLOCK(pmap); 1608} 1609 1610static void 1611mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1612 vm_prot_t prot) 1613{ 1614 1615 //debugf("mmu_booke_enter_quick: s\n"); 1616 1617 PMAP_LOCK(pmap); 1618 mmu_booke_enter_locked(mmu, pmap, va, m, 1619 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1620 PMAP_UNLOCK(pmap); 1621 1622 //debugf("mmu_booke_enter_quick e\n"); 1623} 1624 1625/* 1626 * Remove the given range of addresses from the specified map. 1627 * 1628 * It is assumed that the start and end are properly rounded to the page size. 1629 */ 1630static void 1631mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1632{ 1633 pte_t *pte; 1634 u_int8_t hold_flag; 1635 1636 int su = (pmap == kernel_pmap); 1637 1638 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1639 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1640 1641 if (su) { 1642 KASSERT(((va >= virtual_avail) && (va <= VM_MAX_KERNEL_ADDRESS)), 1643 ("mmu_booke_enter: kernel pmap, non kernel va")); 1644 } else { 1645 KASSERT((va <= VM_MAXUSER_ADDRESS), 1646 ("mmu_booke_enter: user pmap, non user va")); 1647 } 1648 1649 if (PMAP_REMOVE_DONE(pmap)) { 1650 //debugf("mmu_booke_remove: e (empty)\n"); 1651 return; 1652 } 1653 1654 hold_flag = PTBL_HOLD_FLAG(pmap); 1655 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1656 1657 vm_page_lock_queues(); 1658 PMAP_LOCK(pmap); 1659 for (; va < endva; va += PAGE_SIZE) { 1660 pte = pte_find(mmu, pmap, va); 1661 if ((pte != NULL) && PTE_ISVALID(pte)) { 1662 pte_remove(mmu, pmap, va, hold_flag); 1663 1664 /* Flush mapping from TLB0. */ 1665 tlb0_flush_entry(pmap, va); 1666 } 1667 } 1668 PMAP_UNLOCK(pmap); 1669 vm_page_unlock_queues(); 1670 1671 //debugf("mmu_booke_remove: e\n"); 1672} 1673 1674/* 1675 * Remove physical page from all pmaps in which it resides. 1676 */ 1677static void 1678mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1679{ 1680 pv_entry_t pv, pvn; 1681 u_int8_t hold_flag; 1682 1683 //debugf("mmu_booke_remove_all: s\n"); 1684 1685 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1686 1687 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1688 pvn = TAILQ_NEXT(pv, pv_link); 1689 1690 PMAP_LOCK(pv->pv_pmap); 1691 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1692 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1693 1694 /* Flush mapping from TLB0. */ 1695 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 1696 PMAP_UNLOCK(pv->pv_pmap); 1697 } 1698 vm_page_flag_clear(m, PG_WRITEABLE); 1699 1700 //debugf("mmu_booke_remove_all: e\n"); 1701} 1702 1703/* 1704 * Map a range of physical addresses into kernel virtual address space. 1705 * 1706 * The value passed in *virt is a suggested virtual address for the mapping. 1707 * Architectures which can support a direct-mapped physical to virtual region 1708 * can return the appropriate address within that region, leaving '*virt' 1709 * unchanged. We cannot and therefore do not; *virt is updated with the 1710 * first usable address after the mapped region. 1711 */ 1712static vm_offset_t 1713mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1714 vm_offset_t pa_end, int prot) 1715{ 1716 vm_offset_t sva = *virt; 1717 vm_offset_t va = sva; 1718 1719 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1720 // sva, pa_start, pa_end); 1721 1722 while (pa_start < pa_end) { 1723 mmu_booke_kenter(mmu, va, pa_start); 1724 va += PAGE_SIZE; 1725 pa_start += PAGE_SIZE; 1726 } 1727 *virt = va; 1728 1729 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1730 return (sva); 1731} 1732 1733/* 1734 * The pmap must be activated before it's address space can be accessed in any 1735 * way. 1736 */ 1737static void 1738mmu_booke_activate(mmu_t mmu, struct thread *td) 1739{ 1740 pmap_t pmap; 1741 1742 pmap = &td->td_proc->p_vmspace->vm_pmap; 1743 1744 //debugf("mmu_booke_activate: s (proc = '%s', id = %d, pmap = 0x%08x)\n", 1745 // td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1746 1747 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1748 1749 mtx_lock_spin(&sched_lock); 1750 1751 pmap->pm_active |= PCPU_GET(cpumask); 1752 PCPU_SET(curpmap, pmap); 1753 1754 if (!pmap->pm_tid) 1755 tid_alloc(pmap); 1756 1757 /* Load PID0 register with pmap tid value. */ 1758 load_pid0(pmap->pm_tid); 1759 1760 mtx_unlock_spin(&sched_lock); 1761 1762 //debugf("mmu_booke_activate: e (tid = %d for '%s')\n", pmap->pm_tid, 1763 // td->td_proc->p_comm); 1764} 1765 1766/* 1767 * Deactivate the specified process's address space. 1768 */ 1769static void 1770mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1771{ 1772 pmap_t pmap; 1773 1774 pmap = &td->td_proc->p_vmspace->vm_pmap; 1775 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1776 PCPU_SET(curpmap, NULL); 1777} 1778 1779/* 1780 * Copy the range specified by src_addr/len 1781 * from the source map to the range dst_addr/len 1782 * in the destination map. 1783 * 1784 * This routine is only advisory and need not do anything. 1785 */ 1786static void 1787mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 1788 vm_size_t len, vm_offset_t src_addr) 1789{ 1790 1791} 1792 1793/* 1794 * Set the physical protection on the specified range of this map as requested. 1795 */ 1796static void 1797mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1798 vm_prot_t prot) 1799{ 1800 vm_offset_t va; 1801 vm_page_t m; 1802 pte_t *pte; 1803 1804 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1805 mmu_booke_remove(mmu, pmap, sva, eva); 1806 return; 1807 } 1808 1809 if (prot & VM_PROT_WRITE) 1810 return; 1811 1812 vm_page_lock_queues(); 1813 PMAP_LOCK(pmap); 1814 for (va = sva; va < eva; va += PAGE_SIZE) { 1815 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1816 if (PTE_ISVALID(pte)) { 1817 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1818 1819 /* Handle modified pages. */ 1820 if (PTE_ISMODIFIED(pte)) 1821 vm_page_dirty(m); 1822 1823 /* Referenced pages. */ 1824 if (PTE_ISREFERENCED(pte)) 1825 vm_page_flag_set(m, PG_REFERENCED); 1826 1827 /* Flush mapping from TLB0. */ 1828 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1829 PTE_REFERENCED); 1830 tlb0_flush_entry(pmap, va); 1831 } 1832 } 1833 } 1834 PMAP_UNLOCK(pmap); 1835 vm_page_unlock_queues(); 1836} 1837 1838/* 1839 * Clear the write and modified bits in each of the given page's mappings. 1840 */ 1841static void 1842mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1843{ 1844 pv_entry_t pv; 1845 pte_t *pte; 1846 1847 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1848 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1849 (m->flags & PG_WRITEABLE) == 0) 1850 return; 1851 1852 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1853 PMAP_LOCK(pv->pv_pmap); 1854 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1855 if (PTE_ISVALID(pte)) { 1856 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1857 1858 /* Handle modified pages. */ 1859 if (PTE_ISMODIFIED(pte)) 1860 vm_page_dirty(m); 1861 1862 /* Referenced pages. */ 1863 if (PTE_ISREFERENCED(pte)) 1864 vm_page_flag_set(m, PG_REFERENCED); 1865 1866 /* Flush mapping from TLB0. */ 1867 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1868 PTE_REFERENCED); 1869 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 1870 } 1871 } 1872 PMAP_UNLOCK(pv->pv_pmap); 1873 } 1874 vm_page_flag_clear(m, PG_WRITEABLE); 1875} 1876 1877static boolean_t 1878mmu_booke_page_executable(mmu_t mmu, vm_page_t m) 1879{ 1880 pv_entry_t pv; 1881 pte_t *pte; 1882 boolean_t executable; 1883 1884 executable = FALSE; 1885 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1886 PMAP_LOCK(pv->pv_pmap); 1887 pte = pte_find(mmu, pv->pv_pmap, pv->pv_va); 1888 if (pte != NULL && PTE_ISVALID(pte) && (pte->flags & PTE_UX)) 1889 executable = TRUE; 1890 PMAP_UNLOCK(pv->pv_pmap); 1891 if (executable) 1892 break; 1893 } 1894 1895 return (executable); 1896} 1897 1898/* 1899 * Atomically extract and hold the physical page with the given 1900 * pmap and virtual address pair if that mapping permits the given 1901 * protection. 1902 */ 1903static vm_page_t 1904mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 1905 vm_prot_t prot) 1906{ 1907 pte_t *pte; 1908 vm_page_t m; 1909 u_int32_t pte_wbit; 1910 1911 m = NULL; 1912 vm_page_lock_queues(); 1913 PMAP_LOCK(pmap); 1914 pte = pte_find(mmu, pmap, va); 1915 1916 if ((pte != NULL) && PTE_ISVALID(pte)) { 1917 if (pmap == kernel_pmap) 1918 pte_wbit = PTE_SW; 1919 else 1920 pte_wbit = PTE_UW; 1921 1922 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 1923 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1924 vm_page_hold(m); 1925 } 1926 } 1927 1928 vm_page_unlock_queues(); 1929 PMAP_UNLOCK(pmap); 1930 return (m); 1931} 1932 1933/* 1934 * Initialize a vm_page's machine-dependent fields. 1935 */ 1936static void 1937mmu_booke_page_init(mmu_t mmu, vm_page_t m) 1938{ 1939 1940 TAILQ_INIT(&m->md.pv_list); 1941} 1942 1943/* 1944 * mmu_booke_zero_page_area zeros the specified hardware page by 1945 * mapping it into virtual memory and using bzero to clear 1946 * its contents. 1947 * 1948 * off and size must reside within a single page. 1949 */ 1950static void 1951mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1952{ 1953 vm_offset_t va; 1954 1955 //debugf("mmu_booke_zero_page_area: s\n"); 1956 1957 mtx_lock(&zero_page_mutex); 1958 va = zero_page_va; 1959 1960 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 1961 bzero((caddr_t)va + off, size); 1962 mmu_booke_kremove(mmu, va); 1963 1964 mtx_unlock(&zero_page_mutex); 1965 1966 //debugf("mmu_booke_zero_page_area: e\n"); 1967} 1968 1969/* 1970 * mmu_booke_zero_page zeros the specified hardware page. 1971 */ 1972static void 1973mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 1974{ 1975 1976 //debugf("mmu_booke_zero_page: s\n"); 1977 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 1978 //debugf("mmu_booke_zero_page: e\n"); 1979} 1980 1981/* 1982 * mmu_booke_copy_page copies the specified (machine independent) page by 1983 * mapping the page into virtual memory and using memcopy to copy the page, 1984 * one machine dependent page at a time. 1985 */ 1986static void 1987mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 1988{ 1989 vm_offset_t sva, dva; 1990 1991 //debugf("mmu_booke_copy_page: s\n"); 1992 1993 mtx_lock(©_page_mutex); 1994 sva = copy_page_src_va; 1995 dva = copy_page_dst_va; 1996 1997 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 1998 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 1999 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2000 mmu_booke_kremove(mmu, dva); 2001 mmu_booke_kremove(mmu, sva); 2002 2003 mtx_unlock(©_page_mutex); 2004 2005 //debugf("mmu_booke_copy_page: e\n"); 2006} 2007 2008#if 0 2009/* 2010 * Remove all pages from specified address space, this aids process exit 2011 * speeds. This is much faster than mmu_booke_remove in the case of running 2012 * down an entire address space. Only works for the current pmap. 2013 */ 2014void 2015mmu_booke_remove_pages(pmap_t pmap) 2016{ 2017} 2018#endif 2019 2020/* 2021 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2022 * into virtual memory and using bzero to clear its contents. This is intended 2023 * to be called from the vm_pagezero process only and outside of Giant. No 2024 * lock is required. 2025 */ 2026static void 2027mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2028{ 2029 vm_offset_t va; 2030 2031 //debugf("mmu_booke_zero_page_idle: s\n"); 2032 2033 va = zero_page_idle_va; 2034 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2035 bzero((caddr_t)va, PAGE_SIZE); 2036 mmu_booke_kremove(mmu, va); 2037 2038 //debugf("mmu_booke_zero_page_idle: e\n"); 2039} 2040 2041/* 2042 * Return whether or not the specified physical page was modified 2043 * in any of physical maps. 2044 */ 2045static boolean_t 2046mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2047{ 2048 pte_t *pte; 2049 pv_entry_t pv; 2050 2051 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2052 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2053 return (FALSE); 2054 2055 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2056 PMAP_LOCK(pv->pv_pmap); 2057 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2058 if (!PTE_ISVALID(pte)) 2059 goto make_sure_to_unlock; 2060 2061 if (PTE_ISMODIFIED(pte)) { 2062 PMAP_UNLOCK(pv->pv_pmap); 2063 return (TRUE); 2064 } 2065 } 2066make_sure_to_unlock: 2067 PMAP_UNLOCK(pv->pv_pmap); 2068 } 2069 return (FALSE); 2070} 2071 2072/* 2073 * Return whether or not the specified virtual address is elgible 2074 * for prefault. 2075 */ 2076static boolean_t 2077mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2078{ 2079 2080 return (FALSE); 2081} 2082 2083/* 2084 * Clear the modify bits on the specified physical page. 2085 */ 2086static void 2087mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2088{ 2089 pte_t *pte; 2090 pv_entry_t pv; 2091 2092 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2093 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2094 return; 2095 2096 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2097 PMAP_LOCK(pv->pv_pmap); 2098 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2099 if (!PTE_ISVALID(pte)) 2100 goto make_sure_to_unlock; 2101 2102 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2103 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2104 PTE_REFERENCED); 2105 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2106 } 2107 } 2108make_sure_to_unlock: 2109 PMAP_UNLOCK(pv->pv_pmap); 2110 } 2111} 2112 2113/* 2114 * Return a count of reference bits for a page, clearing those bits. 2115 * It is not necessary for every reference bit to be cleared, but it 2116 * is necessary that 0 only be returned when there are truly no 2117 * reference bits set. 2118 * 2119 * XXX: The exact number of bits to check and clear is a matter that 2120 * should be tested and standardized at some point in the future for 2121 * optimal aging of shared pages. 2122 */ 2123static int 2124mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2125{ 2126 pte_t *pte; 2127 pv_entry_t pv; 2128 int count; 2129 2130 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2131 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2132 return (0); 2133 2134 count = 0; 2135 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2136 PMAP_LOCK(pv->pv_pmap); 2137 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2138 if (!PTE_ISVALID(pte)) 2139 goto make_sure_to_unlock; 2140 2141 if (PTE_ISREFERENCED(pte)) { 2142 pte->flags &= ~PTE_REFERENCED; 2143 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2144 2145 if (++count > 4) { 2146 PMAP_UNLOCK(pv->pv_pmap); 2147 break; 2148 } 2149 } 2150 } 2151make_sure_to_unlock: 2152 PMAP_UNLOCK(pv->pv_pmap); 2153 } 2154 return (count); 2155} 2156 2157/* 2158 * Clear the reference bit on the specified physical page. 2159 */ 2160static void 2161mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2162{ 2163 pte_t *pte; 2164 pv_entry_t pv; 2165 2166 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2167 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2168 return; 2169 2170 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2171 PMAP_LOCK(pv->pv_pmap); 2172 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2173 if (!PTE_ISVALID(pte)) 2174 goto make_sure_to_unlock; 2175 2176 if (PTE_ISREFERENCED(pte)) { 2177 pte->flags &= ~PTE_REFERENCED; 2178 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2179 } 2180 } 2181make_sure_to_unlock: 2182 PMAP_UNLOCK(pv->pv_pmap); 2183 } 2184} 2185 2186/* 2187 * Change wiring attribute for a map/virtual-address pair. 2188 */ 2189static void 2190mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2191{ 2192 pte_t *pte;; 2193 2194 PMAP_LOCK(pmap); 2195 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2196 if (wired) { 2197 if (!PTE_ISWIRED(pte)) { 2198 pte->flags |= PTE_WIRED; 2199 pmap->pm_stats.wired_count++; 2200 } 2201 } else { 2202 if (PTE_ISWIRED(pte)) { 2203 pte->flags &= ~PTE_WIRED; 2204 pmap->pm_stats.wired_count--; 2205 } 2206 } 2207 } 2208 PMAP_UNLOCK(pmap); 2209} 2210 2211/* 2212 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2213 * page. This count may be changed upwards or downwards in the future; it is 2214 * only necessary that true be returned for a small subset of pmaps for proper 2215 * page aging. 2216 */ 2217static boolean_t 2218mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2219{ 2220 pv_entry_t pv; 2221 int loops; 2222 2223 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2224 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2225 return (FALSE); 2226 2227 loops = 0; 2228 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2229 2230 if (pv->pv_pmap == pmap) 2231 return (TRUE); 2232 2233 if (++loops >= 16) 2234 break; 2235 } 2236 return (FALSE); 2237} 2238 2239/* 2240 * Return the number of managed mappings to the given physical page that are 2241 * wired. 2242 */ 2243static int 2244mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2245{ 2246 pv_entry_t pv; 2247 pte_t *pte; 2248 int count = 0; 2249 2250 if ((m->flags & PG_FICTITIOUS) != 0) 2251 return (count); 2252 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2253 2254 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2255 PMAP_LOCK(pv->pv_pmap); 2256 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2257 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2258 count++; 2259 PMAP_UNLOCK(pv->pv_pmap); 2260 } 2261 2262 return (count); 2263} 2264 2265static int 2266mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2267{ 2268 int i; 2269 vm_offset_t va; 2270 2271 /* 2272 * This currently does not work for entries that 2273 * overlap TLB1 entries. 2274 */ 2275 for (i = 0; i < tlb1_idx; i ++) { 2276 if (tlb1_iomapped(i, pa, size, &va) == 0) 2277 return (0); 2278 } 2279 2280 return (EFAULT); 2281} 2282 2283/* 2284 * Map a set of physical memory pages into the kernel virtual address space. 2285 * Return a pointer to where it is mapped. This routine is intended to be used 2286 * for mapping device memory, NOT real memory. 2287 */ 2288static void * 2289mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2290{ 2291 uintptr_t va; 2292 2293 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2294 if (bootverbose) 2295 printf("Wiring VA=%x to PA=%x (size=%x), using TLB1[%d]\n", 2296 va, pa, size, tlb1_idx); 2297 tlb1_set_entry(va, pa, size, _TLB_ENTRY_IO); 2298 return ((void *)va); 2299} 2300 2301/* 2302 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2303 */ 2304static void 2305mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2306{ 2307 vm_offset_t base, offset; 2308 2309 //debugf("mmu_booke_unmapdev: s (va = 0x%08x)\n", va); 2310 2311 /* 2312 * Unmap only if this is inside kernel virtual space. 2313 */ 2314 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2315 base = trunc_page(va); 2316 offset = va & PAGE_MASK; 2317 size = roundup(offset + size, PAGE_SIZE); 2318 kmem_free(kernel_map, base, size); 2319 } 2320 2321 //debugf("mmu_booke_unmapdev: e\n"); 2322} 2323 2324/* 2325 * mmu_booke_object_init_pt preloads the ptes for a given object 2326 * into the specified pmap. This eliminates the blast of soft 2327 * faults on process startup and immediately after an mmap. 2328 */ 2329static void 2330mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2331 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2332{ 2333 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2334 KASSERT(object->type == OBJT_DEVICE, 2335 ("mmu_booke_object_init_pt: non-device object")); 2336} 2337 2338/* 2339 * Perform the pmap work for mincore. 2340 */ 2341static int 2342mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2343{ 2344 2345 TODO; 2346 return (0); 2347} 2348 2349/**************************************************************************/ 2350/* TID handling */ 2351/**************************************************************************/ 2352/* 2353 * Flush all entries from TLB0 matching given tid. 2354 */ 2355static void 2356tid_flush(tlbtid_t tid) 2357{ 2358 int i, entryidx, way; 2359 2360 //debugf("tid_flush: s (tid = %d)\n", tid); 2361 2362 mtx_lock_spin(&tlb0_mutex); 2363 2364 for (i = 0; i < TLB0_SIZE; i++) { 2365 if (MAS1_GETTID(tlb0[i].mas1) == tid) { 2366 way = i / TLB0_ENTRIES_PER_WAY; 2367 entryidx = i - (way * TLB0_ENTRIES_PER_WAY); 2368 2369 //debugf("tid_flush: inval tlb0 entry %d\n", i); 2370 tlb0_inval_entry(entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT, way); 2371 } 2372 } 2373 2374 mtx_unlock_spin(&tlb0_mutex); 2375 2376 //debugf("tid_flush: e\n"); 2377} 2378 2379/* 2380 * Allocate a TID. If necessary, steal one from someone else. 2381 * The new TID is flushed from the TLB before returning. 2382 */ 2383static tlbtid_t 2384tid_alloc(pmap_t pmap) 2385{ 2386 tlbtid_t tid; 2387 static tlbtid_t next_tid = TID_MIN; 2388 2389 //struct thread *td; 2390 //struct proc *p; 2391 2392 //td = PCPU_GET(curthread); 2393 //p = td->td_proc; 2394 //debugf("tid_alloc: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 2395 //printf("tid_alloc: proc %d '%s'\n", p->p_pid, p->p_comm); 2396 2397 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2398 2399 /* 2400 * Find a likely TID, allocate unused if possible, 2401 * skip reserved entries. 2402 */ 2403 tid = next_tid; 2404 while (tidbusy[tid] != NULL) { 2405 if (tid == next_tid) 2406 break; 2407 2408 if (tid == TID_MAX) 2409 tid = TID_MIN; 2410 else 2411 tid++; 2412 2413 } 2414 2415 /* Now clean it out */ 2416 tid_flush(tid); 2417 2418 /* If we are stealing pmap then clear its tid */ 2419 if (tidbusy[tid]) { 2420 //debugf("warning: stealing tid %d\n", tid); 2421 tidbusy[tid]->pm_tid = 0; 2422 } 2423 2424 /* Calculate next tid */ 2425 if (tid == TID_MAX) 2426 next_tid = TID_MIN; 2427 else 2428 next_tid = tid + 1; 2429 2430 tidbusy[tid] = pmap; 2431 pmap->pm_tid = tid; 2432 2433 //debugf("tid_alloc: e (%02d next = %02d)\n", tid, next_tid); 2434 return (tid); 2435} 2436 2437#if 0 2438/* 2439 * Free this pmap's TID. 2440 */ 2441static void 2442tid_free(pmap_t pmap) 2443{ 2444 tlbtid_t oldtid; 2445 2446 oldtid = pmap->pm_tid; 2447 2448 if (oldtid == 0) { 2449 panic("tid_free: freeing kernel tid"); 2450 } 2451 2452#ifdef DEBUG 2453 if (tidbusy[oldtid] == 0) 2454 debugf("tid_free: freeing free tid %d\n", oldtid); 2455 if (tidbusy[oldtid] != pmap) { 2456 debugf("tid_free: freeing someone esle's tid\n " 2457 "tidbusy[%d] = 0x%08x pmap = 0x%08x\n", 2458 oldtid, (u_int32_t)tidbusy[oldtid], (u_int32_t)pmap); 2459 } 2460#endif 2461 2462 tidbusy[oldtid] = NULL; 2463 tid_flush(oldtid); 2464} 2465#endif 2466 2467#if 0 2468#if DEBUG 2469static void 2470tid_print_busy(void) 2471{ 2472 int i; 2473 2474 for (i = 0; i < TID_MAX; i++) { 2475 debugf("tid %d = pmap 0x%08x", i, (u_int32_t)tidbusy[i]); 2476 if (tidbusy[i]) 2477 debugf(" pmap->tid = %d", tidbusy[i]->pm_tid); 2478 debugf("\n"); 2479 } 2480 2481} 2482#endif /* DEBUG */ 2483#endif 2484 2485/**************************************************************************/ 2486/* TLB0 handling */ 2487/**************************************************************************/ 2488 2489static void 2490tlb_print_entry(int i, u_int32_t mas1, u_int32_t mas2, u_int32_t mas3, u_int32_t mas7) 2491{ 2492 int as; 2493 char desc[3]; 2494 tlbtid_t tid; 2495 vm_size_t size; 2496 unsigned int tsize; 2497 2498 desc[2] = '\0'; 2499 if (mas1 & MAS1_VALID) 2500 desc[0] = 'V'; 2501 else 2502 desc[0] = ' '; 2503 2504 if (mas1 & MAS1_IPROT) 2505 desc[1] = 'P'; 2506 else 2507 desc[1] = ' '; 2508 2509 as = (mas1 & MAS1_TS) ? 1 : 0; 2510 tid = MAS1_GETTID(mas1); 2511 2512 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2513 size = 0; 2514 if (tsize) 2515 size = tsize2size(tsize); 2516 2517 debugf("%3d: (%s) [AS=%d] " 2518 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2519 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2520 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2521} 2522 2523/* Convert TLB0 va and way number to tlb0[] table index. */ 2524static inline unsigned int 2525tlb0_tableidx(vm_offset_t va, unsigned int way) 2526{ 2527 unsigned int idx; 2528 2529 idx = (way * TLB0_ENTRIES_PER_WAY); 2530 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2531 return (idx); 2532} 2533 2534/* 2535 * Write given entry to TLB0 hardware. 2536 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2537 */ 2538static void 2539tlb0_write_entry(unsigned int idx, unsigned int way) 2540{ 2541 u_int32_t mas0, mas7, nv; 2542 2543 /* Clear high order RPN bits. */ 2544 mas7 = 0; 2545 2546 /* Preserve NV. */ 2547 mas0 = mfspr(SPR_MAS0); 2548 nv = mas0 & (TLB0_NWAYS - 1); 2549 2550 /* Select entry. */ 2551 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way) | nv; 2552 2553 //debugf("tlb0_write_entry: s (idx=%d way=%d mas0=0x%08x " 2554 // "mas1=0x%08x mas2=0x%08x mas3=0x%08x)\n", 2555 // idx, way, mas0, tlb0[idx].mas1, 2556 // tlb0[idx].mas2, tlb0[idx].mas3); 2557 2558 mtspr(SPR_MAS0, mas0); 2559 __asm volatile("isync"); 2560 mtspr(SPR_MAS1, tlb0[idx].mas1); 2561 __asm volatile("isync"); 2562 mtspr(SPR_MAS2, tlb0[idx].mas2); 2563 __asm volatile("isync"); 2564 mtspr(SPR_MAS3, tlb0[idx].mas3); 2565 __asm volatile("isync"); 2566 mtspr(SPR_MAS7, mas7); 2567 __asm volatile("isync; tlbwe; isync; msync"); 2568 2569 //debugf("tlb0_write_entry: e\n"); 2570} 2571 2572/* 2573 * Invalidate TLB0 entry, clear correspondig tlb0 table element. 2574 */ 2575static void 2576tlb0_inval_entry(vm_offset_t va, unsigned int way) 2577{ 2578 int idx = tlb0_tableidx(va, way); 2579 2580 //debugf("tlb0_inval_entry: s (va=0x%08x way=%d idx=%d)\n", 2581 // va, way, idx); 2582 2583 tlb0[idx].mas1 = 1 << MAS1_TSIZE_SHIFT; /* !MAS1_VALID */ 2584 tlb0[idx].mas2 = va & MAS2_EPN; 2585 tlb0[idx].mas3 = 0; 2586 2587 tlb0_write_entry(idx, way); 2588 2589 //debugf("tlb0_inval_entry: e\n"); 2590} 2591 2592/* 2593 * Invalidate TLB0 entry that corresponds to pmap/va. 2594 */ 2595static void 2596tlb0_flush_entry(pmap_t pmap, vm_offset_t va) 2597{ 2598 int idx, way; 2599 2600 //debugf("tlb0_flush_entry: s (pmap=0x%08x va=0x%08x)\n", 2601 // (u_int32_t)pmap, va); 2602 2603 mtx_lock_spin(&tlb0_mutex); 2604 2605 /* Check all TLB0 ways. */ 2606 for (way = 0; way < TLB0_NWAYS; way ++) { 2607 idx = tlb0_tableidx(va, way); 2608 2609 /* Invalidate only if entry matches va and pmap tid. */ 2610 if (((MAS1_GETTID(tlb0[idx].mas1) == pmap->pm_tid) && 2611 ((tlb0[idx].mas2 & MAS2_EPN) == va))) { 2612 tlb0_inval_entry(va, way); 2613 } 2614 } 2615 2616 mtx_unlock_spin(&tlb0_mutex); 2617 2618 //debugf("tlb0_flush_entry: e\n"); 2619} 2620 2621/* Clean TLB0 hardware and tlb0[] table. */ 2622static void 2623tlb0_init(void) 2624{ 2625 int entryidx, way; 2626 2627 debugf("tlb0_init: TLB0_SIZE = %d TLB0_NWAYS = %d\n", 2628 TLB0_SIZE, TLB0_NWAYS); 2629 2630 mtx_lock_spin(&tlb0_mutex); 2631 2632 for (way = 0; way < TLB0_NWAYS; way ++) { 2633 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2634 tlb0_inval_entry(entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT, way); 2635 } 2636 } 2637 2638 mtx_unlock_spin(&tlb0_mutex); 2639} 2640 2641#if 0 2642#if DEBUG 2643/* Print out tlb0 entries for given va. */ 2644static void 2645tlb0_print_tlbentries_va(vm_offset_t va) 2646{ 2647 u_int32_t mas0, mas1, mas2, mas3, mas7; 2648 int way, idx; 2649 2650 debugf("TLB0 entries for va = 0x%08x:\n", va); 2651 for (way = 0; way < TLB0_NWAYS; way ++) { 2652 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2653 mtspr(SPR_MAS0, mas0); 2654 __asm volatile("isync"); 2655 2656 mas2 = va & MAS2_EPN; 2657 mtspr(SPR_MAS2, mas2); 2658 __asm volatile("isync; tlbre"); 2659 2660 mas1 = mfspr(SPR_MAS1); 2661 mas2 = mfspr(SPR_MAS2); 2662 mas3 = mfspr(SPR_MAS3); 2663 mas7 = mfspr(SPR_MAS7); 2664 2665 idx = tlb0_tableidx(va, way); 2666 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2667 } 2668} 2669 2670/* Print out contents of the MAS registers for each TLB0 entry */ 2671static void 2672tlb0_print_tlbentries(void) 2673{ 2674 u_int32_t mas0, mas1, mas2, mas3, mas7; 2675 int entryidx, way, idx; 2676 2677 debugf("TLB0 entries:\n"); 2678 for (way = 0; way < TLB0_NWAYS; way ++) { 2679 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2680 2681 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2682 mtspr(SPR_MAS0, mas0); 2683 __asm volatile("isync"); 2684 2685 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2686 mtspr(SPR_MAS2, mas2); 2687 2688 __asm volatile("isync; tlbre"); 2689 2690 mas1 = mfspr(SPR_MAS1); 2691 mas2 = mfspr(SPR_MAS2); 2692 mas3 = mfspr(SPR_MAS3); 2693 mas7 = mfspr(SPR_MAS7); 2694 2695 idx = tlb0_tableidx(mas2, way); 2696 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2697 } 2698 } 2699} 2700 2701/* Print out kernel tlb0[] table. */ 2702static void 2703tlb0_print_entries(void) 2704{ 2705 int i; 2706 2707 debugf("tlb0[] table entries:\n"); 2708 for (i = 0; i < TLB0_SIZE; i++) { 2709 tlb_print_entry(i, tlb0[i].mas1, 2710 tlb0[i].mas2, tlb0[i].mas3, 0); 2711 } 2712} 2713#endif /* DEBUG */ 2714#endif 2715 2716/**************************************************************************/ 2717/* TLB1 handling */ 2718/**************************************************************************/ 2719/* 2720 * Write given entry to TLB1 hardware. 2721 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2722 */ 2723static void 2724tlb1_write_entry(unsigned int idx) 2725{ 2726 u_int32_t mas0, mas7; 2727 2728 //debugf("tlb1_write_entry: s\n"); 2729 2730 /* Clear high order RPN bits */ 2731 mas7 = 0; 2732 2733 /* Select entry */ 2734 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2735 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2736 2737 mtspr(SPR_MAS0, mas0); 2738 __asm volatile("isync"); 2739 mtspr(SPR_MAS1, tlb1[idx].mas1); 2740 __asm volatile("isync"); 2741 mtspr(SPR_MAS2, tlb1[idx].mas2); 2742 __asm volatile("isync"); 2743 mtspr(SPR_MAS3, tlb1[idx].mas3); 2744 __asm volatile("isync"); 2745 mtspr(SPR_MAS7, mas7); 2746 __asm volatile("isync; tlbwe; isync; msync"); 2747 2748 //debugf("tlb1_write_entry: e\n");; 2749} 2750 2751/* 2752 * Return the largest uint value log such that 2^log <= num. 2753 */ 2754static unsigned int 2755ilog2(unsigned int num) 2756{ 2757 int lz; 2758 2759 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2760 return (31 - lz); 2761} 2762 2763/* 2764 * Convert TLB TSIZE value to mapped region size. 2765 */ 2766static vm_size_t 2767tsize2size(unsigned int tsize) 2768{ 2769 2770 /* 2771 * size = 4^tsize KB 2772 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2773 */ 2774 2775 return ((1 << (2 * tsize)) * 1024); 2776} 2777 2778/* 2779 * Convert region size (must be power of 4) to TLB TSIZE value. 2780 */ 2781static unsigned int 2782size2tsize(vm_size_t size) 2783{ 2784 2785 /* 2786 * tsize = log2(size) / 2 - 5 2787 */ 2788 2789 return (ilog2(size) / 2 - 5); 2790} 2791 2792/* 2793 * Setup entry in a sw tlb1 table, write entry to TLB1 hardware. 2794 * This routine is used for low level operations on the TLB1, 2795 * for creating temporaray as well as permanent mappings (tlb_set_entry). 2796 * 2797 * We assume kernel mappings only, thus all entries created have supervisor 2798 * permission bits set nad user permission bits cleared. 2799 * 2800 * Provided mapping size must be a power of 4. 2801 * Mapping flags must be a combination of MAS2_[WIMG]. 2802 * Entry TID is set to _tid which must not exceed 8 bit value. 2803 * Entry TS is set to either 0 or MAS1_TS based on provided _ts. 2804 */ 2805static void 2806__tlb1_set_entry(unsigned int idx, vm_offset_t va, vm_offset_t pa, 2807 vm_size_t size, u_int32_t flags, unsigned int _tid, unsigned int _ts) 2808{ 2809 int tsize; 2810 u_int32_t ts, tid; 2811 2812 //debugf("__tlb1_set_entry: s (idx = %d va = 0x%08x pa = 0x%08x " 2813 // "size = 0x%08x flags = 0x%08x _tid = %d _ts = %d\n", 2814 // idx, va, pa, size, flags, _tid, _ts); 2815 2816 /* Convert size to TSIZE */ 2817 tsize = size2tsize(size); 2818 //debugf("__tlb1_set_entry: tsize = %d\n", tsize); 2819 2820 tid = (_tid << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2821 ts = (_ts) ? MAS1_TS : 0; 2822 tlb1[idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2823 tlb1[idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2824 2825 tlb1[idx].mas2 = (va & MAS2_EPN) | flags; 2826 2827 /* Set supervisor rwx permission bits */ 2828 tlb1[idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2829 2830 //debugf("__tlb1_set_entry: mas1 = %08x mas2 = %08x mas3 = 0x%08x\n", 2831 // tlb1[idx].mas1, tlb1[idx].mas2, tlb1[idx].mas3); 2832 2833 tlb1_write_entry(idx); 2834 //debugf("__tlb1_set_entry: e\n"); 2835} 2836 2837/* 2838 * Register permanent kernel mapping in TLB1. 2839 * 2840 * Entries are created starting from index 0 (current free entry is 2841 * kept in tlb1_idx) and are not supposed to be invalidated. 2842 */ 2843static int 2844tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, u_int32_t flags) 2845{ 2846 //debugf("tlb1_set_entry: s (tlb1_idx = %d va = 0x%08x pa = 0x%08x " 2847 // "size = 0x%08x flags = 0x%08x\n", 2848 // tlb1_idx, va, pa, size, flags); 2849 2850 if (tlb1_idx >= TLB1_SIZE) { 2851 //debugf("tlb1_set_entry: e (tlb1 full!)\n"); 2852 return (-1); 2853 } 2854 2855 /* TS = 0, TID = 0 */ 2856 __tlb1_set_entry(tlb1_idx++, va, pa, size, flags, KERNEL_TID, 0); 2857 //debugf("tlb1_set_entry: e\n"); 2858 return (0); 2859} 2860 2861/* 2862 * Invalidate TLB1 entry, clear correspondig tlb1 table element. 2863 * This routine is used to clear temporary entries created 2864 * early in a locore.S or through the use of __tlb1_set_entry(). 2865 */ 2866void 2867tlb1_inval_entry(unsigned int idx) 2868{ 2869 vm_offset_t va; 2870 2871 va = tlb1[idx].mas2 & MAS2_EPN; 2872 2873 tlb1[idx].mas1 = 0; /* !MAS1_VALID */ 2874 tlb1[idx].mas2 = 0; 2875 tlb1[idx].mas3 = 0; 2876 2877 tlb1_write_entry(idx); 2878} 2879 2880static int 2881tlb1_entry_size_cmp(const void *a, const void *b) 2882{ 2883 const vm_size_t *sza; 2884 const vm_size_t *szb; 2885 2886 sza = a; 2887 szb = b; 2888 if (*sza > *szb) 2889 return (-1); 2890 else if (*sza < *szb) 2891 return (1); 2892 else 2893 return (0); 2894} 2895 2896/* 2897 * Mapin contiguous RAM region into the TLB1 using maximum of 2898 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2899 * 2900 * If necessarry round up last entry size and return total size 2901 * used by all allocated entries. 2902 */ 2903vm_size_t 2904tlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2905{ 2906 vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2907 vm_size_t mapped_size, sz, esz; 2908 unsigned int log; 2909 int i; 2910 2911 debugf("tlb1_mapin_region:\n"); 2912 debugf(" region size = 0x%08x va = 0x%08x pa = 0x%08x\n", size, va, pa); 2913 2914 mapped_size = 0; 2915 sz = size; 2916 memset(entry_size, 0, sizeof(entry_size)); 2917 2918 /* Calculate entry sizes. */ 2919 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2920 2921 /* Largest region that is power of 4 and fits within size */ 2922 log = ilog2(sz)/2; 2923 esz = 1 << (2 * log); 2924 2925 /* Minimum region size is 4KB */ 2926 if (esz < (1 << 12)) 2927 esz = 1 << 12; 2928 2929 /* If this is last entry cover remaining size. */ 2930 if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2931 while (esz < sz) 2932 esz = esz << 2; 2933 } 2934 2935 entry_size[i] = esz; 2936 mapped_size += esz; 2937 if (esz < sz) 2938 sz -= esz; 2939 else 2940 sz = 0; 2941 } 2942 2943 /* Sort entry sizes, required to get proper entry address alignment. */ 2944 qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2945 sizeof(vm_size_t), tlb1_entry_size_cmp); 2946 2947 /* Load TLB1 entries. */ 2948 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2949 esz = entry_size[i]; 2950 if (!esz) 2951 break; 2952 debugf(" entry %d: sz = 0x%08x (va = 0x%08x pa = 0x%08x)\n", 2953 tlb1_idx, esz, va, pa); 2954 tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 2955 2956 va += esz; 2957 pa += esz; 2958 } 2959 2960 debugf(" mapped size 0x%08x (wasted space 0x%08x)\n", 2961 mapped_size, mapped_size - size); 2962 2963 return (mapped_size); 2964} 2965 2966/* 2967 * TLB1 initialization routine, to be called after the very first 2968 * assembler level setup done in locore.S. 2969 */ 2970void 2971tlb1_init(vm_offset_t ccsrbar) 2972{ 2973 uint32_t mas0; 2974 2975 /* TBL1[1] is used to map the kernel. Save that entry. */ 2976 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 2977 mtspr(SPR_MAS0, mas0); 2978 __asm __volatile("isync; tlbre"); 2979 2980 tlb1[1].mas1 = mfspr(SPR_MAS1); 2981 tlb1[1].mas2 = mfspr(SPR_MAS2); 2982 tlb1[1].mas3 = mfspr(SPR_MAS3); 2983 2984 /* Mapin CCSRBAR in TLB1[0] */ 2985 __tlb1_set_entry(0, CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, 2986 _TLB_ENTRY_IO, KERNEL_TID, 0); 2987 2988 /* Setup TLB miss defaults */ 2989 set_mas4_defaults(); 2990 2991 /* Reset next available TLB1 entry index. */ 2992 tlb1_idx = 2; 2993} 2994 2995/* 2996 * Setup MAS4 defaults. 2997 * These values are loaded to MAS0-2 on a TLB miss. 2998 */ 2999static void 3000set_mas4_defaults(void) 3001{ 3002 u_int32_t mas4; 3003 3004 /* Defaults: TLB0, PID0, TSIZED=4K */ 3005 mas4 = MAS4_TLBSELD0; 3006 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3007 3008 mtspr(SPR_MAS4, mas4); 3009 __asm volatile("isync"); 3010} 3011 3012/* 3013 * Print out contents of the MAS registers for each TLB1 entry 3014 */ 3015void 3016tlb1_print_tlbentries(void) 3017{ 3018 u_int32_t mas0, mas1, mas2, mas3, mas7; 3019 int i; 3020 3021 debugf("TLB1 entries:\n"); 3022 for (i = 0; i < TLB1_SIZE; i++) { 3023 3024 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3025 mtspr(SPR_MAS0, mas0); 3026 3027 __asm volatile("isync; tlbre"); 3028 3029 mas1 = mfspr(SPR_MAS1); 3030 mas2 = mfspr(SPR_MAS2); 3031 mas3 = mfspr(SPR_MAS3); 3032 mas7 = mfspr(SPR_MAS7); 3033 3034 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3035 } 3036} 3037 3038/* 3039 * Print out contents of the in-ram tlb1 table. 3040 */ 3041void 3042tlb1_print_entries(void) 3043{ 3044 int i; 3045 3046 debugf("tlb1[] table entries:\n"); 3047 for (i = 0; i < TLB1_SIZE; i++) 3048 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3049} 3050 3051/* 3052 * Return 0 if the physical IO range is encompassed by one of the 3053 * the TLB1 entries, otherwise return related error code. 3054 */ 3055static int 3056tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3057{ 3058 u_int32_t prot; 3059 vm_paddr_t pa_start; 3060 vm_paddr_t pa_end; 3061 unsigned int entry_tsize; 3062 vm_size_t entry_size; 3063 3064 *va = (vm_offset_t)NULL; 3065 3066 /* Skip invalid entries */ 3067 if (!(tlb1[i].mas1 & MAS1_VALID)) 3068 return (EINVAL); 3069 3070 /* 3071 * The entry must be cache-inhibited, guarded, and r/w 3072 * so it can function as an i/o page 3073 */ 3074 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3075 if (prot != (MAS2_I | MAS2_G)) 3076 return (EPERM); 3077 3078 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3079 if (prot != (MAS3_SR | MAS3_SW)) 3080 return (EPERM); 3081 3082 /* The address should be within the entry range. */ 3083 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3084 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3085 3086 entry_size = tsize2size(entry_tsize); 3087 pa_start = tlb1[i].mas3 & MAS3_RPN; 3088 pa_end = pa_start + entry_size - 1; 3089 3090 if ((pa < pa_start) || ((pa + size) > pa_end)) 3091 return (ERANGE); 3092 3093 /* Return virtual address of this mapping. */ 3094 *va = (tlb1[i].mas2 & MAS2_EPN) + (pa - pa_start); 3095 return (0); 3096} 3097