mmu_oea.c revision 143200
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 143200 2005-03-07 01:46:06Z grehan $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <dev/ofw/openfirm.h> 131 132#include <vm/vm.h> 133#include <vm/vm_param.h> 134#include <vm/vm_kern.h> 135#include <vm/vm_page.h> 136#include <vm/vm_map.h> 137#include <vm/vm_object.h> 138#include <vm/vm_extern.h> 139#include <vm/vm_pageout.h> 140#include <vm/vm_pager.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/powerpc.h> 145#include <machine/bat.h> 146#include <machine/frame.h> 147#include <machine/md_var.h> 148#include <machine/psl.h> 149#include <machine/pte.h> 150#include <machine/sr.h> 151 152#define PMAP_DEBUG 153 154#define TODO panic("%s: not implemented", __func__); 155 156#define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 157#define TLBSYNC() __asm __volatile("tlbsync"); 158#define SYNC() __asm __volatile("sync"); 159#define EIEIO() __asm __volatile("eieio"); 160 161#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 162#define VSID_TO_SR(vsid) ((vsid) & 0xf) 163#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 164 165#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 166#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 167#define PVO_WIRED 0x010 /* PVO entry is wired */ 168#define PVO_MANAGED 0x020 /* PVO entry is managed */ 169#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 170#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 171 bootstrap */ 172#define PVO_FAKE 0x100 /* fictitious phys page */ 173#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 174#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 175#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 176#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 177#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 178#define PVO_PTEGIDX_CLR(pvo) \ 179 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 180#define PVO_PTEGIDX_SET(pvo, i) \ 181 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 182 183#define PMAP_PVO_CHECK(pvo) 184 185struct ofw_map { 186 vm_offset_t om_va; 187 vm_size_t om_len; 188 vm_offset_t om_pa; 189 u_int om_mode; 190}; 191 192int pmap_bootstrapped = 0; 193 194/* 195 * Virtual and physical address of message buffer. 196 */ 197struct msgbuf *msgbufp; 198vm_offset_t msgbuf_phys; 199 200int pmap_pagedaemon_waken; 201 202/* 203 * Map of physical memory regions. 204 */ 205vm_offset_t phys_avail[128]; 206u_int phys_avail_count; 207static struct mem_region *regions; 208static struct mem_region *pregions; 209int regions_sz, pregions_sz; 210static struct ofw_map *translations; 211 212/* 213 * First and last available kernel virtual addresses. 214 */ 215vm_offset_t virtual_avail; 216vm_offset_t virtual_end; 217vm_offset_t kernel_vm_end; 218 219/* 220 * Kernel pmap. 221 */ 222struct pmap kernel_pmap_store; 223extern struct pmap ofw_pmap; 224 225/* 226 * Lock for the pteg and pvo tables. 227 */ 228struct mtx pmap_table_mutex; 229 230/* 231 * PTEG data. 232 */ 233static struct pteg *pmap_pteg_table; 234u_int pmap_pteg_count; 235u_int pmap_pteg_mask; 236 237/* 238 * PVO data. 239 */ 240struct pvo_head *pmap_pvo_table; /* pvo entries by pteg index */ 241struct pvo_head pmap_pvo_kunmanaged = 242 LIST_HEAD_INITIALIZER(pmap_pvo_kunmanaged); /* list of unmanaged pages */ 243struct pvo_head pmap_pvo_unmanaged = 244 LIST_HEAD_INITIALIZER(pmap_pvo_unmanaged); /* list of unmanaged pages */ 245 246uma_zone_t pmap_upvo_zone; /* zone for pvo entries for unmanaged pages */ 247uma_zone_t pmap_mpvo_zone; /* zone for pvo entries for managed pages */ 248 249#define BPVO_POOL_SIZE 32768 250static struct pvo_entry *pmap_bpvo_pool; 251static int pmap_bpvo_pool_index = 0; 252 253#define VSID_NBPW (sizeof(u_int32_t) * 8) 254static u_int pmap_vsid_bitmap[NPMAPS / VSID_NBPW]; 255 256static boolean_t pmap_initialized = FALSE; 257 258/* 259 * Statistics. 260 */ 261u_int pmap_pte_valid = 0; 262u_int pmap_pte_overflow = 0; 263u_int pmap_pte_replacements = 0; 264u_int pmap_pvo_entries = 0; 265u_int pmap_pvo_enter_calls = 0; 266u_int pmap_pvo_remove_calls = 0; 267u_int pmap_pte_spills = 0; 268SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_valid, CTLFLAG_RD, &pmap_pte_valid, 269 0, ""); 270SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_overflow, CTLFLAG_RD, 271 &pmap_pte_overflow, 0, ""); 272SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_replacements, CTLFLAG_RD, 273 &pmap_pte_replacements, 0, ""); 274SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_entries, CTLFLAG_RD, &pmap_pvo_entries, 275 0, ""); 276SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_enter_calls, CTLFLAG_RD, 277 &pmap_pvo_enter_calls, 0, ""); 278SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_remove_calls, CTLFLAG_RD, 279 &pmap_pvo_remove_calls, 0, ""); 280SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_spills, CTLFLAG_RD, 281 &pmap_pte_spills, 0, ""); 282 283struct pvo_entry *pmap_pvo_zeropage; 284 285vm_offset_t pmap_rkva_start = VM_MIN_KERNEL_ADDRESS; 286u_int pmap_rkva_count = 4; 287 288/* 289 * Allocate physical memory for use in pmap_bootstrap. 290 */ 291static vm_offset_t pmap_bootstrap_alloc(vm_size_t, u_int); 292 293/* 294 * PTE calls. 295 */ 296static int pmap_pte_insert(u_int, struct pte *); 297 298/* 299 * PVO calls. 300 */ 301static int pmap_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 302 vm_offset_t, vm_offset_t, u_int, int); 303static void pmap_pvo_remove(struct pvo_entry *, int); 304static struct pvo_entry *pmap_pvo_find_va(pmap_t, vm_offset_t, int *); 305static struct pte *pmap_pvo_to_pte(const struct pvo_entry *, int); 306 307/* 308 * Utility routines. 309 */ 310static struct pvo_entry *pmap_rkva_alloc(void); 311static void pmap_pa_map(struct pvo_entry *, vm_offset_t, 312 struct pte *, int *); 313static void pmap_pa_unmap(struct pvo_entry *, struct pte *, int *); 314static void pmap_syncicache(vm_offset_t, vm_size_t); 315static boolean_t pmap_query_bit(vm_page_t, int); 316static u_int pmap_clear_bit(vm_page_t, int, int *); 317static void tlbia(void); 318 319static __inline int 320va_to_sr(u_int *sr, vm_offset_t va) 321{ 322 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 323} 324 325static __inline u_int 326va_to_pteg(u_int sr, vm_offset_t addr) 327{ 328 u_int hash; 329 330 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 331 ADDR_PIDX_SHFT); 332 return (hash & pmap_pteg_mask); 333} 334 335static __inline struct pvo_head * 336pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 337{ 338 struct vm_page *pg; 339 340 pg = PHYS_TO_VM_PAGE(pa); 341 342 if (pg_p != NULL) 343 *pg_p = pg; 344 345 if (pg == NULL) 346 return (&pmap_pvo_unmanaged); 347 348 return (&pg->md.mdpg_pvoh); 349} 350 351static __inline struct pvo_head * 352vm_page_to_pvoh(vm_page_t m) 353{ 354 355 return (&m->md.mdpg_pvoh); 356} 357 358static __inline void 359pmap_attr_clear(vm_page_t m, int ptebit) 360{ 361 362 m->md.mdpg_attrs &= ~ptebit; 363} 364 365static __inline int 366pmap_attr_fetch(vm_page_t m) 367{ 368 369 return (m->md.mdpg_attrs); 370} 371 372static __inline void 373pmap_attr_save(vm_page_t m, int ptebit) 374{ 375 376 m->md.mdpg_attrs |= ptebit; 377} 378 379static __inline int 380pmap_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 381{ 382 if (pt->pte_hi == pvo_pt->pte_hi) 383 return (1); 384 385 return (0); 386} 387 388static __inline int 389pmap_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 390{ 391 return (pt->pte_hi & ~PTE_VALID) == 392 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 393 ((va >> ADDR_API_SHFT) & PTE_API) | which); 394} 395 396static __inline void 397pmap_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 398{ 399 /* 400 * Construct a PTE. Default to IMB initially. Valid bit only gets 401 * set when the real pte is set in memory. 402 * 403 * Note: Don't set the valid bit for correct operation of tlb update. 404 */ 405 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 406 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 407 pt->pte_lo = pte_lo; 408} 409 410static __inline void 411pmap_pte_synch(struct pte *pt, struct pte *pvo_pt) 412{ 413 414 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 415} 416 417static __inline void 418pmap_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 419{ 420 421 /* 422 * As shown in Section 7.6.3.2.3 423 */ 424 pt->pte_lo &= ~ptebit; 425 TLBIE(va); 426 EIEIO(); 427 TLBSYNC(); 428 SYNC(); 429} 430 431static __inline void 432pmap_pte_set(struct pte *pt, struct pte *pvo_pt) 433{ 434 435 pvo_pt->pte_hi |= PTE_VALID; 436 437 /* 438 * Update the PTE as defined in section 7.6.3.1. 439 * Note that the REF/CHG bits are from pvo_pt and thus should havce 440 * been saved so this routine can restore them (if desired). 441 */ 442 pt->pte_lo = pvo_pt->pte_lo; 443 EIEIO(); 444 pt->pte_hi = pvo_pt->pte_hi; 445 SYNC(); 446 pmap_pte_valid++; 447} 448 449static __inline void 450pmap_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 451{ 452 453 pvo_pt->pte_hi &= ~PTE_VALID; 454 455 /* 456 * Force the reg & chg bits back into the PTEs. 457 */ 458 SYNC(); 459 460 /* 461 * Invalidate the pte. 462 */ 463 pt->pte_hi &= ~PTE_VALID; 464 465 SYNC(); 466 TLBIE(va); 467 EIEIO(); 468 TLBSYNC(); 469 SYNC(); 470 471 /* 472 * Save the reg & chg bits. 473 */ 474 pmap_pte_synch(pt, pvo_pt); 475 pmap_pte_valid--; 476} 477 478static __inline void 479pmap_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 480{ 481 482 /* 483 * Invalidate the PTE 484 */ 485 pmap_pte_unset(pt, pvo_pt, va); 486 pmap_pte_set(pt, pvo_pt); 487} 488 489/* 490 * Quick sort callout for comparing memory regions. 491 */ 492static int mr_cmp(const void *a, const void *b); 493static int om_cmp(const void *a, const void *b); 494 495static int 496mr_cmp(const void *a, const void *b) 497{ 498 const struct mem_region *regiona; 499 const struct mem_region *regionb; 500 501 regiona = a; 502 regionb = b; 503 if (regiona->mr_start < regionb->mr_start) 504 return (-1); 505 else if (regiona->mr_start > regionb->mr_start) 506 return (1); 507 else 508 return (0); 509} 510 511static int 512om_cmp(const void *a, const void *b) 513{ 514 const struct ofw_map *mapa; 515 const struct ofw_map *mapb; 516 517 mapa = a; 518 mapb = b; 519 if (mapa->om_pa < mapb->om_pa) 520 return (-1); 521 else if (mapa->om_pa > mapb->om_pa) 522 return (1); 523 else 524 return (0); 525} 526 527static vm_size_t 528pmap_tunable_physmem(void) 529{ 530 char *cp; 531 vm_size_t retval; 532 533 retval = 0; 534 535 if ((cp = getenv("hw.physmem")) != NULL) { 536 u_int64_t allowmem, sanity; 537 char *ep; 538 539 sanity = allowmem = strtouq(cp, &ep, 0); 540 if ((ep != cp) && (*ep != 0)) { 541 switch(*ep) { 542 case 'g': 543 case 'G': 544 /* 545 * Can't have more than 4G of RAM 546 */ 547 if (allowmem > 4) { 548 printf("Invalid memory size '%s'\n", 549 cp); 550 return (0); 551 } 552 allowmem <<= 10; 553 case 'm': 554 case 'M': 555 allowmem <<= 10; 556 case 'k': 557 case 'K': 558 allowmem <<= 10; 559 break; 560 default: 561 allowmem = sanity = 0; 562 } 563 if (allowmem < sanity) 564 allowmem = 0; 565 } 566 if (allowmem == 0) 567 printf("Ignoring invalid memory size of '%s'\n", cp); 568 else 569 retval = allowmem; 570 freeenv(cp); 571 } 572 573 return (retval); 574} 575 576void 577pmap_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 578{ 579 ihandle_t mmui; 580 phandle_t chosen, mmu; 581 int sz; 582 int i, j; 583 int ofw_mappings; 584 vm_size_t size, physsz, hwphyssz; 585 vm_offset_t pa, va, off; 586 u_int batl, batu; 587 588 /* 589 * Set up BAT0 to map the lowest 256 MB area 590 */ 591 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 592 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 593 594 /* 595 * Map PCI memory space. 596 */ 597 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 598 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 599 600 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 601 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 602 603 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 604 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 605 606 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 607 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 608 609 /* 610 * Map obio devices. 611 */ 612 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 613 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 614 615 /* 616 * Use an IBAT and a DBAT to map the bottom segment of memory 617 * where we are. 618 */ 619 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 620 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 621 __asm ("mtibatu 0,%0; mtibatl 0,%1; isync; \n" 622 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 623 :: "r"(batu), "r"(batl)); 624 625#if 0 626 /* map frame buffer */ 627 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 628 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 629 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 630 :: "r"(batu), "r"(batl)); 631#endif 632 633#if 1 634 /* map pci space */ 635 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 636 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 637 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 638 :: "r"(batu), "r"(batl)); 639#endif 640 641 /* 642 * Set the start and end of kva. 643 */ 644 virtual_avail = VM_MIN_KERNEL_ADDRESS; 645 virtual_end = VM_MAX_KERNEL_ADDRESS; 646 647 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 648 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 649 650 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 651 for (i = 0; i < pregions_sz; i++) { 652 vm_offset_t pa; 653 vm_offset_t end; 654 655 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 656 pregions[i].mr_start, 657 pregions[i].mr_start + pregions[i].mr_size, 658 pregions[i].mr_size); 659 /* 660 * Install entries into the BAT table to allow all 661 * of physmem to be convered by on-demand BAT entries. 662 * The loop will sometimes set the same battable element 663 * twice, but that's fine since they won't be used for 664 * a while yet. 665 */ 666 pa = pregions[i].mr_start & 0xf0000000; 667 end = pregions[i].mr_start + pregions[i].mr_size; 668 do { 669 u_int n = pa >> ADDR_SR_SHFT; 670 671 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 672 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 673 pa += SEGMENT_LENGTH; 674 } while (pa < end); 675 } 676 677 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 678 panic("pmap_bootstrap: phys_avail too small"); 679 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 680 phys_avail_count = 0; 681 physsz = 0; 682 hwphyssz = pmap_tunable_physmem(); 683 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 684 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 685 regions[i].mr_start + regions[i].mr_size, 686 regions[i].mr_size); 687 if (hwphyssz != 0 && 688 (physsz + regions[i].mr_size) >= hwphyssz) { 689 if (physsz < hwphyssz) { 690 phys_avail[j] = regions[i].mr_start; 691 phys_avail[j + 1] = regions[i].mr_start + 692 hwphyssz - physsz; 693 physsz = hwphyssz; 694 phys_avail_count++; 695 } 696 break; 697 } 698 phys_avail[j] = regions[i].mr_start; 699 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 700 phys_avail_count++; 701 physsz += regions[i].mr_size; 702 } 703 physmem = btoc(physsz); 704 705 /* 706 * Allocate PTEG table. 707 */ 708#ifdef PTEGCOUNT 709 pmap_pteg_count = PTEGCOUNT; 710#else 711 pmap_pteg_count = 0x1000; 712 713 while (pmap_pteg_count < physmem) 714 pmap_pteg_count <<= 1; 715 716 pmap_pteg_count >>= 1; 717#endif /* PTEGCOUNT */ 718 719 size = pmap_pteg_count * sizeof(struct pteg); 720 CTR2(KTR_PMAP, "pmap_bootstrap: %d PTEGs, %d bytes", pmap_pteg_count, 721 size); 722 pmap_pteg_table = (struct pteg *)pmap_bootstrap_alloc(size, size); 723 CTR1(KTR_PMAP, "pmap_bootstrap: PTEG table at %p", pmap_pteg_table); 724 bzero((void *)pmap_pteg_table, pmap_pteg_count * sizeof(struct pteg)); 725 pmap_pteg_mask = pmap_pteg_count - 1; 726 727 /* 728 * Allocate pv/overflow lists. 729 */ 730 size = sizeof(struct pvo_head) * pmap_pteg_count; 731 pmap_pvo_table = (struct pvo_head *)pmap_bootstrap_alloc(size, 732 PAGE_SIZE); 733 CTR1(KTR_PMAP, "pmap_bootstrap: PVO table at %p", pmap_pvo_table); 734 for (i = 0; i < pmap_pteg_count; i++) 735 LIST_INIT(&pmap_pvo_table[i]); 736 737 /* 738 * Initialize the lock that synchronizes access to the pteg and pvo 739 * tables. 740 */ 741 mtx_init(&pmap_table_mutex, "pmap table", NULL, MTX_DEF); 742 743 /* 744 * Allocate the message buffer. 745 */ 746 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE, 0); 747 748 /* 749 * Initialise the unmanaged pvo pool. 750 */ 751 pmap_bpvo_pool = (struct pvo_entry *)pmap_bootstrap_alloc( 752 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 753 pmap_bpvo_pool_index = 0; 754 755 /* 756 * Make sure kernel vsid is allocated as well as VSID 0. 757 */ 758 pmap_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 759 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 760 pmap_vsid_bitmap[0] |= 1; 761 762 /* 763 * Set up the Open Firmware pmap and add it's mappings. 764 */ 765 pmap_pinit(&ofw_pmap); 766 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 767 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 768 if ((chosen = OF_finddevice("/chosen")) == -1) 769 panic("pmap_bootstrap: can't find /chosen"); 770 OF_getprop(chosen, "mmu", &mmui, 4); 771 if ((mmu = OF_instance_to_package(mmui)) == -1) 772 panic("pmap_bootstrap: can't get mmu package"); 773 if ((sz = OF_getproplen(mmu, "translations")) == -1) 774 panic("pmap_bootstrap: can't get ofw translation count"); 775 translations = NULL; 776 for (i = 0; phys_avail[i] != 0; i += 2) { 777 if (phys_avail[i + 1] >= sz) { 778 translations = (struct ofw_map *)phys_avail[i]; 779 break; 780 } 781 } 782 if (translations == NULL) 783 panic("pmap_bootstrap: no space to copy translations"); 784 bzero(translations, sz); 785 if (OF_getprop(mmu, "translations", translations, sz) == -1) 786 panic("pmap_bootstrap: can't get ofw translations"); 787 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 788 sz /= sizeof(*translations); 789 qsort(translations, sz, sizeof (*translations), om_cmp); 790 for (i = 0, ofw_mappings = 0; i < sz; i++) { 791 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 792 translations[i].om_pa, translations[i].om_va, 793 translations[i].om_len); 794 795 /* 796 * If the mapping is 1:1, let the RAM and device on-demand 797 * BAT tables take care of the translation. 798 */ 799 if (translations[i].om_va == translations[i].om_pa) 800 continue; 801 802 /* Enter the pages */ 803 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 804 struct vm_page m; 805 806 m.phys_addr = translations[i].om_pa + off; 807 pmap_enter(&ofw_pmap, translations[i].om_va + off, &m, 808 VM_PROT_ALL, 1); 809 ofw_mappings++; 810 } 811 } 812#ifdef SMP 813 TLBSYNC(); 814#endif 815 816 /* 817 * Initialize the kernel pmap (which is statically allocated). 818 */ 819 PMAP_LOCK_INIT(kernel_pmap); 820 for (i = 0; i < 16; i++) { 821 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 822 } 823 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 824 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 825 kernel_pmap->pm_active = ~0; 826 827 /* 828 * Allocate a kernel stack with a guard page for thread0 and map it 829 * into the kernel page map. 830 */ 831 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 832 kstack0_phys = pa; 833 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 834 CTR2(KTR_PMAP, "pmap_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 835 kstack0); 836 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 837 for (i = 0; i < KSTACK_PAGES; i++) { 838 pa = kstack0_phys + i * PAGE_SIZE; 839 va = kstack0 + i * PAGE_SIZE; 840 pmap_kenter(va, pa); 841 TLBIE(va); 842 } 843 844 /* 845 * Calculate the last available physical address. 846 */ 847 for (i = 0; phys_avail[i + 2] != 0; i += 2) 848 ; 849 Maxmem = powerpc_btop(phys_avail[i + 1]); 850 851 /* 852 * Allocate virtual address space for the message buffer. 853 */ 854 msgbufp = (struct msgbuf *)virtual_avail; 855 virtual_avail += round_page(MSGBUF_SIZE); 856 857 /* 858 * Initialize hardware. 859 */ 860 for (i = 0; i < 16; i++) { 861 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 862 } 863 __asm __volatile ("mtsr %0,%1" 864 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 865 __asm __volatile ("mtsr %0,%1" 866 :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 867 __asm __volatile ("sync; mtsdr1 %0; isync" 868 :: "r"((u_int)pmap_pteg_table | (pmap_pteg_mask >> 10))); 869 tlbia(); 870 871 pmap_bootstrapped++; 872} 873 874/* 875 * Activate a user pmap. The pmap must be activated before it's address 876 * space can be accessed in any way. 877 */ 878void 879pmap_activate(struct thread *td) 880{ 881 pmap_t pm, pmr; 882 883 /* 884 * Load all the data we need up front to encourage the compiler to 885 * not issue any loads while we have interrupts disabled below. 886 */ 887 pm = &td->td_proc->p_vmspace->vm_pmap; 888 889 if ((pmr = (pmap_t)pmap_kextract((vm_offset_t)pm)) == NULL) 890 pmr = pm; 891 892 pm->pm_active |= PCPU_GET(cpumask); 893 PCPU_SET(curpmap, pmr); 894} 895 896void 897pmap_deactivate(struct thread *td) 898{ 899 pmap_t pm; 900 901 pm = &td->td_proc->p_vmspace->vm_pmap; 902 pm->pm_active &= ~(PCPU_GET(cpumask)); 903 PCPU_SET(curpmap, NULL); 904} 905 906vm_offset_t 907pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 908{ 909 910 return (va); 911} 912 913void 914pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 915{ 916 struct pvo_entry *pvo; 917 918 PMAP_LOCK(pm); 919 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 920 921 if (pvo != NULL) { 922 if (wired) { 923 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 924 pm->pm_stats.wired_count++; 925 pvo->pvo_vaddr |= PVO_WIRED; 926 } else { 927 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 928 pm->pm_stats.wired_count--; 929 pvo->pvo_vaddr &= ~PVO_WIRED; 930 } 931 } 932 PMAP_UNLOCK(pm); 933} 934 935void 936pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 937 vm_size_t len, vm_offset_t src_addr) 938{ 939 940 /* 941 * This is not needed as it's mainly an optimisation. 942 * It may want to be implemented later though. 943 */ 944} 945 946void 947pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 948{ 949 vm_offset_t dst; 950 vm_offset_t src; 951 952 dst = VM_PAGE_TO_PHYS(mdst); 953 src = VM_PAGE_TO_PHYS(msrc); 954 955 kcopy((void *)src, (void *)dst, PAGE_SIZE); 956} 957 958/* 959 * Zero a page of physical memory by temporarily mapping it into the tlb. 960 */ 961void 962pmap_zero_page(vm_page_t m) 963{ 964 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 965 caddr_t va; 966 967 if (pa < SEGMENT_LENGTH) { 968 va = (caddr_t) pa; 969 } else if (pmap_initialized) { 970 if (pmap_pvo_zeropage == NULL) 971 pmap_pvo_zeropage = pmap_rkva_alloc(); 972 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 973 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 974 } else { 975 panic("pmap_zero_page: can't zero pa %#x", pa); 976 } 977 978 bzero(va, PAGE_SIZE); 979 980 if (pa >= SEGMENT_LENGTH) 981 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 982} 983 984void 985pmap_zero_page_area(vm_page_t m, int off, int size) 986{ 987 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 988 caddr_t va; 989 990 if (pa < SEGMENT_LENGTH) { 991 va = (caddr_t) pa; 992 } else if (pmap_initialized) { 993 if (pmap_pvo_zeropage == NULL) 994 pmap_pvo_zeropage = pmap_rkva_alloc(); 995 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 996 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 997 } else { 998 panic("pmap_zero_page: can't zero pa %#x", pa); 999 } 1000 1001 bzero(va + off, size); 1002 1003 if (pa >= SEGMENT_LENGTH) 1004 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 1005} 1006 1007void 1008pmap_zero_page_idle(vm_page_t m) 1009{ 1010 1011 /* XXX this is called outside of Giant, is pmap_zero_page safe? */ 1012 /* XXX maybe have a dedicated mapping for this to avoid the problem? */ 1013 mtx_lock(&Giant); 1014 pmap_zero_page(m); 1015 mtx_unlock(&Giant); 1016} 1017 1018/* 1019 * Map the given physical page at the specified virtual address in the 1020 * target pmap with the protection requested. If specified the page 1021 * will be wired down. 1022 */ 1023void 1024pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1025 boolean_t wired) 1026{ 1027 struct pvo_head *pvo_head; 1028 uma_zone_t zone; 1029 vm_page_t pg; 1030 u_int pte_lo, pvo_flags, was_exec, i; 1031 int error; 1032 1033 if (!pmap_initialized) { 1034 pvo_head = &pmap_pvo_kunmanaged; 1035 zone = pmap_upvo_zone; 1036 pvo_flags = 0; 1037 pg = NULL; 1038 was_exec = PTE_EXEC; 1039 } else { 1040 pvo_head = vm_page_to_pvoh(m); 1041 pg = m; 1042 zone = pmap_mpvo_zone; 1043 pvo_flags = PVO_MANAGED; 1044 was_exec = 0; 1045 } 1046 if (pmap_bootstrapped) 1047 vm_page_lock_queues(); 1048 PMAP_LOCK(pmap); 1049 1050 /* XXX change the pvo head for fake pages */ 1051 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) 1052 pvo_head = &pmap_pvo_kunmanaged; 1053 1054 /* 1055 * If this is a managed page, and it's the first reference to the page, 1056 * clear the execness of the page. Otherwise fetch the execness. 1057 */ 1058 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1059 if (LIST_EMPTY(pvo_head)) { 1060 pmap_attr_clear(pg, PTE_EXEC); 1061 } else { 1062 was_exec = pmap_attr_fetch(pg) & PTE_EXEC; 1063 } 1064 } 1065 1066 /* 1067 * Assume the page is cache inhibited and access is guarded unless 1068 * it's in our available memory array. 1069 */ 1070 pte_lo = PTE_I | PTE_G; 1071 for (i = 0; i < pregions_sz; i++) { 1072 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 1073 (VM_PAGE_TO_PHYS(m) < 1074 (pregions[i].mr_start + pregions[i].mr_size))) { 1075 pte_lo &= ~(PTE_I | PTE_G); 1076 break; 1077 } 1078 } 1079 1080 if (prot & VM_PROT_WRITE) 1081 pte_lo |= PTE_BW; 1082 else 1083 pte_lo |= PTE_BR; 1084 1085 if (prot & VM_PROT_EXECUTE) 1086 pvo_flags |= PVO_EXECUTABLE; 1087 1088 if (wired) 1089 pvo_flags |= PVO_WIRED; 1090 1091 if ((m->flags & PG_FICTITIOUS) != 0) 1092 pvo_flags |= PVO_FAKE; 1093 1094 error = pmap_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1095 pte_lo, pvo_flags); 1096 1097 /* 1098 * Flush the real page from the instruction cache if this page is 1099 * mapped executable and cacheable and was not previously mapped (or 1100 * was not mapped executable). 1101 */ 1102 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1103 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1104 /* 1105 * Flush the real memory from the cache. 1106 */ 1107 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1108 if (pg != NULL) 1109 pmap_attr_save(pg, PTE_EXEC); 1110 } 1111 if (pmap_bootstrapped) 1112 vm_page_unlock_queues(); 1113 1114 /* XXX syncicache always until problems are sorted */ 1115 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1116 PMAP_UNLOCK(pmap); 1117} 1118 1119vm_page_t 1120pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_page_t mpte) 1121{ 1122 1123 vm_page_busy(m); 1124 vm_page_unlock_queues(); 1125 VM_OBJECT_UNLOCK(m->object); 1126 mtx_lock(&Giant); 1127 pmap_enter(pm, va, m, VM_PROT_READ | VM_PROT_EXECUTE, FALSE); 1128 mtx_unlock(&Giant); 1129 VM_OBJECT_LOCK(m->object); 1130 vm_page_lock_queues(); 1131 vm_page_wakeup(m); 1132 return (NULL); 1133} 1134 1135vm_paddr_t 1136pmap_extract(pmap_t pm, vm_offset_t va) 1137{ 1138 struct pvo_entry *pvo; 1139 vm_paddr_t pa; 1140 1141 PMAP_LOCK(pm); 1142 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1143 if (pvo == NULL) 1144 pa = 0; 1145 else 1146 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1147 PMAP_UNLOCK(pm); 1148 return (pa); 1149} 1150 1151/* 1152 * Atomically extract and hold the physical page with the given 1153 * pmap and virtual address pair if that mapping permits the given 1154 * protection. 1155 */ 1156vm_page_t 1157pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1158{ 1159 struct pvo_entry *pvo; 1160 vm_page_t m; 1161 1162 m = NULL; 1163 mtx_lock(&Giant); 1164 vm_page_lock_queues(); 1165 PMAP_LOCK(pmap); 1166 pvo = pmap_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1167 if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) && 1168 ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW || 1169 (prot & VM_PROT_WRITE) == 0)) { 1170 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1171 vm_page_hold(m); 1172 } 1173 vm_page_unlock_queues(); 1174 PMAP_UNLOCK(pmap); 1175 mtx_unlock(&Giant); 1176 return (m); 1177} 1178 1179/* 1180 * Grow the number of kernel page table entries. Unneeded. 1181 */ 1182void 1183pmap_growkernel(vm_offset_t addr) 1184{ 1185} 1186 1187void 1188pmap_init(void) 1189{ 1190 1191 CTR0(KTR_PMAP, "pmap_init"); 1192 1193 pmap_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1194 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1195 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1196 pmap_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1197 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1198 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1199 pmap_initialized = TRUE; 1200} 1201 1202void 1203pmap_init2(void) 1204{ 1205 1206 CTR0(KTR_PMAP, "pmap_init2"); 1207} 1208 1209boolean_t 1210pmap_is_modified(vm_page_t m) 1211{ 1212 1213 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1214 return (FALSE); 1215 1216 return (pmap_query_bit(m, PTE_CHG)); 1217} 1218 1219/* 1220 * pmap_is_prefaultable: 1221 * 1222 * Return whether or not the specified virtual address is elgible 1223 * for prefault. 1224 */ 1225boolean_t 1226pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 1227{ 1228 1229 return (FALSE); 1230} 1231 1232void 1233pmap_clear_reference(vm_page_t m) 1234{ 1235 1236 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1237 return; 1238 pmap_clear_bit(m, PTE_REF, NULL); 1239} 1240 1241void 1242pmap_clear_modify(vm_page_t m) 1243{ 1244 1245 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1246 return; 1247 pmap_clear_bit(m, PTE_CHG, NULL); 1248} 1249 1250/* 1251 * pmap_ts_referenced: 1252 * 1253 * Return a count of reference bits for a page, clearing those bits. 1254 * It is not necessary for every reference bit to be cleared, but it 1255 * is necessary that 0 only be returned when there are truly no 1256 * reference bits set. 1257 * 1258 * XXX: The exact number of bits to check and clear is a matter that 1259 * should be tested and standardized at some point in the future for 1260 * optimal aging of shared pages. 1261 */ 1262int 1263pmap_ts_referenced(vm_page_t m) 1264{ 1265 int count; 1266 1267 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1268 return (0); 1269 1270 count = pmap_clear_bit(m, PTE_REF, NULL); 1271 1272 return (count); 1273} 1274 1275/* 1276 * Map a wired page into kernel virtual address space. 1277 */ 1278void 1279pmap_kenter(vm_offset_t va, vm_offset_t pa) 1280{ 1281 u_int pte_lo; 1282 int error; 1283 int i; 1284 1285#if 0 1286 if (va < VM_MIN_KERNEL_ADDRESS) 1287 panic("pmap_kenter: attempt to enter non-kernel address %#x", 1288 va); 1289#endif 1290 1291 pte_lo = PTE_I | PTE_G; 1292 for (i = 0; i < pregions_sz; i++) { 1293 if ((pa >= pregions[i].mr_start) && 1294 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1295 pte_lo &= ~(PTE_I | PTE_G); 1296 break; 1297 } 1298 } 1299 1300 PMAP_LOCK(kernel_pmap); 1301 error = pmap_pvo_enter(kernel_pmap, pmap_upvo_zone, 1302 &pmap_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1303 1304 if (error != 0 && error != ENOENT) 1305 panic("pmap_kenter: failed to enter va %#x pa %#x: %d", va, 1306 pa, error); 1307 1308 /* 1309 * Flush the real memory from the instruction cache. 1310 */ 1311 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1312 pmap_syncicache(pa, PAGE_SIZE); 1313 } 1314 PMAP_UNLOCK(kernel_pmap); 1315} 1316 1317/* 1318 * Extract the physical page address associated with the given kernel virtual 1319 * address. 1320 */ 1321vm_offset_t 1322pmap_kextract(vm_offset_t va) 1323{ 1324 struct pvo_entry *pvo; 1325 vm_paddr_t pa; 1326 1327#ifdef UMA_MD_SMALL_ALLOC 1328 /* 1329 * Allow direct mappings 1330 */ 1331 if (va < VM_MIN_KERNEL_ADDRESS) { 1332 return (va); 1333 } 1334#endif 1335 1336 PMAP_LOCK(kernel_pmap); 1337 pvo = pmap_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1338 KASSERT(pvo != NULL, ("pmap_kextract: no addr found")); 1339 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1340 PMAP_UNLOCK(kernel_pmap); 1341 return (pa); 1342} 1343 1344/* 1345 * Remove a wired page from kernel virtual address space. 1346 */ 1347void 1348pmap_kremove(vm_offset_t va) 1349{ 1350 1351 pmap_remove(kernel_pmap, va, va + PAGE_SIZE); 1352} 1353 1354/* 1355 * Map a range of physical addresses into kernel virtual address space. 1356 * 1357 * The value passed in *virt is a suggested virtual address for the mapping. 1358 * Architectures which can support a direct-mapped physical to virtual region 1359 * can return the appropriate address within that region, leaving '*virt' 1360 * unchanged. We cannot and therefore do not; *virt is updated with the 1361 * first usable address after the mapped region. 1362 */ 1363vm_offset_t 1364pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 1365{ 1366 vm_offset_t sva, va; 1367 1368 sva = *virt; 1369 va = sva; 1370 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1371 pmap_kenter(va, pa_start); 1372 *virt = va; 1373 return (sva); 1374} 1375 1376int 1377pmap_mincore(pmap_t pmap, vm_offset_t addr) 1378{ 1379 TODO; 1380 return (0); 1381} 1382 1383void 1384pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1385 vm_pindex_t pindex, vm_size_t size) 1386{ 1387 1388 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 1389 KASSERT(object->type == OBJT_DEVICE, 1390 ("pmap_object_init_pt: non-device object")); 1391 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1392 ("pmap_object_init_pt: non current pmap")); 1393} 1394 1395/* 1396 * Lower the permission for all mappings to a given page. 1397 */ 1398void 1399pmap_page_protect(vm_page_t m, vm_prot_t prot) 1400{ 1401 struct pvo_head *pvo_head; 1402 struct pvo_entry *pvo, *next_pvo; 1403 struct pte *pt; 1404 pmap_t pmap; 1405 1406 /* 1407 * Since the routine only downgrades protection, if the 1408 * maximal protection is desired, there isn't any change 1409 * to be made. 1410 */ 1411 if ((prot & (VM_PROT_READ|VM_PROT_WRITE)) == 1412 (VM_PROT_READ|VM_PROT_WRITE)) 1413 return; 1414 1415 pvo_head = vm_page_to_pvoh(m); 1416 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1417 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1418 PMAP_PVO_CHECK(pvo); /* sanity check */ 1419 pmap = pvo->pvo_pmap; 1420 PMAP_LOCK(pmap); 1421 1422 /* 1423 * Downgrading to no mapping at all, we just remove the entry. 1424 */ 1425 if ((prot & VM_PROT_READ) == 0) { 1426 pmap_pvo_remove(pvo, -1); 1427 PMAP_UNLOCK(pmap); 1428 continue; 1429 } 1430 1431 /* 1432 * If EXEC permission is being revoked, just clear the flag 1433 * in the PVO. 1434 */ 1435 if ((prot & VM_PROT_EXECUTE) == 0) 1436 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1437 1438 /* 1439 * If this entry is already RO, don't diddle with the page 1440 * table. 1441 */ 1442 if ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_BR) { 1443 PMAP_UNLOCK(pmap); 1444 PMAP_PVO_CHECK(pvo); 1445 continue; 1446 } 1447 1448 /* 1449 * Grab the PTE before we diddle the bits so pvo_to_pte can 1450 * verify the pte contents are as expected. 1451 */ 1452 pt = pmap_pvo_to_pte(pvo, -1); 1453 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1454 pvo->pvo_pte.pte_lo |= PTE_BR; 1455 if (pt != NULL) 1456 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1457 PMAP_UNLOCK(pmap); 1458 PMAP_PVO_CHECK(pvo); /* sanity check */ 1459 } 1460 1461 /* 1462 * Downgrading from writeable: clear the VM page flag 1463 */ 1464 if ((prot & VM_PROT_WRITE) != VM_PROT_WRITE) 1465 vm_page_flag_clear(m, PG_WRITEABLE); 1466} 1467 1468/* 1469 * Returns true if the pmap's pv is one of the first 1470 * 16 pvs linked to from this page. This count may 1471 * be changed upwards or downwards in the future; it 1472 * is only necessary that true be returned for a small 1473 * subset of pmaps for proper page aging. 1474 */ 1475boolean_t 1476pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 1477{ 1478 int loops; 1479 struct pvo_entry *pvo; 1480 1481 if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) 1482 return FALSE; 1483 1484 loops = 0; 1485 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1486 if (pvo->pvo_pmap == pmap) 1487 return (TRUE); 1488 if (++loops >= 16) 1489 break; 1490 } 1491 1492 return (FALSE); 1493} 1494 1495static u_int pmap_vsidcontext; 1496 1497void 1498pmap_pinit(pmap_t pmap) 1499{ 1500 int i, mask; 1501 u_int entropy; 1502 1503 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("pmap_pinit: virt pmap")); 1504 PMAP_LOCK_INIT(pmap); 1505 1506 entropy = 0; 1507 __asm __volatile("mftb %0" : "=r"(entropy)); 1508 1509 /* 1510 * Allocate some segment registers for this pmap. 1511 */ 1512 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1513 u_int hash, n; 1514 1515 /* 1516 * Create a new value by mutiplying by a prime and adding in 1517 * entropy from the timebase register. This is to make the 1518 * VSID more random so that the PT hash function collides 1519 * less often. (Note that the prime casues gcc to do shifts 1520 * instead of a multiply.) 1521 */ 1522 pmap_vsidcontext = (pmap_vsidcontext * 0x1105) + entropy; 1523 hash = pmap_vsidcontext & (NPMAPS - 1); 1524 if (hash == 0) /* 0 is special, avoid it */ 1525 continue; 1526 n = hash >> 5; 1527 mask = 1 << (hash & (VSID_NBPW - 1)); 1528 hash = (pmap_vsidcontext & 0xfffff); 1529 if (pmap_vsid_bitmap[n] & mask) { /* collision? */ 1530 /* anything free in this bucket? */ 1531 if (pmap_vsid_bitmap[n] == 0xffffffff) { 1532 entropy = (pmap_vsidcontext >> 20); 1533 continue; 1534 } 1535 i = ffs(~pmap_vsid_bitmap[i]) - 1; 1536 mask = 1 << i; 1537 hash &= 0xfffff & ~(VSID_NBPW - 1); 1538 hash |= i; 1539 } 1540 pmap_vsid_bitmap[n] |= mask; 1541 for (i = 0; i < 16; i++) 1542 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1543 return; 1544 } 1545 1546 panic("pmap_pinit: out of segments"); 1547} 1548 1549/* 1550 * Initialize the pmap associated with process 0. 1551 */ 1552void 1553pmap_pinit0(pmap_t pm) 1554{ 1555 1556 pmap_pinit(pm); 1557 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1558} 1559 1560/* 1561 * Set the physical protection on the specified range of this map as requested. 1562 */ 1563void 1564pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1565{ 1566 struct pvo_entry *pvo; 1567 struct pte *pt; 1568 int pteidx; 1569 1570 CTR4(KTR_PMAP, "pmap_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1571 eva, prot); 1572 1573 1574 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1575 ("pmap_protect: non current pmap")); 1576 1577 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1578 mtx_lock(&Giant); 1579 pmap_remove(pm, sva, eva); 1580 mtx_unlock(&Giant); 1581 return; 1582 } 1583 1584 mtx_lock(&Giant); 1585 vm_page_lock_queues(); 1586 PMAP_LOCK(pm); 1587 for (; sva < eva; sva += PAGE_SIZE) { 1588 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1589 if (pvo == NULL) 1590 continue; 1591 1592 if ((prot & VM_PROT_EXECUTE) == 0) 1593 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1594 1595 /* 1596 * Grab the PTE pointer before we diddle with the cached PTE 1597 * copy. 1598 */ 1599 pt = pmap_pvo_to_pte(pvo, pteidx); 1600 /* 1601 * Change the protection of the page. 1602 */ 1603 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1604 pvo->pvo_pte.pte_lo |= PTE_BR; 1605 1606 /* 1607 * If the PVO is in the page table, update that pte as well. 1608 */ 1609 if (pt != NULL) 1610 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1611 } 1612 vm_page_unlock_queues(); 1613 PMAP_UNLOCK(pm); 1614 mtx_unlock(&Giant); 1615} 1616 1617/* 1618 * Map a list of wired pages into kernel virtual address space. This is 1619 * intended for temporary mappings which do not need page modification or 1620 * references recorded. Existing mappings in the region are overwritten. 1621 */ 1622void 1623pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 1624{ 1625 vm_offset_t va; 1626 1627 va = sva; 1628 while (count-- > 0) { 1629 pmap_kenter(va, VM_PAGE_TO_PHYS(*m)); 1630 va += PAGE_SIZE; 1631 m++; 1632 } 1633} 1634 1635/* 1636 * Remove page mappings from kernel virtual address space. Intended for 1637 * temporary mappings entered by pmap_qenter. 1638 */ 1639void 1640pmap_qremove(vm_offset_t sva, int count) 1641{ 1642 vm_offset_t va; 1643 1644 va = sva; 1645 while (count-- > 0) { 1646 pmap_kremove(va); 1647 va += PAGE_SIZE; 1648 } 1649} 1650 1651void 1652pmap_release(pmap_t pmap) 1653{ 1654 int idx, mask; 1655 1656 /* 1657 * Free segment register's VSID 1658 */ 1659 if (pmap->pm_sr[0] == 0) 1660 panic("pmap_release"); 1661 1662 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1663 mask = 1 << (idx % VSID_NBPW); 1664 idx /= VSID_NBPW; 1665 pmap_vsid_bitmap[idx] &= ~mask; 1666 PMAP_LOCK_DESTROY(pmap); 1667} 1668 1669/* 1670 * Remove the given range of addresses from the specified map. 1671 */ 1672void 1673pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1674{ 1675 struct pvo_entry *pvo; 1676 int pteidx; 1677 1678 vm_page_lock_queues(); 1679 PMAP_LOCK(pm); 1680 for (; sva < eva; sva += PAGE_SIZE) { 1681 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1682 if (pvo != NULL) { 1683 pmap_pvo_remove(pvo, pteidx); 1684 } 1685 } 1686 PMAP_UNLOCK(pm); 1687 vm_page_unlock_queues(); 1688} 1689 1690/* 1691 * Remove physical page from all pmaps in which it resides. pmap_pvo_remove() 1692 * will reflect changes in pte's back to the vm_page. 1693 */ 1694void 1695pmap_remove_all(vm_page_t m) 1696{ 1697 struct pvo_head *pvo_head; 1698 struct pvo_entry *pvo, *next_pvo; 1699 pmap_t pmap; 1700 1701 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1702 1703 pvo_head = vm_page_to_pvoh(m); 1704 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1705 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1706 1707 PMAP_PVO_CHECK(pvo); /* sanity check */ 1708 pmap = pvo->pvo_pmap; 1709 PMAP_LOCK(pmap); 1710 pmap_pvo_remove(pvo, -1); 1711 PMAP_UNLOCK(pmap); 1712 } 1713 vm_page_flag_clear(m, PG_WRITEABLE); 1714} 1715 1716/* 1717 * Remove all pages from specified address space, this aids process exit 1718 * speeds. This is much faster than pmap_remove in the case of running down 1719 * an entire address space. Only works for the current pmap. 1720 */ 1721void 1722pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1723{ 1724} 1725 1726/* 1727 * Allocate a physical page of memory directly from the phys_avail map. 1728 * Can only be called from pmap_bootstrap before avail start and end are 1729 * calculated. 1730 */ 1731static vm_offset_t 1732pmap_bootstrap_alloc(vm_size_t size, u_int align) 1733{ 1734 vm_offset_t s, e; 1735 int i, j; 1736 1737 size = round_page(size); 1738 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1739 if (align != 0) 1740 s = (phys_avail[i] + align - 1) & ~(align - 1); 1741 else 1742 s = phys_avail[i]; 1743 e = s + size; 1744 1745 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1746 continue; 1747 1748 if (s == phys_avail[i]) { 1749 phys_avail[i] += size; 1750 } else if (e == phys_avail[i + 1]) { 1751 phys_avail[i + 1] -= size; 1752 } else { 1753 for (j = phys_avail_count * 2; j > i; j -= 2) { 1754 phys_avail[j] = phys_avail[j - 2]; 1755 phys_avail[j + 1] = phys_avail[j - 1]; 1756 } 1757 1758 phys_avail[i + 3] = phys_avail[i + 1]; 1759 phys_avail[i + 1] = s; 1760 phys_avail[i + 2] = e; 1761 phys_avail_count++; 1762 } 1763 1764 return (s); 1765 } 1766 panic("pmap_bootstrap_alloc: could not allocate memory"); 1767} 1768 1769/* 1770 * Return an unmapped pvo for a kernel virtual address. 1771 * Used by pmap functions that operate on physical pages. 1772 */ 1773static struct pvo_entry * 1774pmap_rkva_alloc(void) 1775{ 1776 struct pvo_entry *pvo; 1777 struct pte *pt; 1778 vm_offset_t kva; 1779 int pteidx; 1780 1781 if (pmap_rkva_count == 0) 1782 panic("pmap_rkva_alloc: no more reserved KVAs"); 1783 1784 kva = pmap_rkva_start + (PAGE_SIZE * --pmap_rkva_count); 1785 pmap_kenter(kva, 0); 1786 1787 pvo = pmap_pvo_find_va(kernel_pmap, kva, &pteidx); 1788 1789 if (pvo == NULL) 1790 panic("pmap_kva_alloc: pmap_pvo_find_va failed"); 1791 1792 pt = pmap_pvo_to_pte(pvo, pteidx); 1793 1794 if (pt == NULL) 1795 panic("pmap_kva_alloc: pmap_pvo_to_pte failed"); 1796 1797 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1798 PVO_PTEGIDX_CLR(pvo); 1799 1800 pmap_pte_overflow++; 1801 1802 return (pvo); 1803} 1804 1805static void 1806pmap_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1807 int *depth_p) 1808{ 1809 struct pte *pt; 1810 1811 /* 1812 * If this pvo already has a valid pte, we need to save it so it can 1813 * be restored later. We then just reload the new PTE over the old 1814 * slot. 1815 */ 1816 if (saved_pt != NULL) { 1817 pt = pmap_pvo_to_pte(pvo, -1); 1818 1819 if (pt != NULL) { 1820 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1821 PVO_PTEGIDX_CLR(pvo); 1822 pmap_pte_overflow++; 1823 } 1824 1825 *saved_pt = pvo->pvo_pte; 1826 1827 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1828 } 1829 1830 pvo->pvo_pte.pte_lo |= pa; 1831 1832 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1833 panic("pmap_pa_map: could not spill pvo %p", pvo); 1834 1835 if (depth_p != NULL) 1836 (*depth_p)++; 1837} 1838 1839static void 1840pmap_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1841{ 1842 struct pte *pt; 1843 1844 pt = pmap_pvo_to_pte(pvo, -1); 1845 1846 if (pt != NULL) { 1847 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1848 PVO_PTEGIDX_CLR(pvo); 1849 pmap_pte_overflow++; 1850 } 1851 1852 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1853 1854 /* 1855 * If there is a saved PTE and it's valid, restore it and return. 1856 */ 1857 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1858 if (depth_p != NULL && --(*depth_p) == 0) 1859 panic("pmap_pa_unmap: restoring but depth == 0"); 1860 1861 pvo->pvo_pte = *saved_pt; 1862 1863 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1864 panic("pmap_pa_unmap: could not spill pvo %p", pvo); 1865 } 1866} 1867 1868static void 1869pmap_syncicache(vm_offset_t pa, vm_size_t len) 1870{ 1871 __syncicache((void *)pa, len); 1872} 1873 1874static void 1875tlbia(void) 1876{ 1877 caddr_t i; 1878 1879 SYNC(); 1880 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1881 TLBIE(i); 1882 EIEIO(); 1883 } 1884 TLBSYNC(); 1885 SYNC(); 1886} 1887 1888static int 1889pmap_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1890 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1891{ 1892 struct pvo_entry *pvo; 1893 u_int sr; 1894 int first; 1895 u_int ptegidx; 1896 int i; 1897 int bootstrap; 1898 1899 pmap_pvo_enter_calls++; 1900 first = 0; 1901 bootstrap = 0; 1902 1903 /* 1904 * Compute the PTE Group index. 1905 */ 1906 va &= ~ADDR_POFF; 1907 sr = va_to_sr(pm->pm_sr, va); 1908 ptegidx = va_to_pteg(sr, va); 1909 1910 /* 1911 * Remove any existing mapping for this page. Reuse the pvo entry if 1912 * there is a mapping. 1913 */ 1914 mtx_lock(&pmap_table_mutex); 1915 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1916 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1917 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1918 (pvo->pvo_pte.pte_lo & PTE_PP) == 1919 (pte_lo & PTE_PP)) { 1920 mtx_unlock(&pmap_table_mutex); 1921 return (0); 1922 } 1923 pmap_pvo_remove(pvo, -1); 1924 break; 1925 } 1926 } 1927 1928 /* 1929 * If we aren't overwriting a mapping, try to allocate. 1930 */ 1931 if (pmap_initialized) { 1932 pvo = uma_zalloc(zone, M_NOWAIT); 1933 } else { 1934 if (pmap_bpvo_pool_index >= BPVO_POOL_SIZE) { 1935 panic("pmap_enter: bpvo pool exhausted, %d, %d, %d", 1936 pmap_bpvo_pool_index, BPVO_POOL_SIZE, 1937 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1938 } 1939 pvo = &pmap_bpvo_pool[pmap_bpvo_pool_index]; 1940 pmap_bpvo_pool_index++; 1941 bootstrap = 1; 1942 } 1943 1944 if (pvo == NULL) { 1945 mtx_unlock(&pmap_table_mutex); 1946 return (ENOMEM); 1947 } 1948 1949 pmap_pvo_entries++; 1950 pvo->pvo_vaddr = va; 1951 pvo->pvo_pmap = pm; 1952 LIST_INSERT_HEAD(&pmap_pvo_table[ptegidx], pvo, pvo_olink); 1953 pvo->pvo_vaddr &= ~ADDR_POFF; 1954 if (flags & VM_PROT_EXECUTE) 1955 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1956 if (flags & PVO_WIRED) 1957 pvo->pvo_vaddr |= PVO_WIRED; 1958 if (pvo_head != &pmap_pvo_kunmanaged) 1959 pvo->pvo_vaddr |= PVO_MANAGED; 1960 if (bootstrap) 1961 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1962 if (flags & PVO_FAKE) 1963 pvo->pvo_vaddr |= PVO_FAKE; 1964 1965 pmap_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1966 1967 /* 1968 * Remember if the list was empty and therefore will be the first 1969 * item. 1970 */ 1971 if (LIST_FIRST(pvo_head) == NULL) 1972 first = 1; 1973 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1974 1975 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1976 pm->pm_stats.wired_count++; 1977 pm->pm_stats.resident_count++; 1978 1979 /* 1980 * We hope this succeeds but it isn't required. 1981 */ 1982 i = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 1983 if (i >= 0) { 1984 PVO_PTEGIDX_SET(pvo, i); 1985 } else { 1986 panic("pmap_pvo_enter: overflow"); 1987 pmap_pte_overflow++; 1988 } 1989 mtx_unlock(&pmap_table_mutex); 1990 1991 return (first ? ENOENT : 0); 1992} 1993 1994static void 1995pmap_pvo_remove(struct pvo_entry *pvo, int pteidx) 1996{ 1997 struct pte *pt; 1998 1999 /* 2000 * If there is an active pte entry, we need to deactivate it (and 2001 * save the ref & cfg bits). 2002 */ 2003 pt = pmap_pvo_to_pte(pvo, pteidx); 2004 if (pt != NULL) { 2005 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 2006 PVO_PTEGIDX_CLR(pvo); 2007 } else { 2008 pmap_pte_overflow--; 2009 } 2010 2011 /* 2012 * Update our statistics. 2013 */ 2014 pvo->pvo_pmap->pm_stats.resident_count--; 2015 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 2016 pvo->pvo_pmap->pm_stats.wired_count--; 2017 2018 /* 2019 * Save the REF/CHG bits into their cache if the page is managed. 2020 */ 2021 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2022 struct vm_page *pg; 2023 2024 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 2025 if (pg != NULL) { 2026 pmap_attr_save(pg, pvo->pvo_pte.pte_lo & 2027 (PTE_REF | PTE_CHG)); 2028 } 2029 } 2030 2031 /* 2032 * Remove this PVO from the PV list. 2033 */ 2034 LIST_REMOVE(pvo, pvo_vlink); 2035 2036 /* 2037 * Remove this from the overflow list and return it to the pool 2038 * if we aren't going to reuse it. 2039 */ 2040 LIST_REMOVE(pvo, pvo_olink); 2041 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2042 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? pmap_mpvo_zone : 2043 pmap_upvo_zone, pvo); 2044 pmap_pvo_entries--; 2045 pmap_pvo_remove_calls++; 2046} 2047 2048static __inline int 2049pmap_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2050{ 2051 int pteidx; 2052 2053 /* 2054 * We can find the actual pte entry without searching by grabbing 2055 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2056 * noticing the HID bit. 2057 */ 2058 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2059 if (pvo->pvo_pte.pte_hi & PTE_HID) 2060 pteidx ^= pmap_pteg_mask * 8; 2061 2062 return (pteidx); 2063} 2064 2065static struct pvo_entry * 2066pmap_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2067{ 2068 struct pvo_entry *pvo; 2069 int ptegidx; 2070 u_int sr; 2071 2072 va &= ~ADDR_POFF; 2073 sr = va_to_sr(pm->pm_sr, va); 2074 ptegidx = va_to_pteg(sr, va); 2075 2076 mtx_lock(&pmap_table_mutex); 2077 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 2078 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2079 if (pteidx_p) 2080 *pteidx_p = pmap_pvo_pte_index(pvo, ptegidx); 2081 break; 2082 } 2083 } 2084 mtx_unlock(&pmap_table_mutex); 2085 2086 return (pvo); 2087} 2088 2089static struct pte * 2090pmap_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2091{ 2092 struct pte *pt; 2093 2094 /* 2095 * If we haven't been supplied the ptegidx, calculate it. 2096 */ 2097 if (pteidx == -1) { 2098 int ptegidx; 2099 u_int sr; 2100 2101 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2102 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2103 pteidx = pmap_pvo_pte_index(pvo, ptegidx); 2104 } 2105 2106 pt = &pmap_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2107 2108 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2109 panic("pmap_pvo_to_pte: pvo %p has valid pte in pvo but no " 2110 "valid pte index", pvo); 2111 } 2112 2113 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2114 panic("pmap_pvo_to_pte: pvo %p has valid pte index in pvo " 2115 "pvo but no valid pte", pvo); 2116 } 2117 2118 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2119 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 2120 panic("pmap_pvo_to_pte: pvo %p has valid pte in " 2121 "pmap_pteg_table %p but invalid in pvo", pvo, pt); 2122 } 2123 2124 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2125 != 0) { 2126 panic("pmap_pvo_to_pte: pvo %p pte does not match " 2127 "pte %p in pmap_pteg_table", pvo, pt); 2128 } 2129 2130 return (pt); 2131 } 2132 2133 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 2134 panic("pmap_pvo_to_pte: pvo %p has invalid pte %p in " 2135 "pmap_pteg_table but valid in pvo", pvo, pt); 2136 } 2137 2138 return (NULL); 2139} 2140 2141/* 2142 * XXX: THIS STUFF SHOULD BE IN pte.c? 2143 */ 2144int 2145pmap_pte_spill(vm_offset_t addr) 2146{ 2147 struct pvo_entry *source_pvo, *victim_pvo; 2148 struct pvo_entry *pvo; 2149 int ptegidx, i, j; 2150 u_int sr; 2151 struct pteg *pteg; 2152 struct pte *pt; 2153 2154 pmap_pte_spills++; 2155 2156 sr = mfsrin(addr); 2157 ptegidx = va_to_pteg(sr, addr); 2158 2159 /* 2160 * Have to substitute some entry. Use the primary hash for this. 2161 * Use low bits of timebase as random generator. 2162 */ 2163 pteg = &pmap_pteg_table[ptegidx]; 2164 mtx_lock(&pmap_table_mutex); 2165 __asm __volatile("mftb %0" : "=r"(i)); 2166 i &= 7; 2167 pt = &pteg->pt[i]; 2168 2169 source_pvo = NULL; 2170 victim_pvo = NULL; 2171 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 2172 /* 2173 * We need to find a pvo entry for this address. 2174 */ 2175 PMAP_PVO_CHECK(pvo); 2176 if (source_pvo == NULL && 2177 pmap_pte_match(&pvo->pvo_pte, sr, addr, 2178 pvo->pvo_pte.pte_hi & PTE_HID)) { 2179 /* 2180 * Now found an entry to be spilled into the pteg. 2181 * The PTE is now valid, so we know it's active. 2182 */ 2183 j = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 2184 2185 if (j >= 0) { 2186 PVO_PTEGIDX_SET(pvo, j); 2187 pmap_pte_overflow--; 2188 PMAP_PVO_CHECK(pvo); 2189 mtx_unlock(&pmap_table_mutex); 2190 return (1); 2191 } 2192 2193 source_pvo = pvo; 2194 2195 if (victim_pvo != NULL) 2196 break; 2197 } 2198 2199 /* 2200 * We also need the pvo entry of the victim we are replacing 2201 * so save the R & C bits of the PTE. 2202 */ 2203 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2204 pmap_pte_compare(pt, &pvo->pvo_pte)) { 2205 victim_pvo = pvo; 2206 if (source_pvo != NULL) 2207 break; 2208 } 2209 } 2210 2211 if (source_pvo == NULL) { 2212 mtx_unlock(&pmap_table_mutex); 2213 return (0); 2214 } 2215 2216 if (victim_pvo == NULL) { 2217 if ((pt->pte_hi & PTE_HID) == 0) 2218 panic("pmap_pte_spill: victim p-pte (%p) has no pvo" 2219 "entry", pt); 2220 2221 /* 2222 * If this is a secondary PTE, we need to search it's primary 2223 * pvo bucket for the matching PVO. 2224 */ 2225 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx ^ pmap_pteg_mask], 2226 pvo_olink) { 2227 PMAP_PVO_CHECK(pvo); 2228 /* 2229 * We also need the pvo entry of the victim we are 2230 * replacing so save the R & C bits of the PTE. 2231 */ 2232 if (pmap_pte_compare(pt, &pvo->pvo_pte)) { 2233 victim_pvo = pvo; 2234 break; 2235 } 2236 } 2237 2238 if (victim_pvo == NULL) 2239 panic("pmap_pte_spill: victim s-pte (%p) has no pvo" 2240 "entry", pt); 2241 } 2242 2243 /* 2244 * We are invalidating the TLB entry for the EA we are replacing even 2245 * though it's valid. If we don't, we lose any ref/chg bit changes 2246 * contained in the TLB entry. 2247 */ 2248 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2249 2250 pmap_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2251 pmap_pte_set(pt, &source_pvo->pvo_pte); 2252 2253 PVO_PTEGIDX_CLR(victim_pvo); 2254 PVO_PTEGIDX_SET(source_pvo, i); 2255 pmap_pte_replacements++; 2256 2257 PMAP_PVO_CHECK(victim_pvo); 2258 PMAP_PVO_CHECK(source_pvo); 2259 2260 mtx_unlock(&pmap_table_mutex); 2261 return (1); 2262} 2263 2264static int 2265pmap_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2266{ 2267 struct pte *pt; 2268 int i; 2269 2270 /* 2271 * First try primary hash. 2272 */ 2273 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2274 if ((pt->pte_hi & PTE_VALID) == 0) { 2275 pvo_pt->pte_hi &= ~PTE_HID; 2276 pmap_pte_set(pt, pvo_pt); 2277 return (i); 2278 } 2279 } 2280 2281 /* 2282 * Now try secondary hash. 2283 */ 2284 ptegidx ^= pmap_pteg_mask; 2285 ptegidx++; 2286 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2287 if ((pt->pte_hi & PTE_VALID) == 0) { 2288 pvo_pt->pte_hi |= PTE_HID; 2289 pmap_pte_set(pt, pvo_pt); 2290 return (i); 2291 } 2292 } 2293 2294 panic("pmap_pte_insert: overflow"); 2295 return (-1); 2296} 2297 2298static boolean_t 2299pmap_query_bit(vm_page_t m, int ptebit) 2300{ 2301 struct pvo_entry *pvo; 2302 struct pte *pt; 2303 2304#if 0 2305 if (pmap_attr_fetch(m) & ptebit) 2306 return (TRUE); 2307#endif 2308 2309 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2310 PMAP_PVO_CHECK(pvo); /* sanity check */ 2311 2312 /* 2313 * See if we saved the bit off. If so, cache it and return 2314 * success. 2315 */ 2316 if (pvo->pvo_pte.pte_lo & ptebit) { 2317 pmap_attr_save(m, ptebit); 2318 PMAP_PVO_CHECK(pvo); /* sanity check */ 2319 return (TRUE); 2320 } 2321 } 2322 2323 /* 2324 * No luck, now go through the hard part of looking at the PTEs 2325 * themselves. Sync so that any pending REF/CHG bits are flushed to 2326 * the PTEs. 2327 */ 2328 SYNC(); 2329 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2330 PMAP_PVO_CHECK(pvo); /* sanity check */ 2331 2332 /* 2333 * See if this pvo has a valid PTE. if so, fetch the 2334 * REF/CHG bits from the valid PTE. If the appropriate 2335 * ptebit is set, cache it and return success. 2336 */ 2337 pt = pmap_pvo_to_pte(pvo, -1); 2338 if (pt != NULL) { 2339 pmap_pte_synch(pt, &pvo->pvo_pte); 2340 if (pvo->pvo_pte.pte_lo & ptebit) { 2341 pmap_attr_save(m, ptebit); 2342 PMAP_PVO_CHECK(pvo); /* sanity check */ 2343 return (TRUE); 2344 } 2345 } 2346 } 2347 2348 return (FALSE); 2349} 2350 2351static u_int 2352pmap_clear_bit(vm_page_t m, int ptebit, int *origbit) 2353{ 2354 u_int count; 2355 struct pvo_entry *pvo; 2356 struct pte *pt; 2357 int rv; 2358 2359 /* 2360 * Clear the cached value. 2361 */ 2362 rv = pmap_attr_fetch(m); 2363 pmap_attr_clear(m, ptebit); 2364 2365 /* 2366 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2367 * we can reset the right ones). note that since the pvo entries and 2368 * list heads are accessed via BAT0 and are never placed in the page 2369 * table, we don't have to worry about further accesses setting the 2370 * REF/CHG bits. 2371 */ 2372 SYNC(); 2373 2374 /* 2375 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2376 * valid pte clear the ptebit from the valid pte. 2377 */ 2378 count = 0; 2379 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2380 PMAP_PVO_CHECK(pvo); /* sanity check */ 2381 pt = pmap_pvo_to_pte(pvo, -1); 2382 if (pt != NULL) { 2383 pmap_pte_synch(pt, &pvo->pvo_pte); 2384 if (pvo->pvo_pte.pte_lo & ptebit) { 2385 count++; 2386 pmap_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2387 } 2388 } 2389 rv |= pvo->pvo_pte.pte_lo; 2390 pvo->pvo_pte.pte_lo &= ~ptebit; 2391 PMAP_PVO_CHECK(pvo); /* sanity check */ 2392 } 2393 2394 if (origbit != NULL) { 2395 *origbit = rv; 2396 } 2397 2398 return (count); 2399} 2400 2401/* 2402 * Return true if the physical range is encompassed by the battable[idx] 2403 */ 2404static int 2405pmap_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2406{ 2407 u_int prot; 2408 u_int32_t start; 2409 u_int32_t end; 2410 u_int32_t bat_ble; 2411 2412 /* 2413 * Return immediately if not a valid mapping 2414 */ 2415 if (!battable[idx].batu & BAT_Vs) 2416 return (EINVAL); 2417 2418 /* 2419 * The BAT entry must be cache-inhibited, guarded, and r/w 2420 * so it can function as an i/o page 2421 */ 2422 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2423 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2424 return (EPERM); 2425 2426 /* 2427 * The address should be within the BAT range. Assume that the 2428 * start address in the BAT has the correct alignment (thus 2429 * not requiring masking) 2430 */ 2431 start = battable[idx].batl & BAT_PBS; 2432 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2433 end = start | (bat_ble << 15) | 0x7fff; 2434 2435 if ((pa < start) || ((pa + size) > end)) 2436 return (ERANGE); 2437 2438 return (0); 2439} 2440 2441int 2442pmap_dev_direct_mapped(vm_offset_t pa, vm_size_t size) 2443{ 2444 int i; 2445 2446 /* 2447 * This currently does not work for entries that 2448 * overlap 256M BAT segments. 2449 */ 2450 2451 for(i = 0; i < 16; i++) 2452 if (pmap_bat_mapped(i, pa, size) == 0) 2453 return (0); 2454 2455 return (EFAULT); 2456} 2457 2458/* 2459 * Map a set of physical memory pages into the kernel virtual 2460 * address space. Return a pointer to where it is mapped. This 2461 * routine is intended to be used for mapping device memory, 2462 * NOT real memory. 2463 */ 2464void * 2465pmap_mapdev(vm_offset_t pa, vm_size_t size) 2466{ 2467 vm_offset_t va, tmpva, ppa, offset; 2468 int i; 2469 2470 ppa = trunc_page(pa); 2471 offset = pa & PAGE_MASK; 2472 size = roundup(offset + size, PAGE_SIZE); 2473 2474 GIANT_REQUIRED; 2475 2476 /* 2477 * If the physical address lies within a valid BAT table entry, 2478 * return the 1:1 mapping. This currently doesn't work 2479 * for regions that overlap 256M BAT segments. 2480 */ 2481 for (i = 0; i < 16; i++) { 2482 if (pmap_bat_mapped(i, pa, size) == 0) 2483 return ((void *) pa); 2484 } 2485 2486 va = kmem_alloc_nofault(kernel_map, size); 2487 if (!va) 2488 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2489 2490 for (tmpva = va; size > 0;) { 2491 pmap_kenter(tmpva, ppa); 2492 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2493 size -= PAGE_SIZE; 2494 tmpva += PAGE_SIZE; 2495 ppa += PAGE_SIZE; 2496 } 2497 2498 return ((void *)(va + offset)); 2499} 2500 2501void 2502pmap_unmapdev(vm_offset_t va, vm_size_t size) 2503{ 2504 vm_offset_t base, offset; 2505 2506 /* 2507 * If this is outside kernel virtual space, then it's a 2508 * battable entry and doesn't require unmapping 2509 */ 2510 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2511 base = trunc_page(va); 2512 offset = va & PAGE_MASK; 2513 size = roundup(offset + size, PAGE_SIZE); 2514 kmem_free(kernel_map, base, size); 2515 } 2516} 2517