1219820Sjeff/* 2219820Sjeff * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3219820Sjeff * 4219820Sjeff * This software is available to you under a choice of one of two 5219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 6219820Sjeff * General Public License (GPL) Version 2, available from the file 7219820Sjeff * COPYING in the main directory of this source tree, or the 8219820Sjeff * OpenIB.org BSD license below: 9219820Sjeff * 10219820Sjeff * Redistribution and use in source and binary forms, with or 11219820Sjeff * without modification, are permitted provided that the following 12219820Sjeff * conditions are met: 13219820Sjeff * 14219820Sjeff * - Redistributions of source code must retain the above 15219820Sjeff * copyright notice, this list of conditions and the following 16219820Sjeff * disclaimer. 17219820Sjeff * 18219820Sjeff * - Redistributions in binary form must reproduce the above 19219820Sjeff * copyright notice, this list of conditions and the following 20219820Sjeff * disclaimer in the documentation and/or other materials 21219820Sjeff * provided with the distribution. 22219820Sjeff * 23219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30219820Sjeff * SOFTWARE. 31219820Sjeff */ 32219820Sjeff 33219820Sjeff#ifndef MLX4_QP_H 34219820Sjeff#define MLX4_QP_H 35219820Sjeff 36219820Sjeff#include <linux/types.h> 37219820Sjeff 38219820Sjeff#include <linux/mlx4/device.h> 39219820Sjeff 40219820Sjeff#define MLX4_INVALID_LKEY 0x100 41219820Sjeff 42255932Salfredenum ib_m_qp_attr_mask { 43255932Salfred IB_M_EXT_CLASS_1 = 1 << 28, 44255932Salfred IB_M_EXT_CLASS_2 = 1 << 29, 45255932Salfred IB_M_EXT_CLASS_3 = 1 << 30, 46255932Salfred 47255932Salfred IB_M_QP_MOD_VEND_MASK = (IB_M_EXT_CLASS_1 | IB_M_EXT_CLASS_2 | 48255932Salfred IB_M_EXT_CLASS_3) 49255932Salfred}; 50255932Salfred 51219820Sjeffenum mlx4_qp_optpar { 52219820Sjeff MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 53219820Sjeff MLX4_QP_OPTPAR_RRE = 1 << 1, 54219820Sjeff MLX4_QP_OPTPAR_RAE = 1 << 2, 55219820Sjeff MLX4_QP_OPTPAR_RWE = 1 << 3, 56219820Sjeff MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 57219820Sjeff MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 58219820Sjeff MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 59219820Sjeff MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 60219820Sjeff MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 61219820Sjeff MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 62219820Sjeff MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 63219820Sjeff MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 64219820Sjeff MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 65219820Sjeff MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 66219820Sjeff MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 67219820Sjeff MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20 68219820Sjeff}; 69219820Sjeff 70219820Sjeffenum mlx4_qp_state { 71219820Sjeff MLX4_QP_STATE_RST = 0, 72219820Sjeff MLX4_QP_STATE_INIT = 1, 73219820Sjeff MLX4_QP_STATE_RTR = 2, 74219820Sjeff MLX4_QP_STATE_RTS = 3, 75219820Sjeff MLX4_QP_STATE_SQER = 4, 76219820Sjeff MLX4_QP_STATE_SQD = 5, 77219820Sjeff MLX4_QP_STATE_ERR = 6, 78219820Sjeff MLX4_QP_STATE_SQ_DRAINING = 7, 79219820Sjeff MLX4_QP_NUM_STATE 80219820Sjeff}; 81219820Sjeff 82219820Sjeffenum { 83219820Sjeff MLX4_QP_ST_RC = 0x0, 84219820Sjeff MLX4_QP_ST_UC = 0x1, 85219820Sjeff MLX4_QP_ST_RD = 0x2, 86219820Sjeff MLX4_QP_ST_UD = 0x3, 87219820Sjeff MLX4_QP_ST_XRC = 0x6, 88219820Sjeff MLX4_QP_ST_MLX = 0x7 89219820Sjeff}; 90219820Sjeff 91219820Sjeffenum { 92219820Sjeff MLX4_QP_PM_MIGRATED = 0x3, 93219820Sjeff MLX4_QP_PM_ARMED = 0x0, 94219820Sjeff MLX4_QP_PM_REARM = 0x1 95219820Sjeff}; 96219820Sjeff 97219820Sjeffenum { 98219820Sjeff /* params1 */ 99219820Sjeff MLX4_QP_BIT_SRE = 1 << 15, 100219820Sjeff MLX4_QP_BIT_SWE = 1 << 14, 101219820Sjeff MLX4_QP_BIT_SAE = 1 << 13, 102219820Sjeff /* params2 */ 103219820Sjeff MLX4_QP_BIT_RRE = 1 << 15, 104219820Sjeff MLX4_QP_BIT_RWE = 1 << 14, 105219820Sjeff MLX4_QP_BIT_RAE = 1 << 13, 106219820Sjeff MLX4_QP_BIT_RIC = 1 << 4, 107272407Shselasky MLX4_QP_BIT_COLL_SYNC_RQ = 1 << 2, 108272407Shselasky MLX4_QP_BIT_COLL_SYNC_SQ = 1 << 1, 109272407Shselasky MLX4_QP_BIT_COLL_MASTER = 1 << 0 110219820Sjeff}; 111219820Sjeff 112255932Salfredenum { 113255932Salfred MLX4_RSS_HASH_XOR = 0, 114255932Salfred MLX4_RSS_HASH_TOP = 1, 115255932Salfred 116255932Salfred MLX4_RSS_UDP_IPV6 = 1 << 0, 117255932Salfred MLX4_RSS_UDP_IPV4 = 1 << 1, 118255932Salfred MLX4_RSS_TCP_IPV6 = 1 << 2, 119255932Salfred MLX4_RSS_IPV6 = 1 << 3, 120255932Salfred MLX4_RSS_TCP_IPV4 = 1 << 4, 121255932Salfred MLX4_RSS_IPV4 = 1 << 5, 122255932Salfred 123255932Salfred /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 124255932Salfred MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 125255932Salfred /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 126255932Salfred MLX4_RSS_QPC_FLAG_OFFSET = 13, 127255932Salfred}; 128255932Salfred 129255932Salfredstruct mlx4_rss_context { 130255932Salfred __be32 base_qpn; 131255932Salfred __be32 default_qpn; 132255932Salfred u16 reserved; 133255932Salfred u8 hash_fn; 134255932Salfred u8 flags; 135255932Salfred __be32 rss_key[10]; 136255932Salfred __be32 base_qpn_udp; 137255932Salfred}; 138255932Salfred 139219820Sjeffstruct mlx4_qp_path { 140219820Sjeff u8 fl; 141272407Shselasky u8 vlan_control; 142255932Salfred u8 disable_pkey_check; 143219820Sjeff u8 pkey_index; 144219820Sjeff u8 counter_index; 145219820Sjeff u8 grh_mylmc; 146219820Sjeff __be16 rlid; 147219820Sjeff u8 ackto; 148219820Sjeff u8 mgid_index; 149219820Sjeff u8 static_rate; 150219820Sjeff u8 hop_limit; 151219820Sjeff __be32 tclass_flowlabel; 152219820Sjeff u8 rgid[16]; 153219820Sjeff u8 sched_queue; 154219820Sjeff u8 vlan_index; 155255932Salfred u8 feup; 156272407Shselasky u8 fvl_rx; 157219820Sjeff u8 reserved4[2]; 158219820Sjeff u8 dmac[6]; 159219820Sjeff}; 160219820Sjeff 161272407Shselaskyenum { /* fl */ 162272407Shselasky MLX4_FL_CV = 1 << 6, 163272407Shselasky MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2, 164272407Shselasky MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1, 165272407Shselasky MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0, 166272407Shselasky}; 167272407Shselaskyenum { /* vlan_control */ 168272407Shselasky MLX4_VLAN_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7, 169272407Shselasky MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, 170272407Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, 171272407Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1,/* 802.1p priorty tag*/ 172272407Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 173272407Shselasky}; 174272407Shselasky 175272407Shselaskyenum { /* feup */ 176272407Shselasky MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */ 177272407Shselasky MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */ 178272407Shselasky MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */ 179272407Shselasky}; 180272407Shselasky 181272407Shselaskyenum { /* fvl_rx */ 182272407Shselasky MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */ 183272407Shselasky}; 184272407Shselasky 185219820Sjeffstruct mlx4_qp_context { 186219820Sjeff __be32 flags; 187219820Sjeff __be32 pd; 188219820Sjeff u8 mtu_msgmax; 189219820Sjeff u8 rq_size_stride; 190219820Sjeff u8 sq_size_stride; 191219820Sjeff u8 rlkey; 192219820Sjeff __be32 usr_page; 193219820Sjeff __be32 local_qpn; 194219820Sjeff __be32 remote_qpn; 195219820Sjeff struct mlx4_qp_path pri_path; 196219820Sjeff struct mlx4_qp_path alt_path; 197219820Sjeff __be32 params1; 198219820Sjeff u32 reserved1; 199219820Sjeff __be32 next_send_psn; 200219820Sjeff __be32 cqn_send; 201219820Sjeff u32 reserved2[2]; 202219820Sjeff __be32 last_acked_psn; 203219820Sjeff __be32 ssn; 204219820Sjeff __be32 params2; 205219820Sjeff __be32 rnr_nextrecvpsn; 206219820Sjeff __be32 xrcd; 207219820Sjeff __be32 cqn_recv; 208219820Sjeff __be64 db_rec_addr; 209219820Sjeff __be32 qkey; 210219820Sjeff __be32 srqn; 211219820Sjeff __be32 msn; 212219820Sjeff __be16 rq_wqe_counter; 213219820Sjeff __be16 sq_wqe_counter; 214219820Sjeff u32 reserved3[2]; 215219820Sjeff __be32 param3; 216219820Sjeff __be32 nummmcpeers_basemkey; 217219820Sjeff u8 log_page_size; 218219820Sjeff u8 reserved4[2]; 219219820Sjeff u8 mtt_base_addr_h; 220219820Sjeff __be32 mtt_base_addr_l; 221255932Salfred u32 reserved5[10]; 222219820Sjeff}; 223219820Sjeff 224272407Shselaskystruct mlx4_update_qp_context { 225272407Shselasky __be64 qp_mask; 226272407Shselasky __be64 primary_addr_path_mask; 227272407Shselasky __be64 secondary_addr_path_mask; 228272407Shselasky u64 reserved1; 229272407Shselasky struct mlx4_qp_context qp_context; 230272407Shselasky u64 reserved2[58]; 231272407Shselasky}; 232272407Shselasky 233272407Shselaskyenum { 234272407Shselasky MLX4_UPD_QP_MASK_PM_STATE = 32, 235272407Shselasky MLX4_UPD_QP_MASK_VSD = 33, 236272407Shselasky}; 237272407Shselasky 238272407Shselaskyenum { 239272407Shselasky MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, 240272407Shselasky MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, 241272407Shselasky MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, 242272407Shselasky MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, 243272407Shselasky MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, 244272407Shselasky MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, 245272407Shselasky MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, 246272407Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, 247272407Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, 248272407Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, 249272407Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, 250272407Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, 251272407Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, 252272407Shselasky MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, 253272407Shselasky MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, 254272407Shselasky MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, 255272407Shselasky MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, 256272407Shselasky}; 257272407Shselasky 258272407Shselaskyenum { /* param3 */ 259272407Shselasky MLX4_STRIP_VLAN = 1 << 30 260272407Shselasky}; 261272407Shselasky 262272407Shselasky 263219820Sjeff/* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 264219820Sjeff#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 265219820Sjeff 266219820Sjeffenum { 267219820Sjeff MLX4_WQE_CTRL_NEC = 1 << 29, 268219820Sjeff MLX4_WQE_CTRL_FENCE = 1 << 6, 269219820Sjeff MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 270219820Sjeff MLX4_WQE_CTRL_SOLICITED = 1 << 1, 271219820Sjeff MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 272219820Sjeff MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 273219820Sjeff MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 274219820Sjeff MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 275219820Sjeff MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 276219820Sjeff}; 277219820Sjeff 278219820Sjeffstruct mlx4_wqe_ctrl_seg { 279219820Sjeff __be32 owner_opcode; 280219820Sjeff __be16 vlan_tag; 281219820Sjeff u8 ins_vlan; 282219820Sjeff u8 fence_size; 283219820Sjeff /* 284219820Sjeff * High 24 bits are SRC remote buffer; low 8 bits are flags: 285219820Sjeff * [7] SO (strong ordering) 286219820Sjeff * [5] TCP/UDP checksum 287219820Sjeff * [4] IP checksum 288219820Sjeff * [3:2] C (generate completion queue entry) 289219820Sjeff * [1] SE (solicited event) 290255932Salfred * [0] FL (force loopback) 291219820Sjeff */ 292255932Salfred union { 293255932Salfred __be32 srcrb_flags; 294255932Salfred __be16 srcrb_flags16[2]; 295255932Salfred }; 296219820Sjeff /* 297219820Sjeff * imm is immediate data for send/RDMA write w/ immediate; 298219820Sjeff * also invalidation key for send with invalidate; input 299219820Sjeff * modifier for WQEs on CCQs. 300219820Sjeff */ 301219820Sjeff __be32 imm; 302219820Sjeff}; 303219820Sjeff 304219820Sjeffenum { 305219820Sjeff MLX4_WQE_MLX_VL15 = 1 << 17, 306255932Salfred MLX4_WQE_MLX_SLR = 1 << 16 307219820Sjeff}; 308219820Sjeff 309219820Sjeffstruct mlx4_wqe_mlx_seg { 310219820Sjeff u8 owner; 311219820Sjeff u8 reserved1[2]; 312219820Sjeff u8 opcode; 313255932Salfred __be16 sched_prio; 314255932Salfred u8 reserved2; 315219820Sjeff u8 size; 316219820Sjeff /* 317219820Sjeff * [17] VL15 318219820Sjeff * [16] SLR 319219820Sjeff * [15:12] static rate 320219820Sjeff * [11:8] SL 321219820Sjeff * [4] ICRC 322219820Sjeff * [3:2] C 323219820Sjeff * [0] FL (force loopback) 324219820Sjeff */ 325219820Sjeff __be32 flags; 326219820Sjeff __be16 rlid; 327219820Sjeff u16 reserved3; 328219820Sjeff}; 329219820Sjeff 330219820Sjeffstruct mlx4_wqe_datagram_seg { 331219820Sjeff __be32 av[8]; 332219820Sjeff __be32 dqpn; 333219820Sjeff __be32 qkey; 334219820Sjeff __be16 vlan; 335219820Sjeff u8 mac[6]; 336219820Sjeff}; 337219820Sjeff 338219820Sjeffstruct mlx4_wqe_lso_seg { 339219820Sjeff __be32 mss_hdr_size; 340219820Sjeff __be32 header[0]; 341219820Sjeff}; 342219820Sjeff 343272407Shselaskyenum mlx4_wqe_bind_seg_flags2 { 344272407Shselasky MLX4_WQE_BIND_TYPE_2 = (1<<31), 345272407Shselasky MLX4_WQE_BIND_ZERO_BASED = (1<<30), 346272407Shselasky}; 347272407Shselasky 348219820Sjeffstruct mlx4_wqe_bind_seg { 349219820Sjeff __be32 flags1; 350219820Sjeff __be32 flags2; 351219820Sjeff __be32 new_rkey; 352219820Sjeff __be32 lkey; 353219820Sjeff __be64 addr; 354219820Sjeff __be64 length; 355219820Sjeff}; 356219820Sjeff 357219820Sjeffenum { 358219820Sjeff MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 359219820Sjeff MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 360272407Shselasky MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, 361272407Shselasky MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, 362272407Shselasky MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 363219820Sjeff}; 364219820Sjeff 365219820Sjeffstruct mlx4_wqe_fmr_seg { 366219820Sjeff __be32 flags; 367219820Sjeff __be32 mem_key; 368219820Sjeff __be64 buf_list; 369219820Sjeff __be64 start_addr; 370219820Sjeff __be64 reg_len; 371219820Sjeff __be32 offset; 372219820Sjeff __be32 page_size; 373219820Sjeff u32 reserved[2]; 374219820Sjeff}; 375219820Sjeff 376219820Sjeffstruct mlx4_wqe_fmr_ext_seg { 377219820Sjeff u8 flags; 378219820Sjeff u8 reserved; 379219820Sjeff __be16 app_mask; 380219820Sjeff __be16 wire_app_tag; 381219820Sjeff __be16 mem_app_tag; 382219820Sjeff __be32 wire_ref_tag_base; 383219820Sjeff __be32 mem_ref_tag_base; 384219820Sjeff}; 385219820Sjeff 386219820Sjeffstruct mlx4_wqe_local_inval_seg { 387272407Shselasky u64 reserved1; 388219820Sjeff __be32 mem_key; 389272407Shselasky u32 reserved2; 390272407Shselasky u64 reserved3[2]; 391219820Sjeff}; 392219820Sjeff 393219820Sjeffstruct mlx4_wqe_raddr_seg { 394219820Sjeff __be64 raddr; 395219820Sjeff __be32 rkey; 396219820Sjeff u32 reserved; 397219820Sjeff}; 398219820Sjeff 399219820Sjeffstruct mlx4_wqe_atomic_seg { 400219820Sjeff __be64 swap_add; 401219820Sjeff __be64 compare; 402219820Sjeff}; 403219820Sjeff 404219820Sjeffstruct mlx4_wqe_masked_atomic_seg { 405219820Sjeff __be64 swap_add; 406219820Sjeff __be64 compare; 407219820Sjeff __be64 swap_add_mask; 408219820Sjeff __be64 compare_mask; 409219820Sjeff}; 410219820Sjeff 411219820Sjeffstruct mlx4_wqe_data_seg { 412219820Sjeff __be32 byte_count; 413219820Sjeff __be32 lkey; 414219820Sjeff __be64 addr; 415219820Sjeff}; 416219820Sjeff 417219820Sjeffenum { 418219820Sjeff MLX4_INLINE_ALIGN = 64, 419219820Sjeff MLX4_INLINE_SEG = 1 << 31, 420219820Sjeff}; 421219820Sjeff 422219820Sjeffstruct mlx4_wqe_inline_seg { 423219820Sjeff __be32 byte_count; 424219820Sjeff}; 425219820Sjeff 426219820Sjeffint mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 427219820Sjeff enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 428219820Sjeff struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 429219820Sjeff int sqd_event, struct mlx4_qp *qp); 430219820Sjeff 431219820Sjeffint mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 432219820Sjeff struct mlx4_qp_context *context); 433219820Sjeff 434219820Sjeffint mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 435219820Sjeff struct mlx4_qp_context *context, 436219820Sjeff struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 437219820Sjeff 438219820Sjeffstatic inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 439219820Sjeff{ 440219820Sjeff return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 441219820Sjeff} 442219820Sjeff 443219820Sjeffvoid mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 444219820Sjeff 445219820Sjeff#endif /* MLX4_QP_H */ 446