mlx4_en.h revision 219820
168651Skris/* 268651Skris * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 368651Skris * 468651Skris * This software is available to you under a choice of one of two 568651Skris * licenses. You may choose to be licensed under the terms of the GNU 668651Skris * General Public License (GPL) Version 2, available from the file 768651Skris * COPYING in the main directory of this source tree, or the 8296465Sdelphij * OpenIB.org BSD license below: 968651Skris * 1068651Skris * Redistribution and use in source and binary forms, with or 1168651Skris * without modification, are permitted provided that the following 1268651Skris * conditions are met: 1368651Skris * 1468651Skris * - Redistributions of source code must retain the above 15296465Sdelphij * copyright notice, this list of conditions and the following 1668651Skris * disclaimer. 1768651Skris * 1868651Skris * - Redistributions in binary form must reproduce the above 1968651Skris * copyright notice, this list of conditions and the following 2068651Skris * disclaimer in the documentation and/or other materials 2168651Skris * provided with the distribution. 22296465Sdelphij * 2368651Skris * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2468651Skris * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2568651Skris * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 2668651Skris * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 2768651Skris * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 2868651Skris * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 2968651Skris * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 3068651Skris * SOFTWARE. 3168651Skris * 3268651Skris */ 3368651Skris 3468651Skris#ifndef _MLX4_EN_H_ 3568651Skris#define _MLX4_EN_H_ 3668651Skris 37296465Sdelphij#include <sys/cdefs.h> 3868651Skris 3968651Skris#include <linux/types.h> 40296465Sdelphij#include <linux/compiler.h> 4168651Skris#include <linux/list.h> 4268651Skris#include <linux/mutex.h> 4368651Skris#include <linux/netdevice.h> 4468651Skris 4568651Skris#include <linux/mlx4/device.h> 4668651Skris#include <linux/mlx4/qp.h> 4768651Skris#include <linux/mlx4/cq.h> 4868651Skris#include <linux/mlx4/srq.h> 4968651Skris#include <linux/mlx4/doorbell.h> 5068651Skris#include <linux/mlx4/cmd.h> 5168651Skris 52296465Sdelphij#include <net/if_media.h> 5368651Skris#include <netinet/tcp_lro.h> 5468651Skris 5568651Skris#include "en_port.h" 5668651Skris 5768651Skris#define DRV_NAME "mlx4_en" 5868651Skris#define DRV_VERSION "1.5.2" 5968651Skris#define DRV_RELDATE "July 2010" 6068651Skris 6168651Skris/* XXX */ 6268651Skris#define NETIF_MSG_LINK 0x1 6368651Skris#define NETIF_MSG_IFDOWN 0x2 6468651Skris#define NETIF_MSG_HW 0x4 65296465Sdelphij#define NETIF_MSG_DRV 0x8 6668651Skris#define NETIF_MSG_INTR 0x10 6768651Skris#define NETIF_MSG_RX_ERR 0x20 6868651Skris 6968651Skris#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 7068651Skris 7168651Skris#define en_print(level, priv, format, arg...) \ 7268651Skris { \ 7368651Skris if ((priv)->registered) \ 7468651Skris printk(level "%s: %s: " format, DRV_NAME, \ 75296465Sdelphij (priv->dev)->if_xname, ## arg); \ 7668651Skris else \ 7768651Skris printk(level "%s: %s: Port %d: " format, \ 7868651Skris DRV_NAME, dev_name(&priv->mdev->pdev->dev), \ 79296465Sdelphij (priv)->port, ## arg); \ 80296465Sdelphij } 81296465Sdelphij 82296465Sdelphij#define en_dbg(mlevel, priv, format, arg...) \ 83296465Sdelphij if (NETIF_MSG_##mlevel & priv->msg_enable) \ 84296465Sdelphij en_print(KERN_DEBUG, priv, format, ## arg) 85296465Sdelphij#define en_warn(priv, format, arg...) \ 86296465Sdelphij en_print(KERN_WARNING, priv, format, ## arg) 87296465Sdelphij#define en_err(priv, format, arg...) \ 88296465Sdelphij en_print(KERN_ERR, priv, format, ## arg) 89296465Sdelphij#define en_info(priv, format, arg...) \ 90296465Sdelphij en_print(KERN_INFO, priv, format, ## arg) 9168651Skris 9268651Skris#define mlx4_err(mdev, format, arg...) \ 93296465Sdelphij printk(KERN_ERR "%s %s: " format , DRV_NAME ,\ 94296465Sdelphij dev_name(&mdev->pdev->dev) , ## arg) 95296465Sdelphij#define mlx4_info(mdev, format, arg...) \ 9668651Skris printk(KERN_INFO "%s %s: " format , DRV_NAME ,\ 97296465Sdelphij dev_name(&mdev->pdev->dev) , ## arg) 98296465Sdelphij#define mlx4_warn(mdev, format, arg...) \ 99296465Sdelphij printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\ 100296465Sdelphij dev_name(&mdev->pdev->dev) , ## arg) 101296465Sdelphij 10268651Skris/* 10368651Skris * Device constants 104296465Sdelphij */ 105296465Sdelphij 10668651Skris 107296465Sdelphij#define MLX4_EN_PAGE_SHIFT 12 108296465Sdelphij#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 109296465Sdelphij#define MAX_TX_RINGS (MLX4_EN_NUM_HASH_RINGS + 1 + MLX4_EN_NUM_PPP_RINGS) 110296465Sdelphij#define MAX_RX_RINGS 16 111296465Sdelphij#define TXBB_SIZE 64 112296465Sdelphij#define HEADROOM (2048 / TXBB_SIZE + 1) 113296465Sdelphij#define STAMP_STRIDE 64 114296465Sdelphij#define STAMP_DWORDS (STAMP_STRIDE / 4) 115296465Sdelphij#define STAMP_SHIFT 31 116296465Sdelphij#define STAMP_VAL 0x7fffffff 11768651Skris#define STATS_DELAY (HZ / 4) 118296465Sdelphij 119296465Sdelphij/* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 120296465Sdelphij#define MAX_DESC_SIZE 512 121296465Sdelphij#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 122296465Sdelphij 12368651Skris/* 12468651Skris * OS related constants and tunables 125296465Sdelphij */ 126296465Sdelphij 12768651Skris#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 128296465Sdelphij 129296465Sdelphij#define MLX4_EN_MAX_LRO_DESCRIPTORS 32 130296465Sdelphij#define MLX4_EN_NUM_IPFRAG_SESSIONS 16 131296465Sdelphij 132296465Sdelphij/* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 133296465Sdelphij * and 4K allocations) */ 134296465Sdelphij#if MJUMPAGESIZE == 4096 135296465Sdelphijenum { 136296465Sdelphij FRAG_SZ0 = MCLBYTES, 137296465Sdelphij FRAG_SZ1 = MJUMPAGESIZE, 138296465Sdelphij FRAG_SZ2 = MJUMPAGESIZE, 139296465Sdelphij}; 14068651Skris#define MLX4_EN_MAX_RX_FRAGS 3 141296465Sdelphij#elif MJUMPAGESIZE == 8192 142296465Sdelphijenum { 14368651Skris FRAG_SZ0 = MCLBYTES, 144296465Sdelphij FRAG_SZ1 = MJUMPAGESIZE, 145296465Sdelphij}; 146296465Sdelphij#define MLX4_EN_MAX_RX_FRAGS 2 147296465Sdelphij#elif MJUMPAGESIZE == 8192 148296465Sdelphij#else 149296465Sdelphij#error "Unknown PAGE_SIZE" 150296465Sdelphij#endif 151296465Sdelphij 152296465Sdelphij/* Maximum ring sizes */ 153296465Sdelphij#define MLX4_EN_MAX_TX_SIZE 8192 15468651Skris#define MLX4_EN_MAX_RX_SIZE 8192 155296465Sdelphij 156296465Sdelphij#define MLX4_EN_MIN_RX_SIZE (128) 157296465Sdelphij#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 15868651Skris 159296465Sdelphij#define MLX4_EN_SMALL_PKT_SIZE 64 160296465Sdelphij#define MLX4_EN_TX_HASH_SIZE 256 161296465Sdelphij#define MLX4_EN_TX_HASH_MASK (MLX4_EN_TX_HASH_SIZE - 1) 162296465Sdelphij#define MLX4_EN_NUM_HASH_RINGS 4 163296465Sdelphij#define MLX4_EN_NUM_PPP_RINGS 8 16468651Skris#define MLX4_EN_DEF_TX_RING_SIZE 512 165296465Sdelphij#define MLX4_EN_DEF_TX_QUEUE_SIZE 4096 16668651Skris#define MLX4_EN_DEF_RX_RING_SIZE 1024 167296465Sdelphij#define MLX4_EN_MAX_RX_POLL 16 168296465Sdelphij 16968651Skris/* Target number of bytes to coalesce with interrupt moderation */ 170296465Sdelphij#define MLX4_EN_RX_COAL_TARGET 0x20000 171296465Sdelphij#define MLX4_EN_RX_COAL_TIME 0x10 172296465Sdelphij 173296465Sdelphij#define MLX4_EN_TX_COAL_PKTS 5 174296465Sdelphij#define MLX4_EN_TX_COAL_TIME 0x80 175296465Sdelphij 17668651Skris#define MLX4_EN_RX_RATE_LOW 400000 177296465Sdelphij#define MLX4_EN_RX_COAL_TIME_LOW 0 178296465Sdelphij#define MLX4_EN_RX_RATE_HIGH 450000 179296465Sdelphij#define MLX4_EN_RX_COAL_TIME_HIGH 128 180296465Sdelphij#define MLX4_EN_RX_SIZE_THRESH 1024 181296465Sdelphij#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 182296465Sdelphij#define MLX4_EN_SAMPLE_INTERVAL 0 183296465Sdelphij#define MLX4_EN_AVG_PKT_SMALL 256 18468651Skris 185296465Sdelphij#define MLX4_EN_AUTO_CONF 0xffff 186296465Sdelphij 187296465Sdelphij#define MLX4_EN_DEF_RX_PAUSE 1 188296465Sdelphij#define MLX4_EN_DEF_TX_PAUSE 1 189296465Sdelphij 190296465Sdelphij/* Interval between sucessive polls in the Tx routine when polling is used 191296465Sdelphij instead of interrupts (in per-core Tx rings) - should be power of 2 */ 192296465Sdelphij#define MLX4_EN_TX_POLL_MODER 16 193296465Sdelphij#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 194296465Sdelphij 195296465Sdelphij#define ETH_LLC_SNAP_SIZE 8 196296465Sdelphij 197296465Sdelphij#define SMALL_PACKET_SIZE (MHLEN) 198296465Sdelphij#define HEADER_COPY_SIZE (128) 199296465Sdelphij#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN) 200296465Sdelphij 201100928Snectar#define MLX4_EN_MIN_MTU 46 202296465Sdelphij#define ETH_BCAST 0xffffffffffffULL 20368651Skris 204296465Sdelphij#define MLX4_EN_LOOPBACK_RETRIES 5 205296465Sdelphij#define MLX4_EN_LOOPBACK_TIMEOUT 100 206296465Sdelphij 207296465Sdelphij#ifdef MLX4_EN_PERF_STAT 20868651Skris/* Number of samples to 'average' */ 209100928Snectar#define AVG_SIZE 128 210296465Sdelphij#define AVG_FACTOR 1024 21168651Skris#define NUM_PERF_STATS NUM_PERF_COUNTERS 212296465Sdelphij 213296465Sdelphij#define INC_PERF_COUNTER(cnt) (++(cnt)) 214296465Sdelphij#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 215296465Sdelphij#define AVG_PERF_COUNTER(cnt, sample) \ 216296465Sdelphij ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 217100928Snectar#define GET_PERF_COUNTER(cnt) (cnt) 218296465Sdelphij#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 21968651Skris 220296465Sdelphij#else 221296465Sdelphij 222296465Sdelphij#define NUM_PERF_STATS 0 223296465Sdelphij#define INC_PERF_COUNTER(cnt) do {} while (0) 22468651Skris#define ADD_PERF_COUNTER(cnt, add) do {} while (0) 225296465Sdelphij#define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 226296465Sdelphij#define GET_PERF_COUNTER(cnt) (0) 227296465Sdelphij#define GET_AVG_PERF_COUNTER(cnt) (0) 228296465Sdelphij#endif /* MLX4_EN_PERF_STAT */ 229296465Sdelphij 230100928Snectar/* 231296465Sdelphij * Configurables 23268651Skris */ 233296465Sdelphij 234296465Sdelphijenum cq_type { 235296465Sdelphij RX = 0, 236100928Snectar TX = 1, 237296465Sdelphij}; 23868651Skris 239296465Sdelphij 240296465Sdelphij/* 241296465Sdelphij * Useful macros 242296465Sdelphij */ 243296465Sdelphij#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 244100928Snectar#define XNOR(x, y) (!(x) == !(y)) 245296465Sdelphij#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 24668651Skris 247296465Sdelphij 248296465Sdelphijstruct mlx4_en_tx_info { 249296465Sdelphij struct mbuf *mb; 250296465Sdelphij u32 nr_txbb; 251296465Sdelphij u8 nr_segs; 252296465Sdelphij u8 data_offset; 253296465Sdelphij u8 inl; 254296465Sdelphij}; 255296465Sdelphij 256296465Sdelphij 257296465Sdelphij#define MLX4_EN_BIT_DESC_OWN 0x80000000 258296465Sdelphij#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 259296465Sdelphij#define MLX4_EN_MEMTYPE_PAD 0x100 260296465Sdelphij#define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 261296465Sdelphij 262296465Sdelphij 263296465Sdelphijstruct mlx4_en_tx_desc { 264296465Sdelphij struct mlx4_wqe_ctrl_seg ctrl; 26568651Skris union { 26668651Skris struct mlx4_wqe_data_seg data; /* at least one data segment */ 267296465Sdelphij struct mlx4_wqe_lso_seg lso; 268296465Sdelphij struct mlx4_wqe_inline_seg inl; 269296465Sdelphij }; 270296465Sdelphij}; 271296465Sdelphij 272296465Sdelphij#define MLX4_EN_USE_SRQ 0x01000000 273296465Sdelphij 27468651Skrisstruct mlx4_en_tx_ring { 275296465Sdelphij spinlock_t tx_lock; 27668651Skris struct mlx4_hwq_resources wqres; 277296465Sdelphij u32 size ; /* number of TXBBs */ 278296465Sdelphij u32 size_mask; 279296465Sdelphij u16 stride; 280296465Sdelphij u16 cqn; /* index of port CQ associated with this ring */ 281296465Sdelphij u32 prod; 282296465Sdelphij u32 cons; 283296465Sdelphij u32 buf_size; 284296465Sdelphij u32 doorbell_qpn; 285296465Sdelphij void *buf; 286296465Sdelphij u16 poll_cnt; 287296465Sdelphij int blocked; 288296465Sdelphij struct buf_ring *br; 289296465Sdelphij struct mlx4_en_tx_info *tx_info; 290296465Sdelphij u8 *bounce_buf; 291296465Sdelphij u32 last_nr_txbb; 292296465Sdelphij struct mlx4_qp qp; 293296465Sdelphij struct mlx4_qp_context context; 294296465Sdelphij int qpn; 295296465Sdelphij enum mlx4_qp_state qp_state; 296296465Sdelphij struct mlx4_srq dummy; 297296465Sdelphij unsigned long bytes; 298296465Sdelphij unsigned long packets; 299296465Sdelphij unsigned long errors; 300296465Sdelphij spinlock_t comp_lock; 301296465Sdelphij struct mlx4_bf bf; 302296465Sdelphij bool bf_enabled; 303296465Sdelphij u64 watchdog_time; 304296465Sdelphij}; 305296465Sdelphij 306296465Sdelphijstruct mlx4_en_ipfrag { 307296465Sdelphij struct mbuf *fragments; 308296465Sdelphij struct mbuf *last; 309296465Sdelphij __be32 saddr; 310296465Sdelphij __be32 daddr; 311296465Sdelphij __be16 id; 312296465Sdelphij u8 protocol; 313296465Sdelphij int total_len; 314296465Sdelphij u16 offset; 315296465Sdelphij}; 316296465Sdelphij 317296465Sdelphijstruct mlx4_en_rx_desc { 318296465Sdelphij /* actual number of entries depends on rx ring stride */ 319296465Sdelphij struct mlx4_wqe_data_seg data[0]; 32068651Skris}; 321296465Sdelphij 322296465Sdelphijstruct mlx4_en_rx_ring { 323296465Sdelphij struct mlx4_hwq_resources wqres; 324296465Sdelphij u32 size ; /* number of Rx descs*/ 325296465Sdelphij u32 actual_size; 326296465Sdelphij u32 size_mask; 327296465Sdelphij u16 stride; 32868651Skris u16 log_stride; 329296465Sdelphij u16 cqn; /* index of port CQ associated with this ring */ 330296465Sdelphij u32 prod; 331296465Sdelphij u32 cons; 332296465Sdelphij u32 buf_size; 33368651Skris void *buf; 334296465Sdelphij void *rx_info; 33568651Skris unsigned long bytes; 336296465Sdelphij unsigned long packets; 337296465Sdelphij unsigned long errors; 338296465Sdelphij unsigned int use_frags; 339296465Sdelphij struct lro_ctrl lro; 340296465Sdelphij struct mlx4_en_ipfrag ipfrag[MLX4_EN_NUM_IPFRAG_SESSIONS]; 341296465Sdelphij}; 342296465Sdelphij 343296465Sdelphij 344296465Sdelphijstatic inline int mlx4_en_can_lro(__be16 status) 345296465Sdelphij{ 346296465Sdelphij return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 347296465Sdelphij MLX4_CQE_STATUS_IPV4F | 348296465Sdelphij MLX4_CQE_STATUS_IPV6 | 349296465Sdelphij MLX4_CQE_STATUS_IPV4OPT | 350296465Sdelphij MLX4_CQE_STATUS_TCP | 351296465Sdelphij MLX4_CQE_STATUS_UDP | 352296465Sdelphij MLX4_CQE_STATUS_IPOK)) == 353296465Sdelphij cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 354296465Sdelphij MLX4_CQE_STATUS_IPOK | 355296465Sdelphij MLX4_CQE_STATUS_TCP); 356296465Sdelphij} 357296465Sdelphij 358296465Sdelphijstruct mlx4_en_cq { 359296465Sdelphij struct mlx4_cq mcq; 360296465Sdelphij struct mlx4_hwq_resources wqres; 361296465Sdelphij int ring; 362296465Sdelphij spinlock_t lock; 363296465Sdelphij struct net_device *dev; 364296465Sdelphij /* Per-core Tx cq processing support */ 365296465Sdelphij struct timer_list timer; 36668651Skris int size; 36768651Skris int buf_size; 368296465Sdelphij unsigned vector; 369296465Sdelphij enum cq_type is_tx; 37068651Skris u16 moder_time; 371296465Sdelphij u16 moder_cnt; 372296465Sdelphij struct mlx4_cqe *buf; 373296465Sdelphij struct task cq_task; 374296465Sdelphij struct taskqueue *tq; 375296465Sdelphij#define MLX4_EN_OPCODE_ERROR 0x1e 376296465Sdelphij u32 tot_rx; 377296465Sdelphij}; 378296465Sdelphij 379296465Sdelphijstruct mlx4_en_port_profile { 38068651Skris u32 flags; 38168651Skris u32 tx_ring_num; 382296465Sdelphij u32 rx_ring_num; 383296465Sdelphij u32 tx_ring_size; 384296465Sdelphij u32 rx_ring_size; 385296465Sdelphij u8 rx_pause; 386296465Sdelphij u8 rx_ppp; 38768651Skris u8 tx_pause; 38868651Skris u8 tx_ppp; 389296465Sdelphij}; 390296465Sdelphij 391296465Sdelphijstruct mlx4_en_profile { 392 int rss_xor; 393 int num_lro; 394 int ip_reasm; 395 int tcp_rss; 396 int udp_rss; 397 u8 rss_mask; 398 u32 active_ports; 399 u32 small_pkt_int; 400 u8 no_reset; 401 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 402}; 403 404struct mlx4_en_dev { 405 struct mlx4_dev *dev; 406 struct pci_dev *pdev; 407 struct mutex state_lock; 408 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 409 u32 port_cnt; 410 bool device_up; 411 struct mlx4_en_profile profile; 412 u32 LSO_support; 413 struct workqueue_struct *workqueue; 414 struct device *dma_device; 415 void __iomem *uar_map; 416 struct mlx4_uar priv_uar; 417 struct mlx4_mr mr; 418 u32 priv_pdn; 419 spinlock_t uar_lock; 420 u8 mac_removed[MLX4_MAX_PORTS + 1]; 421}; 422 423 424struct mlx4_en_rss_map { 425 int base_qpn; 426 struct mlx4_qp qps[MAX_RX_RINGS]; 427 enum mlx4_qp_state state[MAX_RX_RINGS]; 428 struct mlx4_qp indir_qp; 429 enum mlx4_qp_state indir_state; 430}; 431 432struct mlx4_en_rss_context { 433 __be32 base_qpn; 434 __be32 default_qpn; 435 u16 reserved; 436 u8 hash_fn; 437 u8 flags; 438 __be32 rss_key[10]; 439 __be32 base_qpn_udp; 440}; 441 442struct mlx4_en_port_state { 443 int link_state; 444 int link_speed; 445 int transciver; 446}; 447 448struct mlx4_en_pkt_stats { 449 unsigned long broadcast; 450 unsigned long rx_prio[8]; 451 unsigned long tx_prio[8]; 452#define NUM_PKT_STATS 17 453}; 454 455struct mlx4_en_port_stats { 456 unsigned long tso_packets; 457 unsigned long queue_stopped; 458 unsigned long wake_queue; 459 unsigned long tx_timeout; 460 unsigned long rx_alloc_failed; 461 unsigned long rx_chksum_good; 462 unsigned long rx_chksum_none; 463 unsigned long tx_chksum_offload; 464}; 465 466struct mlx4_en_perf_stats { 467 u32 tx_poll; 468 u64 tx_pktsz_avg; 469 u32 inflight_avg; 470 u32 tx_coal_avg; 471 u32 rx_coal_avg; 472}; 473 474struct mlx4_en_frag_info { 475 u16 frag_size; 476 u16 frag_prefix_size; 477}; 478 479struct mlx4_en_tx_hash_entry { 480 u8 cnt; 481 unsigned int small_pkts; 482 unsigned int big_pkts; 483 unsigned int ring; 484}; 485 486struct mlx4_en_priv { 487 struct mlx4_en_dev *mdev; 488 struct mlx4_en_port_profile *prof; 489 struct net_device *dev; 490 bool vlgrp_modified; 491 u32 vlan_register[VLAN_FLTR_SIZE]; 492 u32 vlan_unregister[VLAN_FLTR_SIZE]; 493 u32 vlans[VLAN_FLTR_SIZE]; 494 spinlock_t vlan_lock; 495 struct mlx4_en_port_state port_state; 496 spinlock_t stats_lock; 497 498 unsigned long last_moder_packets; 499 unsigned long last_moder_tx_packets; 500 unsigned long last_moder_bytes; 501 unsigned long last_moder_jiffies; 502 int last_moder_time; 503 u16 rx_usecs; 504 u16 rx_frames; 505 u16 tx_usecs; 506 u16 tx_frames; 507 u32 pkt_rate_low; 508 u16 rx_usecs_low; 509 u32 pkt_rate_high; 510 u16 rx_usecs_high; 511 u16 sample_interval; 512 u16 adaptive_rx_coal; 513 u32 msg_enable; 514 u32 loopback_ok; 515 u32 validate_loopback; 516 517 struct mlx4_hwq_resources res; 518 int link_state; 519 int last_link_state; 520 bool port_up; 521 int port; 522 int registered; 523 int allocated; 524 int rx_csum; 525 u64 mac; 526 int mac_index; 527 unsigned max_mtu; 528 int base_qpn; 529 530 struct mlx4_en_rss_map rss_map; 531 u16 tx_prio_map[8]; 532 u32 flags; 533#define MLX4_EN_FLAG_PROMISC 0x1 534 u32 tx_ring_num; 535 u32 rx_ring_num; 536 u32 udp_rings; 537 u32 rx_mb_size; 538 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 539 u16 num_frags; 540 u16 log_rx_info; 541 542 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS]; 543 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS]; 544 struct mlx4_en_cq tx_cq[MAX_TX_RINGS]; 545 struct mlx4_en_cq rx_cq[MAX_RX_RINGS]; 546 struct mlx4_en_tx_hash_entry tx_hash[MLX4_EN_TX_HASH_SIZE]; 547 struct work_struct mcast_task; 548 struct work_struct watchdog_task; 549 struct work_struct linkstate_task; 550 struct delayed_work stats_task; 551 struct mlx4_en_perf_stats pstats; 552 struct mlx4_en_pkt_stats pkstats; 553 struct mlx4_en_port_stats port_stats; 554 struct mlx4_en_stat_out_mbox hw_stats; 555 struct ifmedia media; 556 eventhandler_tag vlan_attach; 557 eventhandler_tag vlan_detach; 558 struct callout watchdog_timer; 559 volatile int blocked; 560 struct sysctl_oid *sysctl; 561 struct sysctl_ctx_list conf_ctx; 562 struct sysctl_ctx_list stat_ctx; 563}; 564 565 566int mlx4_en_transmit(struct net_device *dev, struct mbuf *mb); 567void mlx4_en_qflush(struct net_device *dev); 568 569int mlx4_en_rx_frags(struct mlx4_en_priv *priv, struct mlx4_en_rx_ring *ring, 570 struct mbuf *mb, struct mlx4_cqe *cqe); 571void mlx4_en_flush_frags(struct mlx4_en_priv *priv, 572 struct mlx4_en_rx_ring *ring); 573void mlx4_en_destroy_netdev(struct net_device *dev); 574int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 575 struct mlx4_en_port_profile *prof); 576 577int mlx4_en_start_port(struct net_device *dev); 578void mlx4_en_stop_port(struct net_device *dev); 579 580void mlx4_en_free_resources(struct mlx4_en_priv *priv); 581int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 582 583int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 584 int entries, int ring, enum cq_type mode); 585void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 586int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 587void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 588int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 589int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 590 591void mlx4_en_poll_tx_cq(unsigned long data); 592void mlx4_en_tx_irq(struct mlx4_cq *mcq); 593u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb); 594 595int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring, 596 u32 size, u16 stride); 597void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring); 598int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 599 struct mlx4_en_tx_ring *ring, 600 int cq); 601void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 602 struct mlx4_en_tx_ring *ring); 603 604int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 605 struct mlx4_en_rx_ring *ring, u32 size); 606void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 607 struct mlx4_en_rx_ring *ring); 608int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 609void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 610 struct mlx4_en_rx_ring *ring); 611int mlx4_en_process_rx_cq(struct net_device *dev, 612 struct mlx4_en_cq *cq, 613 int budget); 614int mlx4_en_process_rx_cq_mb(struct net_device *dev, 615 struct mlx4_en_cq *cq, 616 int budget); 617void mlx4_en_tx_que(void *context, int pending); 618void mlx4_en_rx_que(void *context, int pending); 619void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 620 int is_tx, int rss, int qpn, int cqn, 621 struct mlx4_qp_context *context); 622void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 623int mlx4_en_map_buffer(struct mlx4_buf *buf); 624void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 625 626void mlx4_en_calc_rx_buf(struct net_device *dev); 627void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num); 628int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 629void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 630int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 631void mlx4_en_rx_irq(struct mlx4_cq *mcq); 632 633int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 634int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, u32 *vlans); 635int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 636 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 637int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 638 u8 promisc); 639 640int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 641int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 642 643#define MLX4_EN_NUM_SELF_TEST 5 644void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 645u64 mlx4_en_mac_to_u64(u8 *addr); 646 647/* 648 * Globals 649 */ 650extern const struct ethtool_ops mlx4_en_ethtool_ops; 651#endif 652