pic.h revision 211994 
1/*-
2 * Copyright (c) 2003-2009 RMI Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of RMI Corporation, nor the names of its contributors,
14 *    may be used to endorse or promote products derived from this software
15 *    without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * RMI_BSD
30 * $FreeBSD: head/sys/mips/rmi/pic.h 211994 2010-08-30 13:05:21Z jchandra $
31 */
32#ifndef _RMI_PIC_H_
33#define	_RMI_PIC_H_
34
35#include <sys/cdefs.h>
36#include <sys/lock.h>
37#include <sys/mutex.h>
38#include <mips/rmi/iomap.h>
39
40#define	PIC_IRT_WD_INDEX		0
41#define	PIC_IRT_TIMER_INDEX(i)		(1 + (i))
42#define	PIC_IRT_UART_0_INDEX		9
43#define	PIC_IRT_UART_1_INDEX		10
44#define	PIC_IRT_I2C_0_INDEX		11
45#define	PIC_IRT_I2C_1_INDEX		12
46#define	PIC_IRT_PCMCIA_INDEX		13
47#define	PIC_IRT_GPIO_INDEX		14
48#define	PIC_IRT_HYPER_INDEX		15
49#define	PIC_IRT_PCIX_INDEX		16
50#define	PIC_IRT_GMAC0_INDEX		17
51#define	PIC_IRT_GMAC1_INDEX		18
52#define	PIC_IRT_GMAC2_INDEX		19
53#define	PIC_IRT_GMAC3_INDEX		20
54#define	PIC_IRT_XGS0_INDEX		21
55#define	PIC_IRT_XGS1_INDEX		22
56#define	PIC_IRT_HYPER_FATAL_INDEX	23
57#define	PIC_IRT_PCIX_FATAL_INDEX	24
58#define	PIC_IRT_BRIDGE_AERR_INDEX	25
59#define	PIC_IRT_BRIDGE_BERR_INDEX	26
60#define	PIC_IRT_BRIDGE_TB_INDEX		27
61#define	PIC_IRT_BRIDGE_AERR_NMI_INDEX	28
62
63/* numbering for XLS */
64#define	PIC_IRT_BRIDGE_ERR_INDEX	25
65#define	PIC_IRT_PCIE_LINK0_INDEX	26
66#define	PIC_IRT_PCIE_LINK1_INDEX	27
67#define	PIC_IRT_PCIE_LINK2_INDEX	23
68#define	PIC_IRT_PCIE_LINK3_INDEX	24
69#define	PIC_IRT_PCIE_INT_INDEX		28
70#define	PIC_IRT_PCIE_FATAL_INDEX	29
71#define	PIC_IRT_GPIO_B_INDEX		30
72#define	PIC_IRT_USB_INDEX		31
73#define	PIC_NUM_IRTS			32
74
75#define	PIC_CLOCK_TIMER			7
76
77#define	PIC_CTRL			0x00
78#define	PIC_IPI				0x04
79#define	PIC_INT_ACK			0x06
80
81#define	WD_MAX_VAL_0			0x08
82#define	WD_MAX_VAL_1			0x09
83#define	WD_MASK_0			0x0a
84#define	WD_MASK_1			0x0b
85#define	WD_HEARBEAT_0			0x0c
86#define	WD_HEARBEAT_1			0x0d
87
88#define	PIC_IRT_0_BASE			0x40
89#define	PIC_IRT_1_BASE			0x80
90#define	PIC_TIMER_MAXVAL_0_BASE		0x100
91#define	PIC_TIMER_MAXVAL_1_BASE		0x110
92#define	PIC_TIMER_COUNT_0_BASE		0x120
93#define	PIC_TIMER_COUNT_1_BASE		0x130
94
95#define	PIC_IRT_0(picintr)	(PIC_IRT_0_BASE + (picintr))
96#define	PIC_IRT_1(picintr)	(PIC_IRT_1_BASE + (picintr))
97
98#define	PIC_TIMER_MAXVAL_0(i)	(PIC_TIMER_MAXVAL_0_BASE + (i))
99#define	PIC_TIMER_MAXVAL_1(i)	(PIC_TIMER_MAXVAL_1_BASE + (i))
100#define	PIC_TIMER_COUNT_0(i)	(PIC_TIMER_COUNT_0_BASE + (i))
101#define	PIC_TIMER_COUNT_1(i)	(PIC_TIMER_COUNT_0_BASE + (i))
102#define	PIC_TIMER_HZ		66000000U
103
104/*
105 * We use a simple mapping form PIC interrupts to CPU IRQs.
106 * The PIC interrupts 0-31 are mapped to CPU irq's 8-39.
107 * this leaves the lower 0-7 for the cpu interrupts (like
108 * count/compare, msgrng) and 40-63 for IPIs
109 */
110#define	PIC_IRQ_BASE		8
111#define	PIC_INTR_TO_IRQ(i)	(PIC_IRQ_BASE + (i))
112#define	PIC_IRQ_TO_INTR(i)	((i) - PIC_IRQ_BASE)
113
114#define	PIC_WD_IRQ		(PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
115#define	PIC_TIMER_IRQ(i)	(PIC_IRQ_BASE + PIC_IRT_TIMER_INDEX(i))
116#define	PIC_CLOCK_IRQ		PIC_TIMER_IRQ(PIC_CLOCK_TIMER)
117
118#define	PIC_UART_0_IRQ		(PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX)
119#define	PIC_UART_1_IRQ		(PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX)
120#define	PIC_I2C_0_IRQ		(PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX)
121#define	PIC_I2C_1_IRQ		(PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX)
122#define	PIC_PCMCIA_IRQ		(PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX)
123#define	PIC_GPIO_IRQ		(PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX)
124#define	PIC_HYPER_IRQ		(PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX)
125#define	PIC_PCIX_IRQ		(PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX)
126#define	PIC_GMAC_0_IRQ		(PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX)
127#define	PIC_GMAC_1_IRQ		(PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX)
128#define	PIC_GMAC_2_IRQ		(PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX)
129#define	PIC_GMAC_3_IRQ		(PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX)
130#define	PIC_XGS_0_IRQ		(PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX)
131#define	PIC_XGS_1_IRQ		(PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX)
132#define	PIC_HYPER_FATAL_IRQ	(PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX)
133#define	PIC_PCIX_FATAL_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX)
134#define	PIC_BRIDGE_AERR_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX)
135#define	PIC_BRIDGE_BERR_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
136#define	PIC_BRIDGE_TB_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
137#define	PIC_BRIDGE_AERR_NMI_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
138#define	PIC_BRIDGE_ERR_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
139#define	PIC_PCIE_LINK0_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
140#define	PIC_PCIE_LINK1_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
141#define	PIC_PCIE_LINK2_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX)
142#define	PIC_PCIE_LINK3_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX)
143#define	PIC_PCIE_INT_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_INT__INDEX)
144#define	PIC_PCIE_FATAL_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX)
145#define	PIC_GPIO_B_IRQ		(PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
146#define	PIC_USB_IRQ		(PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
147
148#define	PIC_IRQ_IS_PICINTR(irq)	((irq) >= PIC_IRQ_BASE && 		\
149				 (irq) < PIC_IRQ_BASE + PIC_NUM_IRTS)
150#define	PIC_IS_EDGE_TRIGGERED(i) ((i) >= PIC_IRT_TIMER_INDEX(0) &&	\
151				  (i) <= PIC_IRT_TIMER_INDEX(7))
152
153extern struct mtx xlr_pic_lock;
154
155static __inline uint32_t
156pic_read_control(void)
157{
158	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
159	uint32_t reg;
160
161	mtx_lock_spin(&xlr_pic_lock);
162	xlr_read_reg(mmio, PIC_CTRL);
163	mtx_unlock_spin(&xlr_pic_lock);
164	return (reg);
165}
166
167static __inline void
168pic_write_control(uint32_t control)
169{
170	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
171
172	mtx_lock_spin(&xlr_pic_lock);
173	xlr_write_reg(mmio, PIC_CTRL, control);
174	mtx_unlock_spin(&xlr_pic_lock);
175}
176
177static __inline void
178pic_update_control(__uint32_t control)
179{
180	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
181
182	mtx_lock_spin(&xlr_pic_lock);
183	xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
184	mtx_unlock_spin(&xlr_pic_lock);
185}
186
187static __inline void
188pic_ack(int picintr)
189{
190	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
191
192	xlr_write_reg(mmio, PIC_INT_ACK, 1 << picintr);
193}
194
195static __inline
196void pic_send_ipi(int cpu, int ipi)
197{
198	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
199	int tid, pid;
200
201	tid = cpu & 0x3;
202	pid = (cpu >> 2) & 0x7;
203	xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi);
204}
205
206static __inline
207void pic_setup_intr(int picintr, int irq, uint32_t cpumask, int level)
208{
209        xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
210
211	mtx_lock_spin(&xlr_pic_lock);
212	xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask);
213	xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1 << 31) | (level << 30) |
214	    (1 << 6) | irq));
215	mtx_unlock_spin(&xlr_pic_lock);
216}
217
218static __inline void
219pic_init_timer(int timer)
220{
221	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
222	uint32_t val;
223
224	mtx_lock_spin(&xlr_pic_lock);
225	val = xlr_read_reg(mmio, PIC_CTRL);
226	val |= (1 << (8 + timer));
227	xlr_write_reg(mmio, PIC_CTRL, val);
228	mtx_unlock_spin(&xlr_pic_lock);
229}
230
231static __inline void
232pic_set_timer(int timer, uint64_t maxval)
233{
234	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
235
236	xlr_write_reg(mmio, PIC_TIMER_MAXVAL_0(timer),
237	    (maxval & 0xffffffff));
238	xlr_write_reg(mmio, PIC_TIMER_MAXVAL_1(timer),
239	    (maxval >> 32) & 0xffffffff);
240}
241
242static __inline uint32_t
243pic_timer_count32(int timer)
244 {
245	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
246
247	return (xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer)));
248}
249
250/*
251 * The timer can wrap 32 bits between the two reads, so we
252 * need additional logic to detect that.
253 */
254static __inline uint64_t
255pic_timer_count(int timer)
256{
257	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
258	uint32_t tu1, tu2, tl;
259
260	tu1 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer));
261	tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
262	tu2 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer));
263	if (tu2 != tu1)
264		tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
265	return (((uint64_t)tu2 << 32) | tl);
266}
267
268#endif	/* _RMI_PIC_H_ */
269