xref: /freebsd-10.1-release/sys/mips/rmi/msgring_xls.cfg

/*********************************************************************
 *
 * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
 * reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in
 * the documentation and/or other materials provided with the
 * distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 *
 * *****************************RMI_2**********************************/


/* 
 * This file defines the message ring configuration for XLS two core. It tries to allow 
 * many different point-point communications between the message stations on the message ring
 * and as result is _not_ the best configuration for performance
 *
 * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
 * security engine and the general purpose DMA engines. It provides a high bandwidth,
 * low latency communication links. On traditional processors, this communication goes through
 * which inherently does not scale very well with increasing number of cpus. 
 * 
 * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
 * have software configured credits to send messages to any agent. Every receiving agent on the
 * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is 
 * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits 
 * across all sending agents should not exceed the bucket size. 
 *
 * Below are the receiving agents and the max number of buckets they can have
 * 	CPU 0	: 8 buckets
 * 	CPU 1	: 8 buckets
 * 
 *	GMAC	: 8 buckets	
 *	
 *	SEC	: 8 buckets
 * 
 *	DMA	: 8 buckets
 * 
 *	CMP	: Currently disabled. 
 *
 * The bucket size of a bucket should be aligned to the bucket's starting index in that
 * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station 
 * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
 *
 * The format of the file is pretty straight forward. Each bucket definition has the size
 * and the list of sending agents to that bucket with the number of credits to send.
 * 
 * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
 *
 *  Following are the currently supported bucket names
 *  cpu_0_0
 *  cpu_0_1
 *  cpu_0_2
 *  cpu_0_3
 *  cpu_0_4
 *  cpu_0_5
 *  cpu_0_6
 *  cpu_0_7
 *  
 *  cpu_1_0
 *  cpu_1_1
 *  cpu_1_2
 *  cpu_1_3
 *  cpu_1_4
 *  cpu_1_5
 *  cpu_1_6
 *  cpu_1_7
 *
 *  enabled only for xls-b0
 *  cpu_2_0
 *  cpu_2_1
 *  cpu_2_2
 *  cpu_2_3
 *  cpu_2_4
 *  cpu_2_5
 *  cpu_2_6
 *  cpu_2_7
 *  
 *  enabled only for xls-b0
 *  cpu_3_0
 *  cpu_3_1
 *  cpu_3_2
 *  cpu_3_3
 *  cpu_3_4
 *  cpu_3_5
 *  cpu_3_6
 *  cpu_3_7
 *
 *  gmac0_rfr
 *  gmac0_tx_0
 *  gmac0_tx_1
 *  gmac0_tx_2
 *  gmac0_tx_3
 *  
 *  gmac1_rfr
 *  gmac1_tx_0
 *  gmac1_tx_1
 *  gmac1_tx_2
 *  gmac1_tx_3
 *
 *  sec_pipe_0
 *  sec_rsa
 *
 * Following are the currently supported Tx Agent/Station names
 *
 *  tx_stn_cpu_0
 *  tx_stn_cpu_1
 *
 *  tx_stn_gmac0
 *  tx_stn_gmac1
 *
 *  tx_stn_dma
 *
 *  tx_stn_sec
 *
 * 
 */

/*************************************************************/
// CPU_0 Message Station 

bucket "cpu_0_0" { 
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  6;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
	"tx_stn_cpu_0" 1;
        "tx_stn_cpu_1" 1; /* NEEDED BY RMIOS IPSEC */
}
bucket "cpu_0_1" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_0_2" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_0_3" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_0_4" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_0_5" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_0_6" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_0_7" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}

/*************************************************************/
// CPU_1 Message Station 

bucket "cpu_1_0" { 
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_1_1" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_1_2" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_1_3" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  4;
	"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
        "tx_stn_dma" 2;
        "tx_stn_cmp" 2;
}
bucket "cpu_1_4" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_1_5" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_1_6" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}
bucket "cpu_1_7" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
        "tx_stn_cmp" 4;
}

/*************************************************************/
// CPU_2 Message Station 

bucket "cpu_2_0" { 
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_2_1" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_2_2" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_2_3" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  4;
	"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
    "tx_stn_dma" 2;
    "tx_stn_cmp" 2;
}
bucket "cpu_2_4" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_2_5" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_2_6" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_2_7" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}


/*************************************************************/
// CPU_3 Message Station 
bucket "cpu_3_0" { 
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_3_1" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_3_2" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_3_3" { 
	size 32; 
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_sec"  4;
	"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
    "tx_stn_dma" 2;
    "tx_stn_cmp" 2;
}
bucket "cpu_3_4" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_3_5" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_3_6" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}
bucket "cpu_3_7" {
	size 32;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
	"tx_stn_dma" 4;
    "tx_stn_cmp" 4;
}

/*************************************************************/

// GMAC Message Station 

bucket "gmac0_rfr" {
	size 32;
	"tx_stn_cpu_0" 4;
	"tx_stn_cpu_1" 4;
	"tx_stn_cpu_2" 4;
	"tx_stn_cpu_3" 4;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
}

bucket "gmac0_tx_0" {
	size 32;
	"tx_stn_cpu_0" 8;
	"tx_stn_cpu_1" 8;
	"tx_stn_cpu_2" 8;
	"tx_stn_cpu_3" 8;
}

bucket "gmac0_tx_1" {
	size 32;
	"tx_stn_cpu_0" 8;
	"tx_stn_cpu_1" 8;
	"tx_stn_cpu_2" 8;
	"tx_stn_cpu_3" 8;
}

bucket "gmac0_tx_2" {
	size 32;
	"tx_stn_cpu_0" 8;
	"tx_stn_cpu_1" 8;
	"tx_stn_cpu_2" 8;
	"tx_stn_cpu_3" 8;
}

bucket "gmac0_tx_3" {
	size 32;
	"tx_stn_cpu_0" 8;
	"tx_stn_cpu_1" 8;
	"tx_stn_cpu_2" 8;
	"tx_stn_cpu_3" 8;
}

bucket "gmac1_rfr" {
	size 32;
	"tx_stn_cpu_0" 4;
	"tx_stn_cpu_1" 4;
	"tx_stn_cpu_2" 4;
	"tx_stn_cpu_3" 4;
	"tx_stn_gmac0" 8;
	"tx_stn_gmac1" 8;
}

bucket "gmac1_tx_0" {
	size 32;
	"tx_stn_cpu_0" 8;
	"tx_stn_cpu_1" 8;
	"tx_stn_cpu_2" 8;
	"tx_stn_cpu_3" 8;
}

bucket "gmac1_tx_1" {
	size 32;
	"tx_stn_cpu_0" 8;
	"tx_stn_cpu_1" 8;
	"tx_stn_cpu_2" 8;
	"tx_stn_cpu_3" 8;
}

bucket "gmac1_tx_2" {
	size 32;
	"tx_stn_cpu_0" 8;
	"tx_stn_cpu_1" 8;
	"tx_stn_cpu_2" 8;
	"tx_stn_cpu_3" 8;
}

bucket "gmac1_tx_3" {
	size 32;
	"tx_stn_cpu_0" 8;
	"tx_stn_cpu_1" 8;
	"tx_stn_cpu_2" 8;
	"tx_stn_cpu_3" 8;
}

/*************************************************************/
// Security Message Station 

bucket "sec_pipe_0" {
	size 128;
	"tx_stn_cpu_0" 32;
	"tx_stn_cpu_1" 32;
	"tx_stn_cpu_2" 32;
	"tx_stn_cpu_3" 32;
}

bucket "sec_rsa_ecc" {
	size 128;
	"tx_stn_cpu_0" 32;
	"tx_stn_cpu_1" 32;
	"tx_stn_cpu_2" 32;
	"tx_stn_cpu_3" 32;
}

bucket "dma_rsvd_0" {
	size 64;
	"tx_stn_cpu_0" 16;
	"tx_stn_cpu_1" 16;
	"tx_stn_cpu_2" 16;
	"tx_stn_cpu_3" 16;
}
bucket "dma_rsvd_1" {
	size 64;
	"tx_stn_cpu_0" 16;
	"tx_stn_cpu_1" 16;
	"tx_stn_cpu_2" 16;
	"tx_stn_cpu_3" 16;
}

bucket "dma_rsvd_2" {
	size 64;
	"tx_stn_cpu_0" 16;
	"tx_stn_cpu_1" 16;
	"tx_stn_cpu_2" 16;
	"tx_stn_cpu_3" 16;
}

bucket "dma_rsvd_3" {
	size 64;
	"tx_stn_cpu_0" 16;
	"tx_stn_cpu_1" 16;
	"tx_stn_cpu_2" 16;
	"tx_stn_cpu_3" 16;
}

/*************************************************************/
// Compression Message Station

bucket "cmp_0" {
        size 32; 
        "tx_stn_cpu_0" 16;
        "tx_stn_cpu_1" 16;
}

bucket "cmp_1" { 
        size 32;
        "tx_stn_cpu_0" 16;
        "tx_stn_cpu_1" 16;
}

bucket "cmp_2" {
        size 32; 
        "tx_stn_cpu_0" 16;
        "tx_stn_cpu_1" 16;
}

bucket "cmp_3" {      
        size 32;
        "tx_stn_cpu_0" 16;
        "tx_stn_cpu_1" 16;
}