177943Sdfr/*-
277943Sdfr * Copyright (c) 2003-2009 RMI Corporation
377943Sdfr * All rights reserved.
477943Sdfr *
577943Sdfr * Redistribution and use in source and binary forms, with or without
677943Sdfr * modification, are permitted provided that the following conditions
777943Sdfr * are met:
877943Sdfr * 1. Redistributions of source code must retain the above copyright
977943Sdfr *    notice, this list of conditions and the following disclaimer.
1077943Sdfr * 2. Redistributions in binary form must reproduce the above copyright
1177943Sdfr *    notice, this list of conditions and the following disclaimer in the
1277943Sdfr *    documentation and/or other materials provided with the distribution.
1377943Sdfr * 3. Neither the name of RMI Corporation, nor the names of its contributors,
1477943Sdfr *    may be used to endorse or promote products derived from this software
1577943Sdfr *    without specific prior written permission.
1677943Sdfr *
1777943Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
1877943Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1977943Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2077943Sdfr * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
2177943Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2277943Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2377943Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2477943Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2577943Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2677943Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27113038Sobrien * SUCH DAMAGE.
28113038Sobrien *
2978327Sobrien * RMI_BSD
3077943Sdfr * $FreeBSD$
3177943Sdfr */
3277943Sdfr#ifndef _RMI_IOMAP_H_
3377943Sdfr#define _RMI_IOMAP_H_
3477943Sdfr
3577943Sdfr#include <machine/endian.h>
3677943Sdfr#define XLR_DEVICE_REGISTER_BASE	0x1EF00000
3777943Sdfr#define DEFAULT_XLR_IO_BASE 0xffffffffbef00000ULL
38294445Semaste#define XLR_IO_SIZE                   0x1000
39294445Semaste
40294445Semaste#define XLR_IO_BRIDGE_OFFSET          0x00000
41294445Semaste
42294445Semaste#define XLR_IO_DDR2_CHN0_OFFSET       0x01000
43294445Semaste#define XLR_IO_DDR2_CHN1_OFFSET       0x02000
44294445Semaste#define XLR_IO_DDR2_CHN2_OFFSET       0x03000
45294445Semaste#define XLR_IO_DDR2_CHN3_OFFSET       0x04000
46294445Semaste
47294445Semaste#define XLR_IO_RLD2_CHN0_OFFSET       0x05000
48294445Semaste#define XLR_IO_RLD2_CHN1_OFFSET       0x06000
49294445Semaste
50294981Ssmh#define XLR_IO_SRAM_OFFSET            0x07000
51294981Ssmh
52294445Semaste#define XLR_IO_PIC_OFFSET             0x08000
53294445Semaste#define XLR_IO_PCIX_OFFSET            0x09000
54294445Semaste#define XLR_IO_HT_OFFSET              0x0A000
55294445Semaste
56294445Semaste#define XLR_IO_SECURITY_OFFSET        0x0B000
57294445Semaste
58294445Semaste#define XLR_IO_GMAC_0_OFFSET          0x0C000
59294445Semaste#define XLR_IO_GMAC_1_OFFSET          0x0D000
60294445Semaste#define XLR_IO_GMAC_2_OFFSET          0x0E000
61294445Semaste#define XLR_IO_GMAC_3_OFFSET          0x0F000
62294445Semaste
63294445Semaste#define XLR_IO_SPI4_0_OFFSET          0x10000
64294445Semaste#define XLR_IO_XGMAC_0_OFFSET         0x11000
65294445Semaste#define XLR_IO_SPI4_1_OFFSET          0x12000
66294445Semaste#define XLR_IO_XGMAC_1_OFFSET         0x13000
67294445Semaste
68294445Semaste#define XLR_IO_UART_0_OFFSET          0x14000
69294445Semaste#define XLR_IO_UART_1_OFFSET          0x15000
70294445Semaste#define XLR_UART0ADDR                 (XLR_IO_UART_0_OFFSET+XLR_DEVICE_REGISTER_BASE)
71294445Semaste
72294445Semaste
73294445Semaste
74294445Semaste#define XLR_IO_I2C_0_OFFSET           0x16000
75294445Semaste#define XLR_IO_I2C_1_OFFSET           0x17000
76294445Semaste
77294445Semaste#define XLR_IO_GPIO_OFFSET            0x18000
78294445Semaste
79294445Semaste#define XLR_IO_FLASH_OFFSET           0x19000
80294445Semaste
81294445Semaste#define XLR_IO_TB_OFFSET           	  0x1C000
82294445Semaste
83294445Semaste#define XLR_IO_GMAC_4_OFFSET          0x20000
84294445Semaste#define XLR_IO_GMAC_5_OFFSET          0x21000
85294445Semaste#define XLR_IO_GMAC_6_OFFSET          0x22000
86294445Semaste#define XLR_IO_GMAC_7_OFFSET          0x23000
87294445Semaste
88294445Semaste#define XLR_IO_PCIE_0_OFFSET          0x1E000
89294445Semaste#define XLR_IO_PCIE_1_OFFSET          0x1F000
90294445Semaste
91294445Semaste#define XLR_IO_USB_0_OFFSET           0x24000
92294445Semaste#define XLR_IO_USB_1_OFFSET           0x25000
93294445Semaste
94294445Semaste#define XLR_IO_COMP_OFFSET            0x1d000
95294445Semaste
96294445Semaste/* Base Address (Virtual) of the PCI Config address space
97294445Semaste * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
98294445Semaste * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
99294445Semaste * ie 1<<24 = 16M
100294445Semaste */
101294445Semaste#define DEFAULT_PCI_CONFIG_BASE         0x18000000
102294445Semaste#define DEFAULT_HT_TYPE0_CFG_BASE       0x16000000
10377943Sdfr#define DEFAULT_HT_TYPE1_CFG_BASE       0x17000000
10477943Sdfr
10577943Sdfrtypedef volatile __uint32_t xlr_reg_t;
10677943Sdfrextern unsigned long xlr_io_base;
10777943Sdfr
10877943Sdfr#define xlr_io_mmio(offset) ((xlr_reg_t *)(xlr_io_base+(offset)))
10977943Sdfr
11077943Sdfr#define xlr_read_reg(base, offset) (__ntohl((base)[(offset)]))
11177943Sdfr#define xlr_write_reg(base, offset, value) ((base)[(offset)] = __htonl((value)))
11277943Sdfr
11377943Sdfrextern void on_chip_init(void);
114294445Semaste
115294445Semaste#endif				/* _RMI_IOMAP_H_ */
116294445Semaste