1224110Sjchandra/*- 2224110Sjchandra * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3224110Sjchandra * reserved. 4224110Sjchandra * 5224110Sjchandra * Redistribution and use in source and binary forms, with or without 6224110Sjchandra * modification, are permitted provided that the following conditions are 7224110Sjchandra * met: 8224110Sjchandra * 9224110Sjchandra * 1. Redistributions of source code must retain the above copyright 10224110Sjchandra * notice, this list of conditions and the following disclaimer. 11224110Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12224110Sjchandra * notice, this list of conditions and the following disclaimer in 13224110Sjchandra * the documentation and/or other materials provided with the 14224110Sjchandra * distribution. 15224110Sjchandra * 16224110Sjchandra * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17224110Sjchandra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18224110Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19224110Sjchandra * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20224110Sjchandra * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21224110Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22224110Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23224110Sjchandra * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24224110Sjchandra * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25224110Sjchandra * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26224110Sjchandra * THE POSSIBILITY OF SUCH DAMAGE. 27224110Sjchandra * 28225394Sjchandra * NETLOGIC_BSD 29224110Sjchandra * $FreeBSD$ 30225394Sjchandra */ 31224110Sjchandra 32225394Sjchandra#ifndef __NLM_HAL_SYS_H__ 33233533Sjchandra#define __NLM_HAL_SYS_H__ 34224110Sjchandra 35224110Sjchandra/** 36224110Sjchandra* @file_name sys.h 37224110Sjchandra* @author Netlogic Microsystems 38224110Sjchandra* @brief HAL for System configuration registers 39224110Sjchandra*/ 40225394Sjchandra#define SYS_CHIP_RESET 0x00 41225394Sjchandra#define SYS_POWER_ON_RESET_CFG 0x01 42225394Sjchandra#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 43225394Sjchandra#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 44225394Sjchandra#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 45225394Sjchandra#define SYS_EFUSE_DEVICE_CFG3 0x05 46225394Sjchandra#define SYS_EFUSE_DEVICE_CFG4 0x06 47225394Sjchandra#define SYS_EFUSE_DEVICE_CFG5 0x07 48225394Sjchandra#define SYS_EFUSE_DEVICE_CFG6 0x08 49225394Sjchandra#define SYS_EFUSE_DEVICE_CFG7 0x09 50225394Sjchandra#define SYS_PLL_CTRL 0x0a 51225394Sjchandra#define SYS_CPU_RESET 0x0b 52225394Sjchandra#define SYS_CPU_NONCOHERENT_MODE 0x0d 53225394Sjchandra#define SYS_CORE_DFS_DIS_CTRL 0x0e 54225394Sjchandra#define SYS_CORE_DFS_RST_CTRL 0x0f 55225394Sjchandra#define SYS_CORE_DFS_BYP_CTRL 0x10 56225394Sjchandra#define SYS_CORE_DFS_PHA_CTRL 0x11 57225394Sjchandra#define SYS_CORE_DFS_DIV_INC_CTRL 0x12 58225394Sjchandra#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 59225394Sjchandra#define SYS_CORE_DFS_DIV_VALUE 0x14 60225394Sjchandra#define SYS_RESET 0x15 61225394Sjchandra#define SYS_DFS_DIS_CTRL 0x16 62225394Sjchandra#define SYS_DFS_RST_CTRL 0x17 63225394Sjchandra#define SYS_DFS_BYP_CTRL 0x18 64225394Sjchandra#define SYS_DFS_DIV_INC_CTRL 0x19 65225394Sjchandra#define SYS_DFS_DIV_DEC_CTRL 0x1a 66225394Sjchandra#define SYS_DFS_DIV_VALUE0 0x1b 67225394Sjchandra#define SYS_DFS_DIV_VALUE1 0x1c 68225394Sjchandra#define SYS_SENSE_AMP_DLY 0x1d 69225394Sjchandra#define SYS_SOC_SENSE_AMP_DLY 0x1e 70225394Sjchandra#define SYS_CTRL0 0x1f 71225394Sjchandra#define SYS_CTRL1 0x20 72225394Sjchandra#define SYS_TIMEOUT_BS1 0x21 73225394Sjchandra#define SYS_BYTE_SWAP 0x22 74225394Sjchandra#define SYS_VRM_VID 0x23 75225394Sjchandra#define SYS_PWR_RAM_CMD 0x24 76225394Sjchandra#define SYS_PWR_RAM_ADDR 0x25 77225394Sjchandra#define SYS_PWR_RAM_DATA0 0x26 78225394Sjchandra#define SYS_PWR_RAM_DATA1 0x27 79225394Sjchandra#define SYS_PWR_RAM_DATA2 0x28 80225394Sjchandra#define SYS_PWR_UCODE 0x29 81225394Sjchandra#define SYS_CPU0_PWR_STATUS 0x2a 82225394Sjchandra#define SYS_CPU1_PWR_STATUS 0x2b 83225394Sjchandra#define SYS_CPU2_PWR_STATUS 0x2c 84225394Sjchandra#define SYS_CPU3_PWR_STATUS 0x2d 85225394Sjchandra#define SYS_CPU4_PWR_STATUS 0x2e 86225394Sjchandra#define SYS_CPU5_PWR_STATUS 0x2f 87225394Sjchandra#define SYS_CPU6_PWR_STATUS 0x30 88225394Sjchandra#define SYS_CPU7_PWR_STATUS 0x31 89225394Sjchandra#define SYS_STATUS 0x32 90225394Sjchandra#define SYS_INT_POL 0x33 91225394Sjchandra#define SYS_INT_TYPE 0x34 92225394Sjchandra#define SYS_INT_STATUS 0x35 93225394Sjchandra#define SYS_INT_MASK0 0x36 94225394Sjchandra#define SYS_INT_MASK1 0x37 95225394Sjchandra#define SYS_UCO_S_ECC 0x38 96225394Sjchandra#define SYS_UCO_M_ECC 0x39 97225394Sjchandra#define SYS_UCO_ADDR 0x3a 98255368Sjchandra#define SYS_PLL_DFS_BYP_CTRL 0x3a /* Bx stepping */ 99225394Sjchandra#define SYS_UCO_INSTR 0x3b 100225394Sjchandra#define SYS_MEM_BIST0 0x3c 101225394Sjchandra#define SYS_MEM_BIST1 0x3d 102255368Sjchandra#define SYS_PLL_DFS_DIV_VALUE 0x3d /* Bx stepping */ 103225394Sjchandra#define SYS_MEM_BIST2 0x3e 104225394Sjchandra#define SYS_MEM_BIST3 0x3f 105225394Sjchandra#define SYS_MEM_BIST4 0x40 106225394Sjchandra#define SYS_MEM_BIST5 0x41 107225394Sjchandra#define SYS_MEM_BIST6 0x42 108225394Sjchandra#define SYS_MEM_BIST7 0x43 109225394Sjchandra#define SYS_MEM_BIST8 0x44 110225394Sjchandra#define SYS_MEM_BIST9 0x45 111225394Sjchandra#define SYS_MEM_BIST10 0x46 112225394Sjchandra#define SYS_MEM_BIST11 0x47 113225394Sjchandra#define SYS_MEM_BIST12 0x48 114225394Sjchandra#define SYS_SCRTCH0 0x49 115225394Sjchandra#define SYS_SCRTCH1 0x4a 116225394Sjchandra#define SYS_SCRTCH2 0x4b 117225394Sjchandra#define SYS_SCRTCH3 0x4c 118224110Sjchandra 119224110Sjchandra#if !defined(LOCORE) && !defined(__ASSEMBLY__) 120224110Sjchandra 121225394Sjchandra#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 122225394Sjchandra#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) 123225394Sjchandra#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 124225394Sjchandra#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 125224110Sjchandra 126233533Sjchandraenum { 127233533Sjchandra /* Don't change order and it must start from zero */ 128233533Sjchandra DFS_DEVICE_NAE = 0, 129233533Sjchandra DFS_DEVICE_SAE, 130233533Sjchandra DFS_DEVICE_RSA, 131233533Sjchandra DFS_DEVICE_DTRE, 132233533Sjchandra DFS_DEVICE_CMP, 133233533Sjchandra DFS_DEVICE_KBP, 134233533Sjchandra DFS_DEVICE_DMC, 135233533Sjchandra DFS_DEVICE_NAND, 136233533Sjchandra DFS_DEVICE_MMC, 137233533Sjchandra DFS_DEVICE_NOR, 138233533Sjchandra DFS_DEVICE_CORE, 139233533Sjchandra DFS_DEVICE_REGEX_SLOW, 140233533Sjchandra DFS_DEVICE_REGEX_FAST, 141233533Sjchandra DFS_DEVICE_SATA, 142233533Sjchandra INVALID_DFS_DEVICE = 0xFF 143233533Sjchandra}; 144233533Sjchandra 145245879Sjchandrastatic __inline 146245879Sjchandravoid nlm_sys_enable_block(uint64_t sys_base, int block) 147245879Sjchandra{ 148245879Sjchandra uint32_t dfsdis, mask; 149245879Sjchandra 150245879Sjchandra mask = 1 << block; 151245879Sjchandra dfsdis = nlm_read_sys_reg(sys_base, SYS_DFS_DIS_CTRL); 152245879Sjchandra if ((dfsdis & mask) == 0) 153245879Sjchandra return; /* already enabled, nothing to do */ 154245879Sjchandra dfsdis &= ~mask; 155245879Sjchandra nlm_write_sys_reg(sys_base, SYS_DFS_DIS_CTRL, dfsdis); 156245879Sjchandra} 157245879Sjchandra 158224110Sjchandra#endif 159224110Sjchandra#endif 160