nlm_hal.c revision 227783 
1/*-
2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
3 * reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in
13 *    the documentation and/or other materials provided with the
14 *    distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * NETLOGIC_BSD */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/mips/nlm/hal/nlm_hal.c 227783 2011-11-21 08:12:36Z jchandra $");
32#include <sys/param.h>
33#include <sys/types.h>
34#include <sys/systm.h>
35
36#include <mips/nlm/hal/mips-extns.h>
37#include <mips/nlm/hal/haldefs.h>
38#include <mips/nlm/hal/iomap.h>
39#include <mips/nlm/hal/sys.h>
40#include <mips/nlm/hal/pic.h>
41#include <mips/nlm/xlp.h>
42
43#include <mips/nlm/hal/uart.h>
44#include <mips/nlm/hal/mmu.h>
45#include <mips/nlm/hal/pcibus.h>
46#include <mips/nlm/hal/usb.h>
47
48int pic_irt_ehci0;
49int pic_irt_ehci1;
50int pic_irt_uart0;
51int pic_irt_uart1;
52int pic_irt_pcie_lnk0;
53int pic_irt_pcie_lnk1;
54int pic_irt_pcie_lnk2;
55int pic_irt_pcie_lnk3;
56
57uint32_t
58xlp_get_cpu_frequency(int core)
59{
60	uint64_t sysbase = nlm_get_sys_regbase(nlm_nodeid());
61	uint64_t num;
62	unsigned int pll_divf, pll_divr, dfs_div, ext_div;
63	unsigned int rstval, dfsval, denom;
64
65	rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
66	dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
67	pll_divf = ((rstval >> 10) & 0x7f) + 1;
68	pll_divr = ((rstval >> 8)  & 0x3) + 1;
69	ext_div  = ((rstval >> 30) & 0x3) + 1;
70	dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;
71
72	num = 800000000ULL * pll_divf;
73	denom = 3 * pll_divr * ext_div * dfs_div;
74	num = num/denom;
75	return (num);
76}
77
78void
79nlm_pic_irt_init(void)
80{
81	pic_irt_ehci0 = nlm_irtstart(nlm_get_usb_pcibase(nlm_nodeid(), 0));
82	pic_irt_ehci1 = nlm_irtstart(nlm_get_usb_pcibase(nlm_nodeid(), 3));
83	pic_irt_uart0 = nlm_irtstart(nlm_get_uart_pcibase(nlm_nodeid(), 0));
84	pic_irt_uart1 = nlm_irtstart(nlm_get_uart_pcibase(nlm_nodeid(), 1));
85
86	/* Hardcoding the PCIE IRT information as PIC doesn't
87	   understand any value other than 78,79,80,81 for PCIE0/1/2/3 */
88	pic_irt_pcie_lnk0 = 78;
89	pic_irt_pcie_lnk1 = 79;
90	pic_irt_pcie_lnk2 = 80;
91	pic_irt_pcie_lnk3 = 81;
92}
93/*
94 * Find the IRQ for the link, each link has a different interrupt
95 * at the XLP pic
96 */
97int xlp_pcie_link_irt(int link)
98{
99
100	if( (link < 0) || (link > 3))
101		return (-1);
102
103	return (pic_irt_pcie_lnk0 + link);
104}
105
106int
107xlp_irt_to_irq(int irt)
108{
109	if (irt == pic_irt_ehci0)
110	    return PIC_EHCI_0_IRQ;
111	else if (irt == pic_irt_ehci1)
112	    return PIC_EHCI_1_IRQ;
113	else if (irt == pic_irt_uart0)
114	    return PIC_UART_0_IRQ;
115	else if (irt == pic_irt_uart1)
116	    return PIC_UART_1_IRQ;
117	else if (irt == pic_irt_pcie_lnk0)
118	    return PIC_PCIE_0_IRQ;
119	else if (irt == pic_irt_pcie_lnk1)
120	    return PIC_PCIE_1_IRQ;
121	else if (irt == pic_irt_pcie_lnk2)
122	    return PIC_PCIE_2_IRQ;
123	else if (irt == pic_irt_pcie_lnk3)
124	    return PIC_PCIE_3_IRQ;
125	else {
126	    printf("Cannot find irq for IRT %d\n", irt);
127	    return 0;
128	 }
129}
130
131int
132xlp_irq_to_irt(int irq)
133{
134	switch (irq) {
135 		case PIC_EHCI_0_IRQ :
136 			return pic_irt_ehci0;
137 		case PIC_EHCI_1_IRQ :
138 			return pic_irt_ehci1;
139		case PIC_UART_0_IRQ :
140			return pic_irt_uart0;
141		case PIC_UART_1_IRQ :
142			return pic_irt_uart1;
143		case PIC_PCIE_0_IRQ :
144			return pic_irt_pcie_lnk0;
145		case PIC_PCIE_1_IRQ :
146			return pic_irt_pcie_lnk1;
147		case PIC_PCIE_2_IRQ :
148			return pic_irt_pcie_lnk2;
149		case PIC_PCIE_3_IRQ :
150			return pic_irt_pcie_lnk3;
151		default: panic("Bad IRQ %d\n", irq);
152	}
153}
154
155int
156xlp_irq_is_picintr(int irq)
157{
158	switch (irq) {
159		case PIC_MMC_IRQ : return 1;
160 		case PIC_EHCI_0_IRQ : return 1;
161 		case PIC_EHCI_1_IRQ : return 1;
162		case PIC_UART_0_IRQ : return 1;
163		case PIC_UART_1_IRQ : return 1;
164		case PIC_PCIE_0_IRQ : return 1;
165		case PIC_PCIE_1_IRQ : return 1;
166		case PIC_PCIE_2_IRQ : return 1;
167		case PIC_PCIE_3_IRQ : return 1;
168		default: return 0;
169	}
170}
171