pte.h revision 209929
1178172Simp/*- 2209243Sjchandra * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org> 3209243Sjchandra * All rights reserved. 4178172Simp * 5178172Simp * Redistribution and use in source and binary forms, with or without 6178172Simp * modification, are permitted provided that the following conditions 7178172Simp * are met: 8178172Simp * 1. Redistributions of source code must retain the above copyright 9178172Simp * notice, this list of conditions and the following disclaimer. 10178172Simp * 2. Redistributions in binary form must reproduce the above copyright 11178172Simp * notice, this list of conditions and the following disclaimer in the 12178172Simp * documentation and/or other materials provided with the distribution. 13178172Simp * 14209243Sjchandra * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17209243Sjchandra * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24178172Simp * SUCH DAMAGE. 25178172Simp * 26178172Simp * $FreeBSD: head/sys/mips/include/pte.h 209929 2010-07-12 07:42:42Z jchandra $ 27178172Simp */ 28178172Simp 29209243Sjchandra#ifndef _MACHINE_PTE_H_ 30178172Simp#define _MACHINE_PTE_H_ 31178172Simp 32209805Sjchandra#ifndef _LOCORE 33209805Sjchandra/* pt_entry_t is 32 bit for now, has to be made 64 bit for n64 */ 34209805Sjchandratypedef uint32_t pt_entry_t; 35209805Sjchandratypedef pt_entry_t *pd_entry_t; 36209805Sjchandra#endif 37209805Sjchandra 38209243Sjchandra/* 39209243Sjchandra * TLB and PTE management. Most things operate within the context of 40209243Sjchandra * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi 41209482Sjchandra * start with TLBHI_. PTE bits begin with PTE_. 42209243Sjchandra * 43209243Sjchandra * Note that we use the same size VM and TLB pages. 44209243Sjchandra */ 45209243Sjchandra#define TLB_PAGE_SHIFT (PAGE_SHIFT) 46209243Sjchandra#define TLB_PAGE_SIZE (1 << TLB_PAGE_SHIFT) 47209243Sjchandra#define TLB_PAGE_MASK (TLB_PAGE_SIZE - 1) 48178172Simp 49178172Simp/* 50209243Sjchandra * TLB PageMask register. Has mask bits set above the default, 4K, page mask. 51178172Simp */ 52209243Sjchandra#define TLBMASK_SHIFT (13) 53209243Sjchandra#define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT) 54178172Simp 55178172Simp/* 56209243Sjchandra * PFN for EntryLo register. Upper bits are 0, which is to say that 57209243Sjchandra * bit 29 is the last hardware bit; Bits 30 and upwards (EntryLo is 58209243Sjchandra * 64 bit though it can be referred to in 32-bits providing 2 software 59209243Sjchandra * bits safely. We use it as 64 bits to get many software bits, and 60209243Sjchandra * god knows what else.) are unacknowledged by hardware. They may be 61209243Sjchandra * written as anything, but otherwise they have as much meaning as 62209243Sjchandra * other 0 fields. 63178172Simp */ 64209243Sjchandra#define TLBLO_SWBITS_SHIFT (30) 65209243Sjchandra#define TLBLO_SWBITS_MASK (0x3U << TLBLO_SWBITS_SHIFT) 66209243Sjchandra#define TLBLO_PFN_SHIFT (6) 67209243Sjchandra#define TLBLO_PFN_MASK (0x3FFFFFC0) 68209243Sjchandra#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK) 69209243Sjchandra#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT) 70209243Sjchandra#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK) 71209243Sjchandra#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte)))) 72209482Sjchandra 73209243Sjchandra/* 74209805Sjchandra * XXX This comment is not correct for anything more modern than R4K. 75209805Sjchandra * 76209243Sjchandra * VPN for EntryHi register. Upper two bits select user, supervisor, 77209243Sjchandra * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to 78209243Sjchandra * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12 79209243Sjchandra * to bit 8 there is a 5-bit 0 field. Low byte is ASID. 80209243Sjchandra * 81209805Sjchandra * XXX This comment is not correct for FreeBSD. 82209243Sjchandra * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. 83209243Sjchandra */ 84209243Sjchandra#define TLBHI_ASID_MASK (0xff) 85209929Sjchandra#if defined(__mips_n64) 86209929Sjchandra#define TLBHI_R_SHIFT 62 87209929Sjchandra#define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT) 88209929Sjchandra#define TLBHI_R_SUPERVISOR (0x01UL << TLBHI_R_SHIFT) 89209929Sjchandra#define TLBHI_R_KERNEL (0x03UL << TLBHI_R_SHIFT) 90209929Sjchandra#define TLBHI_R_MASK (0x03UL << TLBHI_R_SHIFT) 91209929Sjchandra#define TLBHI_VA_R(va) ((va) & TLBHI_R_MASK) 92209929Sjchandra#define TLBHI_FILL_SHIFT 40 93209929Sjchandra#define TLBHI_VPN2_SHIFT (TLB_PAGE_SHIFT + 1) 94209929Sjchandra#define TLBHI_VPN2_MASK (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT)) 95209929Sjchandra#define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK) 96209929Sjchandra#define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \ 97209929Sjchandra (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \ 98209929Sjchandra ((asid) & TLBHI_ASID_MASK)) 99209929Sjchandra#else 100209645Sjchandra#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) 101209645Sjchandra#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) 102209929Sjchandra#endif 103178172Simp 104209482Sjchandra/* 105209482Sjchandra * TLB flags managed in hardware: 106209482Sjchandra * C: Cache attribute. 107209482Sjchandra * D: Dirty bit. This means a page is writable. It is not 108209482Sjchandra * set at first, and a write is trapped, and the dirty 109209482Sjchandra * bit is set. See also PTE_RO. 110209482Sjchandra * V: Valid bit. Obvious, isn't it? 111209482Sjchandra * G: Global bit. This means that this mapping is present 112209482Sjchandra * in EVERY address space, and to ignore the ASID when 113209482Sjchandra * it is matched. 114209482Sjchandra */ 115209482Sjchandra#define PTE_C(attr) ((attr & 0x07) << 3) 116209482Sjchandra#define PTE_C_UNCACHED (PTE_C(0x02)) 117209482Sjchandra/* 118209482Sjchandra * The preferred cache attribute for cacheable pages, this can be 119209482Sjchandra * implementation dependent. We will use the standard value 0x3 as 120209482Sjchandra * default. 121209482Sjchandra */ 122209482Sjchandra#if defined(CPU_SB1) 123209482Sjchandra#define PTE_C_CACHE (PTE_C(0x05)) 124202031Simp#else 125209482Sjchandra#define PTE_C_CACHE (PTE_C(0x03)) 126202031Simp#endif 127209482Sjchandra#define PTE_D 0x04 128209482Sjchandra#define PTE_V 0x02 129209482Sjchandra#define PTE_G 0x01 130178172Simp 131209482Sjchandra/* 132209482Sjchandra * VM flags managed in software: 133209482Sjchandra * RO: Read only. Never set PTE_D on this page, and don't 134209482Sjchandra * listen to requests to write to it. 135209482Sjchandra * W: Wired. ??? 136209482Sjchandra */ 137209482Sjchandra#define PTE_RO (0x01 << TLBLO_SWBITS_SHIFT) 138209482Sjchandra#define PTE_W (0x02 << TLBLO_SWBITS_SHIFT) 139178172Simp 140209482Sjchandra/* 141209482Sjchandra * PTE management functions for bits defined above. 142209482Sjchandra * 143209482Sjchandra * XXX Can make these atomics, but some users of them are using PTEs in local 144209482Sjchandra * registers and such and don't need the overhead. 145209482Sjchandra */ 146209482Sjchandra#define pte_clear(pte, bit) (*(pte) &= ~(bit)) 147209482Sjchandra#define pte_set(pte, bit) (*(pte) |= (bit)) 148209482Sjchandra#define pte_test(pte, bit) ((*(pte) & (bit)) == (bit)) 149178172Simp 150209243Sjchandra#endif /* !_MACHINE_PTE_H_ */ 151