pmap.c revision 251703
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 251703 2013-06-13 20:46:03Z jeff $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * Since the information managed by this module is 84 * also stored by the logical address mapping module, 85 * this module may throw away valid virtual-to-physical 86 * mappings at almost any time. However, invalidations 87 * of virtual-to-physical mappings must be done as 88 * requested. 89 * 90 * In order to cope with hardware architectures which 91 * make virtual-to-physical map invalidates expensive, 92 * this module may delay invalidate or reduced protection 93 * operations until such time as they are actually 94 * necessary. This module is given full information as 95 * to which processors are currently using which maps, 96 * and to when physical maps must be made correct. 97 */ 98 99#include "opt_cpu.h" 100#include "opt_pmap.h" 101#include "opt_smp.h" 102#include "opt_xbox.h" 103 104#include <sys/param.h> 105#include <sys/systm.h> 106#include <sys/kernel.h> 107#include <sys/ktr.h> 108#include <sys/lock.h> 109#include <sys/malloc.h> 110#include <sys/mman.h> 111#include <sys/msgbuf.h> 112#include <sys/mutex.h> 113#include <sys/proc.h> 114#include <sys/rwlock.h> 115#include <sys/sf_buf.h> 116#include <sys/sx.h> 117#include <sys/vmmeter.h> 118#include <sys/sched.h> 119#include <sys/sysctl.h> 120#ifdef SMP 121#include <sys/smp.h> 122#else 123#include <sys/cpuset.h> 124#endif 125 126#include <vm/vm.h> 127#include <vm/vm_param.h> 128#include <vm/vm_kern.h> 129#include <vm/vm_page.h> 130#include <vm/vm_map.h> 131#include <vm/vm_object.h> 132#include <vm/vm_extern.h> 133#include <vm/vm_pageout.h> 134#include <vm/vm_pager.h> 135#include <vm/uma.h> 136 137#include <machine/cpu.h> 138#include <machine/cputypes.h> 139#include <machine/md_var.h> 140#include <machine/pcb.h> 141#include <machine/specialreg.h> 142#ifdef SMP 143#include <machine/smp.h> 144#endif 145 146#ifdef XBOX 147#include <machine/xbox.h> 148#endif 149 150#include <xen/interface/xen.h> 151#include <xen/hypervisor.h> 152#include <machine/xen/hypercall.h> 153#include <machine/xen/xenvar.h> 154#include <machine/xen/xenfunc.h> 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#define DIAGNOSTIC 165 166#if !defined(DIAGNOSTIC) 167#ifdef __GNUC_GNU_INLINE__ 168#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 169#else 170#define PMAP_INLINE extern inline 171#endif 172#else 173#define PMAP_INLINE 174#endif 175 176#ifdef PV_STATS 177#define PV_STAT(x) do { x ; } while (0) 178#else 179#define PV_STAT(x) do { } while (0) 180#endif 181 182/* 183 * Get PDEs and PTEs for user/kernel address space 184 */ 185#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 186#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 187 188#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 189#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 190#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 191#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 192#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 193 194#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 195 196#define HAMFISTED_LOCKING 197#ifdef HAMFISTED_LOCKING 198static struct mtx createdelete_lock; 199#endif 200 201struct pmap kernel_pmap_store; 202LIST_HEAD(pmaplist, pmap); 203static struct pmaplist allpmaps; 204static struct mtx allpmaps_lock; 205 206vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 207vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 208int pgeflag = 0; /* PG_G or-in */ 209int pseflag = 0; /* PG_PS or-in */ 210 211int nkpt; 212vm_offset_t kernel_vm_end; 213extern u_int32_t KERNend; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217#endif 218 219static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 220 221static int pat_works; /* Is page attribute table sane? */ 222 223/* 224 * This lock is defined as static in other pmap implementations. It cannot, 225 * however, be defined as static here, because it is (ab)used to serialize 226 * queued page table changes in other sources files. 227 */ 228struct rwlock pvh_global_lock; 229 230/* 231 * Data for the pv entry allocation mechanism 232 */ 233static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 234static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 235static int shpgperproc = PMAP_SHPGPERPROC; 236 237struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 238int pv_maxchunks; /* How many chunks we have KVA for */ 239vm_offset_t pv_vafree; /* freelist stored in the PTE */ 240 241/* 242 * All those kernel PT submaps that BSD is so fond of 243 */ 244struct sysmaps { 245 struct mtx lock; 246 pt_entry_t *CMAP1; 247 pt_entry_t *CMAP2; 248 caddr_t CADDR1; 249 caddr_t CADDR2; 250}; 251static struct sysmaps sysmaps_pcpu[MAXCPU]; 252static pt_entry_t *CMAP3; 253caddr_t ptvmmap = 0; 254static caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_chunk(struct pv_chunk *pc); 282static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 283static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 284static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 285static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 286 vm_offset_t va); 287 288static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 289 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 290static void pmap_flush_page(vm_page_t m); 291static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 292static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 293 vm_page_t *free); 294static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 295 vm_page_t *free); 296static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 297 vm_offset_t va); 298static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 299 vm_page_t m); 300 301static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 302 303static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags); 304static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free); 305static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 306static void pmap_pte_release(pt_entry_t *pte); 307static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 308static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 309 310static __inline void pagezero(void *page); 311 312CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 313CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 314 315/* 316 * If you get an error here, then you set KVA_PAGES wrong! See the 317 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 318 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 319 */ 320CTASSERT(KERNBASE % (1 << 24) == 0); 321 322void 323pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 324{ 325 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 326 327 switch (type) { 328 case SH_PD_SET_VA: 329#if 0 330 xen_queue_pt_update(shadow_pdir_ma, 331 xpmap_ptom(val & ~(PG_RW))); 332#endif 333 xen_queue_pt_update(pdir_ma, 334 xpmap_ptom(val)); 335 break; 336 case SH_PD_SET_VA_MA: 337#if 0 338 xen_queue_pt_update(shadow_pdir_ma, 339 val & ~(PG_RW)); 340#endif 341 xen_queue_pt_update(pdir_ma, val); 342 break; 343 case SH_PD_SET_VA_CLEAR: 344#if 0 345 xen_queue_pt_update(shadow_pdir_ma, 0); 346#endif 347 xen_queue_pt_update(pdir_ma, 0); 348 break; 349 } 350} 351 352/* 353 * Bootstrap the system enough to run with virtual memory. 354 * 355 * On the i386 this is called after mapping has already been enabled 356 * and just syncs the pmap module with what has already been done. 357 * [We can't call it easily with mapping off since the kernel is not 358 * mapped with PA == VA, hence we would have to relocate every address 359 * from the linked base (virtual) address "KERNBASE" to the actual 360 * (physical) address starting relative to 0] 361 */ 362void 363pmap_bootstrap(vm_paddr_t firstaddr) 364{ 365 vm_offset_t va; 366 pt_entry_t *pte, *unused; 367 struct sysmaps *sysmaps; 368 int i; 369 370 /* 371 * Initialize the first available kernel virtual address. However, 372 * using "firstaddr" may waste a few pages of the kernel virtual 373 * address space, because locore may not have mapped every physical 374 * page that it allocated. Preferably, locore would provide a first 375 * unused virtual address in addition to "firstaddr". 376 */ 377 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 378 379 virtual_end = VM_MAX_KERNEL_ADDRESS; 380 381 /* 382 * Initialize the kernel pmap (which is statically allocated). 383 */ 384 PMAP_LOCK_INIT(kernel_pmap); 385 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 386#ifdef PAE 387 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 388#endif 389 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 390 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 391 392 /* 393 * Initialize the global pv list lock. 394 */ 395 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE); 396 397 LIST_INIT(&allpmaps); 398 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 399 mtx_lock_spin(&allpmaps_lock); 400 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 401 mtx_unlock_spin(&allpmaps_lock); 402 if (nkpt == 0) 403 nkpt = NKPT; 404 405 /* 406 * Reserve some special page table entries/VA space for temporary 407 * mapping of pages. 408 */ 409#define SYSMAP(c, p, v, n) \ 410 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 411 412 va = virtual_avail; 413 pte = vtopte(va); 414 415 /* 416 * CMAP1/CMAP2 are used for zeroing and copying pages. 417 * CMAP3 is used for the idle process page zeroing. 418 */ 419 for (i = 0; i < MAXCPU; i++) { 420 sysmaps = &sysmaps_pcpu[i]; 421 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 422 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 423 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 424 PT_SET_MA(sysmaps->CADDR1, 0); 425 PT_SET_MA(sysmaps->CADDR2, 0); 426 } 427 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 428 PT_SET_MA(CADDR3, 0); 429 430 /* 431 * Crashdump maps. 432 */ 433 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 434 435 /* 436 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 437 */ 438 SYSMAP(caddr_t, unused, ptvmmap, 1) 439 440 /* 441 * msgbufp is used to map the system message buffer. 442 */ 443 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 444 445 /* 446 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 447 * respectively. 448 */ 449 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 450 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 451 452 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 453 454 virtual_avail = va; 455 456 /* 457 * Leave in place an identity mapping (virt == phys) for the low 1 MB 458 * physical memory region that is used by the ACPI wakeup code. This 459 * mapping must not have PG_G set. 460 */ 461#ifndef XEN 462 /* 463 * leave here deliberately to show that this is not supported 464 */ 465#ifdef XBOX 466 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 467 * an early stadium, we cannot yet neatly map video memory ... :-( 468 * Better fixes are very welcome! */ 469 if (!arch_i386_is_xbox) 470#endif 471 for (i = 1; i < NKPT; i++) 472 PTD[i] = 0; 473 474 /* Initialize the PAT MSR if present. */ 475 pmap_init_pat(); 476 477 /* Turn on PG_G on kernel page(s) */ 478 pmap_set_pg(); 479#endif 480 481#ifdef HAMFISTED_LOCKING 482 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 483#endif 484} 485 486/* 487 * Setup the PAT MSR. 488 */ 489void 490pmap_init_pat(void) 491{ 492 uint64_t pat_msr; 493 494 /* Bail if this CPU doesn't implement PAT. */ 495 if (!(cpu_feature & CPUID_PAT)) 496 return; 497 498 if (cpu_vendor_id != CPU_VENDOR_INTEL || 499 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 500 /* 501 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 502 * Program 4 and 5 as WP and WC. 503 * Leave 6 and 7 as UC and UC-. 504 */ 505 pat_msr = rdmsr(MSR_PAT); 506 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 507 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 508 PAT_VALUE(5, PAT_WRITE_COMBINING); 509 pat_works = 1; 510 } else { 511 /* 512 * Due to some Intel errata, we can only safely use the lower 4 513 * PAT entries. Thus, just replace PAT Index 2 with WC instead 514 * of UC-. 515 * 516 * Intel Pentium III Processor Specification Update 517 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 518 * or Mode C Paging) 519 * 520 * Intel Pentium IV Processor Specification Update 521 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 522 */ 523 pat_msr = rdmsr(MSR_PAT); 524 pat_msr &= ~PAT_MASK(2); 525 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 526 pat_works = 0; 527 } 528 wrmsr(MSR_PAT, pat_msr); 529} 530 531/* 532 * Initialize a vm_page's machine-dependent fields. 533 */ 534void 535pmap_page_init(vm_page_t m) 536{ 537 538 TAILQ_INIT(&m->md.pv_list); 539 m->md.pat_mode = PAT_WRITE_BACK; 540} 541 542/* 543 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 544 * Requirements: 545 * - Must deal with pages in order to ensure that none of the PG_* bits 546 * are ever set, PG_V in particular. 547 * - Assumes we can write to ptes without pte_store() atomic ops, even 548 * on PAE systems. This should be ok. 549 * - Assumes nothing will ever test these addresses for 0 to indicate 550 * no mapping instead of correctly checking PG_V. 551 * - Assumes a vm_offset_t will fit in a pte (true for i386). 552 * Because PG_V is never set, there can be no mappings to invalidate. 553 */ 554static int ptelist_count = 0; 555static vm_offset_t 556pmap_ptelist_alloc(vm_offset_t *head) 557{ 558 vm_offset_t va; 559 vm_offset_t *phead = (vm_offset_t *)*head; 560 561 if (ptelist_count == 0) { 562 printf("out of memory!!!!!!\n"); 563 return (0); /* Out of memory */ 564 } 565 ptelist_count--; 566 va = phead[ptelist_count]; 567 return (va); 568} 569 570static void 571pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 572{ 573 vm_offset_t *phead = (vm_offset_t *)*head; 574 575 phead[ptelist_count++] = va; 576} 577 578static void 579pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 580{ 581 int i, nstackpages; 582 vm_offset_t va; 583 vm_page_t m; 584 585 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 586 for (i = 0; i < nstackpages; i++) { 587 va = (vm_offset_t)base + i * PAGE_SIZE; 588 m = vm_page_alloc(NULL, i, 589 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 590 VM_ALLOC_ZERO); 591 pmap_qenter(va, &m, 1); 592 } 593 594 *head = (vm_offset_t)base; 595 for (i = npages - 1; i >= nstackpages; i--) { 596 va = (vm_offset_t)base + i * PAGE_SIZE; 597 pmap_ptelist_free(head, va); 598 } 599} 600 601 602/* 603 * Initialize the pmap module. 604 * Called by vm_init, to initialize any structures that the pmap 605 * system needs to map virtual memory. 606 */ 607void 608pmap_init(void) 609{ 610 611 /* 612 * Initialize the address space (zone) for the pv entries. Set a 613 * high water mark so that the system can recover from excessive 614 * numbers of pv entries. 615 */ 616 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 617 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 618 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 619 pv_entry_max = roundup(pv_entry_max, _NPCPV); 620 pv_entry_high_water = 9 * (pv_entry_max / 10); 621 622 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 623 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 624 PAGE_SIZE * pv_maxchunks); 625 if (pv_chunkbase == NULL) 626 panic("pmap_init: not enough kvm for pv chunks"); 627 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 628} 629 630 631SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 632 "Max number of PV entries"); 633SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 634 "Page share factor per proc"); 635 636static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 637 "2/4MB page mapping counters"); 638 639static u_long pmap_pde_mappings; 640SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 641 &pmap_pde_mappings, 0, "2/4MB page mappings"); 642 643/*************************************************** 644 * Low level helper routines..... 645 ***************************************************/ 646 647/* 648 * Determine the appropriate bits to set in a PTE or PDE for a specified 649 * caching mode. 650 */ 651int 652pmap_cache_bits(int mode, boolean_t is_pde) 653{ 654 int pat_flag, pat_index, cache_bits; 655 656 /* The PAT bit is different for PTE's and PDE's. */ 657 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 658 659 /* If we don't support PAT, map extended modes to older ones. */ 660 if (!(cpu_feature & CPUID_PAT)) { 661 switch (mode) { 662 case PAT_UNCACHEABLE: 663 case PAT_WRITE_THROUGH: 664 case PAT_WRITE_BACK: 665 break; 666 case PAT_UNCACHED: 667 case PAT_WRITE_COMBINING: 668 case PAT_WRITE_PROTECTED: 669 mode = PAT_UNCACHEABLE; 670 break; 671 } 672 } 673 674 /* Map the caching mode to a PAT index. */ 675 if (pat_works) { 676 switch (mode) { 677 case PAT_UNCACHEABLE: 678 pat_index = 3; 679 break; 680 case PAT_WRITE_THROUGH: 681 pat_index = 1; 682 break; 683 case PAT_WRITE_BACK: 684 pat_index = 0; 685 break; 686 case PAT_UNCACHED: 687 pat_index = 2; 688 break; 689 case PAT_WRITE_COMBINING: 690 pat_index = 5; 691 break; 692 case PAT_WRITE_PROTECTED: 693 pat_index = 4; 694 break; 695 default: 696 panic("Unknown caching mode %d\n", mode); 697 } 698 } else { 699 switch (mode) { 700 case PAT_UNCACHED: 701 case PAT_UNCACHEABLE: 702 case PAT_WRITE_PROTECTED: 703 pat_index = 3; 704 break; 705 case PAT_WRITE_THROUGH: 706 pat_index = 1; 707 break; 708 case PAT_WRITE_BACK: 709 pat_index = 0; 710 break; 711 case PAT_WRITE_COMBINING: 712 pat_index = 2; 713 break; 714 default: 715 panic("Unknown caching mode %d\n", mode); 716 } 717 } 718 719 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 720 cache_bits = 0; 721 if (pat_index & 0x4) 722 cache_bits |= pat_flag; 723 if (pat_index & 0x2) 724 cache_bits |= PG_NC_PCD; 725 if (pat_index & 0x1) 726 cache_bits |= PG_NC_PWT; 727 return (cache_bits); 728} 729#ifdef SMP 730/* 731 * For SMP, these functions have to use the IPI mechanism for coherence. 732 * 733 * N.B.: Before calling any of the following TLB invalidation functions, 734 * the calling processor must ensure that all stores updating a non- 735 * kernel page table are globally performed. Otherwise, another 736 * processor could cache an old, pre-update entry without being 737 * invalidated. This can happen one of two ways: (1) The pmap becomes 738 * active on another processor after its pm_active field is checked by 739 * one of the following functions but before a store updating the page 740 * table is globally performed. (2) The pmap becomes active on another 741 * processor before its pm_active field is checked but due to 742 * speculative loads one of the following functions stills reads the 743 * pmap as inactive on the other processor. 744 * 745 * The kernel page table is exempt because its pm_active field is 746 * immutable. The kernel page table is always active on every 747 * processor. 748 */ 749void 750pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 751{ 752 cpuset_t other_cpus; 753 u_int cpuid; 754 755 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 756 pmap, va); 757 758 sched_pin(); 759 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 760 invlpg(va); 761 smp_invlpg(va); 762 } else { 763 cpuid = PCPU_GET(cpuid); 764 other_cpus = all_cpus; 765 CPU_CLR(cpuid, &other_cpus); 766 if (CPU_ISSET(cpuid, &pmap->pm_active)) 767 invlpg(va); 768 CPU_AND(&other_cpus, &pmap->pm_active); 769 if (!CPU_EMPTY(&other_cpus)) 770 smp_masked_invlpg(other_cpus, va); 771 } 772 sched_unpin(); 773 PT_UPDATES_FLUSH(); 774} 775 776void 777pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 778{ 779 cpuset_t other_cpus; 780 vm_offset_t addr; 781 u_int cpuid; 782 783 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 784 pmap, sva, eva); 785 786 sched_pin(); 787 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 788 for (addr = sva; addr < eva; addr += PAGE_SIZE) 789 invlpg(addr); 790 smp_invlpg_range(sva, eva); 791 } else { 792 cpuid = PCPU_GET(cpuid); 793 other_cpus = all_cpus; 794 CPU_CLR(cpuid, &other_cpus); 795 if (CPU_ISSET(cpuid, &pmap->pm_active)) 796 for (addr = sva; addr < eva; addr += PAGE_SIZE) 797 invlpg(addr); 798 CPU_AND(&other_cpus, &pmap->pm_active); 799 if (!CPU_EMPTY(&other_cpus)) 800 smp_masked_invlpg_range(other_cpus, sva, eva); 801 } 802 sched_unpin(); 803 PT_UPDATES_FLUSH(); 804} 805 806void 807pmap_invalidate_all(pmap_t pmap) 808{ 809 cpuset_t other_cpus; 810 u_int cpuid; 811 812 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 813 814 sched_pin(); 815 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 816 invltlb(); 817 smp_invltlb(); 818 } else { 819 cpuid = PCPU_GET(cpuid); 820 other_cpus = all_cpus; 821 CPU_CLR(cpuid, &other_cpus); 822 if (CPU_ISSET(cpuid, &pmap->pm_active)) 823 invltlb(); 824 CPU_AND(&other_cpus, &pmap->pm_active); 825 if (!CPU_EMPTY(&other_cpus)) 826 smp_masked_invltlb(other_cpus); 827 } 828 sched_unpin(); 829} 830 831void 832pmap_invalidate_cache(void) 833{ 834 835 sched_pin(); 836 wbinvd(); 837 smp_cache_flush(); 838 sched_unpin(); 839} 840#else /* !SMP */ 841/* 842 * Normal, non-SMP, 486+ invalidation functions. 843 * We inline these within pmap.c for speed. 844 */ 845PMAP_INLINE void 846pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 847{ 848 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 849 pmap, va); 850 851 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 852 invlpg(va); 853 PT_UPDATES_FLUSH(); 854} 855 856PMAP_INLINE void 857pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 858{ 859 vm_offset_t addr; 860 861 if (eva - sva > PAGE_SIZE) 862 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 863 pmap, sva, eva); 864 865 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 866 for (addr = sva; addr < eva; addr += PAGE_SIZE) 867 invlpg(addr); 868 PT_UPDATES_FLUSH(); 869} 870 871PMAP_INLINE void 872pmap_invalidate_all(pmap_t pmap) 873{ 874 875 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 876 877 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 878 invltlb(); 879} 880 881PMAP_INLINE void 882pmap_invalidate_cache(void) 883{ 884 885 wbinvd(); 886} 887#endif /* !SMP */ 888 889#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 890 891void 892pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 893{ 894 895 KASSERT((sva & PAGE_MASK) == 0, 896 ("pmap_invalidate_cache_range: sva not page-aligned")); 897 KASSERT((eva & PAGE_MASK) == 0, 898 ("pmap_invalidate_cache_range: eva not page-aligned")); 899 900 if (cpu_feature & CPUID_SS) 901 ; /* If "Self Snoop" is supported, do nothing. */ 902 else if ((cpu_feature & CPUID_CLFSH) != 0 && 903 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 904 905 /* 906 * Otherwise, do per-cache line flush. Use the mfence 907 * instruction to insure that previous stores are 908 * included in the write-back. The processor 909 * propagates flush to other processors in the cache 910 * coherence domain. 911 */ 912 mfence(); 913 for (; sva < eva; sva += cpu_clflush_line_size) 914 clflush(sva); 915 mfence(); 916 } else { 917 918 /* 919 * No targeted cache flush methods are supported by CPU, 920 * or the supplied range is bigger than 2MB. 921 * Globally invalidate cache. 922 */ 923 pmap_invalidate_cache(); 924 } 925} 926 927void 928pmap_invalidate_cache_pages(vm_page_t *pages, int count) 929{ 930 int i; 931 932 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 933 (cpu_feature & CPUID_CLFSH) == 0) { 934 pmap_invalidate_cache(); 935 } else { 936 for (i = 0; i < count; i++) 937 pmap_flush_page(pages[i]); 938 } 939} 940 941/* 942 * Are we current address space or kernel? N.B. We return FALSE when 943 * a pmap's page table is in use because a kernel thread is borrowing 944 * it. The borrowed page table can change spontaneously, making any 945 * dependence on its continued use subject to a race condition. 946 */ 947static __inline int 948pmap_is_current(pmap_t pmap) 949{ 950 951 return (pmap == kernel_pmap || 952 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 953 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 954} 955 956/* 957 * If the given pmap is not the current or kernel pmap, the returned pte must 958 * be released by passing it to pmap_pte_release(). 959 */ 960pt_entry_t * 961pmap_pte(pmap_t pmap, vm_offset_t va) 962{ 963 pd_entry_t newpf; 964 pd_entry_t *pde; 965 966 pde = pmap_pde(pmap, va); 967 if (*pde & PG_PS) 968 return (pde); 969 if (*pde != 0) { 970 /* are we current address space or kernel? */ 971 if (pmap_is_current(pmap)) 972 return (vtopte(va)); 973 mtx_lock(&PMAP2mutex); 974 newpf = *pde & PG_FRAME; 975 if ((*PMAP2 & PG_FRAME) != newpf) { 976 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 977 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 978 pmap, va, (*PMAP2 & 0xffffffff)); 979 } 980 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 981 } 982 return (NULL); 983} 984 985/* 986 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 987 * being NULL. 988 */ 989static __inline void 990pmap_pte_release(pt_entry_t *pte) 991{ 992 993 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 994 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 995 *PMAP2); 996 rw_wlock(&pvh_global_lock); 997 PT_SET_VA(PMAP2, 0, TRUE); 998 rw_wunlock(&pvh_global_lock); 999 mtx_unlock(&PMAP2mutex); 1000 } 1001} 1002 1003static __inline void 1004invlcaddr(void *caddr) 1005{ 1006 1007 invlpg((u_int)caddr); 1008 PT_UPDATES_FLUSH(); 1009} 1010 1011/* 1012 * Super fast pmap_pte routine best used when scanning 1013 * the pv lists. This eliminates many coarse-grained 1014 * invltlb calls. Note that many of the pv list 1015 * scans are across different pmaps. It is very wasteful 1016 * to do an entire invltlb for checking a single mapping. 1017 * 1018 * If the given pmap is not the current pmap, pvh_global_lock 1019 * must be held and curthread pinned to a CPU. 1020 */ 1021static pt_entry_t * 1022pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1023{ 1024 pd_entry_t newpf; 1025 pd_entry_t *pde; 1026 1027 pde = pmap_pde(pmap, va); 1028 if (*pde & PG_PS) 1029 return (pde); 1030 if (*pde != 0) { 1031 /* are we current address space or kernel? */ 1032 if (pmap_is_current(pmap)) 1033 return (vtopte(va)); 1034 rw_assert(&pvh_global_lock, RA_WLOCKED); 1035 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1036 newpf = *pde & PG_FRAME; 1037 if ((*PMAP1 & PG_FRAME) != newpf) { 1038 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1039 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1040 pmap, va, (u_long)*PMAP1); 1041 1042#ifdef SMP 1043 PMAP1cpu = PCPU_GET(cpuid); 1044#endif 1045 PMAP1changed++; 1046 } else 1047#ifdef SMP 1048 if (PMAP1cpu != PCPU_GET(cpuid)) { 1049 PMAP1cpu = PCPU_GET(cpuid); 1050 invlcaddr(PADDR1); 1051 PMAP1changedcpu++; 1052 } else 1053#endif 1054 PMAP1unchanged++; 1055 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1056 } 1057 return (0); 1058} 1059 1060/* 1061 * Routine: pmap_extract 1062 * Function: 1063 * Extract the physical page address associated 1064 * with the given map/virtual_address pair. 1065 */ 1066vm_paddr_t 1067pmap_extract(pmap_t pmap, vm_offset_t va) 1068{ 1069 vm_paddr_t rtval; 1070 pt_entry_t *pte; 1071 pd_entry_t pde; 1072 pt_entry_t pteval; 1073 1074 rtval = 0; 1075 PMAP_LOCK(pmap); 1076 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1077 if (pde != 0) { 1078 if ((pde & PG_PS) != 0) { 1079 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1080 PMAP_UNLOCK(pmap); 1081 return rtval; 1082 } 1083 pte = pmap_pte(pmap, va); 1084 pteval = *pte ? xpmap_mtop(*pte) : 0; 1085 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1086 pmap_pte_release(pte); 1087 } 1088 PMAP_UNLOCK(pmap); 1089 return (rtval); 1090} 1091 1092/* 1093 * Routine: pmap_extract_ma 1094 * Function: 1095 * Like pmap_extract, but returns machine address 1096 */ 1097vm_paddr_t 1098pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1099{ 1100 vm_paddr_t rtval; 1101 pt_entry_t *pte; 1102 pd_entry_t pde; 1103 1104 rtval = 0; 1105 PMAP_LOCK(pmap); 1106 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1107 if (pde != 0) { 1108 if ((pde & PG_PS) != 0) { 1109 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1110 PMAP_UNLOCK(pmap); 1111 return rtval; 1112 } 1113 pte = pmap_pte(pmap, va); 1114 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1115 pmap_pte_release(pte); 1116 } 1117 PMAP_UNLOCK(pmap); 1118 return (rtval); 1119} 1120 1121/* 1122 * Routine: pmap_extract_and_hold 1123 * Function: 1124 * Atomically extract and hold the physical page 1125 * with the given pmap and virtual address pair 1126 * if that mapping permits the given protection. 1127 */ 1128vm_page_t 1129pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1130{ 1131 pd_entry_t pde; 1132 pt_entry_t pte, *ptep; 1133 vm_page_t m; 1134 vm_paddr_t pa; 1135 1136 pa = 0; 1137 m = NULL; 1138 PMAP_LOCK(pmap); 1139retry: 1140 pde = PT_GET(pmap_pde(pmap, va)); 1141 if (pde != 0) { 1142 if (pde & PG_PS) { 1143 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1144 if (vm_page_pa_tryrelock(pmap, (pde & 1145 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1146 goto retry; 1147 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1148 (va & PDRMASK)); 1149 vm_page_hold(m); 1150 } 1151 } else { 1152 ptep = pmap_pte(pmap, va); 1153 pte = PT_GET(ptep); 1154 pmap_pte_release(ptep); 1155 if (pte != 0 && 1156 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1157 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1158 &pa)) 1159 goto retry; 1160 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1161 vm_page_hold(m); 1162 } 1163 } 1164 } 1165 PA_UNLOCK_COND(pa); 1166 PMAP_UNLOCK(pmap); 1167 return (m); 1168} 1169 1170/*************************************************** 1171 * Low level mapping routines..... 1172 ***************************************************/ 1173 1174/* 1175 * Add a wired page to the kva. 1176 * Note: not SMP coherent. 1177 * 1178 * This function may be used before pmap_bootstrap() is called. 1179 */ 1180void 1181pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1182{ 1183 1184 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1185} 1186 1187void 1188pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1189{ 1190 pt_entry_t *pte; 1191 1192 pte = vtopte(va); 1193 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1194} 1195 1196static __inline void 1197pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1198{ 1199 1200 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1201} 1202 1203/* 1204 * Remove a page from the kernel pagetables. 1205 * Note: not SMP coherent. 1206 * 1207 * This function may be used before pmap_bootstrap() is called. 1208 */ 1209PMAP_INLINE void 1210pmap_kremove(vm_offset_t va) 1211{ 1212 pt_entry_t *pte; 1213 1214 pte = vtopte(va); 1215 PT_CLEAR_VA(pte, FALSE); 1216} 1217 1218/* 1219 * Used to map a range of physical addresses into kernel 1220 * virtual address space. 1221 * 1222 * The value passed in '*virt' is a suggested virtual address for 1223 * the mapping. Architectures which can support a direct-mapped 1224 * physical to virtual region can return the appropriate address 1225 * within that region, leaving '*virt' unchanged. Other 1226 * architectures should map the pages starting at '*virt' and 1227 * update '*virt' with the first usable address after the mapped 1228 * region. 1229 */ 1230vm_offset_t 1231pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1232{ 1233 vm_offset_t va, sva; 1234 1235 va = sva = *virt; 1236 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1237 va, start, end, prot); 1238 while (start < end) { 1239 pmap_kenter(va, start); 1240 va += PAGE_SIZE; 1241 start += PAGE_SIZE; 1242 } 1243 pmap_invalidate_range(kernel_pmap, sva, va); 1244 *virt = va; 1245 return (sva); 1246} 1247 1248 1249/* 1250 * Add a list of wired pages to the kva 1251 * this routine is only used for temporary 1252 * kernel mappings that do not need to have 1253 * page modification or references recorded. 1254 * Note that old mappings are simply written 1255 * over. The page *must* be wired. 1256 * Note: SMP coherent. Uses a ranged shootdown IPI. 1257 */ 1258void 1259pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1260{ 1261 pt_entry_t *endpte, *pte; 1262 vm_paddr_t pa; 1263 vm_offset_t va = sva; 1264 int mclcount = 0; 1265 multicall_entry_t mcl[16]; 1266 multicall_entry_t *mclp = mcl; 1267 int error; 1268 1269 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1270 pte = vtopte(sva); 1271 endpte = pte + count; 1272 while (pte < endpte) { 1273 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1274 1275 mclp->op = __HYPERVISOR_update_va_mapping; 1276 mclp->args[0] = va; 1277 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1278 mclp->args[2] = (uint32_t)(pa >> 32); 1279 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1280 1281 va += PAGE_SIZE; 1282 pte++; 1283 ma++; 1284 mclp++; 1285 mclcount++; 1286 if (mclcount == 16) { 1287 error = HYPERVISOR_multicall(mcl, mclcount); 1288 mclp = mcl; 1289 mclcount = 0; 1290 KASSERT(error == 0, ("bad multicall %d", error)); 1291 } 1292 } 1293 if (mclcount) { 1294 error = HYPERVISOR_multicall(mcl, mclcount); 1295 KASSERT(error == 0, ("bad multicall %d", error)); 1296 } 1297 1298#ifdef INVARIANTS 1299 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1300 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1301#endif 1302} 1303 1304/* 1305 * This routine tears out page mappings from the 1306 * kernel -- it is meant only for temporary mappings. 1307 * Note: SMP coherent. Uses a ranged shootdown IPI. 1308 */ 1309void 1310pmap_qremove(vm_offset_t sva, int count) 1311{ 1312 vm_offset_t va; 1313 1314 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1315 va = sva; 1316 rw_wlock(&pvh_global_lock); 1317 critical_enter(); 1318 while (count-- > 0) { 1319 pmap_kremove(va); 1320 va += PAGE_SIZE; 1321 } 1322 PT_UPDATES_FLUSH(); 1323 pmap_invalidate_range(kernel_pmap, sva, va); 1324 critical_exit(); 1325 rw_wunlock(&pvh_global_lock); 1326} 1327 1328/*************************************************** 1329 * Page table page management routines..... 1330 ***************************************************/ 1331static __inline void 1332pmap_free_zero_pages(vm_page_t free) 1333{ 1334 vm_page_t m; 1335 1336 while (free != NULL) { 1337 m = free; 1338 free = (void *)m->object; 1339 m->object = NULL; 1340 vm_page_free_zero(m); 1341 } 1342} 1343 1344/* 1345 * Decrements a page table page's wire count, which is used to record the 1346 * number of valid page table entries within the page. If the wire count 1347 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1348 * page table page was unmapped and FALSE otherwise. 1349 */ 1350static inline boolean_t 1351pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1352{ 1353 1354 --m->wire_count; 1355 if (m->wire_count == 0) { 1356 _pmap_unwire_ptp(pmap, m, free); 1357 return (TRUE); 1358 } else 1359 return (FALSE); 1360} 1361 1362static void 1363_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1364{ 1365 vm_offset_t pteva; 1366 1367 PT_UPDATES_FLUSH(); 1368 /* 1369 * unmap the page table page 1370 */ 1371 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1372 /* 1373 * page *might* contain residual mapping :-/ 1374 */ 1375 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1376 pmap_zero_page(m); 1377 --pmap->pm_stats.resident_count; 1378 1379 /* 1380 * This is a release store so that the ordinary store unmapping 1381 * the page table page is globally performed before TLB shoot- 1382 * down is begun. 1383 */ 1384 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1385 1386 /* 1387 * Do an invltlb to make the invalidated mapping 1388 * take effect immediately. 1389 */ 1390 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1391 pmap_invalidate_page(pmap, pteva); 1392 1393 /* 1394 * Put page on a list so that it is released after 1395 * *ALL* TLB shootdown is done 1396 */ 1397 m->object = (void *)*free; 1398 *free = m; 1399} 1400 1401/* 1402 * After removing a page table entry, this routine is used to 1403 * conditionally free the page, and manage the hold/wire counts. 1404 */ 1405static int 1406pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1407{ 1408 pd_entry_t ptepde; 1409 vm_page_t mpte; 1410 1411 if (va >= VM_MAXUSER_ADDRESS) 1412 return (0); 1413 ptepde = PT_GET(pmap_pde(pmap, va)); 1414 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1415 return (pmap_unwire_ptp(pmap, mpte, free)); 1416} 1417 1418/* 1419 * Initialize the pmap for the swapper process. 1420 */ 1421void 1422pmap_pinit0(pmap_t pmap) 1423{ 1424 1425 PMAP_LOCK_INIT(pmap); 1426 /* 1427 * Since the page table directory is shared with the kernel pmap, 1428 * which is already included in the list "allpmaps", this pmap does 1429 * not need to be inserted into that list. 1430 */ 1431 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1432#ifdef PAE 1433 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1434#endif 1435 CPU_ZERO(&pmap->pm_active); 1436 PCPU_SET(curpmap, pmap); 1437 TAILQ_INIT(&pmap->pm_pvchunk); 1438 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1439} 1440 1441/* 1442 * Initialize a preallocated and zeroed pmap structure, 1443 * such as one in a vmspace structure. 1444 */ 1445int 1446pmap_pinit(pmap_t pmap) 1447{ 1448 vm_page_t m, ptdpg[NPGPTD + 1]; 1449 int npgptd = NPGPTD + 1; 1450 int i; 1451 1452#ifdef HAMFISTED_LOCKING 1453 mtx_lock(&createdelete_lock); 1454#endif 1455 1456 PMAP_LOCK_INIT(pmap); 1457 1458 /* 1459 * No need to allocate page table space yet but we do need a valid 1460 * page directory table. 1461 */ 1462 if (pmap->pm_pdir == NULL) { 1463 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1464 NBPTD); 1465 if (pmap->pm_pdir == NULL) { 1466 PMAP_LOCK_DESTROY(pmap); 1467#ifdef HAMFISTED_LOCKING 1468 mtx_unlock(&createdelete_lock); 1469#endif 1470 return (0); 1471 } 1472#ifdef PAE 1473 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1474#endif 1475 } 1476 1477 /* 1478 * allocate the page directory page(s) 1479 */ 1480 for (i = 0; i < npgptd;) { 1481 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1482 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1483 if (m == NULL) 1484 VM_WAIT; 1485 else { 1486 ptdpg[i++] = m; 1487 } 1488 } 1489 1490 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1491 1492 for (i = 0; i < NPGPTD; i++) 1493 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1494 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1495 1496 mtx_lock_spin(&allpmaps_lock); 1497 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1498 /* Copy the kernel page table directory entries. */ 1499 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1500 mtx_unlock_spin(&allpmaps_lock); 1501 1502#ifdef PAE 1503 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1504 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1505 bzero(pmap->pm_pdpt, PAGE_SIZE); 1506 for (i = 0; i < NPGPTD; i++) { 1507 vm_paddr_t ma; 1508 1509 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1510 pmap->pm_pdpt[i] = ma | PG_V; 1511 1512 } 1513#endif 1514 for (i = 0; i < NPGPTD; i++) { 1515 pt_entry_t *pd; 1516 vm_paddr_t ma; 1517 1518 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1519 pd = pmap->pm_pdir + (i * NPDEPG); 1520 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1521#if 0 1522 xen_pgd_pin(ma); 1523#endif 1524 } 1525 1526#ifdef PAE 1527 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1528#endif 1529 rw_wlock(&pvh_global_lock); 1530 xen_flush_queue(); 1531 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1532 for (i = 0; i < NPGPTD; i++) { 1533 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1534 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1535 } 1536 xen_flush_queue(); 1537 rw_wunlock(&pvh_global_lock); 1538 CPU_ZERO(&pmap->pm_active); 1539 TAILQ_INIT(&pmap->pm_pvchunk); 1540 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1541 1542#ifdef HAMFISTED_LOCKING 1543 mtx_unlock(&createdelete_lock); 1544#endif 1545 return (1); 1546} 1547 1548/* 1549 * this routine is called if the page table page is not 1550 * mapped correctly. 1551 */ 1552static vm_page_t 1553_pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags) 1554{ 1555 vm_paddr_t ptema; 1556 vm_page_t m; 1557 1558 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1559 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1560 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1561 1562 /* 1563 * Allocate a page table page. 1564 */ 1565 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1566 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1567 if (flags & M_WAITOK) { 1568 PMAP_UNLOCK(pmap); 1569 rw_wunlock(&pvh_global_lock); 1570 VM_WAIT; 1571 rw_wlock(&pvh_global_lock); 1572 PMAP_LOCK(pmap); 1573 } 1574 1575 /* 1576 * Indicate the need to retry. While waiting, the page table 1577 * page may have been allocated. 1578 */ 1579 return (NULL); 1580 } 1581 if ((m->flags & PG_ZERO) == 0) 1582 pmap_zero_page(m); 1583 1584 /* 1585 * Map the pagetable page into the process address space, if 1586 * it isn't already there. 1587 */ 1588 1589 pmap->pm_stats.resident_count++; 1590 1591 ptema = VM_PAGE_TO_MACH(m); 1592 xen_pt_pin(ptema); 1593 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1594 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1595 1596 KASSERT(pmap->pm_pdir[ptepindex], 1597 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1598 return (m); 1599} 1600 1601static vm_page_t 1602pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1603{ 1604 u_int ptepindex; 1605 pd_entry_t ptema; 1606 vm_page_t m; 1607 1608 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1609 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1610 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1611 1612 /* 1613 * Calculate pagetable page index 1614 */ 1615 ptepindex = va >> PDRSHIFT; 1616retry: 1617 /* 1618 * Get the page directory entry 1619 */ 1620 ptema = pmap->pm_pdir[ptepindex]; 1621 1622 /* 1623 * This supports switching from a 4MB page to a 1624 * normal 4K page. 1625 */ 1626 if (ptema & PG_PS) { 1627 /* 1628 * XXX 1629 */ 1630 pmap->pm_pdir[ptepindex] = 0; 1631 ptema = 0; 1632 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1633 pmap_invalidate_all(kernel_pmap); 1634 } 1635 1636 /* 1637 * If the page table page is mapped, we just increment the 1638 * hold count, and activate it. 1639 */ 1640 if (ptema & PG_V) { 1641 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1642 m->wire_count++; 1643 } else { 1644 /* 1645 * Here if the pte page isn't mapped, or if it has 1646 * been deallocated. 1647 */ 1648 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1649 pmap, va, flags); 1650 m = _pmap_allocpte(pmap, ptepindex, flags); 1651 if (m == NULL && (flags & M_WAITOK)) 1652 goto retry; 1653 1654 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1655 } 1656 return (m); 1657} 1658 1659 1660/*************************************************** 1661* Pmap allocation/deallocation routines. 1662 ***************************************************/ 1663 1664#ifdef SMP 1665/* 1666 * Deal with a SMP shootdown of other users of the pmap that we are 1667 * trying to dispose of. This can be a bit hairy. 1668 */ 1669static cpuset_t *lazymask; 1670static u_int lazyptd; 1671static volatile u_int lazywait; 1672 1673void pmap_lazyfix_action(void); 1674 1675void 1676pmap_lazyfix_action(void) 1677{ 1678 1679#ifdef COUNT_IPIS 1680 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1681#endif 1682 if (rcr3() == lazyptd) 1683 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1684 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1685 atomic_store_rel_int(&lazywait, 1); 1686} 1687 1688static void 1689pmap_lazyfix_self(u_int cpuid) 1690{ 1691 1692 if (rcr3() == lazyptd) 1693 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1694 CPU_CLR_ATOMIC(cpuid, lazymask); 1695} 1696 1697 1698static void 1699pmap_lazyfix(pmap_t pmap) 1700{ 1701 cpuset_t mymask, mask; 1702 u_int cpuid, spins; 1703 int lsb; 1704 1705 mask = pmap->pm_active; 1706 while (!CPU_EMPTY(&mask)) { 1707 spins = 50000000; 1708 1709 /* Find least significant set bit. */ 1710 lsb = CPU_FFS(&mask); 1711 MPASS(lsb != 0); 1712 lsb--; 1713 CPU_SETOF(lsb, &mask); 1714 mtx_lock_spin(&smp_ipi_mtx); 1715#ifdef PAE 1716 lazyptd = vtophys(pmap->pm_pdpt); 1717#else 1718 lazyptd = vtophys(pmap->pm_pdir); 1719#endif 1720 cpuid = PCPU_GET(cpuid); 1721 1722 /* Use a cpuset just for having an easy check. */ 1723 CPU_SETOF(cpuid, &mymask); 1724 if (!CPU_CMP(&mask, &mymask)) { 1725 lazymask = &pmap->pm_active; 1726 pmap_lazyfix_self(cpuid); 1727 } else { 1728 atomic_store_rel_int((u_int *)&lazymask, 1729 (u_int)&pmap->pm_active); 1730 atomic_store_rel_int(&lazywait, 0); 1731 ipi_selected(mask, IPI_LAZYPMAP); 1732 while (lazywait == 0) { 1733 ia32_pause(); 1734 if (--spins == 0) 1735 break; 1736 } 1737 } 1738 mtx_unlock_spin(&smp_ipi_mtx); 1739 if (spins == 0) 1740 printf("pmap_lazyfix: spun for 50000000\n"); 1741 mask = pmap->pm_active; 1742 } 1743} 1744 1745#else /* SMP */ 1746 1747/* 1748 * Cleaning up on uniprocessor is easy. For various reasons, we're 1749 * unlikely to have to even execute this code, including the fact 1750 * that the cleanup is deferred until the parent does a wait(2), which 1751 * means that another userland process has run. 1752 */ 1753static void 1754pmap_lazyfix(pmap_t pmap) 1755{ 1756 u_int cr3; 1757 1758 cr3 = vtophys(pmap->pm_pdir); 1759 if (cr3 == rcr3()) { 1760 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1761 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1762 } 1763} 1764#endif /* SMP */ 1765 1766/* 1767 * Release any resources held by the given physical map. 1768 * Called when a pmap initialized by pmap_pinit is being released. 1769 * Should only be called if the map contains no valid mappings. 1770 */ 1771void 1772pmap_release(pmap_t pmap) 1773{ 1774 vm_page_t m, ptdpg[2*NPGPTD+1]; 1775 vm_paddr_t ma; 1776 int i; 1777#ifdef PAE 1778 int npgptd = NPGPTD + 1; 1779#else 1780 int npgptd = NPGPTD; 1781#endif 1782 1783 KASSERT(pmap->pm_stats.resident_count == 0, 1784 ("pmap_release: pmap resident count %ld != 0", 1785 pmap->pm_stats.resident_count)); 1786 PT_UPDATES_FLUSH(); 1787 1788#ifdef HAMFISTED_LOCKING 1789 mtx_lock(&createdelete_lock); 1790#endif 1791 1792 pmap_lazyfix(pmap); 1793 mtx_lock_spin(&allpmaps_lock); 1794 LIST_REMOVE(pmap, pm_list); 1795 mtx_unlock_spin(&allpmaps_lock); 1796 1797 for (i = 0; i < NPGPTD; i++) 1798 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1799 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1800#ifdef PAE 1801 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1802#endif 1803 1804 for (i = 0; i < npgptd; i++) { 1805 m = ptdpg[i]; 1806 ma = VM_PAGE_TO_MACH(m); 1807 /* unpinning L1 and L2 treated the same */ 1808#if 0 1809 xen_pgd_unpin(ma); 1810#else 1811 if (i == NPGPTD) 1812 xen_pgd_unpin(ma); 1813#endif 1814#ifdef PAE 1815 if (i < NPGPTD) 1816 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1817 ("pmap_release: got wrong ptd page")); 1818#endif 1819 m->wire_count--; 1820 atomic_subtract_int(&cnt.v_wire_count, 1); 1821 vm_page_free(m); 1822 } 1823#ifdef PAE 1824 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1825#endif 1826 PMAP_LOCK_DESTROY(pmap); 1827 1828#ifdef HAMFISTED_LOCKING 1829 mtx_unlock(&createdelete_lock); 1830#endif 1831} 1832 1833static int 1834kvm_size(SYSCTL_HANDLER_ARGS) 1835{ 1836 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1837 1838 return (sysctl_handle_long(oidp, &ksize, 0, req)); 1839} 1840SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1841 0, 0, kvm_size, "IU", "Size of KVM"); 1842 1843static int 1844kvm_free(SYSCTL_HANDLER_ARGS) 1845{ 1846 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1847 1848 return (sysctl_handle_long(oidp, &kfree, 0, req)); 1849} 1850SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1851 0, 0, kvm_free, "IU", "Amount of KVM free"); 1852 1853/* 1854 * grow the number of kernel page table entries, if needed 1855 */ 1856void 1857pmap_growkernel(vm_offset_t addr) 1858{ 1859 struct pmap *pmap; 1860 vm_paddr_t ptppaddr; 1861 vm_page_t nkpg; 1862 pd_entry_t newpdir; 1863 1864 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1865 if (kernel_vm_end == 0) { 1866 kernel_vm_end = KERNBASE; 1867 nkpt = 0; 1868 while (pdir_pde(PTD, kernel_vm_end)) { 1869 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1870 nkpt++; 1871 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1872 kernel_vm_end = kernel_map->max_offset; 1873 break; 1874 } 1875 } 1876 } 1877 addr = roundup2(addr, NBPDR); 1878 if (addr - 1 >= kernel_map->max_offset) 1879 addr = kernel_map->max_offset; 1880 while (kernel_vm_end < addr) { 1881 if (pdir_pde(PTD, kernel_vm_end)) { 1882 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1883 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1884 kernel_vm_end = kernel_map->max_offset; 1885 break; 1886 } 1887 continue; 1888 } 1889 1890 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1891 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1892 VM_ALLOC_ZERO); 1893 if (nkpg == NULL) 1894 panic("pmap_growkernel: no memory to grow kernel"); 1895 1896 nkpt++; 1897 1898 if ((nkpg->flags & PG_ZERO) == 0) 1899 pmap_zero_page(nkpg); 1900 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1901 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1902 rw_wlock(&pvh_global_lock); 1903 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1904 mtx_lock_spin(&allpmaps_lock); 1905 LIST_FOREACH(pmap, &allpmaps, pm_list) 1906 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1907 1908 mtx_unlock_spin(&allpmaps_lock); 1909 rw_wunlock(&pvh_global_lock); 1910 1911 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1912 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1913 kernel_vm_end = kernel_map->max_offset; 1914 break; 1915 } 1916 } 1917} 1918 1919 1920/*************************************************** 1921 * page management routines. 1922 ***************************************************/ 1923 1924CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1925CTASSERT(_NPCM == 11); 1926CTASSERT(_NPCPV == 336); 1927 1928static __inline struct pv_chunk * 1929pv_to_chunk(pv_entry_t pv) 1930{ 1931 1932 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1933} 1934 1935#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1936 1937#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1938#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1939 1940static const uint32_t pc_freemask[_NPCM] = { 1941 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1942 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1943 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1944 PC_FREE0_9, PC_FREE10 1945}; 1946 1947SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1948 "Current number of pv entries"); 1949 1950#ifdef PV_STATS 1951static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1952 1953SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1954 "Current number of pv entry chunks"); 1955SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1956 "Current number of pv entry chunks allocated"); 1957SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1958 "Current number of pv entry chunks frees"); 1959SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1960 "Number of times tried to get a chunk page but failed."); 1961 1962static long pv_entry_frees, pv_entry_allocs; 1963static int pv_entry_spare; 1964 1965SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1966 "Current number of pv entry frees"); 1967SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1968 "Current number of pv entry allocs"); 1969SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1970 "Current number of spare pv entries"); 1971#endif 1972 1973/* 1974 * We are in a serious low memory condition. Resort to 1975 * drastic measures to free some pages so we can allocate 1976 * another pv entry chunk. 1977 */ 1978static vm_page_t 1979pmap_pv_reclaim(pmap_t locked_pmap) 1980{ 1981 struct pch newtail; 1982 struct pv_chunk *pc; 1983 pmap_t pmap; 1984 pt_entry_t *pte, tpte; 1985 pv_entry_t pv; 1986 vm_offset_t va; 1987 vm_page_t free, m, m_pc; 1988 uint32_t inuse; 1989 int bit, field, freed; 1990 1991 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1992 pmap = NULL; 1993 free = m_pc = NULL; 1994 TAILQ_INIT(&newtail); 1995 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 1996 free == NULL)) { 1997 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1998 if (pmap != pc->pc_pmap) { 1999 if (pmap != NULL) { 2000 pmap_invalidate_all(pmap); 2001 if (pmap != locked_pmap) 2002 PMAP_UNLOCK(pmap); 2003 } 2004 pmap = pc->pc_pmap; 2005 /* Avoid deadlock and lock recursion. */ 2006 if (pmap > locked_pmap) 2007 PMAP_LOCK(pmap); 2008 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2009 pmap = NULL; 2010 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2011 continue; 2012 } 2013 } 2014 2015 /* 2016 * Destroy every non-wired, 4 KB page mapping in the chunk. 2017 */ 2018 freed = 0; 2019 for (field = 0; field < _NPCM; field++) { 2020 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2021 inuse != 0; inuse &= ~(1UL << bit)) { 2022 bit = bsfl(inuse); 2023 pv = &pc->pc_pventry[field * 32 + bit]; 2024 va = pv->pv_va; 2025 pte = pmap_pte(pmap, va); 2026 tpte = *pte; 2027 if ((tpte & PG_W) == 0) 2028 tpte = pte_load_clear(pte); 2029 pmap_pte_release(pte); 2030 if ((tpte & PG_W) != 0) 2031 continue; 2032 KASSERT(tpte != 0, 2033 ("pmap_pv_reclaim: pmap %p va %x zero pte", 2034 pmap, va)); 2035 if ((tpte & PG_G) != 0) 2036 pmap_invalidate_page(pmap, va); 2037 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2038 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2039 vm_page_dirty(m); 2040 if ((tpte & PG_A) != 0) 2041 vm_page_aflag_set(m, PGA_REFERENCED); 2042 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2043 if (TAILQ_EMPTY(&m->md.pv_list)) 2044 vm_page_aflag_clear(m, PGA_WRITEABLE); 2045 pc->pc_map[field] |= 1UL << bit; 2046 pmap_unuse_pt(pmap, va, &free); 2047 freed++; 2048 } 2049 } 2050 if (freed == 0) { 2051 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2052 continue; 2053 } 2054 /* Every freed mapping is for a 4 KB page. */ 2055 pmap->pm_stats.resident_count -= freed; 2056 PV_STAT(pv_entry_frees += freed); 2057 PV_STAT(pv_entry_spare += freed); 2058 pv_entry_count -= freed; 2059 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2060 for (field = 0; field < _NPCM; field++) 2061 if (pc->pc_map[field] != pc_freemask[field]) { 2062 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2063 pc_list); 2064 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2065 2066 /* 2067 * One freed pv entry in locked_pmap is 2068 * sufficient. 2069 */ 2070 if (pmap == locked_pmap) 2071 goto out; 2072 break; 2073 } 2074 if (field == _NPCM) { 2075 PV_STAT(pv_entry_spare -= _NPCPV); 2076 PV_STAT(pc_chunk_count--); 2077 PV_STAT(pc_chunk_frees++); 2078 /* Entire chunk is free; return it. */ 2079 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2080 pmap_qremove((vm_offset_t)pc, 1); 2081 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2082 break; 2083 } 2084 } 2085out: 2086 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2087 if (pmap != NULL) { 2088 pmap_invalidate_all(pmap); 2089 if (pmap != locked_pmap) 2090 PMAP_UNLOCK(pmap); 2091 } 2092 if (m_pc == NULL && pv_vafree != 0 && free != NULL) { 2093 m_pc = free; 2094 free = (void *)m_pc->object; 2095 /* Recycle a freed page table page. */ 2096 m_pc->wire_count = 1; 2097 atomic_add_int(&cnt.v_wire_count, 1); 2098 } 2099 pmap_free_zero_pages(free); 2100 return (m_pc); 2101} 2102 2103/* 2104 * free the pv_entry back to the free list 2105 */ 2106static void 2107free_pv_entry(pmap_t pmap, pv_entry_t pv) 2108{ 2109 struct pv_chunk *pc; 2110 int idx, field, bit; 2111 2112 rw_assert(&pvh_global_lock, RA_WLOCKED); 2113 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2114 PV_STAT(pv_entry_frees++); 2115 PV_STAT(pv_entry_spare++); 2116 pv_entry_count--; 2117 pc = pv_to_chunk(pv); 2118 idx = pv - &pc->pc_pventry[0]; 2119 field = idx / 32; 2120 bit = idx % 32; 2121 pc->pc_map[field] |= 1ul << bit; 2122 for (idx = 0; idx < _NPCM; idx++) 2123 if (pc->pc_map[idx] != pc_freemask[idx]) { 2124 /* 2125 * 98% of the time, pc is already at the head of the 2126 * list. If it isn't already, move it to the head. 2127 */ 2128 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2129 pc)) { 2130 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2131 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2132 pc_list); 2133 } 2134 return; 2135 } 2136 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2137 free_pv_chunk(pc); 2138} 2139 2140static void 2141free_pv_chunk(struct pv_chunk *pc) 2142{ 2143 vm_page_t m; 2144 2145 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2146 PV_STAT(pv_entry_spare -= _NPCPV); 2147 PV_STAT(pc_chunk_count--); 2148 PV_STAT(pc_chunk_frees++); 2149 /* entire chunk is free, return it */ 2150 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2151 pmap_qremove((vm_offset_t)pc, 1); 2152 vm_page_unwire(m, 0); 2153 vm_page_free(m); 2154 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2155} 2156 2157/* 2158 * get a new pv_entry, allocating a block from the system 2159 * when needed. 2160 */ 2161static pv_entry_t 2162get_pv_entry(pmap_t pmap, boolean_t try) 2163{ 2164 static const struct timeval printinterval = { 60, 0 }; 2165 static struct timeval lastprint; 2166 int bit, field; 2167 pv_entry_t pv; 2168 struct pv_chunk *pc; 2169 vm_page_t m; 2170 2171 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2172 rw_assert(&pvh_global_lock, RA_WLOCKED); 2173 PV_STAT(pv_entry_allocs++); 2174 pv_entry_count++; 2175 if (pv_entry_count > pv_entry_high_water) 2176 if (ratecheck(&lastprint, &printinterval)) 2177 printf("Approaching the limit on PV entries, consider " 2178 "increasing either the vm.pmap.shpgperproc or the " 2179 "vm.pmap.pv_entry_max tunable.\n"); 2180retry: 2181 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2182 if (pc != NULL) { 2183 for (field = 0; field < _NPCM; field++) { 2184 if (pc->pc_map[field]) { 2185 bit = bsfl(pc->pc_map[field]); 2186 break; 2187 } 2188 } 2189 if (field < _NPCM) { 2190 pv = &pc->pc_pventry[field * 32 + bit]; 2191 pc->pc_map[field] &= ~(1ul << bit); 2192 /* If this was the last item, move it to tail */ 2193 for (field = 0; field < _NPCM; field++) 2194 if (pc->pc_map[field] != 0) { 2195 PV_STAT(pv_entry_spare--); 2196 return (pv); /* not full, return */ 2197 } 2198 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2199 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2200 PV_STAT(pv_entry_spare--); 2201 return (pv); 2202 } 2203 } 2204 /* 2205 * Access to the ptelist "pv_vafree" is synchronized by the page 2206 * queues lock. If "pv_vafree" is currently non-empty, it will 2207 * remain non-empty until pmap_ptelist_alloc() completes. 2208 */ 2209 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2210 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2211 if (try) { 2212 pv_entry_count--; 2213 PV_STAT(pc_chunk_tryfail++); 2214 return (NULL); 2215 } 2216 m = pmap_pv_reclaim(pmap); 2217 if (m == NULL) 2218 goto retry; 2219 } 2220 PV_STAT(pc_chunk_count++); 2221 PV_STAT(pc_chunk_allocs++); 2222 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2223 pmap_qenter((vm_offset_t)pc, &m, 1); 2224 if ((m->flags & PG_ZERO) == 0) 2225 pagezero(pc); 2226 pc->pc_pmap = pmap; 2227 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2228 for (field = 1; field < _NPCM; field++) 2229 pc->pc_map[field] = pc_freemask[field]; 2230 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2231 pv = &pc->pc_pventry[0]; 2232 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2233 PV_STAT(pv_entry_spare += _NPCPV - 1); 2234 return (pv); 2235} 2236 2237static __inline pv_entry_t 2238pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2239{ 2240 pv_entry_t pv; 2241 2242 rw_assert(&pvh_global_lock, RA_WLOCKED); 2243 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2244 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2245 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2246 break; 2247 } 2248 } 2249 return (pv); 2250} 2251 2252static void 2253pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2254{ 2255 pv_entry_t pv; 2256 2257 pv = pmap_pvh_remove(pvh, pmap, va); 2258 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2259 free_pv_entry(pmap, pv); 2260} 2261 2262static void 2263pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2264{ 2265 2266 rw_assert(&pvh_global_lock, RA_WLOCKED); 2267 pmap_pvh_free(&m->md, pmap, va); 2268 if (TAILQ_EMPTY(&m->md.pv_list)) 2269 vm_page_aflag_clear(m, PGA_WRITEABLE); 2270} 2271 2272/* 2273 * Conditionally create a pv entry. 2274 */ 2275static boolean_t 2276pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2277{ 2278 pv_entry_t pv; 2279 2280 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2281 rw_assert(&pvh_global_lock, RA_WLOCKED); 2282 if (pv_entry_count < pv_entry_high_water && 2283 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2284 pv->pv_va = va; 2285 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2286 return (TRUE); 2287 } else 2288 return (FALSE); 2289} 2290 2291/* 2292 * pmap_remove_pte: do the things to unmap a page in a process 2293 */ 2294static int 2295pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2296{ 2297 pt_entry_t oldpte; 2298 vm_page_t m; 2299 2300 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2301 pmap, (u_long)*ptq, va); 2302 2303 rw_assert(&pvh_global_lock, RA_WLOCKED); 2304 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2305 oldpte = *ptq; 2306 PT_SET_VA_MA(ptq, 0, TRUE); 2307 KASSERT(oldpte != 0, 2308 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2309 if (oldpte & PG_W) 2310 pmap->pm_stats.wired_count -= 1; 2311 /* 2312 * Machines that don't support invlpg, also don't support 2313 * PG_G. 2314 */ 2315 if (oldpte & PG_G) 2316 pmap_invalidate_page(kernel_pmap, va); 2317 pmap->pm_stats.resident_count -= 1; 2318 if (oldpte & PG_MANAGED) { 2319 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2320 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2321 vm_page_dirty(m); 2322 if (oldpte & PG_A) 2323 vm_page_aflag_set(m, PGA_REFERENCED); 2324 pmap_remove_entry(pmap, m, va); 2325 } 2326 return (pmap_unuse_pt(pmap, va, free)); 2327} 2328 2329/* 2330 * Remove a single page from a process address space 2331 */ 2332static void 2333pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2334{ 2335 pt_entry_t *pte; 2336 2337 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2338 pmap, va); 2339 2340 rw_assert(&pvh_global_lock, RA_WLOCKED); 2341 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2342 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2343 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2344 return; 2345 pmap_remove_pte(pmap, pte, va, free); 2346 pmap_invalidate_page(pmap, va); 2347 if (*PMAP1) 2348 PT_SET_MA(PADDR1, 0); 2349 2350} 2351 2352/* 2353 * Remove the given range of addresses from the specified map. 2354 * 2355 * It is assumed that the start and end are properly 2356 * rounded to the page size. 2357 */ 2358void 2359pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2360{ 2361 vm_offset_t pdnxt; 2362 pd_entry_t ptpaddr; 2363 pt_entry_t *pte; 2364 vm_page_t free = NULL; 2365 int anyvalid; 2366 2367 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2368 pmap, sva, eva); 2369 2370 /* 2371 * Perform an unsynchronized read. This is, however, safe. 2372 */ 2373 if (pmap->pm_stats.resident_count == 0) 2374 return; 2375 2376 anyvalid = 0; 2377 2378 rw_wlock(&pvh_global_lock); 2379 sched_pin(); 2380 PMAP_LOCK(pmap); 2381 2382 /* 2383 * special handling of removing one page. a very 2384 * common operation and easy to short circuit some 2385 * code. 2386 */ 2387 if ((sva + PAGE_SIZE == eva) && 2388 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2389 pmap_remove_page(pmap, sva, &free); 2390 goto out; 2391 } 2392 2393 for (; sva < eva; sva = pdnxt) { 2394 u_int pdirindex; 2395 2396 /* 2397 * Calculate index for next page table. 2398 */ 2399 pdnxt = (sva + NBPDR) & ~PDRMASK; 2400 if (pdnxt < sva) 2401 pdnxt = eva; 2402 if (pmap->pm_stats.resident_count == 0) 2403 break; 2404 2405 pdirindex = sva >> PDRSHIFT; 2406 ptpaddr = pmap->pm_pdir[pdirindex]; 2407 2408 /* 2409 * Weed out invalid mappings. Note: we assume that the page 2410 * directory table is always allocated, and in kernel virtual. 2411 */ 2412 if (ptpaddr == 0) 2413 continue; 2414 2415 /* 2416 * Check for large page. 2417 */ 2418 if ((ptpaddr & PG_PS) != 0) { 2419 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2420 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2421 anyvalid = 1; 2422 continue; 2423 } 2424 2425 /* 2426 * Limit our scan to either the end of the va represented 2427 * by the current page table page, or to the end of the 2428 * range being removed. 2429 */ 2430 if (pdnxt > eva) 2431 pdnxt = eva; 2432 2433 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2434 sva += PAGE_SIZE) { 2435 if ((*pte & PG_V) == 0) 2436 continue; 2437 2438 /* 2439 * The TLB entry for a PG_G mapping is invalidated 2440 * by pmap_remove_pte(). 2441 */ 2442 if ((*pte & PG_G) == 0) 2443 anyvalid = 1; 2444 if (pmap_remove_pte(pmap, pte, sva, &free)) 2445 break; 2446 } 2447 } 2448 PT_UPDATES_FLUSH(); 2449 if (*PMAP1) 2450 PT_SET_VA_MA(PMAP1, 0, TRUE); 2451out: 2452 if (anyvalid) 2453 pmap_invalidate_all(pmap); 2454 sched_unpin(); 2455 rw_wunlock(&pvh_global_lock); 2456 PMAP_UNLOCK(pmap); 2457 pmap_free_zero_pages(free); 2458} 2459 2460/* 2461 * Routine: pmap_remove_all 2462 * Function: 2463 * Removes this physical page from 2464 * all physical maps in which it resides. 2465 * Reflects back modify bits to the pager. 2466 * 2467 * Notes: 2468 * Original versions of this routine were very 2469 * inefficient because they iteratively called 2470 * pmap_remove (slow...) 2471 */ 2472 2473void 2474pmap_remove_all(vm_page_t m) 2475{ 2476 pv_entry_t pv; 2477 pmap_t pmap; 2478 pt_entry_t *pte, tpte; 2479 vm_page_t free; 2480 2481 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2482 ("pmap_remove_all: page %p is not managed", m)); 2483 free = NULL; 2484 rw_wlock(&pvh_global_lock); 2485 sched_pin(); 2486 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2487 pmap = PV_PMAP(pv); 2488 PMAP_LOCK(pmap); 2489 pmap->pm_stats.resident_count--; 2490 pte = pmap_pte_quick(pmap, pv->pv_va); 2491 tpte = *pte; 2492 PT_SET_VA_MA(pte, 0, TRUE); 2493 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 2494 pmap, pv->pv_va)); 2495 if (tpte & PG_W) 2496 pmap->pm_stats.wired_count--; 2497 if (tpte & PG_A) 2498 vm_page_aflag_set(m, PGA_REFERENCED); 2499 2500 /* 2501 * Update the vm_page_t clean and reference bits. 2502 */ 2503 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2504 vm_page_dirty(m); 2505 pmap_unuse_pt(pmap, pv->pv_va, &free); 2506 pmap_invalidate_page(pmap, pv->pv_va); 2507 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2508 free_pv_entry(pmap, pv); 2509 PMAP_UNLOCK(pmap); 2510 } 2511 vm_page_aflag_clear(m, PGA_WRITEABLE); 2512 PT_UPDATES_FLUSH(); 2513 if (*PMAP1) 2514 PT_SET_MA(PADDR1, 0); 2515 sched_unpin(); 2516 rw_wunlock(&pvh_global_lock); 2517 pmap_free_zero_pages(free); 2518} 2519 2520/* 2521 * Set the physical protection on the 2522 * specified range of this map as requested. 2523 */ 2524void 2525pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2526{ 2527 vm_offset_t pdnxt; 2528 pd_entry_t ptpaddr; 2529 pt_entry_t *pte; 2530 int anychanged; 2531 2532 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2533 pmap, sva, eva, prot); 2534 2535 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2536 pmap_remove(pmap, sva, eva); 2537 return; 2538 } 2539 2540#ifdef PAE 2541 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2542 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2543 return; 2544#else 2545 if (prot & VM_PROT_WRITE) 2546 return; 2547#endif 2548 2549 anychanged = 0; 2550 2551 rw_wlock(&pvh_global_lock); 2552 sched_pin(); 2553 PMAP_LOCK(pmap); 2554 for (; sva < eva; sva = pdnxt) { 2555 pt_entry_t obits, pbits; 2556 u_int pdirindex; 2557 2558 pdnxt = (sva + NBPDR) & ~PDRMASK; 2559 if (pdnxt < sva) 2560 pdnxt = eva; 2561 2562 pdirindex = sva >> PDRSHIFT; 2563 ptpaddr = pmap->pm_pdir[pdirindex]; 2564 2565 /* 2566 * Weed out invalid mappings. Note: we assume that the page 2567 * directory table is always allocated, and in kernel virtual. 2568 */ 2569 if (ptpaddr == 0) 2570 continue; 2571 2572 /* 2573 * Check for large page. 2574 */ 2575 if ((ptpaddr & PG_PS) != 0) { 2576 if ((prot & VM_PROT_WRITE) == 0) 2577 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2578#ifdef PAE 2579 if ((prot & VM_PROT_EXECUTE) == 0) 2580 pmap->pm_pdir[pdirindex] |= pg_nx; 2581#endif 2582 anychanged = 1; 2583 continue; 2584 } 2585 2586 if (pdnxt > eva) 2587 pdnxt = eva; 2588 2589 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2590 sva += PAGE_SIZE) { 2591 vm_page_t m; 2592 2593retry: 2594 /* 2595 * Regardless of whether a pte is 32 or 64 bits in 2596 * size, PG_RW, PG_A, and PG_M are among the least 2597 * significant 32 bits. 2598 */ 2599 obits = pbits = *pte; 2600 if ((pbits & PG_V) == 0) 2601 continue; 2602 2603 if ((prot & VM_PROT_WRITE) == 0) { 2604 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2605 (PG_MANAGED | PG_M | PG_RW)) { 2606 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2607 PG_FRAME); 2608 vm_page_dirty(m); 2609 } 2610 pbits &= ~(PG_RW | PG_M); 2611 } 2612#ifdef PAE 2613 if ((prot & VM_PROT_EXECUTE) == 0) 2614 pbits |= pg_nx; 2615#endif 2616 2617 if (pbits != obits) { 2618 obits = *pte; 2619 PT_SET_VA_MA(pte, pbits, TRUE); 2620 if (*pte != pbits) 2621 goto retry; 2622 if (obits & PG_G) 2623 pmap_invalidate_page(pmap, sva); 2624 else 2625 anychanged = 1; 2626 } 2627 } 2628 } 2629 PT_UPDATES_FLUSH(); 2630 if (*PMAP1) 2631 PT_SET_VA_MA(PMAP1, 0, TRUE); 2632 if (anychanged) 2633 pmap_invalidate_all(pmap); 2634 sched_unpin(); 2635 rw_wunlock(&pvh_global_lock); 2636 PMAP_UNLOCK(pmap); 2637} 2638 2639/* 2640 * Insert the given physical page (p) at 2641 * the specified virtual address (v) in the 2642 * target physical map with the protection requested. 2643 * 2644 * If specified, the page will be wired down, meaning 2645 * that the related pte can not be reclaimed. 2646 * 2647 * NB: This is the only routine which MAY NOT lazy-evaluate 2648 * or lose information. That is, this routine must actually 2649 * insert this page into the given map NOW. 2650 */ 2651void 2652pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2653 vm_prot_t prot, boolean_t wired) 2654{ 2655 pd_entry_t *pde; 2656 pt_entry_t *pte; 2657 pt_entry_t newpte, origpte; 2658 pv_entry_t pv; 2659 vm_paddr_t opa, pa; 2660 vm_page_t mpte, om; 2661 boolean_t invlva; 2662 2663 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2664 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2665 va = trunc_page(va); 2666 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2667 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2668 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2669 va)); 2670 if ((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) == 0) 2671 VM_OBJECT_ASSERT_WLOCKED(m->object); 2672 2673 mpte = NULL; 2674 2675 rw_wlock(&pvh_global_lock); 2676 PMAP_LOCK(pmap); 2677 sched_pin(); 2678 2679 /* 2680 * In the case that a page table page is not 2681 * resident, we are creating it here. 2682 */ 2683 if (va < VM_MAXUSER_ADDRESS) { 2684 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2685 } 2686 2687 pde = pmap_pde(pmap, va); 2688 if ((*pde & PG_PS) != 0) 2689 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2690 pte = pmap_pte_quick(pmap, va); 2691 2692 /* 2693 * Page Directory table entry not valid, we need a new PT page 2694 */ 2695 if (pte == NULL) { 2696 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2697 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2698 } 2699 2700 pa = VM_PAGE_TO_PHYS(m); 2701 om = NULL; 2702 opa = origpte = 0; 2703 2704#if 0 2705 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2706 pte, *pte)); 2707#endif 2708 origpte = *pte; 2709 if (origpte) 2710 origpte = xpmap_mtop(origpte); 2711 opa = origpte & PG_FRAME; 2712 2713 /* 2714 * Mapping has not changed, must be protection or wiring change. 2715 */ 2716 if (origpte && (opa == pa)) { 2717 /* 2718 * Wiring change, just update stats. We don't worry about 2719 * wiring PT pages as they remain resident as long as there 2720 * are valid mappings in them. Hence, if a user page is wired, 2721 * the PT page will be also. 2722 */ 2723 if (wired && ((origpte & PG_W) == 0)) 2724 pmap->pm_stats.wired_count++; 2725 else if (!wired && (origpte & PG_W)) 2726 pmap->pm_stats.wired_count--; 2727 2728 /* 2729 * Remove extra pte reference 2730 */ 2731 if (mpte) 2732 mpte->wire_count--; 2733 2734 if (origpte & PG_MANAGED) { 2735 om = m; 2736 pa |= PG_MANAGED; 2737 } 2738 goto validate; 2739 } 2740 2741 pv = NULL; 2742 2743 /* 2744 * Mapping has changed, invalidate old range and fall through to 2745 * handle validating new mapping. 2746 */ 2747 if (opa) { 2748 if (origpte & PG_W) 2749 pmap->pm_stats.wired_count--; 2750 if (origpte & PG_MANAGED) { 2751 om = PHYS_TO_VM_PAGE(opa); 2752 pv = pmap_pvh_remove(&om->md, pmap, va); 2753 } else if (va < VM_MAXUSER_ADDRESS) 2754 printf("va=0x%x is unmanaged :-( \n", va); 2755 2756 if (mpte != NULL) { 2757 mpte->wire_count--; 2758 KASSERT(mpte->wire_count > 0, 2759 ("pmap_enter: missing reference to page table page," 2760 " va: 0x%x", va)); 2761 } 2762 } else 2763 pmap->pm_stats.resident_count++; 2764 2765 /* 2766 * Enter on the PV list if part of our managed memory. 2767 */ 2768 if ((m->oflags & VPO_UNMANAGED) == 0) { 2769 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2770 ("pmap_enter: managed mapping within the clean submap")); 2771 if (pv == NULL) 2772 pv = get_pv_entry(pmap, FALSE); 2773 pv->pv_va = va; 2774 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2775 pa |= PG_MANAGED; 2776 } else if (pv != NULL) 2777 free_pv_entry(pmap, pv); 2778 2779 /* 2780 * Increment counters 2781 */ 2782 if (wired) 2783 pmap->pm_stats.wired_count++; 2784 2785validate: 2786 /* 2787 * Now validate mapping with desired protection/wiring. 2788 */ 2789 newpte = (pt_entry_t)(pa | PG_V); 2790 if ((prot & VM_PROT_WRITE) != 0) { 2791 newpte |= PG_RW; 2792 if ((newpte & PG_MANAGED) != 0) 2793 vm_page_aflag_set(m, PGA_WRITEABLE); 2794 } 2795#ifdef PAE 2796 if ((prot & VM_PROT_EXECUTE) == 0) 2797 newpte |= pg_nx; 2798#endif 2799 if (wired) 2800 newpte |= PG_W; 2801 if (va < VM_MAXUSER_ADDRESS) 2802 newpte |= PG_U; 2803 if (pmap == kernel_pmap) 2804 newpte |= pgeflag; 2805 2806 critical_enter(); 2807 /* 2808 * if the mapping or permission bits are different, we need 2809 * to update the pte. 2810 */ 2811 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2812 if (origpte) { 2813 invlva = FALSE; 2814 origpte = *pte; 2815 PT_SET_VA(pte, newpte | PG_A, FALSE); 2816 if (origpte & PG_A) { 2817 if (origpte & PG_MANAGED) 2818 vm_page_aflag_set(om, PGA_REFERENCED); 2819 if (opa != VM_PAGE_TO_PHYS(m)) 2820 invlva = TRUE; 2821#ifdef PAE 2822 if ((origpte & PG_NX) == 0 && 2823 (newpte & PG_NX) != 0) 2824 invlva = TRUE; 2825#endif 2826 } 2827 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2828 if ((origpte & PG_MANAGED) != 0) 2829 vm_page_dirty(om); 2830 if ((prot & VM_PROT_WRITE) == 0) 2831 invlva = TRUE; 2832 } 2833 if ((origpte & PG_MANAGED) != 0 && 2834 TAILQ_EMPTY(&om->md.pv_list)) 2835 vm_page_aflag_clear(om, PGA_WRITEABLE); 2836 if (invlva) 2837 pmap_invalidate_page(pmap, va); 2838 } else{ 2839 PT_SET_VA(pte, newpte | PG_A, FALSE); 2840 } 2841 2842 } 2843 PT_UPDATES_FLUSH(); 2844 critical_exit(); 2845 if (*PMAP1) 2846 PT_SET_VA_MA(PMAP1, 0, TRUE); 2847 sched_unpin(); 2848 rw_wunlock(&pvh_global_lock); 2849 PMAP_UNLOCK(pmap); 2850} 2851 2852/* 2853 * Maps a sequence of resident pages belonging to the same object. 2854 * The sequence begins with the given page m_start. This page is 2855 * mapped at the given virtual address start. Each subsequent page is 2856 * mapped at a virtual address that is offset from start by the same 2857 * amount as the page is offset from m_start within the object. The 2858 * last page in the sequence is the page with the largest offset from 2859 * m_start that can be mapped at a virtual address less than the given 2860 * virtual address end. Not every virtual page between start and end 2861 * is mapped; only those for which a resident page exists with the 2862 * corresponding offset from m_start are mapped. 2863 */ 2864void 2865pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2866 vm_page_t m_start, vm_prot_t prot) 2867{ 2868 vm_page_t m, mpte; 2869 vm_pindex_t diff, psize; 2870 multicall_entry_t mcl[16]; 2871 multicall_entry_t *mclp = mcl; 2872 int error, count = 0; 2873 2874 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2875 2876 psize = atop(end - start); 2877 mpte = NULL; 2878 m = m_start; 2879 rw_wlock(&pvh_global_lock); 2880 PMAP_LOCK(pmap); 2881 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2882 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2883 prot, mpte); 2884 m = TAILQ_NEXT(m, listq); 2885 if (count == 16) { 2886 error = HYPERVISOR_multicall(mcl, count); 2887 KASSERT(error == 0, ("bad multicall %d", error)); 2888 mclp = mcl; 2889 count = 0; 2890 } 2891 } 2892 if (count) { 2893 error = HYPERVISOR_multicall(mcl, count); 2894 KASSERT(error == 0, ("bad multicall %d", error)); 2895 } 2896 rw_wunlock(&pvh_global_lock); 2897 PMAP_UNLOCK(pmap); 2898} 2899 2900/* 2901 * this code makes some *MAJOR* assumptions: 2902 * 1. Current pmap & pmap exists. 2903 * 2. Not wired. 2904 * 3. Read access. 2905 * 4. No page table pages. 2906 * but is *MUCH* faster than pmap_enter... 2907 */ 2908 2909void 2910pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2911{ 2912 multicall_entry_t mcl, *mclp; 2913 int count = 0; 2914 mclp = &mcl; 2915 2916 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2917 pmap, va, m, prot); 2918 2919 rw_wlock(&pvh_global_lock); 2920 PMAP_LOCK(pmap); 2921 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2922 if (count) 2923 HYPERVISOR_multicall(&mcl, count); 2924 rw_wunlock(&pvh_global_lock); 2925 PMAP_UNLOCK(pmap); 2926} 2927 2928#ifdef notyet 2929void 2930pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2931{ 2932 int i, error, index = 0; 2933 multicall_entry_t mcl[16]; 2934 multicall_entry_t *mclp = mcl; 2935 2936 PMAP_LOCK(pmap); 2937 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2938 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2939 continue; 2940 2941 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2942 if (index == 16) { 2943 error = HYPERVISOR_multicall(mcl, index); 2944 mclp = mcl; 2945 index = 0; 2946 KASSERT(error == 0, ("bad multicall %d", error)); 2947 } 2948 } 2949 if (index) { 2950 error = HYPERVISOR_multicall(mcl, index); 2951 KASSERT(error == 0, ("bad multicall %d", error)); 2952 } 2953 2954 PMAP_UNLOCK(pmap); 2955} 2956#endif 2957 2958static vm_page_t 2959pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2960 vm_prot_t prot, vm_page_t mpte) 2961{ 2962 pt_entry_t *pte; 2963 vm_paddr_t pa; 2964 vm_page_t free; 2965 multicall_entry_t *mcl = *mclpp; 2966 2967 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2968 (m->oflags & VPO_UNMANAGED) != 0, 2969 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2970 rw_assert(&pvh_global_lock, RA_WLOCKED); 2971 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2972 2973 /* 2974 * In the case that a page table page is not 2975 * resident, we are creating it here. 2976 */ 2977 if (va < VM_MAXUSER_ADDRESS) { 2978 u_int ptepindex; 2979 pd_entry_t ptema; 2980 2981 /* 2982 * Calculate pagetable page index 2983 */ 2984 ptepindex = va >> PDRSHIFT; 2985 if (mpte && (mpte->pindex == ptepindex)) { 2986 mpte->wire_count++; 2987 } else { 2988 /* 2989 * Get the page directory entry 2990 */ 2991 ptema = pmap->pm_pdir[ptepindex]; 2992 2993 /* 2994 * If the page table page is mapped, we just increment 2995 * the hold count, and activate it. 2996 */ 2997 if (ptema & PG_V) { 2998 if (ptema & PG_PS) 2999 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 3000 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 3001 mpte->wire_count++; 3002 } else { 3003 mpte = _pmap_allocpte(pmap, ptepindex, 3004 M_NOWAIT); 3005 if (mpte == NULL) 3006 return (mpte); 3007 } 3008 } 3009 } else { 3010 mpte = NULL; 3011 } 3012 3013 /* 3014 * This call to vtopte makes the assumption that we are 3015 * entering the page into the current pmap. In order to support 3016 * quick entry into any pmap, one would likely use pmap_pte_quick. 3017 * But that isn't as quick as vtopte. 3018 */ 3019 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 3020 pte = vtopte(va); 3021 if (*pte & PG_V) { 3022 if (mpte != NULL) { 3023 mpte->wire_count--; 3024 mpte = NULL; 3025 } 3026 return (mpte); 3027 } 3028 3029 /* 3030 * Enter on the PV list if part of our managed memory. 3031 */ 3032 if ((m->oflags & VPO_UNMANAGED) == 0 && 3033 !pmap_try_insert_pv_entry(pmap, va, m)) { 3034 if (mpte != NULL) { 3035 free = NULL; 3036 if (pmap_unwire_ptp(pmap, mpte, &free)) { 3037 pmap_invalidate_page(pmap, va); 3038 pmap_free_zero_pages(free); 3039 } 3040 3041 mpte = NULL; 3042 } 3043 return (mpte); 3044 } 3045 3046 /* 3047 * Increment counters 3048 */ 3049 pmap->pm_stats.resident_count++; 3050 3051 pa = VM_PAGE_TO_PHYS(m); 3052#ifdef PAE 3053 if ((prot & VM_PROT_EXECUTE) == 0) 3054 pa |= pg_nx; 3055#endif 3056 3057#if 0 3058 /* 3059 * Now validate mapping with RO protection 3060 */ 3061 if ((m->oflags & VPO_UNMANAGED) != 0) 3062 pte_store(pte, pa | PG_V | PG_U); 3063 else 3064 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3065#else 3066 /* 3067 * Now validate mapping with RO protection 3068 */ 3069 if ((m->oflags & VPO_UNMANAGED) != 0) 3070 pa = xpmap_ptom(pa | PG_V | PG_U); 3071 else 3072 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3073 3074 mcl->op = __HYPERVISOR_update_va_mapping; 3075 mcl->args[0] = va; 3076 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3077 mcl->args[2] = (uint32_t)(pa >> 32); 3078 mcl->args[3] = 0; 3079 *mclpp = mcl + 1; 3080 *count = *count + 1; 3081#endif 3082 return (mpte); 3083} 3084 3085/* 3086 * Make a temporary mapping for a physical address. This is only intended 3087 * to be used for panic dumps. 3088 */ 3089void * 3090pmap_kenter_temporary(vm_paddr_t pa, int i) 3091{ 3092 vm_offset_t va; 3093 vm_paddr_t ma = xpmap_ptom(pa); 3094 3095 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3096 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3097 invlpg(va); 3098 return ((void *)crashdumpmap); 3099} 3100 3101/* 3102 * This code maps large physical mmap regions into the 3103 * processor address space. Note that some shortcuts 3104 * are taken, but the code works. 3105 */ 3106void 3107pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3108 vm_pindex_t pindex, vm_size_t size) 3109{ 3110 pd_entry_t *pde; 3111 vm_paddr_t pa, ptepa; 3112 vm_page_t p; 3113 int pat_mode; 3114 3115 VM_OBJECT_ASSERT_WLOCKED(object); 3116 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3117 ("pmap_object_init_pt: non-device object")); 3118 if (pseflag && 3119 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3120 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3121 return; 3122 p = vm_page_lookup(object, pindex); 3123 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3124 ("pmap_object_init_pt: invalid page %p", p)); 3125 pat_mode = p->md.pat_mode; 3126 3127 /* 3128 * Abort the mapping if the first page is not physically 3129 * aligned to a 2/4MB page boundary. 3130 */ 3131 ptepa = VM_PAGE_TO_PHYS(p); 3132 if (ptepa & (NBPDR - 1)) 3133 return; 3134 3135 /* 3136 * Skip the first page. Abort the mapping if the rest of 3137 * the pages are not physically contiguous or have differing 3138 * memory attributes. 3139 */ 3140 p = TAILQ_NEXT(p, listq); 3141 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3142 pa += PAGE_SIZE) { 3143 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3144 ("pmap_object_init_pt: invalid page %p", p)); 3145 if (pa != VM_PAGE_TO_PHYS(p) || 3146 pat_mode != p->md.pat_mode) 3147 return; 3148 p = TAILQ_NEXT(p, listq); 3149 } 3150 3151 /* 3152 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3153 * "size" is a multiple of 2/4M, adding the PAT setting to 3154 * "pa" will not affect the termination of this loop. 3155 */ 3156 PMAP_LOCK(pmap); 3157 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3158 size; pa += NBPDR) { 3159 pde = pmap_pde(pmap, addr); 3160 if (*pde == 0) { 3161 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3162 PG_U | PG_RW | PG_V); 3163 pmap->pm_stats.resident_count += NBPDR / 3164 PAGE_SIZE; 3165 pmap_pde_mappings++; 3166 } 3167 /* Else continue on if the PDE is already valid. */ 3168 addr += NBPDR; 3169 } 3170 PMAP_UNLOCK(pmap); 3171 } 3172} 3173 3174/* 3175 * Routine: pmap_change_wiring 3176 * Function: Change the wiring attribute for a map/virtual-address 3177 * pair. 3178 * In/out conditions: 3179 * The mapping must already exist in the pmap. 3180 */ 3181void 3182pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3183{ 3184 pt_entry_t *pte; 3185 3186 rw_wlock(&pvh_global_lock); 3187 PMAP_LOCK(pmap); 3188 pte = pmap_pte(pmap, va); 3189 3190 if (wired && !pmap_pte_w(pte)) { 3191 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3192 pmap->pm_stats.wired_count++; 3193 } else if (!wired && pmap_pte_w(pte)) { 3194 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3195 pmap->pm_stats.wired_count--; 3196 } 3197 3198 /* 3199 * Wiring is not a hardware characteristic so there is no need to 3200 * invalidate TLB. 3201 */ 3202 pmap_pte_release(pte); 3203 PMAP_UNLOCK(pmap); 3204 rw_wunlock(&pvh_global_lock); 3205} 3206 3207 3208 3209/* 3210 * Copy the range specified by src_addr/len 3211 * from the source map to the range dst_addr/len 3212 * in the destination map. 3213 * 3214 * This routine is only advisory and need not do anything. 3215 */ 3216 3217void 3218pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3219 vm_offset_t src_addr) 3220{ 3221 vm_page_t free; 3222 vm_offset_t addr; 3223 vm_offset_t end_addr = src_addr + len; 3224 vm_offset_t pdnxt; 3225 3226 if (dst_addr != src_addr) 3227 return; 3228 3229 if (!pmap_is_current(src_pmap)) { 3230 CTR2(KTR_PMAP, 3231 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3232 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3233 3234 return; 3235 } 3236 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3237 dst_pmap, src_pmap, dst_addr, len, src_addr); 3238 3239#ifdef HAMFISTED_LOCKING 3240 mtx_lock(&createdelete_lock); 3241#endif 3242 3243 rw_wlock(&pvh_global_lock); 3244 if (dst_pmap < src_pmap) { 3245 PMAP_LOCK(dst_pmap); 3246 PMAP_LOCK(src_pmap); 3247 } else { 3248 PMAP_LOCK(src_pmap); 3249 PMAP_LOCK(dst_pmap); 3250 } 3251 sched_pin(); 3252 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3253 pt_entry_t *src_pte, *dst_pte; 3254 vm_page_t dstmpte, srcmpte; 3255 pd_entry_t srcptepaddr; 3256 u_int ptepindex; 3257 3258 KASSERT(addr < UPT_MIN_ADDRESS, 3259 ("pmap_copy: invalid to pmap_copy page tables")); 3260 3261 pdnxt = (addr + NBPDR) & ~PDRMASK; 3262 if (pdnxt < addr) 3263 pdnxt = end_addr; 3264 ptepindex = addr >> PDRSHIFT; 3265 3266 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3267 if (srcptepaddr == 0) 3268 continue; 3269 3270 if (srcptepaddr & PG_PS) { 3271 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3272 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3273 dst_pmap->pm_stats.resident_count += 3274 NBPDR / PAGE_SIZE; 3275 } 3276 continue; 3277 } 3278 3279 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3280 KASSERT(srcmpte->wire_count > 0, 3281 ("pmap_copy: source page table page is unused")); 3282 3283 if (pdnxt > end_addr) 3284 pdnxt = end_addr; 3285 3286 src_pte = vtopte(addr); 3287 while (addr < pdnxt) { 3288 pt_entry_t ptetemp; 3289 ptetemp = *src_pte; 3290 /* 3291 * we only virtual copy managed pages 3292 */ 3293 if ((ptetemp & PG_MANAGED) != 0) { 3294 dstmpte = pmap_allocpte(dst_pmap, addr, 3295 M_NOWAIT); 3296 if (dstmpte == NULL) 3297 goto out; 3298 dst_pte = pmap_pte_quick(dst_pmap, addr); 3299 if (*dst_pte == 0 && 3300 pmap_try_insert_pv_entry(dst_pmap, addr, 3301 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3302 /* 3303 * Clear the wired, modified, and 3304 * accessed (referenced) bits 3305 * during the copy. 3306 */ 3307 KASSERT(ptetemp != 0, ("src_pte not set")); 3308 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3309 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3310 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3311 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3312 dst_pmap->pm_stats.resident_count++; 3313 } else { 3314 free = NULL; 3315 if (pmap_unwire_ptp(dst_pmap, dstmpte, 3316 &free)) { 3317 pmap_invalidate_page(dst_pmap, 3318 addr); 3319 pmap_free_zero_pages(free); 3320 } 3321 goto out; 3322 } 3323 if (dstmpte->wire_count >= srcmpte->wire_count) 3324 break; 3325 } 3326 addr += PAGE_SIZE; 3327 src_pte++; 3328 } 3329 } 3330out: 3331 PT_UPDATES_FLUSH(); 3332 sched_unpin(); 3333 rw_wunlock(&pvh_global_lock); 3334 PMAP_UNLOCK(src_pmap); 3335 PMAP_UNLOCK(dst_pmap); 3336 3337#ifdef HAMFISTED_LOCKING 3338 mtx_unlock(&createdelete_lock); 3339#endif 3340} 3341 3342static __inline void 3343pagezero(void *page) 3344{ 3345#if defined(I686_CPU) 3346 if (cpu_class == CPUCLASS_686) { 3347#if defined(CPU_ENABLE_SSE) 3348 if (cpu_feature & CPUID_SSE2) 3349 sse2_pagezero(page); 3350 else 3351#endif 3352 i686_pagezero(page); 3353 } else 3354#endif 3355 bzero(page, PAGE_SIZE); 3356} 3357 3358/* 3359 * pmap_zero_page zeros the specified hardware page by mapping 3360 * the page into KVM and using bzero to clear its contents. 3361 */ 3362void 3363pmap_zero_page(vm_page_t m) 3364{ 3365 struct sysmaps *sysmaps; 3366 3367 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3368 mtx_lock(&sysmaps->lock); 3369 if (*sysmaps->CMAP2) 3370 panic("pmap_zero_page: CMAP2 busy"); 3371 sched_pin(); 3372 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3373 pagezero(sysmaps->CADDR2); 3374 PT_SET_MA(sysmaps->CADDR2, 0); 3375 sched_unpin(); 3376 mtx_unlock(&sysmaps->lock); 3377} 3378 3379/* 3380 * pmap_zero_page_area zeros the specified hardware page by mapping 3381 * the page into KVM and using bzero to clear its contents. 3382 * 3383 * off and size may not cover an area beyond a single hardware page. 3384 */ 3385void 3386pmap_zero_page_area(vm_page_t m, int off, int size) 3387{ 3388 struct sysmaps *sysmaps; 3389 3390 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3391 mtx_lock(&sysmaps->lock); 3392 if (*sysmaps->CMAP2) 3393 panic("pmap_zero_page_area: CMAP2 busy"); 3394 sched_pin(); 3395 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3396 3397 if (off == 0 && size == PAGE_SIZE) 3398 pagezero(sysmaps->CADDR2); 3399 else 3400 bzero((char *)sysmaps->CADDR2 + off, size); 3401 PT_SET_MA(sysmaps->CADDR2, 0); 3402 sched_unpin(); 3403 mtx_unlock(&sysmaps->lock); 3404} 3405 3406/* 3407 * pmap_zero_page_idle zeros the specified hardware page by mapping 3408 * the page into KVM and using bzero to clear its contents. This 3409 * is intended to be called from the vm_pagezero process only and 3410 * outside of Giant. 3411 */ 3412void 3413pmap_zero_page_idle(vm_page_t m) 3414{ 3415 3416 if (*CMAP3) 3417 panic("pmap_zero_page_idle: CMAP3 busy"); 3418 sched_pin(); 3419 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3420 pagezero(CADDR3); 3421 PT_SET_MA(CADDR3, 0); 3422 sched_unpin(); 3423} 3424 3425/* 3426 * pmap_copy_page copies the specified (machine independent) 3427 * page by mapping the page into virtual memory and using 3428 * bcopy to copy the page, one machine dependent page at a 3429 * time. 3430 */ 3431void 3432pmap_copy_page(vm_page_t src, vm_page_t dst) 3433{ 3434 struct sysmaps *sysmaps; 3435 3436 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3437 mtx_lock(&sysmaps->lock); 3438 if (*sysmaps->CMAP1) 3439 panic("pmap_copy_page: CMAP1 busy"); 3440 if (*sysmaps->CMAP2) 3441 panic("pmap_copy_page: CMAP2 busy"); 3442 sched_pin(); 3443 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3444 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3445 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3446 PT_SET_MA(sysmaps->CADDR1, 0); 3447 PT_SET_MA(sysmaps->CADDR2, 0); 3448 sched_unpin(); 3449 mtx_unlock(&sysmaps->lock); 3450} 3451 3452int unmapped_buf_allowed = 1; 3453 3454void 3455pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 3456 vm_offset_t b_offset, int xfersize) 3457{ 3458 struct sysmaps *sysmaps; 3459 vm_page_t a_pg, b_pg; 3460 char *a_cp, *b_cp; 3461 vm_offset_t a_pg_offset, b_pg_offset; 3462 int cnt; 3463 3464 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3465 mtx_lock(&sysmaps->lock); 3466 if (*sysmaps->CMAP1 != 0) 3467 panic("pmap_copy_pages: CMAP1 busy"); 3468 if (*sysmaps->CMAP2 != 0) 3469 panic("pmap_copy_pages: CMAP2 busy"); 3470 sched_pin(); 3471 while (xfersize > 0) { 3472 a_pg = ma[a_offset >> PAGE_SHIFT]; 3473 a_pg_offset = a_offset & PAGE_MASK; 3474 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3475 b_pg = mb[b_offset >> PAGE_SHIFT]; 3476 b_pg_offset = b_offset & PAGE_MASK; 3477 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3478 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(a_pg) | PG_A); 3479 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 3480 VM_PAGE_TO_MACH(b_pg) | PG_A | PG_M); 3481 a_cp = sysmaps->CADDR1 + a_pg_offset; 3482 b_cp = sysmaps->CADDR2 + b_pg_offset; 3483 bcopy(a_cp, b_cp, cnt); 3484 a_offset += cnt; 3485 b_offset += cnt; 3486 xfersize -= cnt; 3487 } 3488 PT_SET_MA(sysmaps->CADDR1, 0); 3489 PT_SET_MA(sysmaps->CADDR2, 0); 3490 sched_unpin(); 3491 mtx_unlock(&sysmaps->lock); 3492} 3493 3494/* 3495 * Returns true if the pmap's pv is one of the first 3496 * 16 pvs linked to from this page. This count may 3497 * be changed upwards or downwards in the future; it 3498 * is only necessary that true be returned for a small 3499 * subset of pmaps for proper page aging. 3500 */ 3501boolean_t 3502pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3503{ 3504 pv_entry_t pv; 3505 int loops = 0; 3506 boolean_t rv; 3507 3508 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3509 ("pmap_page_exists_quick: page %p is not managed", m)); 3510 rv = FALSE; 3511 rw_wlock(&pvh_global_lock); 3512 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3513 if (PV_PMAP(pv) == pmap) { 3514 rv = TRUE; 3515 break; 3516 } 3517 loops++; 3518 if (loops >= 16) 3519 break; 3520 } 3521 rw_wunlock(&pvh_global_lock); 3522 return (rv); 3523} 3524 3525/* 3526 * pmap_page_wired_mappings: 3527 * 3528 * Return the number of managed mappings to the given physical page 3529 * that are wired. 3530 */ 3531int 3532pmap_page_wired_mappings(vm_page_t m) 3533{ 3534 pv_entry_t pv; 3535 pt_entry_t *pte; 3536 pmap_t pmap; 3537 int count; 3538 3539 count = 0; 3540 if ((m->oflags & VPO_UNMANAGED) != 0) 3541 return (count); 3542 rw_wlock(&pvh_global_lock); 3543 sched_pin(); 3544 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3545 pmap = PV_PMAP(pv); 3546 PMAP_LOCK(pmap); 3547 pte = pmap_pte_quick(pmap, pv->pv_va); 3548 if ((*pte & PG_W) != 0) 3549 count++; 3550 PMAP_UNLOCK(pmap); 3551 } 3552 sched_unpin(); 3553 rw_wunlock(&pvh_global_lock); 3554 return (count); 3555} 3556 3557/* 3558 * Returns TRUE if the given page is mapped. Otherwise, returns FALSE. 3559 */ 3560boolean_t 3561pmap_page_is_mapped(vm_page_t m) 3562{ 3563 3564 if ((m->oflags & VPO_UNMANAGED) != 0) 3565 return (FALSE); 3566 return (!TAILQ_EMPTY(&m->md.pv_list)); 3567} 3568 3569/* 3570 * Remove all pages from specified address space 3571 * this aids process exit speeds. Also, this code 3572 * is special cased for current process only, but 3573 * can have the more generic (and slightly slower) 3574 * mode enabled. This is much faster than pmap_remove 3575 * in the case of running down an entire address space. 3576 */ 3577void 3578pmap_remove_pages(pmap_t pmap) 3579{ 3580 pt_entry_t *pte, tpte; 3581 vm_page_t m, free = NULL; 3582 pv_entry_t pv; 3583 struct pv_chunk *pc, *npc; 3584 int field, idx; 3585 int32_t bit; 3586 uint32_t inuse, bitmask; 3587 int allfree; 3588 3589 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3590 3591 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3592 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3593 return; 3594 } 3595 rw_wlock(&pvh_global_lock); 3596 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3597 PMAP_LOCK(pmap); 3598 sched_pin(); 3599 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3600 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 3601 pc->pc_pmap)); 3602 allfree = 1; 3603 for (field = 0; field < _NPCM; field++) { 3604 inuse = ~pc->pc_map[field] & pc_freemask[field]; 3605 while (inuse != 0) { 3606 bit = bsfl(inuse); 3607 bitmask = 1UL << bit; 3608 idx = field * 32 + bit; 3609 pv = &pc->pc_pventry[idx]; 3610 inuse &= ~bitmask; 3611 3612 pte = vtopte(pv->pv_va); 3613 tpte = *pte ? xpmap_mtop(*pte) : 0; 3614 3615 if (tpte == 0) { 3616 printf( 3617 "TPTE at %p IS ZERO @ VA %08x\n", 3618 pte, pv->pv_va); 3619 panic("bad pte"); 3620 } 3621 3622/* 3623 * We cannot remove wired pages from a process' mapping at this time 3624 */ 3625 if (tpte & PG_W) { 3626 allfree = 0; 3627 continue; 3628 } 3629 3630 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3631 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3632 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3633 m, (uintmax_t)m->phys_addr, 3634 (uintmax_t)tpte)); 3635 3636 KASSERT(m < &vm_page_array[vm_page_array_size], 3637 ("pmap_remove_pages: bad tpte %#jx", 3638 (uintmax_t)tpte)); 3639 3640 3641 PT_CLEAR_VA(pte, FALSE); 3642 3643 /* 3644 * Update the vm_page_t clean/reference bits. 3645 */ 3646 if (tpte & PG_M) 3647 vm_page_dirty(m); 3648 3649 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3650 if (TAILQ_EMPTY(&m->md.pv_list)) 3651 vm_page_aflag_clear(m, PGA_WRITEABLE); 3652 3653 pmap_unuse_pt(pmap, pv->pv_va, &free); 3654 3655 /* Mark free */ 3656 PV_STAT(pv_entry_frees++); 3657 PV_STAT(pv_entry_spare++); 3658 pv_entry_count--; 3659 pc->pc_map[field] |= bitmask; 3660 pmap->pm_stats.resident_count--; 3661 } 3662 } 3663 PT_UPDATES_FLUSH(); 3664 if (allfree) { 3665 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3666 free_pv_chunk(pc); 3667 } 3668 } 3669 PT_UPDATES_FLUSH(); 3670 if (*PMAP1) 3671 PT_SET_MA(PADDR1, 0); 3672 3673 sched_unpin(); 3674 pmap_invalidate_all(pmap); 3675 rw_wunlock(&pvh_global_lock); 3676 PMAP_UNLOCK(pmap); 3677 pmap_free_zero_pages(free); 3678} 3679 3680/* 3681 * pmap_is_modified: 3682 * 3683 * Return whether or not the specified physical page was modified 3684 * in any physical maps. 3685 */ 3686boolean_t 3687pmap_is_modified(vm_page_t m) 3688{ 3689 pv_entry_t pv; 3690 pt_entry_t *pte; 3691 pmap_t pmap; 3692 boolean_t rv; 3693 3694 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3695 ("pmap_is_modified: page %p is not managed", m)); 3696 rv = FALSE; 3697 3698 /* 3699 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 3700 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3701 * is clear, no PTEs can have PG_M set. 3702 */ 3703 VM_OBJECT_ASSERT_WLOCKED(m->object); 3704 if ((m->oflags & VPO_BUSY) == 0 && 3705 (m->aflags & PGA_WRITEABLE) == 0) 3706 return (rv); 3707 rw_wlock(&pvh_global_lock); 3708 sched_pin(); 3709 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3710 pmap = PV_PMAP(pv); 3711 PMAP_LOCK(pmap); 3712 pte = pmap_pte_quick(pmap, pv->pv_va); 3713 rv = (*pte & PG_M) != 0; 3714 PMAP_UNLOCK(pmap); 3715 if (rv) 3716 break; 3717 } 3718 if (*PMAP1) 3719 PT_SET_MA(PADDR1, 0); 3720 sched_unpin(); 3721 rw_wunlock(&pvh_global_lock); 3722 return (rv); 3723} 3724 3725/* 3726 * pmap_is_prefaultable: 3727 * 3728 * Return whether or not the specified virtual address is elgible 3729 * for prefault. 3730 */ 3731static boolean_t 3732pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3733{ 3734 pt_entry_t *pte; 3735 boolean_t rv = FALSE; 3736 3737 return (rv); 3738 3739 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3740 pte = vtopte(addr); 3741 rv = (*pte == 0); 3742 } 3743 return (rv); 3744} 3745 3746boolean_t 3747pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3748{ 3749 boolean_t rv; 3750 3751 PMAP_LOCK(pmap); 3752 rv = pmap_is_prefaultable_locked(pmap, addr); 3753 PMAP_UNLOCK(pmap); 3754 return (rv); 3755} 3756 3757boolean_t 3758pmap_is_referenced(vm_page_t m) 3759{ 3760 pv_entry_t pv; 3761 pt_entry_t *pte; 3762 pmap_t pmap; 3763 boolean_t rv; 3764 3765 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3766 ("pmap_is_referenced: page %p is not managed", m)); 3767 rv = FALSE; 3768 rw_wlock(&pvh_global_lock); 3769 sched_pin(); 3770 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3771 pmap = PV_PMAP(pv); 3772 PMAP_LOCK(pmap); 3773 pte = pmap_pte_quick(pmap, pv->pv_va); 3774 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3775 PMAP_UNLOCK(pmap); 3776 if (rv) 3777 break; 3778 } 3779 if (*PMAP1) 3780 PT_SET_MA(PADDR1, 0); 3781 sched_unpin(); 3782 rw_wunlock(&pvh_global_lock); 3783 return (rv); 3784} 3785 3786void 3787pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3788{ 3789 int i, npages = round_page(len) >> PAGE_SHIFT; 3790 for (i = 0; i < npages; i++) { 3791 pt_entry_t *pte; 3792 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3793 rw_wlock(&pvh_global_lock); 3794 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3795 rw_wunlock(&pvh_global_lock); 3796 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3797 pmap_pte_release(pte); 3798 } 3799} 3800 3801void 3802pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3803{ 3804 int i, npages = round_page(len) >> PAGE_SHIFT; 3805 for (i = 0; i < npages; i++) { 3806 pt_entry_t *pte; 3807 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3808 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3809 rw_wlock(&pvh_global_lock); 3810 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3811 rw_wunlock(&pvh_global_lock); 3812 pmap_pte_release(pte); 3813 } 3814} 3815 3816/* 3817 * Clear the write and modified bits in each of the given page's mappings. 3818 */ 3819void 3820pmap_remove_write(vm_page_t m) 3821{ 3822 pv_entry_t pv; 3823 pmap_t pmap; 3824 pt_entry_t oldpte, *pte; 3825 3826 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3827 ("pmap_remove_write: page %p is not managed", m)); 3828 3829 /* 3830 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 3831 * another thread while the object is locked. Thus, if PGA_WRITEABLE 3832 * is clear, no page table entries need updating. 3833 */ 3834 VM_OBJECT_ASSERT_WLOCKED(m->object); 3835 if ((m->oflags & VPO_BUSY) == 0 && 3836 (m->aflags & PGA_WRITEABLE) == 0) 3837 return; 3838 rw_wlock(&pvh_global_lock); 3839 sched_pin(); 3840 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3841 pmap = PV_PMAP(pv); 3842 PMAP_LOCK(pmap); 3843 pte = pmap_pte_quick(pmap, pv->pv_va); 3844retry: 3845 oldpte = *pte; 3846 if ((oldpte & PG_RW) != 0) { 3847 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3848 3849 /* 3850 * Regardless of whether a pte is 32 or 64 bits 3851 * in size, PG_RW and PG_M are among the least 3852 * significant 32 bits. 3853 */ 3854 PT_SET_VA_MA(pte, newpte, TRUE); 3855 if (*pte != newpte) 3856 goto retry; 3857 3858 if ((oldpte & PG_M) != 0) 3859 vm_page_dirty(m); 3860 pmap_invalidate_page(pmap, pv->pv_va); 3861 } 3862 PMAP_UNLOCK(pmap); 3863 } 3864 vm_page_aflag_clear(m, PGA_WRITEABLE); 3865 PT_UPDATES_FLUSH(); 3866 if (*PMAP1) 3867 PT_SET_MA(PADDR1, 0); 3868 sched_unpin(); 3869 rw_wunlock(&pvh_global_lock); 3870} 3871 3872/* 3873 * pmap_ts_referenced: 3874 * 3875 * Return a count of reference bits for a page, clearing those bits. 3876 * It is not necessary for every reference bit to be cleared, but it 3877 * is necessary that 0 only be returned when there are truly no 3878 * reference bits set. 3879 * 3880 * XXX: The exact number of bits to check and clear is a matter that 3881 * should be tested and standardized at some point in the future for 3882 * optimal aging of shared pages. 3883 */ 3884int 3885pmap_ts_referenced(vm_page_t m) 3886{ 3887 pv_entry_t pv, pvf, pvn; 3888 pmap_t pmap; 3889 pt_entry_t *pte; 3890 int rtval = 0; 3891 3892 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3893 ("pmap_ts_referenced: page %p is not managed", m)); 3894 rw_wlock(&pvh_global_lock); 3895 sched_pin(); 3896 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3897 pvf = pv; 3898 do { 3899 pvn = TAILQ_NEXT(pv, pv_next); 3900 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3901 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3902 pmap = PV_PMAP(pv); 3903 PMAP_LOCK(pmap); 3904 pte = pmap_pte_quick(pmap, pv->pv_va); 3905 if ((*pte & PG_A) != 0) { 3906 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3907 pmap_invalidate_page(pmap, pv->pv_va); 3908 rtval++; 3909 if (rtval > 4) 3910 pvn = NULL; 3911 } 3912 PMAP_UNLOCK(pmap); 3913 } while ((pv = pvn) != NULL && pv != pvf); 3914 } 3915 PT_UPDATES_FLUSH(); 3916 if (*PMAP1) 3917 PT_SET_MA(PADDR1, 0); 3918 sched_unpin(); 3919 rw_wunlock(&pvh_global_lock); 3920 return (rtval); 3921} 3922 3923/* 3924 * Clear the modify bits on the specified physical page. 3925 */ 3926void 3927pmap_clear_modify(vm_page_t m) 3928{ 3929 pv_entry_t pv; 3930 pmap_t pmap; 3931 pt_entry_t *pte; 3932 3933 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3934 ("pmap_clear_modify: page %p is not managed", m)); 3935 VM_OBJECT_ASSERT_WLOCKED(m->object); 3936 KASSERT((m->oflags & VPO_BUSY) == 0, 3937 ("pmap_clear_modify: page %p is busy", m)); 3938 3939 /* 3940 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 3941 * If the object containing the page is locked and the page is not 3942 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 3943 */ 3944 if ((m->aflags & PGA_WRITEABLE) == 0) 3945 return; 3946 rw_wlock(&pvh_global_lock); 3947 sched_pin(); 3948 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3949 pmap = PV_PMAP(pv); 3950 PMAP_LOCK(pmap); 3951 pte = pmap_pte_quick(pmap, pv->pv_va); 3952 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3953 /* 3954 * Regardless of whether a pte is 32 or 64 bits 3955 * in size, PG_M is among the least significant 3956 * 32 bits. 3957 */ 3958 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3959 pmap_invalidate_page(pmap, pv->pv_va); 3960 } 3961 PMAP_UNLOCK(pmap); 3962 } 3963 sched_unpin(); 3964 rw_wunlock(&pvh_global_lock); 3965} 3966 3967/* 3968 * pmap_clear_reference: 3969 * 3970 * Clear the reference bit on the specified physical page. 3971 */ 3972void 3973pmap_clear_reference(vm_page_t m) 3974{ 3975 pv_entry_t pv; 3976 pmap_t pmap; 3977 pt_entry_t *pte; 3978 3979 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3980 ("pmap_clear_reference: page %p is not managed", m)); 3981 rw_wlock(&pvh_global_lock); 3982 sched_pin(); 3983 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3984 pmap = PV_PMAP(pv); 3985 PMAP_LOCK(pmap); 3986 pte = pmap_pte_quick(pmap, pv->pv_va); 3987 if ((*pte & PG_A) != 0) { 3988 /* 3989 * Regardless of whether a pte is 32 or 64 bits 3990 * in size, PG_A is among the least significant 3991 * 32 bits. 3992 */ 3993 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3994 pmap_invalidate_page(pmap, pv->pv_va); 3995 } 3996 PMAP_UNLOCK(pmap); 3997 } 3998 sched_unpin(); 3999 rw_wunlock(&pvh_global_lock); 4000} 4001 4002/* 4003 * Miscellaneous support routines follow 4004 */ 4005 4006/* 4007 * Map a set of physical memory pages into the kernel virtual 4008 * address space. Return a pointer to where it is mapped. This 4009 * routine is intended to be used for mapping device memory, 4010 * NOT real memory. 4011 */ 4012void * 4013pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4014{ 4015 vm_offset_t va, offset; 4016 vm_size_t tmpsize; 4017 4018 offset = pa & PAGE_MASK; 4019 size = round_page(offset + size); 4020 pa = pa & PG_FRAME; 4021 4022 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4023 va = KERNBASE + pa; 4024 else 4025 va = kmem_alloc_nofault(kernel_map, size); 4026 if (!va) 4027 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4028 4029 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4030 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4031 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4032 pmap_invalidate_cache_range(va, va + size); 4033 return ((void *)(va + offset)); 4034} 4035 4036void * 4037pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4038{ 4039 4040 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4041} 4042 4043void * 4044pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4045{ 4046 4047 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4048} 4049 4050void 4051pmap_unmapdev(vm_offset_t va, vm_size_t size) 4052{ 4053 vm_offset_t base, offset; 4054 4055 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4056 return; 4057 base = trunc_page(va); 4058 offset = va & PAGE_MASK; 4059 size = round_page(offset + size); 4060 kmem_free(kernel_map, base, size); 4061} 4062 4063/* 4064 * Sets the memory attribute for the specified page. 4065 */ 4066void 4067pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4068{ 4069 4070 m->md.pat_mode = ma; 4071 if ((m->flags & PG_FICTITIOUS) != 0) 4072 return; 4073 4074 /* 4075 * If "m" is a normal page, flush it from the cache. 4076 * See pmap_invalidate_cache_range(). 4077 * 4078 * First, try to find an existing mapping of the page by sf 4079 * buffer. sf_buf_invalidate_cache() modifies mapping and 4080 * flushes the cache. 4081 */ 4082 if (sf_buf_invalidate_cache(m)) 4083 return; 4084 4085 /* 4086 * If page is not mapped by sf buffer, but CPU does not 4087 * support self snoop, map the page transient and do 4088 * invalidation. In the worst case, whole cache is flushed by 4089 * pmap_invalidate_cache_range(). 4090 */ 4091 if ((cpu_feature & CPUID_SS) == 0) 4092 pmap_flush_page(m); 4093} 4094 4095static void 4096pmap_flush_page(vm_page_t m) 4097{ 4098 struct sysmaps *sysmaps; 4099 vm_offset_t sva, eva; 4100 4101 if ((cpu_feature & CPUID_CLFSH) != 0) { 4102 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4103 mtx_lock(&sysmaps->lock); 4104 if (*sysmaps->CMAP2) 4105 panic("pmap_flush_page: CMAP2 busy"); 4106 sched_pin(); 4107 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4108 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4109 pmap_cache_bits(m->md.pat_mode, 0)); 4110 invlcaddr(sysmaps->CADDR2); 4111 sva = (vm_offset_t)sysmaps->CADDR2; 4112 eva = sva + PAGE_SIZE; 4113 4114 /* 4115 * Use mfence despite the ordering implied by 4116 * mtx_{un,}lock() because clflush is not guaranteed 4117 * to be ordered by any other instruction. 4118 */ 4119 mfence(); 4120 for (; sva < eva; sva += cpu_clflush_line_size) 4121 clflush(sva); 4122 mfence(); 4123 PT_SET_MA(sysmaps->CADDR2, 0); 4124 sched_unpin(); 4125 mtx_unlock(&sysmaps->lock); 4126 } else 4127 pmap_invalidate_cache(); 4128} 4129 4130/* 4131 * Changes the specified virtual address range's memory type to that given by 4132 * the parameter "mode". The specified virtual address range must be 4133 * completely contained within either the kernel map. 4134 * 4135 * Returns zero if the change completed successfully, and either EINVAL or 4136 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4137 * of the virtual address range was not mapped, and ENOMEM is returned if 4138 * there was insufficient memory available to complete the change. 4139 */ 4140int 4141pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4142{ 4143 vm_offset_t base, offset, tmpva; 4144 pt_entry_t *pte; 4145 u_int opte, npte; 4146 pd_entry_t *pde; 4147 boolean_t changed; 4148 4149 base = trunc_page(va); 4150 offset = va & PAGE_MASK; 4151 size = round_page(offset + size); 4152 4153 /* Only supported on kernel virtual addresses. */ 4154 if (base <= VM_MAXUSER_ADDRESS) 4155 return (EINVAL); 4156 4157 /* 4MB pages and pages that aren't mapped aren't supported. */ 4158 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4159 pde = pmap_pde(kernel_pmap, tmpva); 4160 if (*pde & PG_PS) 4161 return (EINVAL); 4162 if ((*pde & PG_V) == 0) 4163 return (EINVAL); 4164 pte = vtopte(va); 4165 if ((*pte & PG_V) == 0) 4166 return (EINVAL); 4167 } 4168 4169 changed = FALSE; 4170 4171 /* 4172 * Ok, all the pages exist and are 4k, so run through them updating 4173 * their cache mode. 4174 */ 4175 for (tmpva = base; size > 0; ) { 4176 pte = vtopte(tmpva); 4177 4178 /* 4179 * The cache mode bits are all in the low 32-bits of the 4180 * PTE, so we can just spin on updating the low 32-bits. 4181 */ 4182 do { 4183 opte = *(u_int *)pte; 4184 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4185 npte |= pmap_cache_bits(mode, 0); 4186 PT_SET_VA_MA(pte, npte, TRUE); 4187 } while (npte != opte && (*pte != npte)); 4188 if (npte != opte) 4189 changed = TRUE; 4190 tmpva += PAGE_SIZE; 4191 size -= PAGE_SIZE; 4192 } 4193 4194 /* 4195 * Flush CPU caches to make sure any data isn't cached that 4196 * shouldn't be, etc. 4197 */ 4198 if (changed) { 4199 pmap_invalidate_range(kernel_pmap, base, tmpva); 4200 pmap_invalidate_cache_range(base, tmpva); 4201 } 4202 return (0); 4203} 4204 4205/* 4206 * perform the pmap work for mincore 4207 */ 4208int 4209pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4210{ 4211 pt_entry_t *ptep, pte; 4212 vm_paddr_t pa; 4213 int val; 4214 4215 PMAP_LOCK(pmap); 4216retry: 4217 ptep = pmap_pte(pmap, addr); 4218 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4219 pmap_pte_release(ptep); 4220 val = 0; 4221 if ((pte & PG_V) != 0) { 4222 val |= MINCORE_INCORE; 4223 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4224 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4225 if ((pte & PG_A) != 0) 4226 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4227 } 4228 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4229 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4230 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4231 pa = pte & PG_FRAME; 4232 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4233 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4234 goto retry; 4235 } else 4236 PA_UNLOCK_COND(*locked_pa); 4237 PMAP_UNLOCK(pmap); 4238 return (val); 4239} 4240 4241void 4242pmap_activate(struct thread *td) 4243{ 4244 pmap_t pmap, oldpmap; 4245 u_int cpuid; 4246 u_int32_t cr3; 4247 4248 critical_enter(); 4249 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4250 oldpmap = PCPU_GET(curpmap); 4251 cpuid = PCPU_GET(cpuid); 4252#if defined(SMP) 4253 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4254 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4255#else 4256 CPU_CLR(cpuid, &oldpmap->pm_active); 4257 CPU_SET(cpuid, &pmap->pm_active); 4258#endif 4259#ifdef PAE 4260 cr3 = vtophys(pmap->pm_pdpt); 4261#else 4262 cr3 = vtophys(pmap->pm_pdir); 4263#endif 4264 /* 4265 * pmap_activate is for the current thread on the current cpu 4266 */ 4267 td->td_pcb->pcb_cr3 = cr3; 4268 PT_UPDATES_FLUSH(); 4269 load_cr3(cr3); 4270 PCPU_SET(curpmap, pmap); 4271 critical_exit(); 4272} 4273 4274void 4275pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4276{ 4277} 4278 4279/* 4280 * Increase the starting virtual address of the given mapping if a 4281 * different alignment might result in more superpage mappings. 4282 */ 4283void 4284pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4285 vm_offset_t *addr, vm_size_t size) 4286{ 4287 vm_offset_t superpage_offset; 4288 4289 if (size < NBPDR) 4290 return; 4291 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4292 offset += ptoa(object->pg_color); 4293 superpage_offset = offset & PDRMASK; 4294 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4295 (*addr & PDRMASK) == superpage_offset) 4296 return; 4297 if ((*addr & PDRMASK) < superpage_offset) 4298 *addr = (*addr & ~PDRMASK) + superpage_offset; 4299 else 4300 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4301} 4302 4303void 4304pmap_suspend() 4305{ 4306 pmap_t pmap; 4307 int i, pdir, offset; 4308 vm_paddr_t pdirma; 4309 mmu_update_t mu[4]; 4310 4311 /* 4312 * We need to remove the recursive mapping structure from all 4313 * our pmaps so that Xen doesn't get confused when it restores 4314 * the page tables. The recursive map lives at page directory 4315 * index PTDPTDI. We assume that the suspend code has stopped 4316 * the other vcpus (if any). 4317 */ 4318 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4319 for (i = 0; i < 4; i++) { 4320 /* 4321 * Figure out which page directory (L2) page 4322 * contains this bit of the recursive map and 4323 * the offset within that page of the map 4324 * entry 4325 */ 4326 pdir = (PTDPTDI + i) / NPDEPG; 4327 offset = (PTDPTDI + i) % NPDEPG; 4328 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4329 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4330 mu[i].val = 0; 4331 } 4332 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4333 } 4334} 4335 4336void 4337pmap_resume() 4338{ 4339 pmap_t pmap; 4340 int i, pdir, offset; 4341 vm_paddr_t pdirma; 4342 mmu_update_t mu[4]; 4343 4344 /* 4345 * Restore the recursive map that we removed on suspend. 4346 */ 4347 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4348 for (i = 0; i < 4; i++) { 4349 /* 4350 * Figure out which page directory (L2) page 4351 * contains this bit of the recursive map and 4352 * the offset within that page of the map 4353 * entry 4354 */ 4355 pdir = (PTDPTDI + i) / NPDEPG; 4356 offset = (PTDPTDI + i) % NPDEPG; 4357 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4358 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4359 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4360 } 4361 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4362 } 4363} 4364 4365#if defined(PMAP_DEBUG) 4366pmap_pid_dump(int pid) 4367{ 4368 pmap_t pmap; 4369 struct proc *p; 4370 int npte = 0; 4371 int index; 4372 4373 sx_slock(&allproc_lock); 4374 FOREACH_PROC_IN_SYSTEM(p) { 4375 if (p->p_pid != pid) 4376 continue; 4377 4378 if (p->p_vmspace) { 4379 int i,j; 4380 index = 0; 4381 pmap = vmspace_pmap(p->p_vmspace); 4382 for (i = 0; i < NPDEPTD; i++) { 4383 pd_entry_t *pde; 4384 pt_entry_t *pte; 4385 vm_offset_t base = i << PDRSHIFT; 4386 4387 pde = &pmap->pm_pdir[i]; 4388 if (pde && pmap_pde_v(pde)) { 4389 for (j = 0; j < NPTEPG; j++) { 4390 vm_offset_t va = base + (j << PAGE_SHIFT); 4391 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4392 if (index) { 4393 index = 0; 4394 printf("\n"); 4395 } 4396 sx_sunlock(&allproc_lock); 4397 return (npte); 4398 } 4399 pte = pmap_pte(pmap, va); 4400 if (pte && pmap_pte_v(pte)) { 4401 pt_entry_t pa; 4402 vm_page_t m; 4403 pa = PT_GET(pte); 4404 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4405 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4406 va, pa, m->hold_count, m->wire_count, m->flags); 4407 npte++; 4408 index++; 4409 if (index >= 2) { 4410 index = 0; 4411 printf("\n"); 4412 } else { 4413 printf(" "); 4414 } 4415 } 4416 } 4417 } 4418 } 4419 } 4420 } 4421 sx_sunlock(&allproc_lock); 4422 return (npte); 4423} 4424#endif 4425 4426#if defined(DEBUG) 4427 4428static void pads(pmap_t pm); 4429void pmap_pvdump(vm_paddr_t pa); 4430 4431/* print address space of pmap*/ 4432static void 4433pads(pmap_t pm) 4434{ 4435 int i, j; 4436 vm_paddr_t va; 4437 pt_entry_t *ptep; 4438 4439 if (pm == kernel_pmap) 4440 return; 4441 for (i = 0; i < NPDEPTD; i++) 4442 if (pm->pm_pdir[i]) 4443 for (j = 0; j < NPTEPG; j++) { 4444 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4445 if (pm == kernel_pmap && va < KERNBASE) 4446 continue; 4447 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4448 continue; 4449 ptep = pmap_pte(pm, va); 4450 if (pmap_pte_v(ptep)) 4451 printf("%x:%x ", va, *ptep); 4452 }; 4453 4454} 4455 4456void 4457pmap_pvdump(vm_paddr_t pa) 4458{ 4459 pv_entry_t pv; 4460 pmap_t pmap; 4461 vm_page_t m; 4462 4463 printf("pa %x", pa); 4464 m = PHYS_TO_VM_PAGE(pa); 4465 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4466 pmap = PV_PMAP(pv); 4467 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4468 pads(pmap); 4469 } 4470 printf(" "); 4471} 4472#endif 4473