pmap.c revision 215470
1/*-
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 * Copyright (c) 1994 John S. Dyson
5 * All rights reserved.
6 * Copyright (c) 1994 David Greenman
7 * All rights reserved.
8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu>
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 *    must display the following acknowledgement:
25 *	This product includes software developed by the University of
26 *	California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 *    may be used to endorse or promote products derived from this software
29 *    without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 *	from:	@(#)pmap.c	7.7 (Berkeley)	5/12/91
44 */
45/*-
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
48 *
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 *    notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 *    notice, this list of conditions and the following disclaimer in the
62 *    documentation and/or other materials provided with the distribution.
63 *
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 * SUCH DAMAGE.
75 */
76
77#include <sys/cdefs.h>
78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 215470 2010-11-18 21:02:40Z cperciva $");
79
80/*
81 *	Manages physical address maps.
82 *
83 *	In addition to hardware address maps, this
84 *	module is called upon to provide software-use-only
85 *	maps which may or may not be stored in the same
86 *	form as hardware maps.  These pseudo-maps are
87 *	used to store intermediate results from copy
88 *	operations to and from address spaces.
89 *
90 *	Since the information managed by this module is
91 *	also stored by the logical address mapping module,
92 *	this module may throw away valid virtual-to-physical
93 *	mappings at almost any time.  However, invalidations
94 *	of virtual-to-physical mappings must be done as
95 *	requested.
96 *
97 *	In order to cope with hardware architectures which
98 *	make virtual-to-physical map invalidates expensive,
99 *	this module may delay invalidate or reduced protection
100 *	operations until such time as they are actually
101 *	necessary.  This module is given full information as
102 *	to which processors are currently using which maps,
103 *	and to when physical maps must be made correct.
104 */
105
106#include "opt_cpu.h"
107#include "opt_pmap.h"
108#include "opt_msgbuf.h"
109#include "opt_smp.h"
110#include "opt_xbox.h"
111
112#include <sys/param.h>
113#include <sys/systm.h>
114#include <sys/kernel.h>
115#include <sys/ktr.h>
116#include <sys/lock.h>
117#include <sys/malloc.h>
118#include <sys/mman.h>
119#include <sys/msgbuf.h>
120#include <sys/mutex.h>
121#include <sys/proc.h>
122#include <sys/sf_buf.h>
123#include <sys/sx.h>
124#include <sys/vmmeter.h>
125#include <sys/sched.h>
126#include <sys/sysctl.h>
127#ifdef SMP
128#include <sys/smp.h>
129#endif
130
131#include <vm/vm.h>
132#include <vm/vm_param.h>
133#include <vm/vm_kern.h>
134#include <vm/vm_page.h>
135#include <vm/vm_map.h>
136#include <vm/vm_object.h>
137#include <vm/vm_extern.h>
138#include <vm/vm_pageout.h>
139#include <vm/vm_pager.h>
140#include <vm/uma.h>
141
142#include <machine/cpu.h>
143#include <machine/cputypes.h>
144#include <machine/md_var.h>
145#include <machine/pcb.h>
146#include <machine/specialreg.h>
147#ifdef SMP
148#include <machine/smp.h>
149#endif
150
151#ifdef XBOX
152#include <machine/xbox.h>
153#endif
154
155#include <xen/interface/xen.h>
156#include <xen/hypervisor.h>
157#include <machine/xen/hypercall.h>
158#include <machine/xen/xenvar.h>
159#include <machine/xen/xenfunc.h>
160
161#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
162#define CPU_ENABLE_SSE
163#endif
164
165#ifndef PMAP_SHPGPERPROC
166#define PMAP_SHPGPERPROC 200
167#endif
168
169#define DIAGNOSTIC
170
171#if !defined(DIAGNOSTIC)
172#ifdef __GNUC_GNU_INLINE__
173#define PMAP_INLINE	__attribute__((__gnu_inline__)) inline
174#else
175#define PMAP_INLINE	extern inline
176#endif
177#else
178#define PMAP_INLINE
179#endif
180
181#define PV_STATS
182#ifdef PV_STATS
183#define PV_STAT(x)	do { x ; } while (0)
184#else
185#define PV_STAT(x)	do { } while (0)
186#endif
187
188#define	pa_index(pa)	((pa) >> PDRSHIFT)
189#define	pa_to_pvh(pa)	(&pv_table[pa_index(pa)])
190
191/*
192 * Get PDEs and PTEs for user/kernel address space
193 */
194#define	pmap_pde(m, v)	(&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
195#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
196
197#define pmap_pde_v(pte)		((*(int *)pte & PG_V) != 0)
198#define pmap_pte_w(pte)		((*(int *)pte & PG_W) != 0)
199#define pmap_pte_m(pte)		((*(int *)pte & PG_M) != 0)
200#define pmap_pte_u(pte)		((*(int *)pte & PG_A) != 0)
201#define pmap_pte_v(pte)		((*(int *)pte & PG_V) != 0)
202
203#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
204
205struct pmap kernel_pmap_store;
206LIST_HEAD(pmaplist, pmap);
207static struct pmaplist allpmaps;
208static struct mtx allpmaps_lock;
209
210vm_offset_t virtual_avail;	/* VA of first avail page (after kernel bss) */
211vm_offset_t virtual_end;	/* VA of last avail page (end of kernel AS) */
212int pgeflag = 0;		/* PG_G or-in */
213int pseflag = 0;		/* PG_PS or-in */
214
215int nkpt;
216vm_offset_t kernel_vm_end;
217extern u_int32_t KERNend;
218
219#ifdef PAE
220pt_entry_t pg_nx;
221#if !defined(XEN)
222static uma_zone_t pdptzone;
223#endif
224#endif
225
226static int pat_works;			/* Is page attribute table sane? */
227
228/*
229 * Data for the pv entry allocation mechanism
230 */
231static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
232static struct md_page *pv_table;
233static int shpgperproc = PMAP_SHPGPERPROC;
234
235struct pv_chunk *pv_chunkbase;		/* KVA block for pv_chunks */
236int pv_maxchunks;			/* How many chunks we have KVA for */
237vm_offset_t pv_vafree;			/* freelist stored in the PTE */
238
239/*
240 * All those kernel PT submaps that BSD is so fond of
241 */
242struct sysmaps {
243	struct	mtx lock;
244	pt_entry_t *CMAP1;
245	pt_entry_t *CMAP2;
246	caddr_t	CADDR1;
247	caddr_t	CADDR2;
248};
249static struct sysmaps sysmaps_pcpu[MAXCPU];
250static pt_entry_t *CMAP3;
251caddr_t ptvmmap = 0;
252static caddr_t CADDR3;
253struct msgbuf *msgbufp = 0;
254
255/*
256 * Crashdump maps.
257 */
258static caddr_t crashdumpmap;
259
260static pt_entry_t *PMAP1 = 0, *PMAP2;
261static pt_entry_t *PADDR1 = 0, *PADDR2;
262#ifdef SMP
263static int PMAP1cpu;
264static int PMAP1changedcpu;
265SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
266	   &PMAP1changedcpu, 0,
267	   "Number of times pmap_pte_quick changed CPU with same PMAP1");
268#endif
269static int PMAP1changed;
270SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
271	   &PMAP1changed, 0,
272	   "Number of times pmap_pte_quick changed PMAP1");
273static int PMAP1unchanged;
274SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
275	   &PMAP1unchanged, 0,
276	   "Number of times pmap_pte_quick didn't change PMAP1");
277static struct mtx PMAP2mutex;
278
279SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
280static int pg_ps_enabled;
281SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
282    "Are large page mappings enabled?");
283
284SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
285	"Max number of PV entries");
286SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
287	"Page share factor per proc");
288SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
289    "2/4MB page mapping counters");
290
291static u_long pmap_pde_mappings;
292SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
293    &pmap_pde_mappings, 0, "2/4MB page mappings");
294
295static void	free_pv_entry(pmap_t pmap, pv_entry_t pv);
296static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try);
297static void	pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
298static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299		    vm_offset_t va);
300
301static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va,
302    vm_page_t m, vm_prot_t prot, vm_page_t mpte);
303static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
304    vm_page_t *free);
305static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
306    vm_page_t *free);
307static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
308					vm_offset_t va);
309static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
310    vm_page_t m);
311
312static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
313
314static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags);
315static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free);
316static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
317static void pmap_pte_release(pt_entry_t *pte);
318static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *);
319static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
320static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr);
321static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
322
323static __inline void pagezero(void *page);
324
325#if defined(PAE) && !defined(XEN)
326static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
327#endif
328#ifndef XEN
329static void pmap_set_pg(void);
330#endif
331
332CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
333CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
334
335/*
336 * If you get an error here, then you set KVA_PAGES wrong! See the
337 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
338 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
339 */
340CTASSERT(KERNBASE % (1 << 24) == 0);
341
342
343
344void
345pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type)
346{
347	vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]);
348
349	switch (type) {
350	case SH_PD_SET_VA:
351#if 0
352		xen_queue_pt_update(shadow_pdir_ma,
353				    xpmap_ptom(val & ~(PG_RW)));
354#endif
355		xen_queue_pt_update(pdir_ma,
356				    xpmap_ptom(val));
357		break;
358	case SH_PD_SET_VA_MA:
359#if 0
360		xen_queue_pt_update(shadow_pdir_ma,
361				    val & ~(PG_RW));
362#endif
363		xen_queue_pt_update(pdir_ma, val);
364		break;
365	case SH_PD_SET_VA_CLEAR:
366#if 0
367		xen_queue_pt_update(shadow_pdir_ma, 0);
368#endif
369		xen_queue_pt_update(pdir_ma, 0);
370		break;
371	}
372}
373
374/*
375 * Move the kernel virtual free pointer to the next
376 * 4MB.  This is used to help improve performance
377 * by using a large (4MB) page for much of the kernel
378 * (.text, .data, .bss)
379 */
380static vm_offset_t
381pmap_kmem_choose(vm_offset_t addr)
382{
383	vm_offset_t newaddr = addr;
384
385#ifndef DISABLE_PSE
386	if (cpu_feature & CPUID_PSE)
387		newaddr = (addr + PDRMASK) & ~PDRMASK;
388#endif
389	return newaddr;
390}
391
392/*
393 *	Bootstrap the system enough to run with virtual memory.
394 *
395 *	On the i386 this is called after mapping has already been enabled
396 *	and just syncs the pmap module with what has already been done.
397 *	[We can't call it easily with mapping off since the kernel is not
398 *	mapped with PA == VA, hence we would have to relocate every address
399 *	from the linked base (virtual) address "KERNBASE" to the actual
400 *	(physical) address starting relative to 0]
401 */
402void
403pmap_bootstrap(vm_paddr_t firstaddr)
404{
405	vm_offset_t va;
406	pt_entry_t *pte, *unused;
407	struct sysmaps *sysmaps;
408	int i;
409
410	/*
411	 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too
412	 * large. It should instead be correctly calculated in locore.s and
413	 * not based on 'first' (which is a physical address, not a virtual
414	 * address, for the start of unused physical memory). The kernel
415	 * page tables are NOT double mapped and thus should not be included
416	 * in this calculation.
417	 */
418	virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
419	virtual_avail = pmap_kmem_choose(virtual_avail);
420
421	virtual_end = VM_MAX_KERNEL_ADDRESS;
422
423	/*
424	 * Initialize the kernel pmap (which is statically allocated).
425	 */
426	PMAP_LOCK_INIT(kernel_pmap);
427	kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
428#ifdef PAE
429	kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
430#endif
431	kernel_pmap->pm_active = -1;	/* don't allow deactivation */
432	TAILQ_INIT(&kernel_pmap->pm_pvchunk);
433	LIST_INIT(&allpmaps);
434	mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
435	mtx_lock_spin(&allpmaps_lock);
436	LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
437	mtx_unlock_spin(&allpmaps_lock);
438	if (nkpt == 0)
439		nkpt = NKPT;
440
441	/*
442	 * Reserve some special page table entries/VA space for temporary
443	 * mapping of pages.
444	 */
445#define	SYSMAP(c, p, v, n)	\
446	v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
447
448	va = virtual_avail;
449	pte = vtopte(va);
450
451	/*
452	 * CMAP1/CMAP2 are used for zeroing and copying pages.
453	 * CMAP3 is used for the idle process page zeroing.
454	 */
455	for (i = 0; i < MAXCPU; i++) {
456		sysmaps = &sysmaps_pcpu[i];
457		mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
458		SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
459		SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
460		PT_SET_MA(sysmaps->CADDR1, 0);
461		PT_SET_MA(sysmaps->CADDR2, 0);
462	}
463	SYSMAP(caddr_t, CMAP3, CADDR3, 1)
464	PT_SET_MA(CADDR3, 0);
465
466	/*
467	 * Crashdump maps.
468	 */
469	SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
470
471	/*
472	 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
473	 */
474	SYSMAP(caddr_t, unused, ptvmmap, 1)
475
476	/*
477	 * msgbufp is used to map the system message buffer.
478	 */
479	SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE)))
480
481	/*
482	 * ptemap is used for pmap_pte_quick
483	 */
484	SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1);
485	SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1);
486
487	mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
488
489	virtual_avail = va;
490
491	/*
492	 * Leave in place an identity mapping (virt == phys) for the low 1 MB
493	 * physical memory region that is used by the ACPI wakeup code.  This
494	 * mapping must not have PG_G set.
495	 */
496#ifndef XEN
497	/*
498	 * leave here deliberately to show that this is not supported
499	 */
500#ifdef XBOX
501	/* FIXME: This is gross, but needed for the XBOX. Since we are in such
502	 * an early stadium, we cannot yet neatly map video memory ... :-(
503	 * Better fixes are very welcome! */
504	if (!arch_i386_is_xbox)
505#endif
506	for (i = 1; i < NKPT; i++)
507		PTD[i] = 0;
508
509	/* Initialize the PAT MSR if present. */
510	pmap_init_pat();
511
512	/* Turn on PG_G on kernel page(s) */
513	pmap_set_pg();
514#endif
515}
516
517/*
518 * Setup the PAT MSR.
519 */
520void
521pmap_init_pat(void)
522{
523	uint64_t pat_msr;
524
525	/* Bail if this CPU doesn't implement PAT. */
526	if (!(cpu_feature & CPUID_PAT))
527		return;
528
529	if (cpu_vendor_id != CPU_VENDOR_INTEL ||
530	    (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) {
531		/*
532		 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-.
533		 * Program 4 and 5 as WP and WC.
534		 * Leave 6 and 7 as UC and UC-.
535		 */
536		pat_msr = rdmsr(MSR_PAT);
537		pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5));
538		pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) |
539		    PAT_VALUE(5, PAT_WRITE_COMBINING);
540		pat_works = 1;
541	} else {
542		/*
543		 * Due to some Intel errata, we can only safely use the lower 4
544		 * PAT entries.  Thus, just replace PAT Index 2 with WC instead
545		 * of UC-.
546		 *
547		 *   Intel Pentium III Processor Specification Update
548		 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
549		 * or Mode C Paging)
550		 *
551		 *   Intel Pentium IV  Processor Specification Update
552		 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
553		 */
554		pat_msr = rdmsr(MSR_PAT);
555		pat_msr &= ~PAT_MASK(2);
556		pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
557		pat_works = 0;
558	}
559	wrmsr(MSR_PAT, pat_msr);
560}
561
562#ifndef XEN
563/*
564 * Set PG_G on kernel pages.  Only the BSP calls this when SMP is turned on.
565 */
566static void
567pmap_set_pg(void)
568{
569	pd_entry_t pdir;
570	pt_entry_t *pte;
571	vm_offset_t va, endva;
572	int i;
573
574	if (pgeflag == 0)
575		return;
576
577	i = KERNLOAD/NBPDR;
578	endva = KERNBASE + KERNend;
579
580	if (pseflag) {
581		va = KERNBASE + KERNLOAD;
582		while (va  < endva) {
583			pdir = kernel_pmap->pm_pdir[KPTDI+i];
584			pdir |= pgeflag;
585			kernel_pmap->pm_pdir[KPTDI+i] = PTD[KPTDI+i] = pdir;
586			invltlb();	/* Play it safe, invltlb() every time */
587			i++;
588			va += NBPDR;
589		}
590	} else {
591		va = (vm_offset_t)btext;
592		while (va < endva) {
593			pte = vtopte(va);
594			if (*pte & PG_V)
595				*pte |= pgeflag;
596			invltlb();	/* Play it safe, invltlb() every time */
597			va += PAGE_SIZE;
598		}
599	}
600}
601#endif
602
603/*
604 * Initialize a vm_page's machine-dependent fields.
605 */
606void
607pmap_page_init(vm_page_t m)
608{
609
610	TAILQ_INIT(&m->md.pv_list);
611	m->md.pat_mode = PAT_WRITE_BACK;
612}
613
614#if defined(PAE) && !defined(XEN)
615static void *
616pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
617{
618
619	/* Inform UMA that this allocator uses kernel_map/object. */
620	*flags = UMA_SLAB_KERNEL;
621	return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL,
622	    0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
623}
624#endif
625
626/*
627 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
628 * Requirements:
629 *  - Must deal with pages in order to ensure that none of the PG_* bits
630 *    are ever set, PG_V in particular.
631 *  - Assumes we can write to ptes without pte_store() atomic ops, even
632 *    on PAE systems.  This should be ok.
633 *  - Assumes nothing will ever test these addresses for 0 to indicate
634 *    no mapping instead of correctly checking PG_V.
635 *  - Assumes a vm_offset_t will fit in a pte (true for i386).
636 * Because PG_V is never set, there can be no mappings to invalidate.
637 */
638static int ptelist_count = 0;
639static vm_offset_t
640pmap_ptelist_alloc(vm_offset_t *head)
641{
642	vm_offset_t va;
643	vm_offset_t *phead = (vm_offset_t *)*head;
644
645	if (ptelist_count == 0) {
646		printf("out of memory!!!!!!\n");
647		return (0);	/* Out of memory */
648	}
649	ptelist_count--;
650	va = phead[ptelist_count];
651	return (va);
652}
653
654static void
655pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
656{
657	vm_offset_t *phead = (vm_offset_t *)*head;
658
659	phead[ptelist_count++] = va;
660}
661
662static void
663pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
664{
665	int i, nstackpages;
666	vm_offset_t va;
667	vm_page_t m;
668
669	nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t));
670	for (i = 0; i < nstackpages; i++) {
671		va = (vm_offset_t)base + i * PAGE_SIZE;
672		m = vm_page_alloc(NULL, i,
673		    VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
674		    VM_ALLOC_ZERO);
675		pmap_qenter(va, &m, 1);
676	}
677
678	*head = (vm_offset_t)base;
679	for (i = npages - 1; i >= nstackpages; i--) {
680		va = (vm_offset_t)base + i * PAGE_SIZE;
681		pmap_ptelist_free(head, va);
682	}
683}
684
685
686/*
687 *	Initialize the pmap module.
688 *	Called by vm_init, to initialize any structures that the pmap
689 *	system needs to map virtual memory.
690 */
691void
692pmap_init(void)
693{
694	vm_page_t mpte;
695	vm_size_t s;
696	int i, pv_npg;
697
698	/*
699	 * Initialize the vm page array entries for the kernel pmap's
700	 * page table pages.
701	 */
702	for (i = 0; i < nkpt; i++) {
703		mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME));
704		KASSERT(mpte >= vm_page_array &&
705		    mpte < &vm_page_array[vm_page_array_size],
706		    ("pmap_init: page table page is out of range"));
707		mpte->pindex = i + KPTDI;
708		mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME);
709	}
710
711        /*
712	 * Initialize the address space (zone) for the pv entries.  Set a
713	 * high water mark so that the system can recover from excessive
714	 * numbers of pv entries.
715	 */
716	TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
717	pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
718	TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
719	pv_entry_max = roundup(pv_entry_max, _NPCPV);
720	pv_entry_high_water = 9 * (pv_entry_max / 10);
721
722	/*
723	 * Are large page mappings enabled?
724	 */
725	TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
726
727	/*
728	 * Calculate the size of the pv head table for superpages.
729	 */
730	for (i = 0; phys_avail[i + 1]; i += 2);
731	pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
732
733	/*
734	 * Allocate memory for the pv head table for superpages.
735	 */
736	s = (vm_size_t)(pv_npg * sizeof(struct md_page));
737	s = round_page(s);
738	pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
739	for (i = 0; i < pv_npg; i++)
740		TAILQ_INIT(&pv_table[i].pv_list);
741
742	pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
743	pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map,
744	    PAGE_SIZE * pv_maxchunks);
745	if (pv_chunkbase == NULL)
746		panic("pmap_init: not enough kvm for pv chunks");
747	pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
748#if defined(PAE) && !defined(XEN)
749	pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
750	    NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
751	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
752	uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
753#endif
754}
755
756
757/***************************************************
758 * Low level helper routines.....
759 ***************************************************/
760
761/*
762 * Determine the appropriate bits to set in a PTE or PDE for a specified
763 * caching mode.
764 */
765int
766pmap_cache_bits(int mode, boolean_t is_pde)
767{
768	int pat_flag, pat_index, cache_bits;
769
770	/* The PAT bit is different for PTE's and PDE's. */
771	pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
772
773	/* If we don't support PAT, map extended modes to older ones. */
774	if (!(cpu_feature & CPUID_PAT)) {
775		switch (mode) {
776		case PAT_UNCACHEABLE:
777		case PAT_WRITE_THROUGH:
778		case PAT_WRITE_BACK:
779			break;
780		case PAT_UNCACHED:
781		case PAT_WRITE_COMBINING:
782		case PAT_WRITE_PROTECTED:
783			mode = PAT_UNCACHEABLE;
784			break;
785		}
786	}
787
788	/* Map the caching mode to a PAT index. */
789	if (pat_works) {
790		switch (mode) {
791			case PAT_UNCACHEABLE:
792				pat_index = 3;
793				break;
794			case PAT_WRITE_THROUGH:
795				pat_index = 1;
796				break;
797			case PAT_WRITE_BACK:
798				pat_index = 0;
799				break;
800			case PAT_UNCACHED:
801				pat_index = 2;
802				break;
803			case PAT_WRITE_COMBINING:
804				pat_index = 5;
805				break;
806			case PAT_WRITE_PROTECTED:
807				pat_index = 4;
808				break;
809			default:
810				panic("Unknown caching mode %d\n", mode);
811		}
812	} else {
813		switch (mode) {
814			case PAT_UNCACHED:
815			case PAT_UNCACHEABLE:
816			case PAT_WRITE_PROTECTED:
817				pat_index = 3;
818				break;
819			case PAT_WRITE_THROUGH:
820				pat_index = 1;
821				break;
822			case PAT_WRITE_BACK:
823				pat_index = 0;
824				break;
825			case PAT_WRITE_COMBINING:
826				pat_index = 2;
827				break;
828			default:
829				panic("Unknown caching mode %d\n", mode);
830		}
831	}
832
833	/* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
834	cache_bits = 0;
835	if (pat_index & 0x4)
836		cache_bits |= pat_flag;
837	if (pat_index & 0x2)
838		cache_bits |= PG_NC_PCD;
839	if (pat_index & 0x1)
840		cache_bits |= PG_NC_PWT;
841	return (cache_bits);
842}
843#ifdef SMP
844/*
845 * For SMP, these functions have to use the IPI mechanism for coherence.
846 *
847 * N.B.: Before calling any of the following TLB invalidation functions,
848 * the calling processor must ensure that all stores updating a non-
849 * kernel page table are globally performed.  Otherwise, another
850 * processor could cache an old, pre-update entry without being
851 * invalidated.  This can happen one of two ways: (1) The pmap becomes
852 * active on another processor after its pm_active field is checked by
853 * one of the following functions but before a store updating the page
854 * table is globally performed. (2) The pmap becomes active on another
855 * processor before its pm_active field is checked but due to
856 * speculative loads one of the following functions stills reads the
857 * pmap as inactive on the other processor.
858 *
859 * The kernel page table is exempt because its pm_active field is
860 * immutable.  The kernel page table is always active on every
861 * processor.
862 */
863void
864pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
865{
866	cpumask_t cpumask, other_cpus;
867
868	CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x",
869	    pmap, va);
870
871	sched_pin();
872	if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
873		invlpg(va);
874		smp_invlpg(va);
875	} else {
876		cpumask = PCPU_GET(cpumask);
877		other_cpus = PCPU_GET(other_cpus);
878		if (pmap->pm_active & cpumask)
879			invlpg(va);
880		if (pmap->pm_active & other_cpus)
881			smp_masked_invlpg(pmap->pm_active & other_cpus, va);
882	}
883	sched_unpin();
884	PT_UPDATES_FLUSH();
885}
886
887void
888pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
889{
890	cpumask_t cpumask, other_cpus;
891	vm_offset_t addr;
892
893	CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x",
894	    pmap, sva, eva);
895
896	sched_pin();
897	if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
898		for (addr = sva; addr < eva; addr += PAGE_SIZE)
899			invlpg(addr);
900		smp_invlpg_range(sva, eva);
901	} else {
902		cpumask = PCPU_GET(cpumask);
903		other_cpus = PCPU_GET(other_cpus);
904		if (pmap->pm_active & cpumask)
905			for (addr = sva; addr < eva; addr += PAGE_SIZE)
906				invlpg(addr);
907		if (pmap->pm_active & other_cpus)
908			smp_masked_invlpg_range(pmap->pm_active & other_cpus,
909			    sva, eva);
910	}
911	sched_unpin();
912	PT_UPDATES_FLUSH();
913}
914
915void
916pmap_invalidate_all(pmap_t pmap)
917{
918	cpumask_t cpumask, other_cpus;
919
920	CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap);
921
922	sched_pin();
923	if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
924		invltlb();
925		smp_invltlb();
926	} else {
927		cpumask = PCPU_GET(cpumask);
928		other_cpus = PCPU_GET(other_cpus);
929		if (pmap->pm_active & cpumask)
930			invltlb();
931		if (pmap->pm_active & other_cpus)
932			smp_masked_invltlb(pmap->pm_active & other_cpus);
933	}
934	sched_unpin();
935}
936
937void
938pmap_invalidate_cache(void)
939{
940
941	sched_pin();
942	wbinvd();
943	smp_cache_flush();
944	sched_unpin();
945}
946#else /* !SMP */
947/*
948 * Normal, non-SMP, 486+ invalidation functions.
949 * We inline these within pmap.c for speed.
950 */
951PMAP_INLINE void
952pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
953{
954	CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x",
955	    pmap, va);
956
957	if (pmap == kernel_pmap || pmap->pm_active)
958		invlpg(va);
959	PT_UPDATES_FLUSH();
960}
961
962PMAP_INLINE void
963pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
964{
965	vm_offset_t addr;
966
967	if (eva - sva > PAGE_SIZE)
968		CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x",
969		    pmap, sva, eva);
970
971	if (pmap == kernel_pmap || pmap->pm_active)
972		for (addr = sva; addr < eva; addr += PAGE_SIZE)
973			invlpg(addr);
974	PT_UPDATES_FLUSH();
975}
976
977PMAP_INLINE void
978pmap_invalidate_all(pmap_t pmap)
979{
980
981	CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap);
982
983	if (pmap == kernel_pmap || pmap->pm_active)
984		invltlb();
985}
986
987PMAP_INLINE void
988pmap_invalidate_cache(void)
989{
990
991	wbinvd();
992}
993#endif /* !SMP */
994
995void
996pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
997{
998
999	KASSERT((sva & PAGE_MASK) == 0,
1000	    ("pmap_invalidate_cache_range: sva not page-aligned"));
1001	KASSERT((eva & PAGE_MASK) == 0,
1002	    ("pmap_invalidate_cache_range: eva not page-aligned"));
1003
1004	if (cpu_feature & CPUID_SS)
1005		; /* If "Self Snoop" is supported, do nothing. */
1006	else if (cpu_feature & CPUID_CLFSH) {
1007
1008		/*
1009		 * Otherwise, do per-cache line flush.  Use the mfence
1010		 * instruction to insure that previous stores are
1011		 * included in the write-back.  The processor
1012		 * propagates flush to other processors in the cache
1013		 * coherence domain.
1014		 */
1015		mfence();
1016		for (; sva < eva; sva += cpu_clflush_line_size)
1017			clflush(sva);
1018		mfence();
1019	} else {
1020
1021		/*
1022		 * No targeted cache flush methods are supported by CPU,
1023		 * globally invalidate cache as a last resort.
1024		 */
1025		pmap_invalidate_cache();
1026	}
1027}
1028
1029/*
1030 * Are we current address space or kernel?  N.B. We return FALSE when
1031 * a pmap's page table is in use because a kernel thread is borrowing
1032 * it.  The borrowed page table can change spontaneously, making any
1033 * dependence on its continued use subject to a race condition.
1034 */
1035static __inline int
1036pmap_is_current(pmap_t pmap)
1037{
1038
1039	return (pmap == kernel_pmap ||
1040	    (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1041		(pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1042}
1043
1044/*
1045 * If the given pmap is not the current or kernel pmap, the returned pte must
1046 * be released by passing it to pmap_pte_release().
1047 */
1048pt_entry_t *
1049pmap_pte(pmap_t pmap, vm_offset_t va)
1050{
1051	pd_entry_t newpf;
1052	pd_entry_t *pde;
1053
1054	pde = pmap_pde(pmap, va);
1055	if (*pde & PG_PS)
1056		return (pde);
1057	if (*pde != 0) {
1058		/* are we current address space or kernel? */
1059		if (pmap_is_current(pmap))
1060			return (vtopte(va));
1061		mtx_lock(&PMAP2mutex);
1062		newpf = *pde & PG_FRAME;
1063		if ((*PMAP2 & PG_FRAME) != newpf) {
1064			vm_page_lock_queues();
1065			PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M);
1066			vm_page_unlock_queues();
1067			CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x",
1068			    pmap, va, (*PMAP2 & 0xffffffff));
1069		}
1070
1071		return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1072	}
1073	return (0);
1074}
1075
1076/*
1077 * Releases a pte that was obtained from pmap_pte().  Be prepared for the pte
1078 * being NULL.
1079 */
1080static __inline void
1081pmap_pte_release(pt_entry_t *pte)
1082{
1083
1084	if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) {
1085		CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx",
1086		    *PMAP2);
1087		PT_SET_VA(PMAP2, 0, TRUE);
1088		mtx_unlock(&PMAP2mutex);
1089	}
1090}
1091
1092static __inline void
1093invlcaddr(void *caddr)
1094{
1095
1096	invlpg((u_int)caddr);
1097	PT_UPDATES_FLUSH();
1098}
1099
1100/*
1101 * Super fast pmap_pte routine best used when scanning
1102 * the pv lists.  This eliminates many coarse-grained
1103 * invltlb calls.  Note that many of the pv list
1104 * scans are across different pmaps.  It is very wasteful
1105 * to do an entire invltlb for checking a single mapping.
1106 *
1107 * If the given pmap is not the current pmap, vm_page_queue_mtx
1108 * must be held and curthread pinned to a CPU.
1109 */
1110static pt_entry_t *
1111pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1112{
1113	pd_entry_t newpf;
1114	pd_entry_t *pde;
1115
1116	pde = pmap_pde(pmap, va);
1117	if (*pde & PG_PS)
1118		return (pde);
1119	if (*pde != 0) {
1120		/* are we current address space or kernel? */
1121		if (pmap_is_current(pmap))
1122			return (vtopte(va));
1123		mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1124		KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1125		newpf = *pde & PG_FRAME;
1126		if ((*PMAP1 & PG_FRAME) != newpf) {
1127			PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M);
1128			CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x",
1129			    pmap, va, (u_long)*PMAP1);
1130
1131#ifdef SMP
1132			PMAP1cpu = PCPU_GET(cpuid);
1133#endif
1134			PMAP1changed++;
1135		} else
1136#ifdef SMP
1137		if (PMAP1cpu != PCPU_GET(cpuid)) {
1138			PMAP1cpu = PCPU_GET(cpuid);
1139			invlcaddr(PADDR1);
1140			PMAP1changedcpu++;
1141		} else
1142#endif
1143			PMAP1unchanged++;
1144		return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1145	}
1146	return (0);
1147}
1148
1149/*
1150 *	Routine:	pmap_extract
1151 *	Function:
1152 *		Extract the physical page address associated
1153 *		with the given map/virtual_address pair.
1154 */
1155vm_paddr_t
1156pmap_extract(pmap_t pmap, vm_offset_t va)
1157{
1158	vm_paddr_t rtval;
1159	pt_entry_t *pte;
1160	pd_entry_t pde;
1161	pt_entry_t pteval;
1162
1163	rtval = 0;
1164	PMAP_LOCK(pmap);
1165	pde = pmap->pm_pdir[va >> PDRSHIFT];
1166	if (pde != 0) {
1167		if ((pde & PG_PS) != 0) {
1168			rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK);
1169			PMAP_UNLOCK(pmap);
1170			return rtval;
1171		}
1172		pte = pmap_pte(pmap, va);
1173		pteval = *pte ? xpmap_mtop(*pte) : 0;
1174		rtval = (pteval & PG_FRAME) | (va & PAGE_MASK);
1175		pmap_pte_release(pte);
1176	}
1177	PMAP_UNLOCK(pmap);
1178	return (rtval);
1179}
1180
1181/*
1182 *	Routine:	pmap_extract_ma
1183 *	Function:
1184 *		Like pmap_extract, but returns machine address
1185 */
1186vm_paddr_t
1187pmap_extract_ma(pmap_t pmap, vm_offset_t va)
1188{
1189	vm_paddr_t rtval;
1190	pt_entry_t *pte;
1191	pd_entry_t pde;
1192
1193	rtval = 0;
1194	PMAP_LOCK(pmap);
1195	pde = pmap->pm_pdir[va >> PDRSHIFT];
1196	if (pde != 0) {
1197		if ((pde & PG_PS) != 0) {
1198			rtval = (pde & ~PDRMASK) | (va & PDRMASK);
1199			PMAP_UNLOCK(pmap);
1200			return rtval;
1201		}
1202		pte = pmap_pte(pmap, va);
1203		rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1204		pmap_pte_release(pte);
1205	}
1206	PMAP_UNLOCK(pmap);
1207	return (rtval);
1208}
1209
1210/*
1211 *	Routine:	pmap_extract_and_hold
1212 *	Function:
1213 *		Atomically extract and hold the physical page
1214 *		with the given pmap and virtual address pair
1215 *		if that mapping permits the given protection.
1216 */
1217vm_page_t
1218pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1219{
1220	pd_entry_t pde;
1221	pt_entry_t pte;
1222	vm_page_t m;
1223	vm_paddr_t pa;
1224
1225	pa = 0;
1226	m = NULL;
1227	PMAP_LOCK(pmap);
1228retry:
1229	pde = PT_GET(pmap_pde(pmap, va));
1230	if (pde != 0) {
1231		if (pde & PG_PS) {
1232			if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1233				if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) |
1234				       (va & PDRMASK), &pa))
1235					goto retry;
1236				m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1237				    (va & PDRMASK));
1238				vm_page_hold(m);
1239			}
1240		} else {
1241			sched_pin();
1242			pte = PT_GET(pmap_pte_quick(pmap, va));
1243			if (*PMAP1)
1244				PT_SET_MA(PADDR1, 0);
1245			if ((pte & PG_V) &&
1246			    ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1247				if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa))
1248					goto retry;
1249				m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1250				vm_page_hold(m);
1251			}
1252			sched_unpin();
1253		}
1254	}
1255	PA_UNLOCK_COND(pa);
1256	PMAP_UNLOCK(pmap);
1257	return (m);
1258}
1259
1260/***************************************************
1261 * Low level mapping routines.....
1262 ***************************************************/
1263
1264/*
1265 * Add a wired page to the kva.
1266 * Note: not SMP coherent.
1267 */
1268void
1269pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1270{
1271	PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag);
1272}
1273
1274void
1275pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma)
1276{
1277	pt_entry_t *pte;
1278
1279	pte = vtopte(va);
1280	pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag);
1281}
1282
1283
1284static __inline void
1285pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1286{
1287	PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1288}
1289
1290/*
1291 * Remove a page from the kernel pagetables.
1292 * Note: not SMP coherent.
1293 */
1294PMAP_INLINE void
1295pmap_kremove(vm_offset_t va)
1296{
1297	pt_entry_t *pte;
1298
1299	pte = vtopte(va);
1300	PT_CLEAR_VA(pte, FALSE);
1301}
1302
1303/*
1304 *	Used to map a range of physical addresses into kernel
1305 *	virtual address space.
1306 *
1307 *	The value passed in '*virt' is a suggested virtual address for
1308 *	the mapping. Architectures which can support a direct-mapped
1309 *	physical to virtual region can return the appropriate address
1310 *	within that region, leaving '*virt' unchanged. Other
1311 *	architectures should map the pages starting at '*virt' and
1312 *	update '*virt' with the first usable address after the mapped
1313 *	region.
1314 */
1315vm_offset_t
1316pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1317{
1318	vm_offset_t va, sva;
1319
1320	va = sva = *virt;
1321	CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x",
1322	    va, start, end, prot);
1323	while (start < end) {
1324		pmap_kenter(va, start);
1325		va += PAGE_SIZE;
1326		start += PAGE_SIZE;
1327	}
1328	pmap_invalidate_range(kernel_pmap, sva, va);
1329	*virt = va;
1330	return (sva);
1331}
1332
1333
1334/*
1335 * Add a list of wired pages to the kva
1336 * this routine is only used for temporary
1337 * kernel mappings that do not need to have
1338 * page modification or references recorded.
1339 * Note that old mappings are simply written
1340 * over.  The page *must* be wired.
1341 * Note: SMP coherent.  Uses a ranged shootdown IPI.
1342 */
1343void
1344pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1345{
1346	pt_entry_t *endpte, *pte;
1347	vm_paddr_t pa;
1348	vm_offset_t va = sva;
1349	int mclcount = 0;
1350	multicall_entry_t mcl[16];
1351	multicall_entry_t *mclp = mcl;
1352	int error;
1353
1354	CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count);
1355	pte = vtopte(sva);
1356	endpte = pte + count;
1357	while (pte < endpte) {
1358		pa = xpmap_ptom(VM_PAGE_TO_PHYS(*ma)) | pgeflag | PG_RW | PG_V | PG_M | PG_A;
1359
1360		mclp->op = __HYPERVISOR_update_va_mapping;
1361		mclp->args[0] = va;
1362		mclp->args[1] = (uint32_t)(pa & 0xffffffff);
1363		mclp->args[2] = (uint32_t)(pa >> 32);
1364		mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0;
1365
1366		va += PAGE_SIZE;
1367		pte++;
1368		ma++;
1369		mclp++;
1370		mclcount++;
1371		if (mclcount == 16) {
1372			error = HYPERVISOR_multicall(mcl, mclcount);
1373			mclp = mcl;
1374			mclcount = 0;
1375			KASSERT(error == 0, ("bad multicall %d", error));
1376		}
1377	}
1378	if (mclcount) {
1379		error = HYPERVISOR_multicall(mcl, mclcount);
1380		KASSERT(error == 0, ("bad multicall %d", error));
1381	}
1382
1383#ifdef INVARIANTS
1384	for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++)
1385		KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE));
1386#endif
1387}
1388
1389
1390/*
1391 * This routine tears out page mappings from the
1392 * kernel -- it is meant only for temporary mappings.
1393 * Note: SMP coherent.  Uses a ranged shootdown IPI.
1394 */
1395void
1396pmap_qremove(vm_offset_t sva, int count)
1397{
1398	vm_offset_t va;
1399
1400	CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count);
1401	va = sva;
1402	vm_page_lock_queues();
1403	critical_enter();
1404	while (count-- > 0) {
1405		pmap_kremove(va);
1406		va += PAGE_SIZE;
1407	}
1408	pmap_invalidate_range(kernel_pmap, sva, va);
1409	critical_exit();
1410	vm_page_unlock_queues();
1411}
1412
1413/***************************************************
1414 * Page table page management routines.....
1415 ***************************************************/
1416static __inline void
1417pmap_free_zero_pages(vm_page_t free)
1418{
1419	vm_page_t m;
1420
1421	while (free != NULL) {
1422		m = free;
1423		free = m->right;
1424		vm_page_free_zero(m);
1425	}
1426}
1427
1428/*
1429 * This routine unholds page table pages, and if the hold count
1430 * drops to zero, then it decrements the wire count.
1431 */
1432static __inline int
1433pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1434{
1435
1436	--m->wire_count;
1437	if (m->wire_count == 0)
1438		return _pmap_unwire_pte_hold(pmap, m, free);
1439	else
1440		return 0;
1441}
1442
1443static int
1444_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1445{
1446	vm_offset_t pteva;
1447
1448	PT_UPDATES_FLUSH();
1449	/*
1450	 * unmap the page table page
1451	 */
1452	xen_pt_unpin(pmap->pm_pdir[m->pindex]);
1453	/*
1454	 * page *might* contain residual mapping :-/
1455	 */
1456	PD_CLEAR_VA(pmap, m->pindex, TRUE);
1457	pmap_zero_page(m);
1458	--pmap->pm_stats.resident_count;
1459
1460	/*
1461	 * This is a release store so that the ordinary store unmapping
1462	 * the page table page is globally performed before TLB shoot-
1463	 * down is begun.
1464	 */
1465	atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1466
1467	/*
1468	 * Do an invltlb to make the invalidated mapping
1469	 * take effect immediately.
1470	 */
1471	pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1472	pmap_invalidate_page(pmap, pteva);
1473
1474	/*
1475	 * Put page on a list so that it is released after
1476	 * *ALL* TLB shootdown is done
1477	 */
1478	m->right = *free;
1479	*free = m;
1480
1481	return 1;
1482}
1483
1484/*
1485 * After removing a page table entry, this routine is used to
1486 * conditionally free the page, and manage the hold/wire counts.
1487 */
1488static int
1489pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free)
1490{
1491	pd_entry_t ptepde;
1492	vm_page_t mpte;
1493
1494	if (va >= VM_MAXUSER_ADDRESS)
1495		return 0;
1496	ptepde = PT_GET(pmap_pde(pmap, va));
1497	mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1498	return pmap_unwire_pte_hold(pmap, mpte, free);
1499}
1500
1501void
1502pmap_pinit0(pmap_t pmap)
1503{
1504
1505	PMAP_LOCK_INIT(pmap);
1506	pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1507#ifdef PAE
1508	pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1509#endif
1510	pmap->pm_active = 0;
1511	PCPU_SET(curpmap, pmap);
1512	TAILQ_INIT(&pmap->pm_pvchunk);
1513	bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1514	mtx_lock_spin(&allpmaps_lock);
1515	LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1516	mtx_unlock_spin(&allpmaps_lock);
1517}
1518
1519/*
1520 * Initialize a preallocated and zeroed pmap structure,
1521 * such as one in a vmspace structure.
1522 */
1523int
1524pmap_pinit(pmap_t pmap)
1525{
1526	vm_page_t m, ptdpg[NPGPTD + 1];
1527	int npgptd = NPGPTD + 1;
1528	static int color;
1529	int i;
1530
1531	PMAP_LOCK_INIT(pmap);
1532
1533	/*
1534	 * No need to allocate page table space yet but we do need a valid
1535	 * page directory table.
1536	 */
1537	if (pmap->pm_pdir == NULL) {
1538		pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map,
1539		    NBPTD);
1540		if (pmap->pm_pdir == NULL) {
1541			PMAP_LOCK_DESTROY(pmap);
1542			return (0);
1543		}
1544#if defined(XEN) && defined(PAE)
1545		pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1);
1546#endif
1547
1548#if defined(PAE) && !defined(XEN)
1549		pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1550		KASSERT(((vm_offset_t)pmap->pm_pdpt &
1551		    ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1552		    ("pmap_pinit: pdpt misaligned"));
1553		KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1554		    ("pmap_pinit: pdpt above 4g"));
1555#endif
1556	}
1557
1558	/*
1559	 * allocate the page directory page(s)
1560	 */
1561	for (i = 0; i < npgptd;) {
1562		m = vm_page_alloc(NULL, color++,
1563		    VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1564		    VM_ALLOC_ZERO);
1565		if (m == NULL)
1566			VM_WAIT;
1567		else {
1568			ptdpg[i++] = m;
1569		}
1570	}
1571	pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1572	for (i = 0; i < NPGPTD; i++) {
1573		if ((ptdpg[i]->flags & PG_ZERO) == 0)
1574			pagezero(&pmap->pm_pdir[i*NPTEPG]);
1575	}
1576
1577	mtx_lock_spin(&allpmaps_lock);
1578	LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1579	mtx_unlock_spin(&allpmaps_lock);
1580	/* Wire in kernel global address entries. */
1581
1582	bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1583#ifdef PAE
1584#ifdef XEN
1585	pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1);
1586	if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0)
1587		bzero(pmap->pm_pdpt, PAGE_SIZE);
1588#endif
1589	for (i = 0; i < NPGPTD; i++) {
1590		vm_paddr_t ma;
1591
1592		ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i]));
1593		pmap->pm_pdpt[i] = ma | PG_V;
1594
1595	}
1596#endif
1597#ifdef XEN
1598	for (i = 0; i < NPGPTD; i++) {
1599		pt_entry_t *pd;
1600		vm_paddr_t ma;
1601
1602		ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i]));
1603		pd = pmap->pm_pdir + (i * NPDEPG);
1604		PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW));
1605#if 0
1606		xen_pgd_pin(ma);
1607#endif
1608	}
1609
1610#ifdef PAE
1611	PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW);
1612#endif
1613	vm_page_lock_queues();
1614	xen_flush_queue();
1615	xen_pgdpt_pin(xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[NPGPTD])));
1616	for (i = 0; i < NPGPTD; i++) {
1617		vm_paddr_t ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i]));
1618		PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE);
1619	}
1620	xen_flush_queue();
1621	vm_page_unlock_queues();
1622#endif
1623	pmap->pm_active = 0;
1624	TAILQ_INIT(&pmap->pm_pvchunk);
1625	bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1626
1627	return (1);
1628}
1629
1630/*
1631 * this routine is called if the page table page is not
1632 * mapped correctly.
1633 */
1634static vm_page_t
1635_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags)
1636{
1637	vm_paddr_t ptema;
1638	vm_page_t m;
1639
1640	KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1641	    (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1642	    ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1643
1644	/*
1645	 * Allocate a page table page.
1646	 */
1647	if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1648	    VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1649		if (flags & M_WAITOK) {
1650			PMAP_UNLOCK(pmap);
1651			vm_page_unlock_queues();
1652			VM_WAIT;
1653			vm_page_lock_queues();
1654			PMAP_LOCK(pmap);
1655		}
1656
1657		/*
1658		 * Indicate the need to retry.  While waiting, the page table
1659		 * page may have been allocated.
1660		 */
1661		return (NULL);
1662	}
1663	if ((m->flags & PG_ZERO) == 0)
1664		pmap_zero_page(m);
1665
1666	/*
1667	 * Map the pagetable page into the process address space, if
1668	 * it isn't already there.
1669	 */
1670	pmap->pm_stats.resident_count++;
1671
1672	ptema = xpmap_ptom(VM_PAGE_TO_PHYS(m));
1673	xen_pt_pin(ptema);
1674	PT_SET_VA_MA(&pmap->pm_pdir[ptepindex],
1675		(ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE);
1676
1677	KASSERT(pmap->pm_pdir[ptepindex],
1678	    ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex));
1679	return (m);
1680}
1681
1682static vm_page_t
1683pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1684{
1685	unsigned ptepindex;
1686	pd_entry_t ptema;
1687	vm_page_t m;
1688
1689	KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1690	    (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1691	    ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1692
1693	/*
1694	 * Calculate pagetable page index
1695	 */
1696	ptepindex = va >> PDRSHIFT;
1697retry:
1698	/*
1699	 * Get the page directory entry
1700	 */
1701	ptema = pmap->pm_pdir[ptepindex];
1702
1703	/*
1704	 * This supports switching from a 4MB page to a
1705	 * normal 4K page.
1706	 */
1707	if (ptema & PG_PS) {
1708		/*
1709		 * XXX
1710		 */
1711		pmap->pm_pdir[ptepindex] = 0;
1712		ptema = 0;
1713		pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
1714		pmap_invalidate_all(kernel_pmap);
1715	}
1716
1717	/*
1718	 * If the page table page is mapped, we just increment the
1719	 * hold count, and activate it.
1720	 */
1721	if (ptema & PG_V) {
1722		m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME);
1723		m->wire_count++;
1724	} else {
1725		/*
1726		 * Here if the pte page isn't mapped, or if it has
1727		 * been deallocated.
1728		 */
1729		CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x",
1730		    pmap, va, flags);
1731		m = _pmap_allocpte(pmap, ptepindex, flags);
1732		if (m == NULL && (flags & M_WAITOK))
1733			goto retry;
1734
1735		KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex));
1736	}
1737	return (m);
1738}
1739
1740
1741/***************************************************
1742* Pmap allocation/deallocation routines.
1743 ***************************************************/
1744
1745#ifdef SMP
1746/*
1747 * Deal with a SMP shootdown of other users of the pmap that we are
1748 * trying to dispose of.  This can be a bit hairy.
1749 */
1750static cpumask_t *lazymask;
1751static u_int lazyptd;
1752static volatile u_int lazywait;
1753
1754void pmap_lazyfix_action(void);
1755
1756void
1757pmap_lazyfix_action(void)
1758{
1759	cpumask_t mymask = PCPU_GET(cpumask);
1760
1761#ifdef COUNT_IPIS
1762	(*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1763#endif
1764	if (rcr3() == lazyptd)
1765		load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1766	atomic_clear_int(lazymask, mymask);
1767	atomic_store_rel_int(&lazywait, 1);
1768}
1769
1770static void
1771pmap_lazyfix_self(cpumask_t mymask)
1772{
1773
1774	if (rcr3() == lazyptd)
1775		load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1776	atomic_clear_int(lazymask, mymask);
1777}
1778
1779
1780static void
1781pmap_lazyfix(pmap_t pmap)
1782{
1783	cpumask_t mymask, mask;
1784	u_int spins;
1785
1786	while ((mask = pmap->pm_active) != 0) {
1787		spins = 50000000;
1788		mask = mask & -mask;	/* Find least significant set bit */
1789		mtx_lock_spin(&smp_ipi_mtx);
1790#ifdef PAE
1791		lazyptd = vtophys(pmap->pm_pdpt);
1792#else
1793		lazyptd = vtophys(pmap->pm_pdir);
1794#endif
1795		mymask = PCPU_GET(cpumask);
1796		if (mask == mymask) {
1797			lazymask = &pmap->pm_active;
1798			pmap_lazyfix_self(mymask);
1799		} else {
1800			atomic_store_rel_int((u_int *)&lazymask,
1801			    (u_int)&pmap->pm_active);
1802			atomic_store_rel_int(&lazywait, 0);
1803			ipi_selected(mask, IPI_LAZYPMAP);
1804			while (lazywait == 0) {
1805				ia32_pause();
1806				if (--spins == 0)
1807					break;
1808			}
1809		}
1810		mtx_unlock_spin(&smp_ipi_mtx);
1811		if (spins == 0)
1812			printf("pmap_lazyfix: spun for 50000000\n");
1813	}
1814}
1815
1816#else	/* SMP */
1817
1818/*
1819 * Cleaning up on uniprocessor is easy.  For various reasons, we're
1820 * unlikely to have to even execute this code, including the fact
1821 * that the cleanup is deferred until the parent does a wait(2), which
1822 * means that another userland process has run.
1823 */
1824static void
1825pmap_lazyfix(pmap_t pmap)
1826{
1827	u_int cr3;
1828
1829	cr3 = vtophys(pmap->pm_pdir);
1830	if (cr3 == rcr3()) {
1831		load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1832		pmap->pm_active &= ~(PCPU_GET(cpumask));
1833	}
1834}
1835#endif	/* SMP */
1836
1837/*
1838 * Release any resources held by the given physical map.
1839 * Called when a pmap initialized by pmap_pinit is being released.
1840 * Should only be called if the map contains no valid mappings.
1841 */
1842void
1843pmap_release(pmap_t pmap)
1844{
1845	vm_page_t m, ptdpg[2*NPGPTD+1];
1846	vm_paddr_t ma;
1847	int i;
1848#ifdef XEN
1849#ifdef PAE
1850	int npgptd = NPGPTD + 1;
1851#else
1852	int npgptd = NPGPTD;
1853#endif
1854#else
1855	int npgptd = NPGPTD;
1856#endif
1857	KASSERT(pmap->pm_stats.resident_count == 0,
1858	    ("pmap_release: pmap resident count %ld != 0",
1859	    pmap->pm_stats.resident_count));
1860	PT_UPDATES_FLUSH();
1861
1862	pmap_lazyfix(pmap);
1863	mtx_lock_spin(&allpmaps_lock);
1864	LIST_REMOVE(pmap, pm_list);
1865	mtx_unlock_spin(&allpmaps_lock);
1866
1867	for (i = 0; i < NPGPTD; i++)
1868		ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME);
1869	pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
1870#if defined(PAE) && defined(XEN)
1871	ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt));
1872#endif
1873
1874	for (i = 0; i < npgptd; i++) {
1875		m = ptdpg[i];
1876		ma = xpmap_ptom(VM_PAGE_TO_PHYS(m));
1877		/* unpinning L1 and L2 treated the same */
1878                xen_pgd_unpin(ma);
1879#ifdef PAE
1880		if (i < NPGPTD)
1881			KASSERT(xpmap_ptom(VM_PAGE_TO_PHYS(m)) == (pmap->pm_pdpt[i] & PG_FRAME),
1882			    ("pmap_release: got wrong ptd page"));
1883#endif
1884		m->wire_count--;
1885		atomic_subtract_int(&cnt.v_wire_count, 1);
1886		vm_page_free(m);
1887	}
1888	PMAP_LOCK_DESTROY(pmap);
1889}
1890
1891static int
1892kvm_size(SYSCTL_HANDLER_ARGS)
1893{
1894	unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
1895
1896	return sysctl_handle_long(oidp, &ksize, 0, req);
1897}
1898SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1899    0, 0, kvm_size, "IU", "Size of KVM");
1900
1901static int
1902kvm_free(SYSCTL_HANDLER_ARGS)
1903{
1904	unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1905
1906	return sysctl_handle_long(oidp, &kfree, 0, req);
1907}
1908SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1909    0, 0, kvm_free, "IU", "Amount of KVM free");
1910
1911/*
1912 * grow the number of kernel page table entries, if needed
1913 */
1914void
1915pmap_growkernel(vm_offset_t addr)
1916{
1917	struct pmap *pmap;
1918	vm_paddr_t ptppaddr;
1919	vm_page_t nkpg;
1920	pd_entry_t newpdir;
1921
1922	mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1923	if (kernel_vm_end == 0) {
1924		kernel_vm_end = KERNBASE;
1925		nkpt = 0;
1926		while (pdir_pde(PTD, kernel_vm_end)) {
1927			kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1928			nkpt++;
1929			if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1930				kernel_vm_end = kernel_map->max_offset;
1931				break;
1932			}
1933		}
1934	}
1935	addr = roundup2(addr, PAGE_SIZE * NPTEPG);
1936	if (addr - 1 >= kernel_map->max_offset)
1937		addr = kernel_map->max_offset;
1938	while (kernel_vm_end < addr) {
1939		if (pdir_pde(PTD, kernel_vm_end)) {
1940			kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1941			if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1942				kernel_vm_end = kernel_map->max_offset;
1943				break;
1944			}
1945			continue;
1946		}
1947
1948		/*
1949		 * This index is bogus, but out of the way
1950		 */
1951		nkpg = vm_page_alloc(NULL, nkpt,
1952		    VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED);
1953		if (!nkpg)
1954			panic("pmap_growkernel: no memory to grow kernel");
1955
1956		nkpt++;
1957
1958		pmap_zero_page(nkpg);
1959		ptppaddr = VM_PAGE_TO_PHYS(nkpg);
1960		newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
1961		vm_page_lock_queues();
1962		PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE);
1963		mtx_lock_spin(&allpmaps_lock);
1964		LIST_FOREACH(pmap, &allpmaps, pm_list)
1965			PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE);
1966
1967		mtx_unlock_spin(&allpmaps_lock);
1968		vm_page_unlock_queues();
1969
1970		kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1971		if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1972			kernel_vm_end = kernel_map->max_offset;
1973			break;
1974		}
1975	}
1976}
1977
1978
1979/***************************************************
1980 * page management routines.
1981 ***************************************************/
1982
1983CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1984CTASSERT(_NPCM == 11);
1985
1986static __inline struct pv_chunk *
1987pv_to_chunk(pv_entry_t pv)
1988{
1989
1990	return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK);
1991}
1992
1993#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1994
1995#define	PC_FREE0_9	0xfffffffful	/* Free values for index 0 through 9 */
1996#define	PC_FREE10	0x0000fffful	/* Free values for index 10 */
1997
1998static uint32_t pc_freemask[11] = {
1999	PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2000	PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2001	PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2002	PC_FREE0_9, PC_FREE10
2003};
2004
2005SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2006	"Current number of pv entries");
2007
2008#ifdef PV_STATS
2009static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2010
2011SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2012	"Current number of pv entry chunks");
2013SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2014	"Current number of pv entry chunks allocated");
2015SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2016	"Current number of pv entry chunks frees");
2017SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2018	"Number of times tried to get a chunk page but failed.");
2019
2020static long pv_entry_frees, pv_entry_allocs;
2021static int pv_entry_spare;
2022
2023SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2024	"Current number of pv entry frees");
2025SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2026	"Current number of pv entry allocs");
2027SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2028	"Current number of spare pv entries");
2029
2030static int pmap_collect_inactive, pmap_collect_active;
2031
2032SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0,
2033	"Current number times pmap_collect called on inactive queue");
2034SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0,
2035	"Current number times pmap_collect called on active queue");
2036#endif
2037
2038/*
2039 * We are in a serious low memory condition.  Resort to
2040 * drastic measures to free some pages so we can allocate
2041 * another pv entry chunk.  This is normally called to
2042 * unmap inactive pages, and if necessary, active pages.
2043 */
2044static void
2045pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq)
2046{
2047	pmap_t pmap;
2048	pt_entry_t *pte, tpte;
2049	pv_entry_t next_pv, pv;
2050	vm_offset_t va;
2051	vm_page_t m, free;
2052
2053	sched_pin();
2054	TAILQ_FOREACH(m, &vpq->pl, pageq) {
2055		if (m->hold_count || m->busy)
2056			continue;
2057		TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) {
2058			va = pv->pv_va;
2059			pmap = PV_PMAP(pv);
2060			/* Avoid deadlock and lock recursion. */
2061			if (pmap > locked_pmap)
2062				PMAP_LOCK(pmap);
2063			else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap))
2064				continue;
2065			pmap->pm_stats.resident_count--;
2066			pte = pmap_pte_quick(pmap, va);
2067			tpte = pte_load_clear(pte);
2068			KASSERT((tpte & PG_W) == 0,
2069			    ("pmap_collect: wired pte %#jx", (uintmax_t)tpte));
2070			if (tpte & PG_A)
2071				vm_page_flag_set(m, PG_REFERENCED);
2072			if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2073				vm_page_dirty(m);
2074			free = NULL;
2075			pmap_unuse_pt(pmap, va, &free);
2076			pmap_invalidate_page(pmap, va);
2077			pmap_free_zero_pages(free);
2078			TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2079			free_pv_entry(pmap, pv);
2080			if (pmap != locked_pmap)
2081				PMAP_UNLOCK(pmap);
2082		}
2083		if (TAILQ_EMPTY(&m->md.pv_list))
2084			vm_page_flag_clear(m, PG_WRITEABLE);
2085	}
2086	sched_unpin();
2087}
2088
2089
2090/*
2091 * free the pv_entry back to the free list
2092 */
2093static void
2094free_pv_entry(pmap_t pmap, pv_entry_t pv)
2095{
2096	vm_page_t m;
2097	struct pv_chunk *pc;
2098	int idx, field, bit;
2099
2100	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2101	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2102	PV_STAT(pv_entry_frees++);
2103	PV_STAT(pv_entry_spare++);
2104	pv_entry_count--;
2105	pc = pv_to_chunk(pv);
2106	idx = pv - &pc->pc_pventry[0];
2107	field = idx / 32;
2108	bit = idx % 32;
2109	pc->pc_map[field] |= 1ul << bit;
2110	/* move to head of list */
2111	TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2112	TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2113	for (idx = 0; idx < _NPCM; idx++)
2114		if (pc->pc_map[idx] != pc_freemask[idx])
2115			return;
2116	PV_STAT(pv_entry_spare -= _NPCPV);
2117	PV_STAT(pc_chunk_count--);
2118	PV_STAT(pc_chunk_frees++);
2119	/* entire chunk is free, return it */
2120	TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2121	m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2122	pmap_qremove((vm_offset_t)pc, 1);
2123	vm_page_unwire(m, 0);
2124	vm_page_free(m);
2125	pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2126}
2127
2128/*
2129 * get a new pv_entry, allocating a block from the system
2130 * when needed.
2131 */
2132static pv_entry_t
2133get_pv_entry(pmap_t pmap, int try)
2134{
2135	static const struct timeval printinterval = { 60, 0 };
2136	static struct timeval lastprint;
2137	static vm_pindex_t colour;
2138	struct vpgqueues *pq;
2139	int bit, field;
2140	pv_entry_t pv;
2141	struct pv_chunk *pc;
2142	vm_page_t m;
2143
2144	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2145	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2146	PV_STAT(pv_entry_allocs++);
2147	pv_entry_count++;
2148	if (pv_entry_count > pv_entry_high_water)
2149		if (ratecheck(&lastprint, &printinterval))
2150			printf("Approaching the limit on PV entries, consider "
2151			    "increasing either the vm.pmap.shpgperproc or the "
2152			    "vm.pmap.pv_entry_max tunable.\n");
2153	pq = NULL;
2154retry:
2155	pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2156	if (pc != NULL) {
2157		for (field = 0; field < _NPCM; field++) {
2158			if (pc->pc_map[field]) {
2159				bit = bsfl(pc->pc_map[field]);
2160				break;
2161			}
2162		}
2163		if (field < _NPCM) {
2164			pv = &pc->pc_pventry[field * 32 + bit];
2165			pc->pc_map[field] &= ~(1ul << bit);
2166			/* If this was the last item, move it to tail */
2167			for (field = 0; field < _NPCM; field++)
2168				if (pc->pc_map[field] != 0) {
2169					PV_STAT(pv_entry_spare--);
2170					return (pv);	/* not full, return */
2171				}
2172			TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2173			TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2174			PV_STAT(pv_entry_spare--);
2175			return (pv);
2176		}
2177	}
2178	/*
2179	 * Access to the ptelist "pv_vafree" is synchronized by the page
2180	 * queues lock.  If "pv_vafree" is currently non-empty, it will
2181	 * remain non-empty until pmap_ptelist_alloc() completes.
2182	 */
2183	if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq ==
2184	    &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) |
2185	    VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2186		if (try) {
2187			pv_entry_count--;
2188			PV_STAT(pc_chunk_tryfail++);
2189			return (NULL);
2190		}
2191		/*
2192		 * Reclaim pv entries: At first, destroy mappings to
2193		 * inactive pages.  After that, if a pv chunk entry
2194		 * is still needed, destroy mappings to active pages.
2195		 */
2196		if (pq == NULL) {
2197			PV_STAT(pmap_collect_inactive++);
2198			pq = &vm_page_queues[PQ_INACTIVE];
2199		} else if (pq == &vm_page_queues[PQ_INACTIVE]) {
2200			PV_STAT(pmap_collect_active++);
2201			pq = &vm_page_queues[PQ_ACTIVE];
2202		} else
2203			panic("get_pv_entry: increase vm.pmap.shpgperproc");
2204		pmap_collect(pmap, pq);
2205		goto retry;
2206	}
2207	PV_STAT(pc_chunk_count++);
2208	PV_STAT(pc_chunk_allocs++);
2209	colour++;
2210	pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2211	pmap_qenter((vm_offset_t)pc, &m, 1);
2212	if ((m->flags & PG_ZERO) == 0)
2213		pagezero(pc);
2214	pc->pc_pmap = pmap;
2215	pc->pc_map[0] = pc_freemask[0] & ~1ul;	/* preallocated bit 0 */
2216	for (field = 1; field < _NPCM; field++)
2217		pc->pc_map[field] = pc_freemask[field];
2218	pv = &pc->pc_pventry[0];
2219	TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2220	PV_STAT(pv_entry_spare += _NPCPV - 1);
2221	return (pv);
2222}
2223
2224static __inline pv_entry_t
2225pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2226{
2227	pv_entry_t pv;
2228
2229	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2230	TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2231		if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2232			TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2233			break;
2234		}
2235	}
2236	return (pv);
2237}
2238
2239static void
2240pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2241{
2242	pv_entry_t pv;
2243
2244	pv = pmap_pvh_remove(pvh, pmap, va);
2245	KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2246	free_pv_entry(pmap, pv);
2247}
2248
2249static void
2250pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2251{
2252
2253	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2254	pmap_pvh_free(&m->md, pmap, va);
2255	if (TAILQ_EMPTY(&m->md.pv_list))
2256		vm_page_flag_clear(m, PG_WRITEABLE);
2257}
2258
2259/*
2260 * Conditionally create a pv entry.
2261 */
2262static boolean_t
2263pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2264{
2265	pv_entry_t pv;
2266
2267	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2268	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2269	if (pv_entry_count < pv_entry_high_water &&
2270	    (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2271		pv->pv_va = va;
2272		TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2273		return (TRUE);
2274	} else
2275		return (FALSE);
2276}
2277
2278/*
2279 * pmap_remove_pte: do the things to unmap a page in a process
2280 */
2281static int
2282pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free)
2283{
2284	pt_entry_t oldpte;
2285	vm_page_t m;
2286
2287	CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x",
2288	    pmap, (u_long)*ptq, va);
2289
2290	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2291	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2292	oldpte = *ptq;
2293	PT_SET_VA_MA(ptq, 0, TRUE);
2294	if (oldpte & PG_W)
2295		pmap->pm_stats.wired_count -= 1;
2296	/*
2297	 * Machines that don't support invlpg, also don't support
2298	 * PG_G.
2299	 */
2300	if (oldpte & PG_G)
2301		pmap_invalidate_page(kernel_pmap, va);
2302	pmap->pm_stats.resident_count -= 1;
2303	/*
2304	 * XXX This is not strictly correctly, but somewhere along the line
2305	 * we are losing the managed bit on some pages. It is unclear to me
2306	 * why, but I think the most likely explanation is that xen's writable
2307	 * page table implementation doesn't respect the unused bits.
2308	 */
2309	if ((oldpte & PG_MANAGED) || ((oldpte & PG_V) && (va < VM_MAXUSER_ADDRESS))
2310		) {
2311		m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME);
2312
2313		if (!(oldpte & PG_MANAGED))
2314			printf("va=0x%x is unmanaged :-( pte=0x%llx\n", va, oldpte);
2315
2316		if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2317			vm_page_dirty(m);
2318		if (oldpte & PG_A)
2319			vm_page_flag_set(m, PG_REFERENCED);
2320		pmap_remove_entry(pmap, m, va);
2321	} else if ((va < VM_MAXUSER_ADDRESS) && (oldpte & PG_V))
2322		printf("va=0x%x is unmanaged :-( pte=0x%llx\n", va, oldpte);
2323
2324	return (pmap_unuse_pt(pmap, va, free));
2325}
2326
2327/*
2328 * Remove a single page from a process address space
2329 */
2330static void
2331pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free)
2332{
2333	pt_entry_t *pte;
2334
2335	CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x",
2336	    pmap, va);
2337
2338	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2339	KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2340	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2341	if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0)
2342		return;
2343	pmap_remove_pte(pmap, pte, va, free);
2344	pmap_invalidate_page(pmap, va);
2345	if (*PMAP1)
2346		PT_SET_MA(PADDR1, 0);
2347
2348}
2349
2350/*
2351 *	Remove the given range of addresses from the specified map.
2352 *
2353 *	It is assumed that the start and end are properly
2354 *	rounded to the page size.
2355 */
2356void
2357pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2358{
2359	vm_offset_t pdnxt;
2360	pd_entry_t ptpaddr;
2361	pt_entry_t *pte;
2362	vm_page_t free = NULL;
2363	int anyvalid;
2364
2365	CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x",
2366	    pmap, sva, eva);
2367
2368	/*
2369	 * Perform an unsynchronized read.  This is, however, safe.
2370	 */
2371	if (pmap->pm_stats.resident_count == 0)
2372		return;
2373
2374	anyvalid = 0;
2375
2376	vm_page_lock_queues();
2377	sched_pin();
2378	PMAP_LOCK(pmap);
2379
2380	/*
2381	 * special handling of removing one page.  a very
2382	 * common operation and easy to short circuit some
2383	 * code.
2384	 */
2385	if ((sva + PAGE_SIZE == eva) &&
2386	    ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2387		pmap_remove_page(pmap, sva, &free);
2388		goto out;
2389	}
2390
2391	for (; sva < eva; sva = pdnxt) {
2392		unsigned pdirindex;
2393
2394		/*
2395		 * Calculate index for next page table.
2396		 */
2397		pdnxt = (sva + NBPDR) & ~PDRMASK;
2398		if (pmap->pm_stats.resident_count == 0)
2399			break;
2400
2401		pdirindex = sva >> PDRSHIFT;
2402		ptpaddr = pmap->pm_pdir[pdirindex];
2403
2404		/*
2405		 * Weed out invalid mappings. Note: we assume that the page
2406		 * directory table is always allocated, and in kernel virtual.
2407		 */
2408		if (ptpaddr == 0)
2409			continue;
2410
2411		/*
2412		 * Check for large page.
2413		 */
2414		if ((ptpaddr & PG_PS) != 0) {
2415			PD_CLEAR_VA(pmap, pdirindex, TRUE);
2416			pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2417			anyvalid = 1;
2418			continue;
2419		}
2420
2421		/*
2422		 * Limit our scan to either the end of the va represented
2423		 * by the current page table page, or to the end of the
2424		 * range being removed.
2425		 */
2426		if (pdnxt > eva)
2427			pdnxt = eva;
2428
2429		for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2430		    sva += PAGE_SIZE) {
2431			if ((*pte & PG_V) == 0)
2432				continue;
2433
2434			/*
2435			 * The TLB entry for a PG_G mapping is invalidated
2436			 * by pmap_remove_pte().
2437			 */
2438			if ((*pte & PG_G) == 0)
2439				anyvalid = 1;
2440			if (pmap_remove_pte(pmap, pte, sva, &free))
2441				break;
2442		}
2443	}
2444	PT_UPDATES_FLUSH();
2445	if (*PMAP1)
2446		PT_SET_VA_MA(PMAP1, 0, TRUE);
2447out:
2448	if (anyvalid)
2449		pmap_invalidate_all(pmap);
2450	sched_unpin();
2451	vm_page_unlock_queues();
2452	PMAP_UNLOCK(pmap);
2453	pmap_free_zero_pages(free);
2454}
2455
2456/*
2457 *	Routine:	pmap_remove_all
2458 *	Function:
2459 *		Removes this physical page from
2460 *		all physical maps in which it resides.
2461 *		Reflects back modify bits to the pager.
2462 *
2463 *	Notes:
2464 *		Original versions of this routine were very
2465 *		inefficient because they iteratively called
2466 *		pmap_remove (slow...)
2467 */
2468
2469void
2470pmap_remove_all(vm_page_t m)
2471{
2472	pv_entry_t pv;
2473	pmap_t pmap;
2474	pt_entry_t *pte, tpte;
2475	vm_page_t free;
2476
2477	KASSERT((m->flags & PG_FICTITIOUS) == 0,
2478	    ("pmap_remove_all: page %p is fictitious", m));
2479	free = NULL;
2480	vm_page_lock_queues();
2481	sched_pin();
2482	while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2483		pmap = PV_PMAP(pv);
2484		PMAP_LOCK(pmap);
2485		pmap->pm_stats.resident_count--;
2486		pte = pmap_pte_quick(pmap, pv->pv_va);
2487
2488		tpte = *pte;
2489		PT_SET_VA_MA(pte, 0, TRUE);
2490		if (tpte & PG_W)
2491			pmap->pm_stats.wired_count--;
2492		if (tpte & PG_A)
2493			vm_page_flag_set(m, PG_REFERENCED);
2494
2495		/*
2496		 * Update the vm_page_t clean and reference bits.
2497		 */
2498		if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2499			vm_page_dirty(m);
2500		pmap_unuse_pt(pmap, pv->pv_va, &free);
2501		pmap_invalidate_page(pmap, pv->pv_va);
2502		TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2503		free_pv_entry(pmap, pv);
2504		PMAP_UNLOCK(pmap);
2505	}
2506	vm_page_flag_clear(m, PG_WRITEABLE);
2507	PT_UPDATES_FLUSH();
2508	if (*PMAP1)
2509		PT_SET_MA(PADDR1, 0);
2510	sched_unpin();
2511	vm_page_unlock_queues();
2512	pmap_free_zero_pages(free);
2513}
2514
2515/*
2516 *	Set the physical protection on the
2517 *	specified range of this map as requested.
2518 */
2519void
2520pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2521{
2522	vm_offset_t pdnxt;
2523	pd_entry_t ptpaddr;
2524	pt_entry_t *pte;
2525	int anychanged;
2526
2527	CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x",
2528	    pmap, sva, eva, prot);
2529
2530	if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2531		pmap_remove(pmap, sva, eva);
2532		return;
2533	}
2534
2535#ifdef PAE
2536	if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
2537	    (VM_PROT_WRITE|VM_PROT_EXECUTE))
2538		return;
2539#else
2540	if (prot & VM_PROT_WRITE)
2541		return;
2542#endif
2543
2544	anychanged = 0;
2545
2546	vm_page_lock_queues();
2547	sched_pin();
2548	PMAP_LOCK(pmap);
2549	for (; sva < eva; sva = pdnxt) {
2550		pt_entry_t obits, pbits;
2551		unsigned pdirindex;
2552
2553		pdnxt = (sva + NBPDR) & ~PDRMASK;
2554
2555		pdirindex = sva >> PDRSHIFT;
2556		ptpaddr = pmap->pm_pdir[pdirindex];
2557
2558		/*
2559		 * Weed out invalid mappings. Note: we assume that the page
2560		 * directory table is always allocated, and in kernel virtual.
2561		 */
2562		if (ptpaddr == 0)
2563			continue;
2564
2565		/*
2566		 * Check for large page.
2567		 */
2568		if ((ptpaddr & PG_PS) != 0) {
2569			if ((prot & VM_PROT_WRITE) == 0)
2570				pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW);
2571#ifdef PAE
2572			if ((prot & VM_PROT_EXECUTE) == 0)
2573				pmap->pm_pdir[pdirindex] |= pg_nx;
2574#endif
2575			anychanged = 1;
2576			continue;
2577		}
2578
2579		if (pdnxt > eva)
2580			pdnxt = eva;
2581
2582		for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2583		    sva += PAGE_SIZE) {
2584			vm_page_t m;
2585
2586retry:
2587			/*
2588			 * Regardless of whether a pte is 32 or 64 bits in
2589			 * size, PG_RW, PG_A, and PG_M are among the least
2590			 * significant 32 bits.
2591			 */
2592			obits = pbits = *pte;
2593			if ((pbits & PG_V) == 0)
2594				continue;
2595
2596			if ((prot & VM_PROT_WRITE) == 0) {
2597				if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
2598				    (PG_MANAGED | PG_M | PG_RW)) {
2599					m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) &
2600					    PG_FRAME);
2601					vm_page_dirty(m);
2602				}
2603				pbits &= ~(PG_RW | PG_M);
2604			}
2605#ifdef PAE
2606			if ((prot & VM_PROT_EXECUTE) == 0)
2607				pbits |= pg_nx;
2608#endif
2609
2610			if (pbits != obits) {
2611#ifdef XEN
2612				obits = *pte;
2613				PT_SET_VA_MA(pte, pbits, TRUE);
2614				if (*pte != pbits)
2615					goto retry;
2616#else
2617#ifdef PAE
2618				if (!atomic_cmpset_64(pte, obits, pbits))
2619					goto retry;
2620#else
2621				if (!atomic_cmpset_int((u_int *)pte, obits,
2622				    pbits))
2623					goto retry;
2624#endif
2625#endif
2626				if (obits & PG_G)
2627					pmap_invalidate_page(pmap, sva);
2628				else
2629					anychanged = 1;
2630			}
2631		}
2632	}
2633	PT_UPDATES_FLUSH();
2634	if (*PMAP1)
2635		PT_SET_VA_MA(PMAP1, 0, TRUE);
2636	if (anychanged)
2637		pmap_invalidate_all(pmap);
2638	sched_unpin();
2639	vm_page_unlock_queues();
2640	PMAP_UNLOCK(pmap);
2641}
2642
2643/*
2644 *	Insert the given physical page (p) at
2645 *	the specified virtual address (v) in the
2646 *	target physical map with the protection requested.
2647 *
2648 *	If specified, the page will be wired down, meaning
2649 *	that the related pte can not be reclaimed.
2650 *
2651 *	NB:  This is the only routine which MAY NOT lazy-evaluate
2652 *	or lose information.  That is, this routine must actually
2653 *	insert this page into the given map NOW.
2654 */
2655void
2656pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
2657    vm_prot_t prot, boolean_t wired)
2658{
2659	pd_entry_t *pde;
2660	pt_entry_t *pte;
2661	pt_entry_t newpte, origpte;
2662	pv_entry_t pv;
2663	vm_paddr_t opa, pa;
2664	vm_page_t mpte, om;
2665	boolean_t invlva;
2666
2667	CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d",
2668	    pmap, va, access, xpmap_ptom(VM_PAGE_TO_PHYS(m)), prot, wired);
2669	va = trunc_page(va);
2670	KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2671	KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
2672	    ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
2673	    va));
2674	KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
2675	    (m->oflags & VPO_BUSY) != 0,
2676	    ("pmap_enter: page %p is not busy", m));
2677
2678	mpte = NULL;
2679
2680	vm_page_lock_queues();
2681	PMAP_LOCK(pmap);
2682	sched_pin();
2683
2684	/*
2685	 * In the case that a page table page is not
2686	 * resident, we are creating it here.
2687	 */
2688	if (va < VM_MAXUSER_ADDRESS) {
2689		mpte = pmap_allocpte(pmap, va, M_WAITOK);
2690	}
2691
2692	pde = pmap_pde(pmap, va);
2693	if ((*pde & PG_PS) != 0)
2694		panic("pmap_enter: attempted pmap_enter on 4MB page");
2695	pte = pmap_pte_quick(pmap, va);
2696
2697	/*
2698	 * Page Directory table entry not valid, we need a new PT page
2699	 */
2700	if (pte == NULL) {
2701		panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
2702			(uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va);
2703	}
2704
2705	pa = VM_PAGE_TO_PHYS(m);
2706	om = NULL;
2707	opa = origpte = 0;
2708
2709#if 0
2710	KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx",
2711		pte, *pte));
2712#endif
2713	origpte = *pte;
2714	if (origpte)
2715		origpte = xpmap_mtop(origpte);
2716	opa = origpte & PG_FRAME;
2717
2718	/*
2719	 * Mapping has not changed, must be protection or wiring change.
2720	 */
2721	if (origpte && (opa == pa)) {
2722		/*
2723		 * Wiring change, just update stats. We don't worry about
2724		 * wiring PT pages as they remain resident as long as there
2725		 * are valid mappings in them. Hence, if a user page is wired,
2726		 * the PT page will be also.
2727		 */
2728		if (wired && ((origpte & PG_W) == 0))
2729			pmap->pm_stats.wired_count++;
2730		else if (!wired && (origpte & PG_W))
2731			pmap->pm_stats.wired_count--;
2732
2733		/*
2734		 * Remove extra pte reference
2735		 */
2736		if (mpte)
2737			mpte->wire_count--;
2738
2739		if (origpte & PG_MANAGED) {
2740			om = m;
2741			pa |= PG_MANAGED;
2742		}
2743		goto validate;
2744	}
2745
2746	pv = NULL;
2747
2748	/*
2749	 * Mapping has changed, invalidate old range and fall through to
2750	 * handle validating new mapping.
2751	 */
2752	if (opa) {
2753		if (origpte & PG_W)
2754			pmap->pm_stats.wired_count--;
2755		if (origpte & PG_MANAGED) {
2756			om = PHYS_TO_VM_PAGE(opa);
2757			pv = pmap_pvh_remove(&om->md, pmap, va);
2758		} else if (va < VM_MAXUSER_ADDRESS)
2759			printf("va=0x%x is unmanaged :-( \n", va);
2760
2761		if (mpte != NULL) {
2762			mpte->wire_count--;
2763			KASSERT(mpte->wire_count > 0,
2764			    ("pmap_enter: missing reference to page table page,"
2765			     " va: 0x%x", va));
2766		}
2767	} else
2768		pmap->pm_stats.resident_count++;
2769
2770	/*
2771	 * Enter on the PV list if part of our managed memory.
2772	 */
2773	if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) {
2774		KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
2775		    ("pmap_enter: managed mapping within the clean submap"));
2776		if (pv == NULL)
2777			pv = get_pv_entry(pmap, FALSE);
2778		pv->pv_va = va;
2779		TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2780		pa |= PG_MANAGED;
2781	} else if (pv != NULL)
2782		free_pv_entry(pmap, pv);
2783
2784	/*
2785	 * Increment counters
2786	 */
2787	if (wired)
2788		pmap->pm_stats.wired_count++;
2789
2790validate:
2791	/*
2792	 * Now validate mapping with desired protection/wiring.
2793	 */
2794	newpte = (pt_entry_t)(pa | PG_V);
2795	if ((prot & VM_PROT_WRITE) != 0) {
2796		newpte |= PG_RW;
2797		if ((newpte & PG_MANAGED) != 0)
2798			vm_page_flag_set(m, PG_WRITEABLE);
2799	}
2800#ifdef PAE
2801	if ((prot & VM_PROT_EXECUTE) == 0)
2802		newpte |= pg_nx;
2803#endif
2804	if (wired)
2805		newpte |= PG_W;
2806	if (va < VM_MAXUSER_ADDRESS)
2807		newpte |= PG_U;
2808	if (pmap == kernel_pmap)
2809		newpte |= pgeflag;
2810
2811	critical_enter();
2812	/*
2813	 * if the mapping or permission bits are different, we need
2814	 * to update the pte.
2815	 */
2816	if ((origpte & ~(PG_M|PG_A)) != newpte) {
2817		if (origpte) {
2818			invlva = FALSE;
2819			origpte = *pte;
2820			PT_SET_VA(pte, newpte | PG_A, FALSE);
2821			if (origpte & PG_A) {
2822				if (origpte & PG_MANAGED)
2823					vm_page_flag_set(om, PG_REFERENCED);
2824				if (opa != VM_PAGE_TO_PHYS(m))
2825					invlva = TRUE;
2826#ifdef PAE
2827				if ((origpte & PG_NX) == 0 &&
2828				    (newpte & PG_NX) != 0)
2829					invlva = TRUE;
2830#endif
2831			}
2832			if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
2833				if ((origpte & PG_MANAGED) != 0)
2834					vm_page_dirty(om);
2835				if ((prot & VM_PROT_WRITE) == 0)
2836					invlva = TRUE;
2837			}
2838			if ((origpte & PG_MANAGED) != 0 &&
2839			    TAILQ_EMPTY(&om->md.pv_list))
2840				vm_page_flag_clear(om, PG_WRITEABLE);
2841			if (invlva)
2842				pmap_invalidate_page(pmap, va);
2843		} else{
2844			PT_SET_VA(pte, newpte | PG_A, FALSE);
2845		}
2846
2847	}
2848	PT_UPDATES_FLUSH();
2849	critical_exit();
2850	if (*PMAP1)
2851		PT_SET_VA_MA(PMAP1, 0, TRUE);
2852	sched_unpin();
2853	vm_page_unlock_queues();
2854	PMAP_UNLOCK(pmap);
2855}
2856
2857/*
2858 * Maps a sequence of resident pages belonging to the same object.
2859 * The sequence begins with the given page m_start.  This page is
2860 * mapped at the given virtual address start.  Each subsequent page is
2861 * mapped at a virtual address that is offset from start by the same
2862 * amount as the page is offset from m_start within the object.  The
2863 * last page in the sequence is the page with the largest offset from
2864 * m_start that can be mapped at a virtual address less than the given
2865 * virtual address end.  Not every virtual page between start and end
2866 * is mapped; only those for which a resident page exists with the
2867 * corresponding offset from m_start are mapped.
2868 */
2869void
2870pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2871    vm_page_t m_start, vm_prot_t prot)
2872{
2873	vm_page_t m, mpte;
2874	vm_pindex_t diff, psize;
2875	multicall_entry_t mcl[16];
2876	multicall_entry_t *mclp = mcl;
2877	int error, count = 0;
2878
2879	VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
2880	psize = atop(end - start);
2881
2882	mpte = NULL;
2883	m = m_start;
2884	vm_page_lock_queues();
2885	PMAP_LOCK(pmap);
2886	while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2887		mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m,
2888		    prot, mpte);
2889		m = TAILQ_NEXT(m, listq);
2890		if (count == 16) {
2891			error = HYPERVISOR_multicall(mcl, count);
2892			KASSERT(error == 0, ("bad multicall %d", error));
2893			mclp = mcl;
2894			count = 0;
2895		}
2896	}
2897	if (count) {
2898		error = HYPERVISOR_multicall(mcl, count);
2899		KASSERT(error == 0, ("bad multicall %d", error));
2900	}
2901	vm_page_unlock_queues();
2902	PMAP_UNLOCK(pmap);
2903}
2904
2905/*
2906 * this code makes some *MAJOR* assumptions:
2907 * 1. Current pmap & pmap exists.
2908 * 2. Not wired.
2909 * 3. Read access.
2910 * 4. No page table pages.
2911 * but is *MUCH* faster than pmap_enter...
2912 */
2913
2914void
2915pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2916{
2917	multicall_entry_t mcl, *mclp;
2918	int count = 0;
2919	mclp = &mcl;
2920
2921	CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x",
2922	    pmap, va, m, prot);
2923
2924	vm_page_lock_queues();
2925	PMAP_LOCK(pmap);
2926	(void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL);
2927	if (count)
2928		HYPERVISOR_multicall(&mcl, count);
2929	vm_page_unlock_queues();
2930	PMAP_UNLOCK(pmap);
2931}
2932
2933#ifdef notyet
2934void
2935pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count)
2936{
2937	int i, error, index = 0;
2938	multicall_entry_t mcl[16];
2939	multicall_entry_t *mclp = mcl;
2940
2941	PMAP_LOCK(pmap);
2942	for (i = 0; i < count; i++, addrs++, pages++, prots++) {
2943		if (!pmap_is_prefaultable_locked(pmap, *addrs))
2944			continue;
2945
2946		(void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL);
2947		if (index == 16) {
2948			error = HYPERVISOR_multicall(mcl, index);
2949			mclp = mcl;
2950			index = 0;
2951			KASSERT(error == 0, ("bad multicall %d", error));
2952		}
2953	}
2954	if (index) {
2955		error = HYPERVISOR_multicall(mcl, index);
2956		KASSERT(error == 0, ("bad multicall %d", error));
2957	}
2958
2959	PMAP_UNLOCK(pmap);
2960}
2961#endif
2962
2963static vm_page_t
2964pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m,
2965    vm_prot_t prot, vm_page_t mpte)
2966{
2967	pt_entry_t *pte;
2968	vm_paddr_t pa;
2969	vm_page_t free;
2970	multicall_entry_t *mcl = *mclpp;
2971
2972	KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2973	    (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0,
2974	    ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2975	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2976	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2977
2978	/*
2979	 * In the case that a page table page is not
2980	 * resident, we are creating it here.
2981	 */
2982	if (va < VM_MAXUSER_ADDRESS) {
2983		unsigned ptepindex;
2984		pd_entry_t ptema;
2985
2986		/*
2987		 * Calculate pagetable page index
2988		 */
2989		ptepindex = va >> PDRSHIFT;
2990		if (mpte && (mpte->pindex == ptepindex)) {
2991			mpte->wire_count++;
2992		} else {
2993			/*
2994			 * Get the page directory entry
2995			 */
2996			ptema = pmap->pm_pdir[ptepindex];
2997
2998			/*
2999			 * If the page table page is mapped, we just increment
3000			 * the hold count, and activate it.
3001			 */
3002			if (ptema & PG_V) {
3003				if (ptema & PG_PS)
3004					panic("pmap_enter_quick: unexpected mapping into 4MB page");
3005				mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME);
3006				mpte->wire_count++;
3007			} else {
3008				mpte = _pmap_allocpte(pmap, ptepindex,
3009				    M_NOWAIT);
3010				if (mpte == NULL)
3011					return (mpte);
3012			}
3013		}
3014	} else {
3015		mpte = NULL;
3016	}
3017
3018	/*
3019	 * This call to vtopte makes the assumption that we are
3020	 * entering the page into the current pmap.  In order to support
3021	 * quick entry into any pmap, one would likely use pmap_pte_quick.
3022	 * But that isn't as quick as vtopte.
3023	 */
3024	KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap"));
3025	pte = vtopte(va);
3026	if (*pte & PG_V) {
3027		if (mpte != NULL) {
3028			mpte->wire_count--;
3029			mpte = NULL;
3030		}
3031		return (mpte);
3032	}
3033
3034	/*
3035	 * Enter on the PV list if part of our managed memory.
3036	 */
3037	if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 &&
3038	    !pmap_try_insert_pv_entry(pmap, va, m)) {
3039		if (mpte != NULL) {
3040			free = NULL;
3041			if (pmap_unwire_pte_hold(pmap, mpte, &free)) {
3042				pmap_invalidate_page(pmap, va);
3043				pmap_free_zero_pages(free);
3044			}
3045
3046			mpte = NULL;
3047		}
3048		return (mpte);
3049	}
3050
3051	/*
3052	 * Increment counters
3053	 */
3054	pmap->pm_stats.resident_count++;
3055
3056	pa = VM_PAGE_TO_PHYS(m);
3057#ifdef PAE
3058	if ((prot & VM_PROT_EXECUTE) == 0)
3059		pa |= pg_nx;
3060#endif
3061
3062#if 0
3063	/*
3064	 * Now validate mapping with RO protection
3065	 */
3066	if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED))
3067		pte_store(pte, pa | PG_V | PG_U);
3068	else
3069		pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3070#else
3071	/*
3072	 * Now validate mapping with RO protection
3073	 */
3074	if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED))
3075		pa = 	xpmap_ptom(pa | PG_V | PG_U);
3076	else
3077		pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED);
3078
3079	mcl->op = __HYPERVISOR_update_va_mapping;
3080	mcl->args[0] = va;
3081	mcl->args[1] = (uint32_t)(pa & 0xffffffff);
3082	mcl->args[2] = (uint32_t)(pa >> 32);
3083	mcl->args[3] = 0;
3084	*mclpp = mcl + 1;
3085	*count = *count + 1;
3086#endif
3087	return mpte;
3088}
3089
3090/*
3091 * Make a temporary mapping for a physical address.  This is only intended
3092 * to be used for panic dumps.
3093 */
3094void *
3095pmap_kenter_temporary(vm_paddr_t pa, int i)
3096{
3097	vm_offset_t va;
3098	vm_paddr_t ma = xpmap_ptom(pa);
3099
3100	va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3101	PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag);
3102	invlpg(va);
3103	return ((void *)crashdumpmap);
3104}
3105
3106/*
3107 * This code maps large physical mmap regions into the
3108 * processor address space.  Note that some shortcuts
3109 * are taken, but the code works.
3110 */
3111void
3112pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
3113		    vm_object_t object, vm_pindex_t pindex,
3114		    vm_size_t size)
3115{
3116	pd_entry_t *pde;
3117	vm_paddr_t pa, ptepa;
3118	vm_page_t p;
3119	int pat_mode;
3120
3121	VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3122	KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3123	    ("pmap_object_init_pt: non-device object"));
3124	if (pseflag &&
3125	    (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3126		if (!vm_object_populate(object, pindex, pindex + atop(size)))
3127			return;
3128		p = vm_page_lookup(object, pindex);
3129		KASSERT(p->valid == VM_PAGE_BITS_ALL,
3130		    ("pmap_object_init_pt: invalid page %p", p));
3131		pat_mode = p->md.pat_mode;
3132		/*
3133		 * Abort the mapping if the first page is not physically
3134		 * aligned to a 2/4MB page boundary.
3135		 */
3136		ptepa = VM_PAGE_TO_PHYS(p);
3137		if (ptepa & (NBPDR - 1))
3138			return;
3139		/*
3140		 * Skip the first page.  Abort the mapping if the rest of
3141		 * the pages are not physically contiguous or have differing
3142		 * memory attributes.
3143		 */
3144		p = TAILQ_NEXT(p, listq);
3145		for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3146		    pa += PAGE_SIZE) {
3147			KASSERT(p->valid == VM_PAGE_BITS_ALL,
3148			    ("pmap_object_init_pt: invalid page %p", p));
3149			if (pa != VM_PAGE_TO_PHYS(p) ||
3150			    pat_mode != p->md.pat_mode)
3151				return;
3152			p = TAILQ_NEXT(p, listq);
3153		}
3154		/* Map using 2/4MB pages. */
3155		PMAP_LOCK(pmap);
3156		for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3157		    size; pa += NBPDR) {
3158			pde = pmap_pde(pmap, addr);
3159			if (*pde == 0) {
3160				pde_store(pde, pa | PG_PS | PG_M | PG_A |
3161				    PG_U | PG_RW | PG_V);
3162				pmap->pm_stats.resident_count += NBPDR /
3163				    PAGE_SIZE;
3164				pmap_pde_mappings++;
3165			}
3166			/* Else continue on if the PDE is already valid. */
3167			addr += NBPDR;
3168		}
3169		PMAP_UNLOCK(pmap);
3170	}
3171}
3172
3173/*
3174 *	Routine:	pmap_change_wiring
3175 *	Function:	Change the wiring attribute for a map/virtual-address
3176 *			pair.
3177 *	In/out conditions:
3178 *			The mapping must already exist in the pmap.
3179 */
3180void
3181pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3182{
3183	pt_entry_t *pte;
3184
3185	vm_page_lock_queues();
3186	PMAP_LOCK(pmap);
3187	pte = pmap_pte(pmap, va);
3188
3189	if (wired && !pmap_pte_w(pte)) {
3190		PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE);
3191		pmap->pm_stats.wired_count++;
3192	} else if (!wired && pmap_pte_w(pte)) {
3193		PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE);
3194		pmap->pm_stats.wired_count--;
3195	}
3196
3197	/*
3198	 * Wiring is not a hardware characteristic so there is no need to
3199	 * invalidate TLB.
3200	 */
3201	pmap_pte_release(pte);
3202	PMAP_UNLOCK(pmap);
3203	vm_page_unlock_queues();
3204}
3205
3206
3207
3208/*
3209 *	Copy the range specified by src_addr/len
3210 *	from the source map to the range dst_addr/len
3211 *	in the destination map.
3212 *
3213 *	This routine is only advisory and need not do anything.
3214 */
3215
3216void
3217pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3218	  vm_offset_t src_addr)
3219{
3220	vm_page_t   free;
3221	vm_offset_t addr;
3222	vm_offset_t end_addr = src_addr + len;
3223	vm_offset_t pdnxt;
3224
3225	if (dst_addr != src_addr)
3226		return;
3227
3228	if (!pmap_is_current(src_pmap)) {
3229		CTR2(KTR_PMAP,
3230		    "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx",
3231		    (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME));
3232
3233		return;
3234	}
3235	CTR5(KTR_PMAP, "pmap_copy:  dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x",
3236	    dst_pmap, src_pmap, dst_addr, len, src_addr);
3237
3238	vm_page_lock_queues();
3239	if (dst_pmap < src_pmap) {
3240		PMAP_LOCK(dst_pmap);
3241		PMAP_LOCK(src_pmap);
3242	} else {
3243		PMAP_LOCK(src_pmap);
3244		PMAP_LOCK(dst_pmap);
3245	}
3246	sched_pin();
3247	for (addr = src_addr; addr < end_addr; addr = pdnxt) {
3248		pt_entry_t *src_pte, *dst_pte;
3249		vm_page_t dstmpte, srcmpte;
3250		pd_entry_t srcptepaddr;
3251		unsigned ptepindex;
3252
3253		KASSERT(addr < UPT_MIN_ADDRESS,
3254		    ("pmap_copy: invalid to pmap_copy page tables"));
3255
3256		pdnxt = (addr + NBPDR) & ~PDRMASK;
3257		ptepindex = addr >> PDRSHIFT;
3258
3259		srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]);
3260		if (srcptepaddr == 0)
3261			continue;
3262
3263		if (srcptepaddr & PG_PS) {
3264			if (dst_pmap->pm_pdir[ptepindex] == 0) {
3265				PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE);
3266				dst_pmap->pm_stats.resident_count +=
3267				    NBPDR / PAGE_SIZE;
3268			}
3269			continue;
3270		}
3271
3272		srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
3273		KASSERT(srcmpte->wire_count > 0,
3274		    ("pmap_copy: source page table page is unused"));
3275
3276		if (pdnxt > end_addr)
3277			pdnxt = end_addr;
3278
3279		src_pte = vtopte(addr);
3280		while (addr < pdnxt) {
3281			pt_entry_t ptetemp;
3282			ptetemp = *src_pte;
3283			/*
3284			 * we only virtual copy managed pages
3285			 */
3286			if ((ptetemp & PG_MANAGED) != 0) {
3287				dstmpte = pmap_allocpte(dst_pmap, addr,
3288				    M_NOWAIT);
3289				if (dstmpte == NULL)
3290					break;
3291				dst_pte = pmap_pte_quick(dst_pmap, addr);
3292				if (*dst_pte == 0 &&
3293				    pmap_try_insert_pv_entry(dst_pmap, addr,
3294				    PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) {
3295					/*
3296					 * Clear the wired, modified, and
3297					 * accessed (referenced) bits
3298					 * during the copy.
3299					 */
3300					KASSERT(ptetemp != 0, ("src_pte not set"));
3301					PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */);
3302					KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)),
3303					    ("no pmap copy expected: 0x%jx saw: 0x%jx",
3304						ptetemp &  ~(PG_W | PG_M | PG_A), *dst_pte));
3305					dst_pmap->pm_stats.resident_count++;
3306	 			} else {
3307					free = NULL;
3308					if (pmap_unwire_pte_hold(dst_pmap,
3309					    dstmpte, &free)) {
3310						pmap_invalidate_page(dst_pmap,
3311						    addr);
3312						pmap_free_zero_pages(free);
3313					}
3314				}
3315				if (dstmpte->wire_count >= srcmpte->wire_count)
3316					break;
3317			}
3318			addr += PAGE_SIZE;
3319			src_pte++;
3320		}
3321	}
3322	PT_UPDATES_FLUSH();
3323	sched_unpin();
3324	vm_page_unlock_queues();
3325	PMAP_UNLOCK(src_pmap);
3326	PMAP_UNLOCK(dst_pmap);
3327}
3328
3329static __inline void
3330pagezero(void *page)
3331{
3332#if defined(I686_CPU)
3333	if (cpu_class == CPUCLASS_686) {
3334#if defined(CPU_ENABLE_SSE)
3335		if (cpu_feature & CPUID_SSE2)
3336			sse2_pagezero(page);
3337		else
3338#endif
3339			i686_pagezero(page);
3340	} else
3341#endif
3342		bzero(page, PAGE_SIZE);
3343}
3344
3345/*
3346 *	pmap_zero_page zeros the specified hardware page by mapping
3347 *	the page into KVM and using bzero to clear its contents.
3348 */
3349void
3350pmap_zero_page(vm_page_t m)
3351{
3352	struct sysmaps *sysmaps;
3353
3354	sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3355	mtx_lock(&sysmaps->lock);
3356	if (*sysmaps->CMAP2)
3357		panic("pmap_zero_page: CMAP2 busy");
3358	sched_pin();
3359	PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M);
3360	pagezero(sysmaps->CADDR2);
3361	PT_SET_MA(sysmaps->CADDR2, 0);
3362	sched_unpin();
3363	mtx_unlock(&sysmaps->lock);
3364}
3365
3366/*
3367 *	pmap_zero_page_area zeros the specified hardware page by mapping
3368 *	the page into KVM and using bzero to clear its contents.
3369 *
3370 *	off and size may not cover an area beyond a single hardware page.
3371 */
3372void
3373pmap_zero_page_area(vm_page_t m, int off, int size)
3374{
3375	struct sysmaps *sysmaps;
3376
3377	sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3378	mtx_lock(&sysmaps->lock);
3379	if (*sysmaps->CMAP2)
3380		panic("pmap_zero_page: CMAP2 busy");
3381	sched_pin();
3382	PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M);
3383
3384	if (off == 0 && size == PAGE_SIZE)
3385		pagezero(sysmaps->CADDR2);
3386	else
3387		bzero((char *)sysmaps->CADDR2 + off, size);
3388	PT_SET_MA(sysmaps->CADDR2, 0);
3389	sched_unpin();
3390	mtx_unlock(&sysmaps->lock);
3391}
3392
3393/*
3394 *	pmap_zero_page_idle zeros the specified hardware page by mapping
3395 *	the page into KVM and using bzero to clear its contents.  This
3396 *	is intended to be called from the vm_pagezero process only and
3397 *	outside of Giant.
3398 */
3399void
3400pmap_zero_page_idle(vm_page_t m)
3401{
3402
3403	if (*CMAP3)
3404		panic("pmap_zero_page: CMAP3 busy");
3405	sched_pin();
3406	PT_SET_MA(CADDR3, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M);
3407	pagezero(CADDR3);
3408	PT_SET_MA(CADDR3, 0);
3409	sched_unpin();
3410}
3411
3412/*
3413 *	pmap_copy_page copies the specified (machine independent)
3414 *	page by mapping the page into virtual memory and using
3415 *	bcopy to copy the page, one machine dependent page at a
3416 *	time.
3417 */
3418void
3419pmap_copy_page(vm_page_t src, vm_page_t dst)
3420{
3421	struct sysmaps *sysmaps;
3422
3423	sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3424	mtx_lock(&sysmaps->lock);
3425	if (*sysmaps->CMAP1)
3426		panic("pmap_copy_page: CMAP1 busy");
3427	if (*sysmaps->CMAP2)
3428		panic("pmap_copy_page: CMAP2 busy");
3429	sched_pin();
3430	PT_SET_MA(sysmaps->CADDR1, PG_V | xpmap_ptom(VM_PAGE_TO_PHYS(src)) | PG_A);
3431	PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(dst)) | PG_A | PG_M);
3432	bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
3433	PT_SET_MA(sysmaps->CADDR1, 0);
3434	PT_SET_MA(sysmaps->CADDR2, 0);
3435	sched_unpin();
3436	mtx_unlock(&sysmaps->lock);
3437}
3438
3439/*
3440 * Returns true if the pmap's pv is one of the first
3441 * 16 pvs linked to from this page.  This count may
3442 * be changed upwards or downwards in the future; it
3443 * is only necessary that true be returned for a small
3444 * subset of pmaps for proper page aging.
3445 */
3446boolean_t
3447pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3448{
3449	pv_entry_t pv;
3450	int loops = 0;
3451	boolean_t rv;
3452
3453	KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
3454	    ("pmap_page_exists_quick: page %p is not managed", m));
3455	rv = FALSE;
3456	vm_page_lock_queues();
3457	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3458		if (PV_PMAP(pv) == pmap) {
3459			rv = TRUE;
3460			break;
3461		}
3462		loops++;
3463		if (loops >= 16)
3464			break;
3465	}
3466	vm_page_unlock_queues();
3467	return (rv);
3468}
3469
3470/*
3471 *	pmap_page_wired_mappings:
3472 *
3473 *	Return the number of managed mappings to the given physical page
3474 *	that are wired.
3475 */
3476int
3477pmap_page_wired_mappings(vm_page_t m)
3478{
3479	pv_entry_t pv;
3480	pt_entry_t *pte;
3481	pmap_t pmap;
3482	int count;
3483
3484	count = 0;
3485	if ((m->flags & PG_FICTITIOUS) != 0)
3486		return (count);
3487	vm_page_lock_queues();
3488	sched_pin();
3489	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3490		pmap = PV_PMAP(pv);
3491		PMAP_LOCK(pmap);
3492		pte = pmap_pte_quick(pmap, pv->pv_va);
3493		if ((*pte & PG_W) != 0)
3494			count++;
3495		PMAP_UNLOCK(pmap);
3496	}
3497	sched_unpin();
3498	vm_page_unlock_queues();
3499	return (count);
3500}
3501
3502/*
3503 * Returns TRUE if the given page is mapped individually or as part of
3504 * a 4mpage.  Otherwise, returns FALSE.
3505 */
3506boolean_t
3507pmap_page_is_mapped(vm_page_t m)
3508{
3509	boolean_t rv;
3510
3511	if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
3512		return (FALSE);
3513	vm_page_lock_queues();
3514	rv = !TAILQ_EMPTY(&m->md.pv_list) ||
3515	    !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list);
3516	vm_page_unlock_queues();
3517	return (rv);
3518}
3519
3520/*
3521 * Remove all pages from specified address space
3522 * this aids process exit speeds.  Also, this code
3523 * is special cased for current process only, but
3524 * can have the more generic (and slightly slower)
3525 * mode enabled.  This is much faster than pmap_remove
3526 * in the case of running down an entire address space.
3527 */
3528void
3529pmap_remove_pages(pmap_t pmap)
3530{
3531	pt_entry_t *pte, tpte;
3532	vm_page_t m, free = NULL;
3533	pv_entry_t pv;
3534	struct pv_chunk *pc, *npc;
3535	int field, idx;
3536	int32_t bit;
3537	uint32_t inuse, bitmask;
3538	int allfree;
3539
3540	CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap);
3541
3542	if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
3543		printf("warning: pmap_remove_pages called with non-current pmap\n");
3544		return;
3545	}
3546	vm_page_lock_queues();
3547	KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap"));
3548	PMAP_LOCK(pmap);
3549	sched_pin();
3550	TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3551		allfree = 1;
3552		for (field = 0; field < _NPCM; field++) {
3553			inuse = (~(pc->pc_map[field])) & pc_freemask[field];
3554			while (inuse != 0) {
3555				bit = bsfl(inuse);
3556				bitmask = 1UL << bit;
3557				idx = field * 32 + bit;
3558				pv = &pc->pc_pventry[idx];
3559				inuse &= ~bitmask;
3560
3561				pte = vtopte(pv->pv_va);
3562				tpte = *pte ? xpmap_mtop(*pte) : 0;
3563
3564				if (tpte == 0) {
3565					printf(
3566					    "TPTE at %p  IS ZERO @ VA %08x\n",
3567					    pte, pv->pv_va);
3568					panic("bad pte");
3569				}
3570
3571/*
3572 * We cannot remove wired pages from a process' mapping at this time
3573 */
3574				if (tpte & PG_W) {
3575					allfree = 0;
3576					continue;
3577				}
3578
3579				m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3580				KASSERT(m->phys_addr == (tpte & PG_FRAME),
3581				    ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3582				    m, (uintmax_t)m->phys_addr,
3583				    (uintmax_t)tpte));
3584
3585				KASSERT(m < &vm_page_array[vm_page_array_size],
3586					("pmap_remove_pages: bad tpte %#jx",
3587					(uintmax_t)tpte));
3588
3589
3590				PT_CLEAR_VA(pte, FALSE);
3591
3592				/*
3593				 * Update the vm_page_t clean/reference bits.
3594				 */
3595				if (tpte & PG_M)
3596					vm_page_dirty(m);
3597
3598				TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3599				if (TAILQ_EMPTY(&m->md.pv_list))
3600					vm_page_flag_clear(m, PG_WRITEABLE);
3601
3602				pmap_unuse_pt(pmap, pv->pv_va, &free);
3603
3604				/* Mark free */
3605				PV_STAT(pv_entry_frees++);
3606				PV_STAT(pv_entry_spare++);
3607				pv_entry_count--;
3608				pc->pc_map[field] |= bitmask;
3609				pmap->pm_stats.resident_count--;
3610			}
3611		}
3612		PT_UPDATES_FLUSH();
3613		if (allfree) {
3614			PV_STAT(pv_entry_spare -= _NPCPV);
3615			PV_STAT(pc_chunk_count--);
3616			PV_STAT(pc_chunk_frees++);
3617			TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3618			m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
3619			pmap_qremove((vm_offset_t)pc, 1);
3620			vm_page_unwire(m, 0);
3621			vm_page_free(m);
3622			pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
3623		}
3624	}
3625	PT_UPDATES_FLUSH();
3626	if (*PMAP1)
3627		PT_SET_MA(PADDR1, 0);
3628
3629	sched_unpin();
3630	pmap_invalidate_all(pmap);
3631	vm_page_unlock_queues();
3632	PMAP_UNLOCK(pmap);
3633	pmap_free_zero_pages(free);
3634}
3635
3636/*
3637 *	pmap_is_modified:
3638 *
3639 *	Return whether or not the specified physical page was modified
3640 *	in any physical maps.
3641 */
3642boolean_t
3643pmap_is_modified(vm_page_t m)
3644{
3645	pv_entry_t pv;
3646	pt_entry_t *pte;
3647	pmap_t pmap;
3648	boolean_t rv;
3649
3650	KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
3651	    ("pmap_is_modified: page %p is not managed", m));
3652	rv = FALSE;
3653
3654	/*
3655	 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be
3656	 * concurrently set while the object is locked.  Thus, if PG_WRITEABLE
3657	 * is clear, no PTEs can have PG_M set.
3658	 */
3659	VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
3660	if ((m->oflags & VPO_BUSY) == 0 &&
3661	    (m->flags & PG_WRITEABLE) == 0)
3662		return (rv);
3663	vm_page_lock_queues();
3664	sched_pin();
3665	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3666		pmap = PV_PMAP(pv);
3667		PMAP_LOCK(pmap);
3668		pte = pmap_pte_quick(pmap, pv->pv_va);
3669		rv = (*pte & PG_M) != 0;
3670		PMAP_UNLOCK(pmap);
3671		if (rv)
3672			break;
3673	}
3674	if (*PMAP1)
3675		PT_SET_MA(PADDR1, 0);
3676	sched_unpin();
3677	vm_page_unlock_queues();
3678	return (rv);
3679}
3680
3681/*
3682 *	pmap_is_prefaultable:
3683 *
3684 *	Return whether or not the specified virtual address is elgible
3685 *	for prefault.
3686 */
3687static boolean_t
3688pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr)
3689{
3690	pt_entry_t *pte;
3691	boolean_t rv = FALSE;
3692
3693	return (rv);
3694
3695	if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) {
3696		pte = vtopte(addr);
3697		rv = (*pte == 0);
3698	}
3699	return (rv);
3700}
3701
3702boolean_t
3703pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3704{
3705	boolean_t rv;
3706
3707	PMAP_LOCK(pmap);
3708	rv = pmap_is_prefaultable_locked(pmap, addr);
3709	PMAP_UNLOCK(pmap);
3710	return (rv);
3711}
3712
3713boolean_t
3714pmap_is_referenced(vm_page_t m)
3715{
3716	pv_entry_t pv;
3717	pt_entry_t *pte;
3718	pmap_t pmap;
3719	boolean_t rv;
3720
3721	KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
3722	    ("pmap_is_referenced: page %p is not managed", m));
3723	rv = FALSE;
3724	vm_page_lock_queues();
3725	sched_pin();
3726	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3727		pmap = PV_PMAP(pv);
3728		PMAP_LOCK(pmap);
3729		pte = pmap_pte_quick(pmap, pv->pv_va);
3730		rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
3731		PMAP_UNLOCK(pmap);
3732		if (rv)
3733			break;
3734	}
3735	if (*PMAP1)
3736		PT_SET_MA(PADDR1, 0);
3737	sched_unpin();
3738	vm_page_unlock_queues();
3739	return (rv);
3740}
3741
3742void
3743pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len)
3744{
3745	int i, npages = round_page(len) >> PAGE_SHIFT;
3746	for (i = 0; i < npages; i++) {
3747		pt_entry_t *pte;
3748		pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE));
3749		pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M)));
3750		PMAP_MARK_PRIV(xpmap_mtop(*pte));
3751		pmap_pte_release(pte);
3752	}
3753}
3754
3755void
3756pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len)
3757{
3758	int i, npages = round_page(len) >> PAGE_SHIFT;
3759	for (i = 0; i < npages; i++) {
3760		pt_entry_t *pte;
3761		pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE));
3762		PMAP_MARK_UNPRIV(xpmap_mtop(*pte));
3763		pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M));
3764		pmap_pte_release(pte);
3765	}
3766}
3767
3768/*
3769 * Clear the write and modified bits in each of the given page's mappings.
3770 */
3771void
3772pmap_remove_write(vm_page_t m)
3773{
3774	pv_entry_t pv;
3775	pmap_t pmap;
3776	pt_entry_t oldpte, *pte;
3777
3778	KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
3779	    ("pmap_remove_write: page %p is not managed", m));
3780
3781	/*
3782	 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by
3783	 * another thread while the object is locked.  Thus, if PG_WRITEABLE
3784	 * is clear, no page table entries need updating.
3785	 */
3786	VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
3787	if ((m->oflags & VPO_BUSY) == 0 &&
3788	    (m->flags & PG_WRITEABLE) == 0)
3789		return;
3790	vm_page_lock_queues();
3791	sched_pin();
3792	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3793		pmap = PV_PMAP(pv);
3794		PMAP_LOCK(pmap);
3795		pte = pmap_pte_quick(pmap, pv->pv_va);
3796retry:
3797		oldpte = *pte;
3798		if ((oldpte & PG_RW) != 0) {
3799			vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M);
3800
3801			/*
3802			 * Regardless of whether a pte is 32 or 64 bits
3803			 * in size, PG_RW and PG_M are among the least
3804			 * significant 32 bits.
3805			 */
3806			PT_SET_VA_MA(pte, newpte, TRUE);
3807			if (*pte != newpte)
3808				goto retry;
3809
3810			if ((oldpte & PG_M) != 0)
3811				vm_page_dirty(m);
3812			pmap_invalidate_page(pmap, pv->pv_va);
3813		}
3814		PMAP_UNLOCK(pmap);
3815	}
3816	vm_page_flag_clear(m, PG_WRITEABLE);
3817	PT_UPDATES_FLUSH();
3818	if (*PMAP1)
3819		PT_SET_MA(PADDR1, 0);
3820	sched_unpin();
3821	vm_page_unlock_queues();
3822}
3823
3824/*
3825 *	pmap_ts_referenced:
3826 *
3827 *	Return a count of reference bits for a page, clearing those bits.
3828 *	It is not necessary for every reference bit to be cleared, but it
3829 *	is necessary that 0 only be returned when there are truly no
3830 *	reference bits set.
3831 *
3832 *	XXX: The exact number of bits to check and clear is a matter that
3833 *	should be tested and standardized at some point in the future for
3834 *	optimal aging of shared pages.
3835 */
3836int
3837pmap_ts_referenced(vm_page_t m)
3838{
3839	pv_entry_t pv, pvf, pvn;
3840	pmap_t pmap;
3841	pt_entry_t *pte;
3842	int rtval = 0;
3843
3844	KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
3845	    ("pmap_ts_referenced: page %p is not managed", m));
3846	vm_page_lock_queues();
3847	sched_pin();
3848	if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3849		pvf = pv;
3850		do {
3851			pvn = TAILQ_NEXT(pv, pv_list);
3852			TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3853			TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3854			pmap = PV_PMAP(pv);
3855			PMAP_LOCK(pmap);
3856			pte = pmap_pte_quick(pmap, pv->pv_va);
3857			if ((*pte & PG_A) != 0) {
3858				PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE);
3859				pmap_invalidate_page(pmap, pv->pv_va);
3860				rtval++;
3861				if (rtval > 4)
3862					pvn = NULL;
3863			}
3864			PMAP_UNLOCK(pmap);
3865		} while ((pv = pvn) != NULL && pv != pvf);
3866	}
3867	PT_UPDATES_FLUSH();
3868	if (*PMAP1)
3869		PT_SET_MA(PADDR1, 0);
3870
3871	sched_unpin();
3872	vm_page_unlock_queues();
3873	return (rtval);
3874}
3875
3876/*
3877 *	Clear the modify bits on the specified physical page.
3878 */
3879void
3880pmap_clear_modify(vm_page_t m)
3881{
3882	pv_entry_t pv;
3883	pmap_t pmap;
3884	pt_entry_t *pte;
3885
3886	KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
3887	    ("pmap_clear_modify: page %p is not managed", m));
3888	VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
3889	KASSERT((m->oflags & VPO_BUSY) == 0,
3890	    ("pmap_clear_modify: page %p is busy", m));
3891
3892	/*
3893	 * If the page is not PG_WRITEABLE, then no PTEs can have PG_M set.
3894	 * If the object containing the page is locked and the page is not
3895	 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set.
3896	 */
3897	if ((m->flags & PG_WRITEABLE) == 0)
3898		return;
3899	vm_page_lock_queues();
3900	sched_pin();
3901	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3902		pmap = PV_PMAP(pv);
3903		PMAP_LOCK(pmap);
3904		pte = pmap_pte_quick(pmap, pv->pv_va);
3905		if ((*pte & PG_M) != 0) {
3906			/*
3907			 * Regardless of whether a pte is 32 or 64 bits
3908			 * in size, PG_M is among the least significant
3909			 * 32 bits.
3910			 */
3911			PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE);
3912			pmap_invalidate_page(pmap, pv->pv_va);
3913		}
3914		PMAP_UNLOCK(pmap);
3915	}
3916	sched_unpin();
3917	vm_page_unlock_queues();
3918}
3919
3920/*
3921 *	pmap_clear_reference:
3922 *
3923 *	Clear the reference bit on the specified physical page.
3924 */
3925void
3926pmap_clear_reference(vm_page_t m)
3927{
3928	pv_entry_t pv;
3929	pmap_t pmap;
3930	pt_entry_t *pte;
3931
3932	KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
3933	    ("pmap_clear_reference: page %p is not managed", m));
3934	vm_page_lock_queues();
3935	sched_pin();
3936	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3937		pmap = PV_PMAP(pv);
3938		PMAP_LOCK(pmap);
3939		pte = pmap_pte_quick(pmap, pv->pv_va);
3940		if ((*pte & PG_A) != 0) {
3941			/*
3942			 * Regardless of whether a pte is 32 or 64 bits
3943			 * in size, PG_A is among the least significant
3944			 * 32 bits.
3945			 */
3946			PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE);
3947			pmap_invalidate_page(pmap, pv->pv_va);
3948		}
3949		PMAP_UNLOCK(pmap);
3950	}
3951	sched_unpin();
3952	vm_page_unlock_queues();
3953}
3954
3955/*
3956 * Miscellaneous support routines follow
3957 */
3958
3959/*
3960 * Map a set of physical memory pages into the kernel virtual
3961 * address space. Return a pointer to where it is mapped. This
3962 * routine is intended to be used for mapping device memory,
3963 * NOT real memory.
3964 */
3965void *
3966pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
3967{
3968	vm_offset_t va, offset;
3969	vm_size_t tmpsize;
3970
3971	offset = pa & PAGE_MASK;
3972	size = roundup(offset + size, PAGE_SIZE);
3973	pa = pa & PG_FRAME;
3974
3975	if (pa < KERNLOAD && pa + size <= KERNLOAD)
3976		va = KERNBASE + pa;
3977	else
3978		va = kmem_alloc_nofault(kernel_map, size);
3979	if (!va)
3980		panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3981
3982	for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
3983		pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
3984	pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
3985	pmap_invalidate_cache_range(va, va + size);
3986	return ((void *)(va + offset));
3987}
3988
3989void *
3990pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3991{
3992
3993	return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
3994}
3995
3996void *
3997pmap_mapbios(vm_paddr_t pa, vm_size_t size)
3998{
3999
4000	return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
4001}
4002
4003void
4004pmap_unmapdev(vm_offset_t va, vm_size_t size)
4005{
4006	vm_offset_t base, offset, tmpva;
4007
4008	if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
4009		return;
4010	base = trunc_page(va);
4011	offset = va & PAGE_MASK;
4012	size = roundup(offset + size, PAGE_SIZE);
4013	critical_enter();
4014	for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE)
4015		pmap_kremove(tmpva);
4016	pmap_invalidate_range(kernel_pmap, va, tmpva);
4017	critical_exit();
4018	kmem_free(kernel_map, base, size);
4019}
4020
4021/*
4022 * Sets the memory attribute for the specified page.
4023 */
4024void
4025pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4026{
4027	struct sysmaps *sysmaps;
4028	vm_offset_t sva, eva;
4029
4030	m->md.pat_mode = ma;
4031	if ((m->flags & PG_FICTITIOUS) != 0)
4032		return;
4033
4034	/*
4035	 * If "m" is a normal page, flush it from the cache.
4036	 * See pmap_invalidate_cache_range().
4037	 *
4038	 * First, try to find an existing mapping of the page by sf
4039	 * buffer. sf_buf_invalidate_cache() modifies mapping and
4040	 * flushes the cache.
4041	 */
4042	if (sf_buf_invalidate_cache(m))
4043		return;
4044
4045	/*
4046	 * If page is not mapped by sf buffer, but CPU does not
4047	 * support self snoop, map the page transient and do
4048	 * invalidation. In the worst case, whole cache is flushed by
4049	 * pmap_invalidate_cache_range().
4050	 */
4051	if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) {
4052		sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4053		mtx_lock(&sysmaps->lock);
4054		if (*sysmaps->CMAP2)
4055			panic("pmap_page_set_memattr: CMAP2 busy");
4056		sched_pin();
4057		PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW |
4058		    xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M |
4059		    pmap_cache_bits(m->md.pat_mode, 0));
4060		invlcaddr(sysmaps->CADDR2);
4061		sva = (vm_offset_t)sysmaps->CADDR2;
4062		eva = sva + PAGE_SIZE;
4063	} else
4064		sva = eva = 0; /* gcc */
4065	pmap_invalidate_cache_range(sva, eva);
4066	if (sva != 0) {
4067		PT_SET_MA(sysmaps->CADDR2, 0);
4068		sched_unpin();
4069		mtx_unlock(&sysmaps->lock);
4070	}
4071}
4072
4073int
4074pmap_change_attr(va, size, mode)
4075	vm_offset_t va;
4076	vm_size_t size;
4077	int mode;
4078{
4079	vm_offset_t base, offset, tmpva;
4080	pt_entry_t *pte;
4081	u_int opte, npte;
4082	pd_entry_t *pde;
4083	boolean_t changed;
4084
4085	base = trunc_page(va);
4086	offset = va & PAGE_MASK;
4087	size = roundup(offset + size, PAGE_SIZE);
4088
4089	/* Only supported on kernel virtual addresses. */
4090	if (base <= VM_MAXUSER_ADDRESS)
4091		return (EINVAL);
4092
4093	/* 4MB pages and pages that aren't mapped aren't supported. */
4094	for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) {
4095		pde = pmap_pde(kernel_pmap, tmpva);
4096		if (*pde & PG_PS)
4097			return (EINVAL);
4098		if ((*pde & PG_V) == 0)
4099			return (EINVAL);
4100		pte = vtopte(va);
4101		if ((*pte & PG_V) == 0)
4102			return (EINVAL);
4103	}
4104
4105	changed = FALSE;
4106
4107	/*
4108	 * Ok, all the pages exist and are 4k, so run through them updating
4109	 * their cache mode.
4110	 */
4111	for (tmpva = base; size > 0; ) {
4112		pte = vtopte(tmpva);
4113
4114		/*
4115		 * The cache mode bits are all in the low 32-bits of the
4116		 * PTE, so we can just spin on updating the low 32-bits.
4117		 */
4118		do {
4119			opte = *(u_int *)pte;
4120			npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT);
4121			npte |= pmap_cache_bits(mode, 0);
4122			PT_SET_VA_MA(pte, npte, TRUE);
4123		} while (npte != opte && (*pte != npte));
4124		if (npte != opte)
4125			changed = TRUE;
4126		tmpva += PAGE_SIZE;
4127		size -= PAGE_SIZE;
4128	}
4129
4130	/*
4131	 * Flush CPU caches to make sure any data isn't cached that shouldn't
4132	 * be, etc.
4133	 */
4134	if (changed) {
4135		pmap_invalidate_range(kernel_pmap, base, tmpva);
4136		pmap_invalidate_cache_range(base, tmpva);
4137	}
4138	return (0);
4139}
4140
4141/*
4142 * perform the pmap work for mincore
4143 */
4144int
4145pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4146{
4147	pt_entry_t *ptep, pte;
4148	vm_paddr_t pa;
4149	int val;
4150
4151	PMAP_LOCK(pmap);
4152retry:
4153	ptep = pmap_pte(pmap, addr);
4154	pte = (ptep != NULL) ? PT_GET(ptep) : 0;
4155	pmap_pte_release(ptep);
4156	val = 0;
4157	if ((pte & PG_V) != 0) {
4158		val |= MINCORE_INCORE;
4159		if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4160			val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4161		if ((pte & PG_A) != 0)
4162			val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4163	}
4164	if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4165	    (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
4166	    (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
4167		pa = pte & PG_FRAME;
4168		/* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4169		if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4170			goto retry;
4171	} else
4172		PA_UNLOCK_COND(*locked_pa);
4173	PMAP_UNLOCK(pmap);
4174	return (val);
4175}
4176
4177void
4178pmap_activate(struct thread *td)
4179{
4180	pmap_t	pmap, oldpmap;
4181	u_int32_t  cr3;
4182
4183	critical_enter();
4184	pmap = vmspace_pmap(td->td_proc->p_vmspace);
4185	oldpmap = PCPU_GET(curpmap);
4186#if defined(SMP)
4187	atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask));
4188	atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask));
4189#else
4190	oldpmap->pm_active &= ~1;
4191	pmap->pm_active |= 1;
4192#endif
4193#ifdef PAE
4194	cr3 = vtophys(pmap->pm_pdpt);
4195#else
4196	cr3 = vtophys(pmap->pm_pdir);
4197#endif
4198	/*
4199	 * pmap_activate is for the current thread on the current cpu
4200	 */
4201	td->td_pcb->pcb_cr3 = cr3;
4202	PT_UPDATES_FLUSH();
4203	load_cr3(cr3);
4204	PCPU_SET(curpmap, pmap);
4205	critical_exit();
4206}
4207
4208void
4209pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4210{
4211}
4212
4213/*
4214 *	Increase the starting virtual address of the given mapping if a
4215 *	different alignment might result in more superpage mappings.
4216 */
4217void
4218pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4219    vm_offset_t *addr, vm_size_t size)
4220{
4221	vm_offset_t superpage_offset;
4222
4223	if (size < NBPDR)
4224		return;
4225	if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4226		offset += ptoa(object->pg_color);
4227	superpage_offset = offset & PDRMASK;
4228	if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
4229	    (*addr & PDRMASK) == superpage_offset)
4230		return;
4231	if ((*addr & PDRMASK) < superpage_offset)
4232		*addr = (*addr & ~PDRMASK) + superpage_offset;
4233	else
4234		*addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
4235}
4236
4237#ifdef XEN
4238
4239void
4240pmap_suspend()
4241{
4242	pmap_t pmap;
4243	int i, pdir, offset;
4244	vm_paddr_t pdirma;
4245	mmu_update_t mu[4];
4246
4247	/*
4248	 * We need to remove the recursive mapping structure from all
4249	 * our pmaps so that Xen doesn't get confused when it restores
4250	 * the page tables. The recursive map lives at page directory
4251	 * index PTDPTDI. We assume that the suspend code has stopped
4252	 * the other vcpus (if any).
4253	 */
4254	LIST_FOREACH(pmap, &allpmaps, pm_list) {
4255		for (i = 0; i < 4; i++) {
4256			/*
4257			 * Figure out which page directory (L2) page
4258			 * contains this bit of the recursive map and
4259			 * the offset within that page of the map
4260			 * entry
4261			 */
4262			pdir = (PTDPTDI + i) / NPDEPG;
4263			offset = (PTDPTDI + i) % NPDEPG;
4264			pdirma = pmap->pm_pdpt[pdir] & PG_FRAME;
4265			mu[i].ptr = pdirma + offset * sizeof(pd_entry_t);
4266			mu[i].val = 0;
4267		}
4268		HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF);
4269	}
4270}
4271
4272void
4273pmap_resume()
4274{
4275	pmap_t pmap;
4276	int i, pdir, offset;
4277	vm_paddr_t pdirma;
4278	mmu_update_t mu[4];
4279
4280	/*
4281	 * Restore the recursive map that we removed on suspend.
4282	 */
4283	LIST_FOREACH(pmap, &allpmaps, pm_list) {
4284		for (i = 0; i < 4; i++) {
4285			/*
4286			 * Figure out which page directory (L2) page
4287			 * contains this bit of the recursive map and
4288			 * the offset within that page of the map
4289			 * entry
4290			 */
4291			pdir = (PTDPTDI + i) / NPDEPG;
4292			offset = (PTDPTDI + i) % NPDEPG;
4293			pdirma = pmap->pm_pdpt[pdir] & PG_FRAME;
4294			mu[i].ptr = pdirma + offset * sizeof(pd_entry_t);
4295			mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V;
4296		}
4297		HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF);
4298	}
4299}
4300
4301#endif
4302
4303#if defined(PMAP_DEBUG)
4304pmap_pid_dump(int pid)
4305{
4306	pmap_t pmap;
4307	struct proc *p;
4308	int npte = 0;
4309	int index;
4310
4311	sx_slock(&allproc_lock);
4312	FOREACH_PROC_IN_SYSTEM(p) {
4313		if (p->p_pid != pid)
4314			continue;
4315
4316		if (p->p_vmspace) {
4317			int i,j;
4318			index = 0;
4319			pmap = vmspace_pmap(p->p_vmspace);
4320			for (i = 0; i < NPDEPTD; i++) {
4321				pd_entry_t *pde;
4322				pt_entry_t *pte;
4323				vm_offset_t base = i << PDRSHIFT;
4324
4325				pde = &pmap->pm_pdir[i];
4326				if (pde && pmap_pde_v(pde)) {
4327					for (j = 0; j < NPTEPG; j++) {
4328						vm_offset_t va = base + (j << PAGE_SHIFT);
4329						if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
4330							if (index) {
4331								index = 0;
4332								printf("\n");
4333							}
4334							sx_sunlock(&allproc_lock);
4335							return npte;
4336						}
4337						pte = pmap_pte(pmap, va);
4338						if (pte && pmap_pte_v(pte)) {
4339							pt_entry_t pa;
4340							vm_page_t m;
4341							pa = PT_GET(pte);
4342							m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
4343							printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
4344								va, pa, m->hold_count, m->wire_count, m->flags);
4345							npte++;
4346							index++;
4347							if (index >= 2) {
4348								index = 0;
4349								printf("\n");
4350							} else {
4351								printf(" ");
4352							}
4353						}
4354					}
4355				}
4356			}
4357		}
4358	}
4359	sx_sunlock(&allproc_lock);
4360	return npte;
4361}
4362#endif
4363
4364#if defined(DEBUG)
4365
4366static void	pads(pmap_t pm);
4367void		pmap_pvdump(vm_paddr_t pa);
4368
4369/* print address space of pmap*/
4370static void
4371pads(pmap_t pm)
4372{
4373	int i, j;
4374	vm_paddr_t va;
4375	pt_entry_t *ptep;
4376
4377	if (pm == kernel_pmap)
4378		return;
4379	for (i = 0; i < NPDEPTD; i++)
4380		if (pm->pm_pdir[i])
4381			for (j = 0; j < NPTEPG; j++) {
4382				va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
4383				if (pm == kernel_pmap && va < KERNBASE)
4384					continue;
4385				if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
4386					continue;
4387				ptep = pmap_pte(pm, va);
4388				if (pmap_pte_v(ptep))
4389					printf("%x:%x ", va, *ptep);
4390			};
4391
4392}
4393
4394void
4395pmap_pvdump(vm_paddr_t pa)
4396{
4397	pv_entry_t pv;
4398	pmap_t pmap;
4399	vm_page_t m;
4400
4401	printf("pa %x", pa);
4402	m = PHYS_TO_VM_PAGE(pa);
4403	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4404		pmap = PV_PMAP(pv);
4405		printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);
4406		pads(pmap);
4407	}
4408	printf(" ");
4409}
4410#endif
4411