pmap.c revision 177525
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 177525 2008-03-23 07:07:27Z kib $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/lock.h> 116#include <sys/malloc.h> 117#include <sys/mman.h> 118#include <sys/msgbuf.h> 119#include <sys/mutex.h> 120#include <sys/proc.h> 121#include <sys/sx.h> 122#include <sys/vmmeter.h> 123#include <sys/sched.h> 124#include <sys/sysctl.h> 125#ifdef SMP 126#include <sys/smp.h> 127#endif 128 129#include <vm/vm.h> 130#include <vm/vm_param.h> 131#include <vm/vm_kern.h> 132#include <vm/vm_page.h> 133#include <vm/vm_map.h> 134#include <vm/vm_object.h> 135#include <vm/vm_extern.h> 136#include <vm/vm_pageout.h> 137#include <vm/vm_pager.h> 138#include <vm/uma.h> 139 140#include <machine/cpu.h> 141#include <machine/cputypes.h> 142#include <machine/md_var.h> 143#include <machine/pcb.h> 144#include <machine/specialreg.h> 145#ifdef SMP 146#include <machine/smp.h> 147#endif 148 149#ifdef XBOX 150#include <machine/xbox.h> 151#endif 152 153#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 154#define CPU_ENABLE_SSE 155#endif 156 157#ifndef PMAP_SHPGPERPROC 158#define PMAP_SHPGPERPROC 200 159#endif 160 161#if !defined(DIAGNOSTIC) 162#define PMAP_INLINE __gnu89_inline 163#else 164#define PMAP_INLINE 165#endif 166 167#define PV_STATS 168#ifdef PV_STATS 169#define PV_STAT(x) do { x ; } while (0) 170#else 171#define PV_STAT(x) do { } while (0) 172#endif 173 174/* 175 * Get PDEs and PTEs for user/kernel address space 176 */ 177#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 178#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 179 180#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 181#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 182#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 183#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 184#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 185 186#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 187 atomic_clear_int((u_int *)(pte), PG_W)) 188#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 189 190struct pmap kernel_pmap_store; 191LIST_HEAD(pmaplist, pmap); 192static struct pmaplist allpmaps; 193static struct mtx allpmaps_lock; 194 195vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 196vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 197int pgeflag = 0; /* PG_G or-in */ 198int pseflag = 0; /* PG_PS or-in */ 199 200static int nkpt; 201vm_offset_t kernel_vm_end; 202extern u_int32_t KERNend; 203 204#ifdef PAE 205pt_entry_t pg_nx; 206static uma_zone_t pdptzone; 207#endif 208 209/* 210 * Data for the pv entry allocation mechanism 211 */ 212static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 213static int shpgperproc = PMAP_SHPGPERPROC; 214 215struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 216int pv_maxchunks; /* How many chunks we have KVA for */ 217vm_offset_t pv_vafree; /* freelist stored in the PTE */ 218 219/* 220 * All those kernel PT submaps that BSD is so fond of 221 */ 222struct sysmaps { 223 struct mtx lock; 224 pt_entry_t *CMAP1; 225 pt_entry_t *CMAP2; 226 caddr_t CADDR1; 227 caddr_t CADDR2; 228}; 229static struct sysmaps sysmaps_pcpu[MAXCPU]; 230pt_entry_t *CMAP1 = 0; 231static pt_entry_t *CMAP3; 232caddr_t CADDR1 = 0, ptvmmap = 0; 233static caddr_t CADDR3; 234struct msgbuf *msgbufp = 0; 235 236/* 237 * Crashdump maps. 238 */ 239static caddr_t crashdumpmap; 240 241static pt_entry_t *PMAP1 = 0, *PMAP2; 242static pt_entry_t *PADDR1 = 0, *PADDR2; 243#ifdef SMP 244static int PMAP1cpu; 245static int PMAP1changedcpu; 246SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 247 &PMAP1changedcpu, 0, 248 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 249#endif 250static int PMAP1changed; 251SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 252 &PMAP1changed, 0, 253 "Number of times pmap_pte_quick changed PMAP1"); 254static int PMAP1unchanged; 255SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 256 &PMAP1unchanged, 0, 257 "Number of times pmap_pte_quick didn't change PMAP1"); 258static struct mtx PMAP2mutex; 259 260static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 261static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 262 263static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 264 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 265static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 266 vm_page_t *free); 267static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 268 vm_page_t *free); 269static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 270 vm_offset_t va); 271static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 272static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 273 vm_page_t m); 274 275static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 276 277static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 278static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 279static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 280static void pmap_pte_release(pt_entry_t *pte); 281static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 282static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 283#ifdef PAE 284static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 285#endif 286 287CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 288CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 289 290/* 291 * If you get an error here, then you set KVA_PAGES wrong! See the 292 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 293 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 294 */ 295CTASSERT(KERNBASE % (1 << 24) == 0); 296 297/* 298 * Move the kernel virtual free pointer to the next 299 * 4MB. This is used to help improve performance 300 * by using a large (4MB) page for much of the kernel 301 * (.text, .data, .bss) 302 */ 303static vm_offset_t 304pmap_kmem_choose(vm_offset_t addr) 305{ 306 vm_offset_t newaddr = addr; 307 308#ifndef DISABLE_PSE 309 if (cpu_feature & CPUID_PSE) 310 newaddr = (addr + PDRMASK) & ~PDRMASK; 311#endif 312 return newaddr; 313} 314 315/* 316 * Bootstrap the system enough to run with virtual memory. 317 * 318 * On the i386 this is called after mapping has already been enabled 319 * and just syncs the pmap module with what has already been done. 320 * [We can't call it easily with mapping off since the kernel is not 321 * mapped with PA == VA, hence we would have to relocate every address 322 * from the linked base (virtual) address "KERNBASE" to the actual 323 * (physical) address starting relative to 0] 324 */ 325void 326pmap_bootstrap(vm_paddr_t firstaddr) 327{ 328 vm_offset_t va; 329 pt_entry_t *pte, *unused; 330 struct sysmaps *sysmaps; 331 int i; 332 333 /* 334 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 335 * large. It should instead be correctly calculated in locore.s and 336 * not based on 'first' (which is a physical address, not a virtual 337 * address, for the start of unused physical memory). The kernel 338 * page tables are NOT double mapped and thus should not be included 339 * in this calculation. 340 */ 341 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 342 virtual_avail = pmap_kmem_choose(virtual_avail); 343 344 virtual_end = VM_MAX_KERNEL_ADDRESS; 345 346 /* 347 * Initialize the kernel pmap (which is statically allocated). 348 */ 349 PMAP_LOCK_INIT(kernel_pmap); 350 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 351#ifdef PAE 352 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 353#endif 354 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 355 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 356 LIST_INIT(&allpmaps); 357 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 358 mtx_lock_spin(&allpmaps_lock); 359 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 360 mtx_unlock_spin(&allpmaps_lock); 361 nkpt = NKPT; 362 363 /* 364 * Reserve some special page table entries/VA space for temporary 365 * mapping of pages. 366 */ 367#define SYSMAP(c, p, v, n) \ 368 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 369 370 va = virtual_avail; 371 pte = vtopte(va); 372 373 /* 374 * CMAP1/CMAP2 are used for zeroing and copying pages. 375 * CMAP3 is used for the idle process page zeroing. 376 */ 377 for (i = 0; i < MAXCPU; i++) { 378 sysmaps = &sysmaps_pcpu[i]; 379 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 380 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 381 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 382 } 383 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 384 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 385 *CMAP3 = 0; 386 387 /* 388 * Crashdump maps. 389 */ 390 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 391 392 /* 393 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 394 */ 395 SYSMAP(caddr_t, unused, ptvmmap, 1) 396 397 /* 398 * msgbufp is used to map the system message buffer. 399 */ 400 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 401 402 /* 403 * ptemap is used for pmap_pte_quick 404 */ 405 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 406 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 407 408 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 409 410 virtual_avail = va; 411 412 *CMAP1 = 0; 413 414 /* 415 * Leave in place an identity mapping (virt == phys) for the low 1 MB 416 * physical memory region that is used by the ACPI wakeup code. This 417 * mapping must not have PG_G set. 418 */ 419#ifdef XBOX 420 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 421 * an early stadium, we cannot yet neatly map video memory ... :-( 422 * Better fixes are very welcome! */ 423 if (!arch_i386_is_xbox) 424#endif 425 for (i = 1; i < NKPT; i++) 426 PTD[i] = 0; 427 428 /* Initialize the PAT MSR if present. */ 429 pmap_init_pat(); 430 431 /* Turn on PG_G on kernel page(s) */ 432 pmap_set_pg(); 433} 434 435/* 436 * Setup the PAT MSR. 437 */ 438void 439pmap_init_pat(void) 440{ 441 uint64_t pat_msr; 442 443 /* Bail if this CPU doesn't implement PAT. */ 444 if (!(cpu_feature & CPUID_PAT)) 445 return; 446 447#ifdef PAT_WORKS 448 /* 449 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 450 * Program 4 and 5 as WP and WC. 451 * Leave 6 and 7 as UC and UC-. 452 */ 453 pat_msr = rdmsr(MSR_PAT); 454 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 455 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 456 PAT_VALUE(5, PAT_WRITE_COMBINING); 457#else 458 /* 459 * Due to some Intel errata, we can only safely use the lower 4 460 * PAT entries. Thus, just replace PAT Index 2 with WC instead 461 * of UC-. 462 * 463 * Intel Pentium III Processor Specification Update 464 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 465 * or Mode C Paging) 466 * 467 * Intel Pentium IV Processor Specification Update 468 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 469 */ 470 pat_msr = rdmsr(MSR_PAT); 471 pat_msr &= ~PAT_MASK(2); 472 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 473#endif 474 wrmsr(MSR_PAT, pat_msr); 475} 476 477/* 478 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 479 */ 480void 481pmap_set_pg(void) 482{ 483 pd_entry_t pdir; 484 pt_entry_t *pte; 485 vm_offset_t va, endva; 486 int i; 487 488 if (pgeflag == 0) 489 return; 490 491 i = KERNLOAD/NBPDR; 492 endva = KERNBASE + KERNend; 493 494 if (pseflag) { 495 va = KERNBASE + KERNLOAD; 496 while (va < endva) { 497 pdir = kernel_pmap->pm_pdir[KPTDI+i]; 498 pdir |= pgeflag; 499 kernel_pmap->pm_pdir[KPTDI+i] = PTD[KPTDI+i] = pdir; 500 invltlb(); /* Play it safe, invltlb() every time */ 501 i++; 502 va += NBPDR; 503 } 504 } else { 505 va = (vm_offset_t)btext; 506 while (va < endva) { 507 pte = vtopte(va); 508 if (*pte) 509 *pte |= pgeflag; 510 invltlb(); /* Play it safe, invltlb() every time */ 511 va += PAGE_SIZE; 512 } 513 } 514} 515 516/* 517 * Initialize a vm_page's machine-dependent fields. 518 */ 519void 520pmap_page_init(vm_page_t m) 521{ 522 523 TAILQ_INIT(&m->md.pv_list); 524} 525 526#ifdef PAE 527 528static MALLOC_DEFINE(M_PMAPPDPT, "pmap", "pmap pdpt"); 529 530static void * 531pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 532{ 533 *flags = UMA_SLAB_PRIV; 534 return (contigmalloc(PAGE_SIZE, M_PMAPPDPT, 0, 0x0ULL, 0xffffffffULL, 535 1, 0)); 536} 537#endif 538 539/* 540 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 541 * Requirements: 542 * - Must deal with pages in order to ensure that none of the PG_* bits 543 * are ever set, PG_V in particular. 544 * - Assumes we can write to ptes without pte_store() atomic ops, even 545 * on PAE systems. This should be ok. 546 * - Assumes nothing will ever test these addresses for 0 to indicate 547 * no mapping instead of correctly checking PG_V. 548 * - Assumes a vm_offset_t will fit in a pte (true for i386). 549 * Because PG_V is never set, there can be no mappings to invalidate. 550 */ 551static vm_offset_t 552pmap_ptelist_alloc(vm_offset_t *head) 553{ 554 pt_entry_t *pte; 555 vm_offset_t va; 556 557 va = *head; 558 if (va == 0) 559 return (va); /* Out of memory */ 560 pte = vtopte(va); 561 *head = *pte; 562 if (*head & PG_V) 563 panic("pmap_ptelist_alloc: va with PG_V set!"); 564 *pte = 0; 565 return (va); 566} 567 568static void 569pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 570{ 571 pt_entry_t *pte; 572 573 if (va & PG_V) 574 panic("pmap_ptelist_free: freeing va with PG_V set!"); 575 pte = vtopte(va); 576 *pte = *head; /* virtual! PG_V is 0 though */ 577 *head = va; 578} 579 580static void 581pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 582{ 583 int i; 584 vm_offset_t va; 585 586 *head = 0; 587 for (i = npages - 1; i >= 0; i--) { 588 va = (vm_offset_t)base + i * PAGE_SIZE; 589 pmap_ptelist_free(head, va); 590 } 591} 592 593 594/* 595 * Initialize the pmap module. 596 * Called by vm_init, to initialize any structures that the pmap 597 * system needs to map virtual memory. 598 */ 599void 600pmap_init(void) 601{ 602 603 /* 604 * Initialize the address space (zone) for the pv entries. Set a 605 * high water mark so that the system can recover from excessive 606 * numbers of pv entries. 607 */ 608 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 609 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 610 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 611 pv_entry_max = roundup(pv_entry_max, _NPCPV); 612 pv_entry_high_water = 9 * (pv_entry_max / 10); 613 614 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 615 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 616 PAGE_SIZE * pv_maxchunks); 617 if (pv_chunkbase == NULL) 618 panic("pmap_init: not enough kvm for pv chunks"); 619 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 620#ifdef PAE 621 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 622 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 623 UMA_ZONE_VM | UMA_ZONE_NOFREE); 624 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 625#endif 626} 627 628 629SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 630SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 631 "Max number of PV entries"); 632SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 633 "Page share factor per proc"); 634 635/*************************************************** 636 * Low level helper routines..... 637 ***************************************************/ 638 639/* 640 * Determine the appropriate bits to set in a PTE or PDE for a specified 641 * caching mode. 642 */ 643static int 644pmap_cache_bits(int mode, boolean_t is_pde) 645{ 646 int pat_flag, pat_index, cache_bits; 647 648 /* The PAT bit is different for PTE's and PDE's. */ 649 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 650 651 /* If we don't support PAT, map extended modes to older ones. */ 652 if (!(cpu_feature & CPUID_PAT)) { 653 switch (mode) { 654 case PAT_UNCACHEABLE: 655 case PAT_WRITE_THROUGH: 656 case PAT_WRITE_BACK: 657 break; 658 case PAT_UNCACHED: 659 case PAT_WRITE_COMBINING: 660 case PAT_WRITE_PROTECTED: 661 mode = PAT_UNCACHEABLE; 662 break; 663 } 664 } 665 666 /* Map the caching mode to a PAT index. */ 667 switch (mode) { 668#ifdef PAT_WORKS 669 case PAT_UNCACHEABLE: 670 pat_index = 3; 671 break; 672 case PAT_WRITE_THROUGH: 673 pat_index = 1; 674 break; 675 case PAT_WRITE_BACK: 676 pat_index = 0; 677 break; 678 case PAT_UNCACHED: 679 pat_index = 2; 680 break; 681 case PAT_WRITE_COMBINING: 682 pat_index = 5; 683 break; 684 case PAT_WRITE_PROTECTED: 685 pat_index = 4; 686 break; 687#else 688 case PAT_UNCACHED: 689 case PAT_UNCACHEABLE: 690 case PAT_WRITE_PROTECTED: 691 pat_index = 3; 692 break; 693 case PAT_WRITE_THROUGH: 694 pat_index = 1; 695 break; 696 case PAT_WRITE_BACK: 697 pat_index = 0; 698 break; 699 case PAT_WRITE_COMBINING: 700 pat_index = 2; 701 break; 702#endif 703 default: 704 panic("Unknown caching mode %d\n", mode); 705 } 706 707 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 708 cache_bits = 0; 709 if (pat_index & 0x4) 710 cache_bits |= pat_flag; 711 if (pat_index & 0x2) 712 cache_bits |= PG_NC_PCD; 713 if (pat_index & 0x1) 714 cache_bits |= PG_NC_PWT; 715 return (cache_bits); 716} 717#ifdef SMP 718/* 719 * For SMP, these functions have to use the IPI mechanism for coherence. 720 * 721 * N.B.: Before calling any of the following TLB invalidation functions, 722 * the calling processor must ensure that all stores updating a non- 723 * kernel page table are globally performed. Otherwise, another 724 * processor could cache an old, pre-update entry without being 725 * invalidated. This can happen one of two ways: (1) The pmap becomes 726 * active on another processor after its pm_active field is checked by 727 * one of the following functions but before a store updating the page 728 * table is globally performed. (2) The pmap becomes active on another 729 * processor before its pm_active field is checked but due to 730 * speculative loads one of the following functions stills reads the 731 * pmap as inactive on the other processor. 732 * 733 * The kernel page table is exempt because its pm_active field is 734 * immutable. The kernel page table is always active on every 735 * processor. 736 */ 737void 738pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 739{ 740 u_int cpumask; 741 u_int other_cpus; 742 743 sched_pin(); 744 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 745 invlpg(va); 746 smp_invlpg(va); 747 } else { 748 cpumask = PCPU_GET(cpumask); 749 other_cpus = PCPU_GET(other_cpus); 750 if (pmap->pm_active & cpumask) 751 invlpg(va); 752 if (pmap->pm_active & other_cpus) 753 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 754 } 755 sched_unpin(); 756} 757 758void 759pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 760{ 761 u_int cpumask; 762 u_int other_cpus; 763 vm_offset_t addr; 764 765 sched_pin(); 766 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 767 for (addr = sva; addr < eva; addr += PAGE_SIZE) 768 invlpg(addr); 769 smp_invlpg_range(sva, eva); 770 } else { 771 cpumask = PCPU_GET(cpumask); 772 other_cpus = PCPU_GET(other_cpus); 773 if (pmap->pm_active & cpumask) 774 for (addr = sva; addr < eva; addr += PAGE_SIZE) 775 invlpg(addr); 776 if (pmap->pm_active & other_cpus) 777 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 778 sva, eva); 779 } 780 sched_unpin(); 781} 782 783void 784pmap_invalidate_all(pmap_t pmap) 785{ 786 u_int cpumask; 787 u_int other_cpus; 788 789 sched_pin(); 790 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 791 invltlb(); 792 smp_invltlb(); 793 } else { 794 cpumask = PCPU_GET(cpumask); 795 other_cpus = PCPU_GET(other_cpus); 796 if (pmap->pm_active & cpumask) 797 invltlb(); 798 if (pmap->pm_active & other_cpus) 799 smp_masked_invltlb(pmap->pm_active & other_cpus); 800 } 801 sched_unpin(); 802} 803 804void 805pmap_invalidate_cache(void) 806{ 807 808 sched_pin(); 809 wbinvd(); 810 smp_cache_flush(); 811 sched_unpin(); 812} 813#else /* !SMP */ 814/* 815 * Normal, non-SMP, 486+ invalidation functions. 816 * We inline these within pmap.c for speed. 817 */ 818PMAP_INLINE void 819pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 820{ 821 822 if (pmap == kernel_pmap || pmap->pm_active) 823 invlpg(va); 824} 825 826PMAP_INLINE void 827pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 828{ 829 vm_offset_t addr; 830 831 if (pmap == kernel_pmap || pmap->pm_active) 832 for (addr = sva; addr < eva; addr += PAGE_SIZE) 833 invlpg(addr); 834} 835 836PMAP_INLINE void 837pmap_invalidate_all(pmap_t pmap) 838{ 839 840 if (pmap == kernel_pmap || pmap->pm_active) 841 invltlb(); 842} 843 844PMAP_INLINE void 845pmap_invalidate_cache(void) 846{ 847 848 wbinvd(); 849} 850#endif /* !SMP */ 851 852/* 853 * Are we current address space or kernel? N.B. We return FALSE when 854 * a pmap's page table is in use because a kernel thread is borrowing 855 * it. The borrowed page table can change spontaneously, making any 856 * dependence on its continued use subject to a race condition. 857 */ 858static __inline int 859pmap_is_current(pmap_t pmap) 860{ 861 862 return (pmap == kernel_pmap || 863 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 864 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 865} 866 867/* 868 * If the given pmap is not the current or kernel pmap, the returned pte must 869 * be released by passing it to pmap_pte_release(). 870 */ 871pt_entry_t * 872pmap_pte(pmap_t pmap, vm_offset_t va) 873{ 874 pd_entry_t newpf; 875 pd_entry_t *pde; 876 877 pde = pmap_pde(pmap, va); 878 if (*pde & PG_PS) 879 return (pde); 880 if (*pde != 0) { 881 /* are we current address space or kernel? */ 882 if (pmap_is_current(pmap)) 883 return (vtopte(va)); 884 mtx_lock(&PMAP2mutex); 885 newpf = *pde & PG_FRAME; 886 if ((*PMAP2 & PG_FRAME) != newpf) { 887 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 888 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 889 } 890 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 891 } 892 return (0); 893} 894 895/* 896 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 897 * being NULL. 898 */ 899static __inline void 900pmap_pte_release(pt_entry_t *pte) 901{ 902 903 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 904 mtx_unlock(&PMAP2mutex); 905} 906 907static __inline void 908invlcaddr(void *caddr) 909{ 910 911 invlpg((u_int)caddr); 912} 913 914/* 915 * Super fast pmap_pte routine best used when scanning 916 * the pv lists. This eliminates many coarse-grained 917 * invltlb calls. Note that many of the pv list 918 * scans are across different pmaps. It is very wasteful 919 * to do an entire invltlb for checking a single mapping. 920 * 921 * If the given pmap is not the current pmap, vm_page_queue_mtx 922 * must be held and curthread pinned to a CPU. 923 */ 924static pt_entry_t * 925pmap_pte_quick(pmap_t pmap, vm_offset_t va) 926{ 927 pd_entry_t newpf; 928 pd_entry_t *pde; 929 930 pde = pmap_pde(pmap, va); 931 if (*pde & PG_PS) 932 return (pde); 933 if (*pde != 0) { 934 /* are we current address space or kernel? */ 935 if (pmap_is_current(pmap)) 936 return (vtopte(va)); 937 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 938 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 939 newpf = *pde & PG_FRAME; 940 if ((*PMAP1 & PG_FRAME) != newpf) { 941 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 942#ifdef SMP 943 PMAP1cpu = PCPU_GET(cpuid); 944#endif 945 invlcaddr(PADDR1); 946 PMAP1changed++; 947 } else 948#ifdef SMP 949 if (PMAP1cpu != PCPU_GET(cpuid)) { 950 PMAP1cpu = PCPU_GET(cpuid); 951 invlcaddr(PADDR1); 952 PMAP1changedcpu++; 953 } else 954#endif 955 PMAP1unchanged++; 956 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 957 } 958 return (0); 959} 960 961/* 962 * Routine: pmap_extract 963 * Function: 964 * Extract the physical page address associated 965 * with the given map/virtual_address pair. 966 */ 967vm_paddr_t 968pmap_extract(pmap_t pmap, vm_offset_t va) 969{ 970 vm_paddr_t rtval; 971 pt_entry_t *pte; 972 pd_entry_t pde; 973 974 rtval = 0; 975 PMAP_LOCK(pmap); 976 pde = pmap->pm_pdir[va >> PDRSHIFT]; 977 if (pde != 0) { 978 if ((pde & PG_PS) != 0) { 979 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 980 PMAP_UNLOCK(pmap); 981 return rtval; 982 } 983 pte = pmap_pte(pmap, va); 984 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 985 pmap_pte_release(pte); 986 } 987 PMAP_UNLOCK(pmap); 988 return (rtval); 989} 990 991/* 992 * Routine: pmap_extract_and_hold 993 * Function: 994 * Atomically extract and hold the physical page 995 * with the given pmap and virtual address pair 996 * if that mapping permits the given protection. 997 */ 998vm_page_t 999pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1000{ 1001 pd_entry_t pde; 1002 pt_entry_t pte; 1003 vm_page_t m; 1004 1005 m = NULL; 1006 vm_page_lock_queues(); 1007 PMAP_LOCK(pmap); 1008 pde = *pmap_pde(pmap, va); 1009 if (pde != 0) { 1010 if (pde & PG_PS) { 1011 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1012 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1013 (va & PDRMASK)); 1014 vm_page_hold(m); 1015 } 1016 } else { 1017 sched_pin(); 1018 pte = *pmap_pte_quick(pmap, va); 1019 if (pte != 0 && 1020 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1021 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1022 vm_page_hold(m); 1023 } 1024 sched_unpin(); 1025 } 1026 } 1027 vm_page_unlock_queues(); 1028 PMAP_UNLOCK(pmap); 1029 return (m); 1030} 1031 1032/*************************************************** 1033 * Low level mapping routines..... 1034 ***************************************************/ 1035 1036/* 1037 * Add a wired page to the kva. 1038 * Note: not SMP coherent. 1039 */ 1040PMAP_INLINE void 1041pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1042{ 1043 pt_entry_t *pte; 1044 1045 pte = vtopte(va); 1046 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1047} 1048 1049PMAP_INLINE void 1050pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1051{ 1052 pt_entry_t *pte; 1053 1054 pte = vtopte(va); 1055 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1056} 1057 1058/* 1059 * Remove a page from the kernel pagetables. 1060 * Note: not SMP coherent. 1061 */ 1062PMAP_INLINE void 1063pmap_kremove(vm_offset_t va) 1064{ 1065 pt_entry_t *pte; 1066 1067 pte = vtopte(va); 1068 pte_clear(pte); 1069} 1070 1071/* 1072 * Used to map a range of physical addresses into kernel 1073 * virtual address space. 1074 * 1075 * The value passed in '*virt' is a suggested virtual address for 1076 * the mapping. Architectures which can support a direct-mapped 1077 * physical to virtual region can return the appropriate address 1078 * within that region, leaving '*virt' unchanged. Other 1079 * architectures should map the pages starting at '*virt' and 1080 * update '*virt' with the first usable address after the mapped 1081 * region. 1082 */ 1083vm_offset_t 1084pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1085{ 1086 vm_offset_t va, sva; 1087 1088 va = sva = *virt; 1089 while (start < end) { 1090 pmap_kenter(va, start); 1091 va += PAGE_SIZE; 1092 start += PAGE_SIZE; 1093 } 1094 pmap_invalidate_range(kernel_pmap, sva, va); 1095 *virt = va; 1096 return (sva); 1097} 1098 1099 1100/* 1101 * Add a list of wired pages to the kva 1102 * this routine is only used for temporary 1103 * kernel mappings that do not need to have 1104 * page modification or references recorded. 1105 * Note that old mappings are simply written 1106 * over. The page *must* be wired. 1107 * Note: SMP coherent. Uses a ranged shootdown IPI. 1108 */ 1109void 1110pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1111{ 1112 pt_entry_t *endpte, oldpte, *pte; 1113 1114 oldpte = 0; 1115 pte = vtopte(sva); 1116 endpte = pte + count; 1117 while (pte < endpte) { 1118 oldpte |= *pte; 1119 pte_store(pte, VM_PAGE_TO_PHYS(*ma) | pgeflag | PG_RW | PG_V); 1120 pte++; 1121 ma++; 1122 } 1123 if ((oldpte & PG_V) != 0) 1124 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1125 PAGE_SIZE); 1126} 1127 1128/* 1129 * This routine tears out page mappings from the 1130 * kernel -- it is meant only for temporary mappings. 1131 * Note: SMP coherent. Uses a ranged shootdown IPI. 1132 */ 1133void 1134pmap_qremove(vm_offset_t sva, int count) 1135{ 1136 vm_offset_t va; 1137 1138 va = sva; 1139 while (count-- > 0) { 1140 pmap_kremove(va); 1141 va += PAGE_SIZE; 1142 } 1143 pmap_invalidate_range(kernel_pmap, sva, va); 1144} 1145 1146/*************************************************** 1147 * Page table page management routines..... 1148 ***************************************************/ 1149static __inline void 1150pmap_free_zero_pages(vm_page_t free) 1151{ 1152 vm_page_t m; 1153 1154 while (free != NULL) { 1155 m = free; 1156 free = m->right; 1157 vm_page_free_zero(m); 1158 } 1159} 1160 1161/* 1162 * This routine unholds page table pages, and if the hold count 1163 * drops to zero, then it decrements the wire count. 1164 */ 1165static __inline int 1166pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1167{ 1168 1169 --m->wire_count; 1170 if (m->wire_count == 0) 1171 return _pmap_unwire_pte_hold(pmap, m, free); 1172 else 1173 return 0; 1174} 1175 1176static int 1177_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1178{ 1179 vm_offset_t pteva; 1180 1181 /* 1182 * unmap the page table page 1183 */ 1184 pmap->pm_pdir[m->pindex] = 0; 1185 --pmap->pm_stats.resident_count; 1186 1187 /* 1188 * This is a release store so that the ordinary store unmapping 1189 * the page table page is globally performed before TLB shoot- 1190 * down is begun. 1191 */ 1192 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1193 1194 /* 1195 * Do an invltlb to make the invalidated mapping 1196 * take effect immediately. 1197 */ 1198 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1199 pmap_invalidate_page(pmap, pteva); 1200 1201 /* 1202 * Put page on a list so that it is released after 1203 * *ALL* TLB shootdown is done 1204 */ 1205 m->right = *free; 1206 *free = m; 1207 1208 return 1; 1209} 1210 1211/* 1212 * After removing a page table entry, this routine is used to 1213 * conditionally free the page, and manage the hold/wire counts. 1214 */ 1215static int 1216pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1217{ 1218 pd_entry_t ptepde; 1219 vm_page_t mpte; 1220 1221 if (va >= VM_MAXUSER_ADDRESS) 1222 return 0; 1223 ptepde = *pmap_pde(pmap, va); 1224 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1225 return pmap_unwire_pte_hold(pmap, mpte, free); 1226} 1227 1228void 1229pmap_pinit0(pmap_t pmap) 1230{ 1231 1232 PMAP_LOCK_INIT(pmap); 1233 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1234#ifdef PAE 1235 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1236#endif 1237 pmap->pm_active = 0; 1238 PCPU_SET(curpmap, pmap); 1239 TAILQ_INIT(&pmap->pm_pvchunk); 1240 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1241 mtx_lock_spin(&allpmaps_lock); 1242 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1243 mtx_unlock_spin(&allpmaps_lock); 1244} 1245 1246/* 1247 * Initialize a preallocated and zeroed pmap structure, 1248 * such as one in a vmspace structure. 1249 */ 1250int 1251pmap_pinit(pmap_t pmap) 1252{ 1253 vm_page_t m, ptdpg[NPGPTD]; 1254 vm_paddr_t pa; 1255 static int color; 1256 int i; 1257 1258 PMAP_LOCK_INIT(pmap); 1259 1260 /* 1261 * No need to allocate page table space yet but we do need a valid 1262 * page directory table. 1263 */ 1264 if (pmap->pm_pdir == NULL) { 1265 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1266 NBPTD); 1267 1268 if (pmap->pm_pdir == NULL) { 1269 PMAP_LOCK_DESTROY(pmap); 1270 return (0); 1271 } 1272#ifdef PAE 1273 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1274 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1275 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1276 ("pmap_pinit: pdpt misaligned")); 1277 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1278 ("pmap_pinit: pdpt above 4g")); 1279#endif 1280 } 1281 1282 /* 1283 * allocate the page directory page(s) 1284 */ 1285 for (i = 0; i < NPGPTD;) { 1286 m = vm_page_alloc(NULL, color++, 1287 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1288 VM_ALLOC_ZERO); 1289 if (m == NULL) 1290 VM_WAIT; 1291 else { 1292 ptdpg[i++] = m; 1293 } 1294 } 1295 1296 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1297 1298 for (i = 0; i < NPGPTD; i++) { 1299 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1300 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1301 } 1302 1303 mtx_lock_spin(&allpmaps_lock); 1304 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1305 mtx_unlock_spin(&allpmaps_lock); 1306 /* Wire in kernel global address entries. */ 1307 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1308 1309 /* install self-referential address mapping entry(s) */ 1310 for (i = 0; i < NPGPTD; i++) { 1311 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1312 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1313#ifdef PAE 1314 pmap->pm_pdpt[i] = pa | PG_V; 1315#endif 1316 } 1317 1318 pmap->pm_active = 0; 1319 TAILQ_INIT(&pmap->pm_pvchunk); 1320 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1321 1322 return (1); 1323} 1324 1325/* 1326 * this routine is called if the page table page is not 1327 * mapped correctly. 1328 */ 1329static vm_page_t 1330_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1331{ 1332 vm_paddr_t ptepa; 1333 vm_page_t m; 1334 1335 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1336 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1337 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1338 1339 /* 1340 * Allocate a page table page. 1341 */ 1342 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1343 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1344 if (flags & M_WAITOK) { 1345 PMAP_UNLOCK(pmap); 1346 vm_page_unlock_queues(); 1347 VM_WAIT; 1348 vm_page_lock_queues(); 1349 PMAP_LOCK(pmap); 1350 } 1351 1352 /* 1353 * Indicate the need to retry. While waiting, the page table 1354 * page may have been allocated. 1355 */ 1356 return (NULL); 1357 } 1358 if ((m->flags & PG_ZERO) == 0) 1359 pmap_zero_page(m); 1360 1361 /* 1362 * Map the pagetable page into the process address space, if 1363 * it isn't already there. 1364 */ 1365 1366 pmap->pm_stats.resident_count++; 1367 1368 ptepa = VM_PAGE_TO_PHYS(m); 1369 pmap->pm_pdir[ptepindex] = 1370 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1371 1372 return m; 1373} 1374 1375static vm_page_t 1376pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1377{ 1378 unsigned ptepindex; 1379 pd_entry_t ptepa; 1380 vm_page_t m; 1381 1382 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1383 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1384 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1385 1386 /* 1387 * Calculate pagetable page index 1388 */ 1389 ptepindex = va >> PDRSHIFT; 1390retry: 1391 /* 1392 * Get the page directory entry 1393 */ 1394 ptepa = pmap->pm_pdir[ptepindex]; 1395 1396 /* 1397 * This supports switching from a 4MB page to a 1398 * normal 4K page. 1399 */ 1400 if (ptepa & PG_PS) { 1401 pmap->pm_pdir[ptepindex] = 0; 1402 ptepa = 0; 1403 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1404 pmap_invalidate_all(kernel_pmap); 1405 } 1406 1407 /* 1408 * If the page table page is mapped, we just increment the 1409 * hold count, and activate it. 1410 */ 1411 if (ptepa) { 1412 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1413 m->wire_count++; 1414 } else { 1415 /* 1416 * Here if the pte page isn't mapped, or if it has 1417 * been deallocated. 1418 */ 1419 m = _pmap_allocpte(pmap, ptepindex, flags); 1420 if (m == NULL && (flags & M_WAITOK)) 1421 goto retry; 1422 } 1423 return (m); 1424} 1425 1426 1427/*************************************************** 1428* Pmap allocation/deallocation routines. 1429 ***************************************************/ 1430 1431#ifdef SMP 1432/* 1433 * Deal with a SMP shootdown of other users of the pmap that we are 1434 * trying to dispose of. This can be a bit hairy. 1435 */ 1436static u_int *lazymask; 1437static u_int lazyptd; 1438static volatile u_int lazywait; 1439 1440void pmap_lazyfix_action(void); 1441 1442void 1443pmap_lazyfix_action(void) 1444{ 1445 u_int mymask = PCPU_GET(cpumask); 1446 1447#ifdef COUNT_IPIS 1448 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1449#endif 1450 if (rcr3() == lazyptd) 1451 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1452 atomic_clear_int(lazymask, mymask); 1453 atomic_store_rel_int(&lazywait, 1); 1454} 1455 1456static void 1457pmap_lazyfix_self(u_int mymask) 1458{ 1459 1460 if (rcr3() == lazyptd) 1461 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1462 atomic_clear_int(lazymask, mymask); 1463} 1464 1465 1466static void 1467pmap_lazyfix(pmap_t pmap) 1468{ 1469 u_int mymask; 1470 u_int mask; 1471 u_int spins; 1472 1473 while ((mask = pmap->pm_active) != 0) { 1474 spins = 50000000; 1475 mask = mask & -mask; /* Find least significant set bit */ 1476 mtx_lock_spin(&smp_ipi_mtx); 1477#ifdef PAE 1478 lazyptd = vtophys(pmap->pm_pdpt); 1479#else 1480 lazyptd = vtophys(pmap->pm_pdir); 1481#endif 1482 mymask = PCPU_GET(cpumask); 1483 if (mask == mymask) { 1484 lazymask = &pmap->pm_active; 1485 pmap_lazyfix_self(mymask); 1486 } else { 1487 atomic_store_rel_int((u_int *)&lazymask, 1488 (u_int)&pmap->pm_active); 1489 atomic_store_rel_int(&lazywait, 0); 1490 ipi_selected(mask, IPI_LAZYPMAP); 1491 while (lazywait == 0) { 1492 ia32_pause(); 1493 if (--spins == 0) 1494 break; 1495 } 1496 } 1497 mtx_unlock_spin(&smp_ipi_mtx); 1498 if (spins == 0) 1499 printf("pmap_lazyfix: spun for 50000000\n"); 1500 } 1501} 1502 1503#else /* SMP */ 1504 1505/* 1506 * Cleaning up on uniprocessor is easy. For various reasons, we're 1507 * unlikely to have to even execute this code, including the fact 1508 * that the cleanup is deferred until the parent does a wait(2), which 1509 * means that another userland process has run. 1510 */ 1511static void 1512pmap_lazyfix(pmap_t pmap) 1513{ 1514 u_int cr3; 1515 1516 cr3 = vtophys(pmap->pm_pdir); 1517 if (cr3 == rcr3()) { 1518 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1519 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1520 } 1521} 1522#endif /* SMP */ 1523 1524/* 1525 * Release any resources held by the given physical map. 1526 * Called when a pmap initialized by pmap_pinit is being released. 1527 * Should only be called if the map contains no valid mappings. 1528 */ 1529void 1530pmap_release(pmap_t pmap) 1531{ 1532 vm_page_t m, ptdpg[NPGPTD]; 1533 int i; 1534 1535 KASSERT(pmap->pm_stats.resident_count == 0, 1536 ("pmap_release: pmap resident count %ld != 0", 1537 pmap->pm_stats.resident_count)); 1538 1539 pmap_lazyfix(pmap); 1540 mtx_lock_spin(&allpmaps_lock); 1541 LIST_REMOVE(pmap, pm_list); 1542 mtx_unlock_spin(&allpmaps_lock); 1543 1544 for (i = 0; i < NPGPTD; i++) 1545 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1546 PG_FRAME); 1547 1548 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 1549 sizeof(*pmap->pm_pdir)); 1550 1551 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1552 1553 for (i = 0; i < NPGPTD; i++) { 1554 m = ptdpg[i]; 1555#ifdef PAE 1556 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1557 ("pmap_release: got wrong ptd page")); 1558#endif 1559 m->wire_count--; 1560 atomic_subtract_int(&cnt.v_wire_count, 1); 1561 vm_page_free_zero(m); 1562 } 1563 PMAP_LOCK_DESTROY(pmap); 1564} 1565 1566static int 1567kvm_size(SYSCTL_HANDLER_ARGS) 1568{ 1569 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1570 1571 return sysctl_handle_long(oidp, &ksize, 0, req); 1572} 1573SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1574 0, 0, kvm_size, "IU", "Size of KVM"); 1575 1576static int 1577kvm_free(SYSCTL_HANDLER_ARGS) 1578{ 1579 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1580 1581 return sysctl_handle_long(oidp, &kfree, 0, req); 1582} 1583SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1584 0, 0, kvm_free, "IU", "Amount of KVM free"); 1585 1586/* 1587 * grow the number of kernel page table entries, if needed 1588 */ 1589void 1590pmap_growkernel(vm_offset_t addr) 1591{ 1592 struct pmap *pmap; 1593 vm_paddr_t ptppaddr; 1594 vm_page_t nkpg; 1595 pd_entry_t newpdir; 1596 pt_entry_t *pde; 1597 1598 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1599 if (kernel_vm_end == 0) { 1600 kernel_vm_end = KERNBASE; 1601 nkpt = 0; 1602 while (pdir_pde(PTD, kernel_vm_end)) { 1603 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1604 nkpt++; 1605 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1606 kernel_vm_end = kernel_map->max_offset; 1607 break; 1608 } 1609 } 1610 } 1611 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1612 if (addr - 1 >= kernel_map->max_offset) 1613 addr = kernel_map->max_offset; 1614 while (kernel_vm_end < addr) { 1615 if (pdir_pde(PTD, kernel_vm_end)) { 1616 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1617 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1618 kernel_vm_end = kernel_map->max_offset; 1619 break; 1620 } 1621 continue; 1622 } 1623 1624 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1625 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1626 if (nkpg == NULL) 1627 panic("pmap_growkernel: no memory to grow kernel"); 1628 1629 nkpt++; 1630 1631 pmap_zero_page(nkpg); 1632 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1633 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1634 pdir_pde(PTD, kernel_vm_end) = newpdir; 1635 1636 mtx_lock_spin(&allpmaps_lock); 1637 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1638 pde = pmap_pde(pmap, kernel_vm_end); 1639 pde_store(pde, newpdir); 1640 } 1641 mtx_unlock_spin(&allpmaps_lock); 1642 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1643 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1644 kernel_vm_end = kernel_map->max_offset; 1645 break; 1646 } 1647 } 1648} 1649 1650 1651/*************************************************** 1652 * page management routines. 1653 ***************************************************/ 1654 1655CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1656CTASSERT(_NPCM == 11); 1657 1658static __inline struct pv_chunk * 1659pv_to_chunk(pv_entry_t pv) 1660{ 1661 1662 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1663} 1664 1665#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1666 1667#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1668#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1669 1670static uint32_t pc_freemask[11] = { 1671 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1672 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1673 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1674 PC_FREE0_9, PC_FREE10 1675}; 1676 1677SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1678 "Current number of pv entries"); 1679 1680#ifdef PV_STATS 1681static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1682 1683SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1684 "Current number of pv entry chunks"); 1685SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1686 "Current number of pv entry chunks allocated"); 1687SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1688 "Current number of pv entry chunks frees"); 1689SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1690 "Number of times tried to get a chunk page but failed."); 1691 1692static long pv_entry_frees, pv_entry_allocs; 1693static int pv_entry_spare; 1694 1695SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1696 "Current number of pv entry frees"); 1697SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1698 "Current number of pv entry allocs"); 1699SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1700 "Current number of spare pv entries"); 1701 1702static int pmap_collect_inactive, pmap_collect_active; 1703 1704SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1705 "Current number times pmap_collect called on inactive queue"); 1706SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1707 "Current number times pmap_collect called on active queue"); 1708#endif 1709 1710/* 1711 * We are in a serious low memory condition. Resort to 1712 * drastic measures to free some pages so we can allocate 1713 * another pv entry chunk. This is normally called to 1714 * unmap inactive pages, and if necessary, active pages. 1715 */ 1716static void 1717pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1718{ 1719 pmap_t pmap; 1720 pt_entry_t *pte, tpte; 1721 pv_entry_t next_pv, pv; 1722 vm_offset_t va; 1723 vm_page_t m, free; 1724 1725 sched_pin(); 1726 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1727 if (m->hold_count || m->busy) 1728 continue; 1729 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1730 va = pv->pv_va; 1731 pmap = PV_PMAP(pv); 1732 /* Avoid deadlock and lock recursion. */ 1733 if (pmap > locked_pmap) 1734 PMAP_LOCK(pmap); 1735 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1736 continue; 1737 pmap->pm_stats.resident_count--; 1738 pte = pmap_pte_quick(pmap, va); 1739 tpte = pte_load_clear(pte); 1740 KASSERT((tpte & PG_W) == 0, 1741 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 1742 if (tpte & PG_A) 1743 vm_page_flag_set(m, PG_REFERENCED); 1744 if (tpte & PG_M) { 1745 KASSERT((tpte & PG_RW), 1746 ("pmap_collect: modified page not writable: va: %#x, pte: %#jx", 1747 va, (uintmax_t)tpte)); 1748 vm_page_dirty(m); 1749 } 1750 free = NULL; 1751 pmap_unuse_pt(pmap, va, &free); 1752 pmap_invalidate_page(pmap, va); 1753 pmap_free_zero_pages(free); 1754 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1755 if (TAILQ_EMPTY(&m->md.pv_list)) 1756 vm_page_flag_clear(m, PG_WRITEABLE); 1757 free_pv_entry(pmap, pv); 1758 if (pmap != locked_pmap) 1759 PMAP_UNLOCK(pmap); 1760 } 1761 } 1762 sched_unpin(); 1763} 1764 1765 1766/* 1767 * free the pv_entry back to the free list 1768 */ 1769static void 1770free_pv_entry(pmap_t pmap, pv_entry_t pv) 1771{ 1772 vm_page_t m; 1773 struct pv_chunk *pc; 1774 int idx, field, bit; 1775 1776 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1777 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1778 PV_STAT(pv_entry_frees++); 1779 PV_STAT(pv_entry_spare++); 1780 pv_entry_count--; 1781 pc = pv_to_chunk(pv); 1782 idx = pv - &pc->pc_pventry[0]; 1783 field = idx / 32; 1784 bit = idx % 32; 1785 pc->pc_map[field] |= 1ul << bit; 1786 /* move to head of list */ 1787 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1788 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1789 for (idx = 0; idx < _NPCM; idx++) 1790 if (pc->pc_map[idx] != pc_freemask[idx]) 1791 return; 1792 PV_STAT(pv_entry_spare -= _NPCPV); 1793 PV_STAT(pc_chunk_count--); 1794 PV_STAT(pc_chunk_frees++); 1795 /* entire chunk is free, return it */ 1796 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1797 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 1798 pmap_qremove((vm_offset_t)pc, 1); 1799 vm_page_unwire(m, 0); 1800 vm_page_free(m); 1801 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 1802} 1803 1804/* 1805 * get a new pv_entry, allocating a block from the system 1806 * when needed. 1807 */ 1808static pv_entry_t 1809get_pv_entry(pmap_t pmap, int try) 1810{ 1811 static const struct timeval printinterval = { 60, 0 }; 1812 static struct timeval lastprint; 1813 static vm_pindex_t colour; 1814 struct vpgqueues *pq; 1815 int bit, field; 1816 pv_entry_t pv; 1817 struct pv_chunk *pc; 1818 vm_page_t m; 1819 1820 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1821 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1822 PV_STAT(pv_entry_allocs++); 1823 pv_entry_count++; 1824 if (pv_entry_count > pv_entry_high_water) 1825 if (ratecheck(&lastprint, &printinterval)) 1826 printf("Approaching the limit on PV entries, consider " 1827 "increasing either the vm.pmap.shpgperproc or the " 1828 "vm.pmap.pv_entry_max tunable.\n"); 1829 pq = NULL; 1830retry: 1831 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 1832 if (pc != NULL) { 1833 for (field = 0; field < _NPCM; field++) { 1834 if (pc->pc_map[field]) { 1835 bit = bsfl(pc->pc_map[field]); 1836 break; 1837 } 1838 } 1839 if (field < _NPCM) { 1840 pv = &pc->pc_pventry[field * 32 + bit]; 1841 pc->pc_map[field] &= ~(1ul << bit); 1842 /* If this was the last item, move it to tail */ 1843 for (field = 0; field < _NPCM; field++) 1844 if (pc->pc_map[field] != 0) { 1845 PV_STAT(pv_entry_spare--); 1846 return (pv); /* not full, return */ 1847 } 1848 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1849 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 1850 PV_STAT(pv_entry_spare--); 1851 return (pv); 1852 } 1853 } 1854 /* 1855 * Access to the ptelist "pv_vafree" is synchronized by the page 1856 * queues lock. If "pv_vafree" is currently non-empty, it will 1857 * remain non-empty until pmap_ptelist_alloc() completes. 1858 */ 1859 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 1860 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 1861 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 1862 if (try) { 1863 pv_entry_count--; 1864 PV_STAT(pc_chunk_tryfail++); 1865 return (NULL); 1866 } 1867 /* 1868 * Reclaim pv entries: At first, destroy mappings to 1869 * inactive pages. After that, if a pv chunk entry 1870 * is still needed, destroy mappings to active pages. 1871 */ 1872 if (pq == NULL) { 1873 PV_STAT(pmap_collect_inactive++); 1874 pq = &vm_page_queues[PQ_INACTIVE]; 1875 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 1876 PV_STAT(pmap_collect_active++); 1877 pq = &vm_page_queues[PQ_ACTIVE]; 1878 } else 1879 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 1880 pmap_collect(pmap, pq); 1881 goto retry; 1882 } 1883 PV_STAT(pc_chunk_count++); 1884 PV_STAT(pc_chunk_allocs++); 1885 colour++; 1886 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 1887 pmap_qenter((vm_offset_t)pc, &m, 1); 1888 pc->pc_pmap = pmap; 1889 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 1890 for (field = 1; field < _NPCM; field++) 1891 pc->pc_map[field] = pc_freemask[field]; 1892 pv = &pc->pc_pventry[0]; 1893 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1894 PV_STAT(pv_entry_spare += _NPCPV - 1); 1895 return (pv); 1896} 1897 1898static void 1899pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 1900{ 1901 pv_entry_t pv; 1902 1903 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1904 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1905 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1906 if (pmap == PV_PMAP(pv) && va == pv->pv_va) 1907 break; 1908 } 1909 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found")); 1910 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1911 if (TAILQ_EMPTY(&m->md.pv_list)) 1912 vm_page_flag_clear(m, PG_WRITEABLE); 1913 free_pv_entry(pmap, pv); 1914} 1915 1916/* 1917 * Create a pv entry for page at pa for 1918 * (pmap, va). 1919 */ 1920static void 1921pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 1922{ 1923 pv_entry_t pv; 1924 1925 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1926 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1927 pv = get_pv_entry(pmap, FALSE); 1928 pv->pv_va = va; 1929 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1930} 1931 1932/* 1933 * Conditionally create a pv entry. 1934 */ 1935static boolean_t 1936pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 1937{ 1938 pv_entry_t pv; 1939 1940 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1941 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1942 if (pv_entry_count < pv_entry_high_water && 1943 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 1944 pv->pv_va = va; 1945 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1946 return (TRUE); 1947 } else 1948 return (FALSE); 1949} 1950 1951/* 1952 * pmap_remove_pte: do the things to unmap a page in a process 1953 */ 1954static int 1955pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 1956{ 1957 pt_entry_t oldpte; 1958 vm_page_t m; 1959 1960 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1961 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1962 oldpte = pte_load_clear(ptq); 1963 if (oldpte & PG_W) 1964 pmap->pm_stats.wired_count -= 1; 1965 /* 1966 * Machines that don't support invlpg, also don't support 1967 * PG_G. 1968 */ 1969 if (oldpte & PG_G) 1970 pmap_invalidate_page(kernel_pmap, va); 1971 pmap->pm_stats.resident_count -= 1; 1972 if (oldpte & PG_MANAGED) { 1973 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 1974 if (oldpte & PG_M) { 1975 KASSERT((oldpte & PG_RW), 1976 ("pmap_remove_pte: modified page not writable: va: %#x, pte: %#jx", 1977 va, (uintmax_t)oldpte)); 1978 vm_page_dirty(m); 1979 } 1980 if (oldpte & PG_A) 1981 vm_page_flag_set(m, PG_REFERENCED); 1982 pmap_remove_entry(pmap, m, va); 1983 } 1984 return (pmap_unuse_pt(pmap, va, free)); 1985} 1986 1987/* 1988 * Remove a single page from a process address space 1989 */ 1990static void 1991pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1992{ 1993 pt_entry_t *pte; 1994 1995 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1996 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1997 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1998 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 1999 return; 2000 pmap_remove_pte(pmap, pte, va, free); 2001 pmap_invalidate_page(pmap, va); 2002} 2003 2004/* 2005 * Remove the given range of addresses from the specified map. 2006 * 2007 * It is assumed that the start and end are properly 2008 * rounded to the page size. 2009 */ 2010void 2011pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2012{ 2013 vm_offset_t pdnxt; 2014 pd_entry_t ptpaddr; 2015 pt_entry_t *pte; 2016 vm_page_t free = NULL; 2017 int anyvalid; 2018 2019 /* 2020 * Perform an unsynchronized read. This is, however, safe. 2021 */ 2022 if (pmap->pm_stats.resident_count == 0) 2023 return; 2024 2025 anyvalid = 0; 2026 2027 vm_page_lock_queues(); 2028 sched_pin(); 2029 PMAP_LOCK(pmap); 2030 2031 /* 2032 * special handling of removing one page. a very 2033 * common operation and easy to short circuit some 2034 * code. 2035 */ 2036 if ((sva + PAGE_SIZE == eva) && 2037 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2038 pmap_remove_page(pmap, sva, &free); 2039 goto out; 2040 } 2041 2042 for (; sva < eva; sva = pdnxt) { 2043 unsigned pdirindex; 2044 2045 /* 2046 * Calculate index for next page table. 2047 */ 2048 pdnxt = (sva + NBPDR) & ~PDRMASK; 2049 if (pdnxt < sva) 2050 pdnxt = eva; 2051 if (pmap->pm_stats.resident_count == 0) 2052 break; 2053 2054 pdirindex = sva >> PDRSHIFT; 2055 ptpaddr = pmap->pm_pdir[pdirindex]; 2056 2057 /* 2058 * Weed out invalid mappings. Note: we assume that the page 2059 * directory table is always allocated, and in kernel virtual. 2060 */ 2061 if (ptpaddr == 0) 2062 continue; 2063 2064 /* 2065 * Check for large page. 2066 */ 2067 if ((ptpaddr & PG_PS) != 0) { 2068 pmap->pm_pdir[pdirindex] = 0; 2069 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2070 anyvalid = 1; 2071 continue; 2072 } 2073 2074 /* 2075 * Limit our scan to either the end of the va represented 2076 * by the current page table page, or to the end of the 2077 * range being removed. 2078 */ 2079 if (pdnxt > eva) 2080 pdnxt = eva; 2081 2082 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2083 sva += PAGE_SIZE) { 2084 if (*pte == 0) 2085 continue; 2086 2087 /* 2088 * The TLB entry for a PG_G mapping is invalidated 2089 * by pmap_remove_pte(). 2090 */ 2091 if ((*pte & PG_G) == 0) 2092 anyvalid = 1; 2093 if (pmap_remove_pte(pmap, pte, sva, &free)) 2094 break; 2095 } 2096 } 2097out: 2098 sched_unpin(); 2099 if (anyvalid) 2100 pmap_invalidate_all(pmap); 2101 vm_page_unlock_queues(); 2102 PMAP_UNLOCK(pmap); 2103 pmap_free_zero_pages(free); 2104} 2105 2106/* 2107 * Routine: pmap_remove_all 2108 * Function: 2109 * Removes this physical page from 2110 * all physical maps in which it resides. 2111 * Reflects back modify bits to the pager. 2112 * 2113 * Notes: 2114 * Original versions of this routine were very 2115 * inefficient because they iteratively called 2116 * pmap_remove (slow...) 2117 */ 2118 2119void 2120pmap_remove_all(vm_page_t m) 2121{ 2122 pv_entry_t pv; 2123 pmap_t pmap; 2124 pt_entry_t *pte, tpte; 2125 vm_page_t free; 2126 2127 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2128 ("pmap_remove_all: page %p is fictitious", m)); 2129 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2130 sched_pin(); 2131 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2132 pmap = PV_PMAP(pv); 2133 PMAP_LOCK(pmap); 2134 pmap->pm_stats.resident_count--; 2135 pte = pmap_pte_quick(pmap, pv->pv_va); 2136 tpte = pte_load_clear(pte); 2137 if (tpte & PG_W) 2138 pmap->pm_stats.wired_count--; 2139 if (tpte & PG_A) 2140 vm_page_flag_set(m, PG_REFERENCED); 2141 2142 /* 2143 * Update the vm_page_t clean and reference bits. 2144 */ 2145 if (tpte & PG_M) { 2146 KASSERT((tpte & PG_RW), 2147 ("pmap_remove_all: modified page not writable: va: %#x, pte: %#jx", 2148 pv->pv_va, (uintmax_t)tpte)); 2149 vm_page_dirty(m); 2150 } 2151 free = NULL; 2152 pmap_unuse_pt(pmap, pv->pv_va, &free); 2153 pmap_invalidate_page(pmap, pv->pv_va); 2154 pmap_free_zero_pages(free); 2155 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2156 free_pv_entry(pmap, pv); 2157 PMAP_UNLOCK(pmap); 2158 } 2159 vm_page_flag_clear(m, PG_WRITEABLE); 2160 sched_unpin(); 2161} 2162 2163/* 2164 * Set the physical protection on the 2165 * specified range of this map as requested. 2166 */ 2167void 2168pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2169{ 2170 vm_offset_t pdnxt; 2171 pd_entry_t ptpaddr; 2172 pt_entry_t *pte; 2173 int anychanged; 2174 2175 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2176 pmap_remove(pmap, sva, eva); 2177 return; 2178 } 2179 2180#ifdef PAE 2181 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2182 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2183 return; 2184#else 2185 if (prot & VM_PROT_WRITE) 2186 return; 2187#endif 2188 2189 anychanged = 0; 2190 2191 vm_page_lock_queues(); 2192 sched_pin(); 2193 PMAP_LOCK(pmap); 2194 for (; sva < eva; sva = pdnxt) { 2195 pt_entry_t obits, pbits; 2196 unsigned pdirindex; 2197 2198 pdnxt = (sva + NBPDR) & ~PDRMASK; 2199 if (pdnxt < sva) 2200 pdnxt = eva; 2201 2202 pdirindex = sva >> PDRSHIFT; 2203 ptpaddr = pmap->pm_pdir[pdirindex]; 2204 2205 /* 2206 * Weed out invalid mappings. Note: we assume that the page 2207 * directory table is always allocated, and in kernel virtual. 2208 */ 2209 if (ptpaddr == 0) 2210 continue; 2211 2212 /* 2213 * Check for large page. 2214 */ 2215 if ((ptpaddr & PG_PS) != 0) { 2216 if ((prot & VM_PROT_WRITE) == 0) 2217 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2218#ifdef PAE 2219 if ((prot & VM_PROT_EXECUTE) == 0) 2220 pmap->pm_pdir[pdirindex] |= pg_nx; 2221#endif 2222 anychanged = 1; 2223 continue; 2224 } 2225 2226 if (pdnxt > eva) 2227 pdnxt = eva; 2228 2229 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2230 sva += PAGE_SIZE) { 2231 vm_page_t m; 2232 2233retry: 2234 /* 2235 * Regardless of whether a pte is 32 or 64 bits in 2236 * size, PG_RW, PG_A, and PG_M are among the least 2237 * significant 32 bits. 2238 */ 2239 obits = pbits = *pte; 2240 if ((pbits & PG_V) == 0) 2241 continue; 2242 if (pbits & PG_MANAGED) { 2243 m = NULL; 2244 if (pbits & PG_A) { 2245 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2246 vm_page_flag_set(m, PG_REFERENCED); 2247 pbits &= ~PG_A; 2248 } 2249 if ((pbits & PG_M) != 0) { 2250 if (m == NULL) 2251 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2252 vm_page_dirty(m); 2253 } 2254 } 2255 2256 if ((prot & VM_PROT_WRITE) == 0) 2257 pbits &= ~(PG_RW | PG_M); 2258#ifdef PAE 2259 if ((prot & VM_PROT_EXECUTE) == 0) 2260 pbits |= pg_nx; 2261#endif 2262 2263 if (pbits != obits) { 2264#ifdef PAE 2265 if (!atomic_cmpset_64(pte, obits, pbits)) 2266 goto retry; 2267#else 2268 if (!atomic_cmpset_int((u_int *)pte, obits, 2269 pbits)) 2270 goto retry; 2271#endif 2272 if (obits & PG_G) 2273 pmap_invalidate_page(pmap, sva); 2274 else 2275 anychanged = 1; 2276 } 2277 } 2278 } 2279 sched_unpin(); 2280 if (anychanged) 2281 pmap_invalidate_all(pmap); 2282 vm_page_unlock_queues(); 2283 PMAP_UNLOCK(pmap); 2284} 2285 2286/* 2287 * Insert the given physical page (p) at 2288 * the specified virtual address (v) in the 2289 * target physical map with the protection requested. 2290 * 2291 * If specified, the page will be wired down, meaning 2292 * that the related pte can not be reclaimed. 2293 * 2294 * NB: This is the only routine which MAY NOT lazy-evaluate 2295 * or lose information. That is, this routine must actually 2296 * insert this page into the given map NOW. 2297 */ 2298void 2299pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2300 vm_prot_t prot, boolean_t wired) 2301{ 2302 vm_paddr_t pa; 2303 pd_entry_t *pde; 2304 pt_entry_t *pte; 2305 vm_paddr_t opa; 2306 pt_entry_t origpte, newpte; 2307 vm_page_t mpte, om; 2308 boolean_t invlva; 2309 2310 va = trunc_page(va); 2311 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2312 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2313 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va)); 2314 2315 mpte = NULL; 2316 2317 vm_page_lock_queues(); 2318 PMAP_LOCK(pmap); 2319 sched_pin(); 2320 2321 /* 2322 * In the case that a page table page is not 2323 * resident, we are creating it here. 2324 */ 2325 if (va < VM_MAXUSER_ADDRESS) { 2326 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2327 } 2328 2329 pde = pmap_pde(pmap, va); 2330 if ((*pde & PG_PS) != 0) 2331 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2332 pte = pmap_pte_quick(pmap, va); 2333 2334 /* 2335 * Page Directory table entry not valid, we need a new PT page 2336 */ 2337 if (pte == NULL) { 2338 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2339 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 2340 } 2341 2342 pa = VM_PAGE_TO_PHYS(m); 2343 om = NULL; 2344 origpte = *pte; 2345 opa = origpte & PG_FRAME; 2346 2347 /* 2348 * Mapping has not changed, must be protection or wiring change. 2349 */ 2350 if (origpte && (opa == pa)) { 2351 /* 2352 * Wiring change, just update stats. We don't worry about 2353 * wiring PT pages as they remain resident as long as there 2354 * are valid mappings in them. Hence, if a user page is wired, 2355 * the PT page will be also. 2356 */ 2357 if (wired && ((origpte & PG_W) == 0)) 2358 pmap->pm_stats.wired_count++; 2359 else if (!wired && (origpte & PG_W)) 2360 pmap->pm_stats.wired_count--; 2361 2362 /* 2363 * Remove extra pte reference 2364 */ 2365 if (mpte) 2366 mpte->wire_count--; 2367 2368 /* 2369 * We might be turning off write access to the page, 2370 * so we go ahead and sense modify status. 2371 */ 2372 if (origpte & PG_MANAGED) { 2373 om = m; 2374 pa |= PG_MANAGED; 2375 } 2376 goto validate; 2377 } 2378 /* 2379 * Mapping has changed, invalidate old range and fall through to 2380 * handle validating new mapping. 2381 */ 2382 if (opa) { 2383 if (origpte & PG_W) 2384 pmap->pm_stats.wired_count--; 2385 if (origpte & PG_MANAGED) { 2386 om = PHYS_TO_VM_PAGE(opa); 2387 pmap_remove_entry(pmap, om, va); 2388 } 2389 if (mpte != NULL) { 2390 mpte->wire_count--; 2391 KASSERT(mpte->wire_count > 0, 2392 ("pmap_enter: missing reference to page table page," 2393 " va: 0x%x", va)); 2394 } 2395 } else 2396 pmap->pm_stats.resident_count++; 2397 2398 /* 2399 * Enter on the PV list if part of our managed memory. 2400 */ 2401 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 2402 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2403 ("pmap_enter: managed mapping within the clean submap")); 2404 pmap_insert_entry(pmap, va, m); 2405 pa |= PG_MANAGED; 2406 } 2407 2408 /* 2409 * Increment counters 2410 */ 2411 if (wired) 2412 pmap->pm_stats.wired_count++; 2413 2414validate: 2415 /* 2416 * Now validate mapping with desired protection/wiring. 2417 */ 2418 newpte = (pt_entry_t)(pa | PG_V); 2419 if ((prot & VM_PROT_WRITE) != 0) { 2420 newpte |= PG_RW; 2421 vm_page_flag_set(m, PG_WRITEABLE); 2422 } 2423#ifdef PAE 2424 if ((prot & VM_PROT_EXECUTE) == 0) 2425 newpte |= pg_nx; 2426#endif 2427 if (wired) 2428 newpte |= PG_W; 2429 if (va < VM_MAXUSER_ADDRESS) 2430 newpte |= PG_U; 2431 if (pmap == kernel_pmap) 2432 newpte |= pgeflag; 2433 2434 /* 2435 * if the mapping or permission bits are different, we need 2436 * to update the pte. 2437 */ 2438 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2439 if (origpte & PG_V) { 2440 invlva = FALSE; 2441 origpte = pte_load_store(pte, newpte | PG_A); 2442 if (origpte & PG_A) { 2443 if (origpte & PG_MANAGED) 2444 vm_page_flag_set(om, PG_REFERENCED); 2445 if (opa != VM_PAGE_TO_PHYS(m)) 2446 invlva = TRUE; 2447#ifdef PAE 2448 if ((origpte & PG_NX) == 0 && 2449 (newpte & PG_NX) != 0) 2450 invlva = TRUE; 2451#endif 2452 } 2453 if (origpte & PG_M) { 2454 KASSERT((origpte & PG_RW), 2455 ("pmap_enter: modified page not writable: va: %#x, pte: %#jx", 2456 va, (uintmax_t)origpte)); 2457 if ((origpte & PG_MANAGED) != 0) 2458 vm_page_dirty(om); 2459 if ((prot & VM_PROT_WRITE) == 0) 2460 invlva = TRUE; 2461 } 2462 if (invlva) 2463 pmap_invalidate_page(pmap, va); 2464 } else 2465 pte_store(pte, newpte | PG_A); 2466 } 2467 sched_unpin(); 2468 vm_page_unlock_queues(); 2469 PMAP_UNLOCK(pmap); 2470} 2471 2472/* 2473 * Maps a sequence of resident pages belonging to the same object. 2474 * The sequence begins with the given page m_start. This page is 2475 * mapped at the given virtual address start. Each subsequent page is 2476 * mapped at a virtual address that is offset from start by the same 2477 * amount as the page is offset from m_start within the object. The 2478 * last page in the sequence is the page with the largest offset from 2479 * m_start that can be mapped at a virtual address less than the given 2480 * virtual address end. Not every virtual page between start and end 2481 * is mapped; only those for which a resident page exists with the 2482 * corresponding offset from m_start are mapped. 2483 */ 2484void 2485pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2486 vm_page_t m_start, vm_prot_t prot) 2487{ 2488 vm_page_t m, mpte; 2489 vm_pindex_t diff, psize; 2490 2491 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2492 psize = atop(end - start); 2493 mpte = NULL; 2494 m = m_start; 2495 PMAP_LOCK(pmap); 2496 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2497 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2498 prot, mpte); 2499 m = TAILQ_NEXT(m, listq); 2500 } 2501 PMAP_UNLOCK(pmap); 2502} 2503 2504/* 2505 * this code makes some *MAJOR* assumptions: 2506 * 1. Current pmap & pmap exists. 2507 * 2. Not wired. 2508 * 3. Read access. 2509 * 4. No page table pages. 2510 * but is *MUCH* faster than pmap_enter... 2511 */ 2512 2513void 2514pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2515{ 2516 2517 PMAP_LOCK(pmap); 2518 (void) pmap_enter_quick_locked(pmap, va, m, prot, NULL); 2519 PMAP_UNLOCK(pmap); 2520} 2521 2522static vm_page_t 2523pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 2524 vm_prot_t prot, vm_page_t mpte) 2525{ 2526 pt_entry_t *pte; 2527 vm_paddr_t pa; 2528 vm_page_t free; 2529 2530 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2531 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 2532 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2533 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2534 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2535 2536 /* 2537 * In the case that a page table page is not 2538 * resident, we are creating it here. 2539 */ 2540 if (va < VM_MAXUSER_ADDRESS) { 2541 unsigned ptepindex; 2542 pd_entry_t ptepa; 2543 2544 /* 2545 * Calculate pagetable page index 2546 */ 2547 ptepindex = va >> PDRSHIFT; 2548 if (mpte && (mpte->pindex == ptepindex)) { 2549 mpte->wire_count++; 2550 } else { 2551 /* 2552 * Get the page directory entry 2553 */ 2554 ptepa = pmap->pm_pdir[ptepindex]; 2555 2556 /* 2557 * If the page table page is mapped, we just increment 2558 * the hold count, and activate it. 2559 */ 2560 if (ptepa) { 2561 if (ptepa & PG_PS) 2562 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2563 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 2564 mpte->wire_count++; 2565 } else { 2566 mpte = _pmap_allocpte(pmap, ptepindex, 2567 M_NOWAIT); 2568 if (mpte == NULL) 2569 return (mpte); 2570 } 2571 } 2572 } else { 2573 mpte = NULL; 2574 } 2575 2576 /* 2577 * This call to vtopte makes the assumption that we are 2578 * entering the page into the current pmap. In order to support 2579 * quick entry into any pmap, one would likely use pmap_pte_quick. 2580 * But that isn't as quick as vtopte. 2581 */ 2582 pte = vtopte(va); 2583 if (*pte) { 2584 if (mpte != NULL) { 2585 mpte->wire_count--; 2586 mpte = NULL; 2587 } 2588 return (mpte); 2589 } 2590 2591 /* 2592 * Enter on the PV list if part of our managed memory. 2593 */ 2594 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2595 !pmap_try_insert_pv_entry(pmap, va, m)) { 2596 if (mpte != NULL) { 2597 free = NULL; 2598 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 2599 pmap_invalidate_page(pmap, va); 2600 pmap_free_zero_pages(free); 2601 } 2602 2603 mpte = NULL; 2604 } 2605 return (mpte); 2606 } 2607 2608 /* 2609 * Increment counters 2610 */ 2611 pmap->pm_stats.resident_count++; 2612 2613 pa = VM_PAGE_TO_PHYS(m); 2614#ifdef PAE 2615 if ((prot & VM_PROT_EXECUTE) == 0) 2616 pa |= pg_nx; 2617#endif 2618 2619 /* 2620 * Now validate mapping with RO protection 2621 */ 2622 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 2623 pte_store(pte, pa | PG_V | PG_U); 2624 else 2625 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 2626 return mpte; 2627} 2628 2629/* 2630 * Make a temporary mapping for a physical address. This is only intended 2631 * to be used for panic dumps. 2632 */ 2633void * 2634pmap_kenter_temporary(vm_paddr_t pa, int i) 2635{ 2636 vm_offset_t va; 2637 2638 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 2639 pmap_kenter(va, pa); 2640 invlpg(va); 2641 return ((void *)crashdumpmap); 2642} 2643 2644/* 2645 * This code maps large physical mmap regions into the 2646 * processor address space. Note that some shortcuts 2647 * are taken, but the code works. 2648 */ 2649void 2650pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2651 vm_object_t object, vm_pindex_t pindex, 2652 vm_size_t size) 2653{ 2654 vm_page_t p; 2655 2656 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2657 KASSERT(object->type == OBJT_DEVICE, 2658 ("pmap_object_init_pt: non-device object")); 2659 if (pseflag && 2660 ((addr & (NBPDR - 1)) == 0) && ((size & (NBPDR - 1)) == 0)) { 2661 int i; 2662 vm_page_t m[1]; 2663 unsigned int ptepindex; 2664 int npdes; 2665 pd_entry_t ptepa; 2666 2667 PMAP_LOCK(pmap); 2668 if (pmap->pm_pdir[ptepindex = (addr >> PDRSHIFT)]) 2669 goto out; 2670 PMAP_UNLOCK(pmap); 2671retry: 2672 p = vm_page_lookup(object, pindex); 2673 if (p != NULL) { 2674 if (vm_page_sleep_if_busy(p, FALSE, "init4p")) 2675 goto retry; 2676 } else { 2677 p = vm_page_alloc(object, pindex, VM_ALLOC_NORMAL); 2678 if (p == NULL) 2679 return; 2680 m[0] = p; 2681 2682 if (vm_pager_get_pages(object, m, 1, 0) != VM_PAGER_OK) { 2683 vm_page_lock_queues(); 2684 vm_page_free(p); 2685 vm_page_unlock_queues(); 2686 return; 2687 } 2688 2689 p = vm_page_lookup(object, pindex); 2690 vm_page_lock_queues(); 2691 vm_page_wakeup(p); 2692 vm_page_unlock_queues(); 2693 } 2694 2695 ptepa = VM_PAGE_TO_PHYS(p); 2696 if (ptepa & (NBPDR - 1)) 2697 return; 2698 2699 p->valid = VM_PAGE_BITS_ALL; 2700 2701 PMAP_LOCK(pmap); 2702 pmap->pm_stats.resident_count += size >> PAGE_SHIFT; 2703 npdes = size >> PDRSHIFT; 2704 for(i = 0; i < npdes; i++) { 2705 pde_store(&pmap->pm_pdir[ptepindex], 2706 ptepa | PG_U | PG_RW | PG_V | PG_PS); 2707 ptepa += NBPDR; 2708 ptepindex += 1; 2709 } 2710 pmap_invalidate_all(pmap); 2711out: 2712 PMAP_UNLOCK(pmap); 2713 } 2714} 2715 2716/* 2717 * Routine: pmap_change_wiring 2718 * Function: Change the wiring attribute for a map/virtual-address 2719 * pair. 2720 * In/out conditions: 2721 * The mapping must already exist in the pmap. 2722 */ 2723void 2724pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2725{ 2726 pt_entry_t *pte; 2727 2728 PMAP_LOCK(pmap); 2729 pte = pmap_pte(pmap, va); 2730 2731 if (wired && !pmap_pte_w(pte)) 2732 pmap->pm_stats.wired_count++; 2733 else if (!wired && pmap_pte_w(pte)) 2734 pmap->pm_stats.wired_count--; 2735 2736 /* 2737 * Wiring is not a hardware characteristic so there is no need to 2738 * invalidate TLB. 2739 */ 2740 pmap_pte_set_w(pte, wired); 2741 pmap_pte_release(pte); 2742 PMAP_UNLOCK(pmap); 2743} 2744 2745 2746 2747/* 2748 * Copy the range specified by src_addr/len 2749 * from the source map to the range dst_addr/len 2750 * in the destination map. 2751 * 2752 * This routine is only advisory and need not do anything. 2753 */ 2754 2755void 2756pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 2757 vm_offset_t src_addr) 2758{ 2759 vm_page_t free; 2760 vm_offset_t addr; 2761 vm_offset_t end_addr = src_addr + len; 2762 vm_offset_t pdnxt; 2763 2764 if (dst_addr != src_addr) 2765 return; 2766 2767 if (!pmap_is_current(src_pmap)) 2768 return; 2769 2770 vm_page_lock_queues(); 2771 if (dst_pmap < src_pmap) { 2772 PMAP_LOCK(dst_pmap); 2773 PMAP_LOCK(src_pmap); 2774 } else { 2775 PMAP_LOCK(src_pmap); 2776 PMAP_LOCK(dst_pmap); 2777 } 2778 sched_pin(); 2779 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 2780 pt_entry_t *src_pte, *dst_pte; 2781 vm_page_t dstmpte, srcmpte; 2782 pd_entry_t srcptepaddr; 2783 unsigned ptepindex; 2784 2785 KASSERT(addr < UPT_MIN_ADDRESS, 2786 ("pmap_copy: invalid to pmap_copy page tables")); 2787 2788 pdnxt = (addr + NBPDR) & ~PDRMASK; 2789 if (pdnxt < addr) 2790 pdnxt = end_addr; 2791 ptepindex = addr >> PDRSHIFT; 2792 2793 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 2794 if (srcptepaddr == 0) 2795 continue; 2796 2797 if (srcptepaddr & PG_PS) { 2798 if (dst_pmap->pm_pdir[ptepindex] == 0) { 2799 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 2800 ~PG_W; 2801 dst_pmap->pm_stats.resident_count += 2802 NBPDR / PAGE_SIZE; 2803 } 2804 continue; 2805 } 2806 2807 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 2808 KASSERT(srcmpte->wire_count > 0, 2809 ("pmap_copy: source page table page is unused")); 2810 2811 if (pdnxt > end_addr) 2812 pdnxt = end_addr; 2813 2814 src_pte = vtopte(addr); 2815 while (addr < pdnxt) { 2816 pt_entry_t ptetemp; 2817 ptetemp = *src_pte; 2818 /* 2819 * we only virtual copy managed pages 2820 */ 2821 if ((ptetemp & PG_MANAGED) != 0) { 2822 dstmpte = pmap_allocpte(dst_pmap, addr, 2823 M_NOWAIT); 2824 if (dstmpte == NULL) 2825 break; 2826 dst_pte = pmap_pte_quick(dst_pmap, addr); 2827 if (*dst_pte == 0 && 2828 pmap_try_insert_pv_entry(dst_pmap, addr, 2829 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 2830 /* 2831 * Clear the wired, modified, and 2832 * accessed (referenced) bits 2833 * during the copy. 2834 */ 2835 *dst_pte = ptetemp & ~(PG_W | PG_M | 2836 PG_A); 2837 dst_pmap->pm_stats.resident_count++; 2838 } else { 2839 free = NULL; 2840 if (pmap_unwire_pte_hold( dst_pmap, 2841 dstmpte, &free)) { 2842 pmap_invalidate_page(dst_pmap, 2843 addr); 2844 pmap_free_zero_pages(free); 2845 } 2846 } 2847 if (dstmpte->wire_count >= srcmpte->wire_count) 2848 break; 2849 } 2850 addr += PAGE_SIZE; 2851 src_pte++; 2852 } 2853 } 2854 sched_unpin(); 2855 vm_page_unlock_queues(); 2856 PMAP_UNLOCK(src_pmap); 2857 PMAP_UNLOCK(dst_pmap); 2858} 2859 2860static __inline void 2861pagezero(void *page) 2862{ 2863#if defined(I686_CPU) 2864 if (cpu_class == CPUCLASS_686) { 2865#if defined(CPU_ENABLE_SSE) 2866 if (cpu_feature & CPUID_SSE2) 2867 sse2_pagezero(page); 2868 else 2869#endif 2870 i686_pagezero(page); 2871 } else 2872#endif 2873 bzero(page, PAGE_SIZE); 2874} 2875 2876/* 2877 * pmap_zero_page zeros the specified hardware page by mapping 2878 * the page into KVM and using bzero to clear its contents. 2879 */ 2880void 2881pmap_zero_page(vm_page_t m) 2882{ 2883 struct sysmaps *sysmaps; 2884 2885 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2886 mtx_lock(&sysmaps->lock); 2887 if (*sysmaps->CMAP2) 2888 panic("pmap_zero_page: CMAP2 busy"); 2889 sched_pin(); 2890 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 2891 invlcaddr(sysmaps->CADDR2); 2892 pagezero(sysmaps->CADDR2); 2893 *sysmaps->CMAP2 = 0; 2894 sched_unpin(); 2895 mtx_unlock(&sysmaps->lock); 2896} 2897 2898/* 2899 * pmap_zero_page_area zeros the specified hardware page by mapping 2900 * the page into KVM and using bzero to clear its contents. 2901 * 2902 * off and size may not cover an area beyond a single hardware page. 2903 */ 2904void 2905pmap_zero_page_area(vm_page_t m, int off, int size) 2906{ 2907 struct sysmaps *sysmaps; 2908 2909 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2910 mtx_lock(&sysmaps->lock); 2911 if (*sysmaps->CMAP2) 2912 panic("pmap_zero_page: CMAP2 busy"); 2913 sched_pin(); 2914 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 2915 invlcaddr(sysmaps->CADDR2); 2916 if (off == 0 && size == PAGE_SIZE) 2917 pagezero(sysmaps->CADDR2); 2918 else 2919 bzero((char *)sysmaps->CADDR2 + off, size); 2920 *sysmaps->CMAP2 = 0; 2921 sched_unpin(); 2922 mtx_unlock(&sysmaps->lock); 2923} 2924 2925/* 2926 * pmap_zero_page_idle zeros the specified hardware page by mapping 2927 * the page into KVM and using bzero to clear its contents. This 2928 * is intended to be called from the vm_pagezero process only and 2929 * outside of Giant. 2930 */ 2931void 2932pmap_zero_page_idle(vm_page_t m) 2933{ 2934 2935 if (*CMAP3) 2936 panic("pmap_zero_page: CMAP3 busy"); 2937 sched_pin(); 2938 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 2939 invlcaddr(CADDR3); 2940 pagezero(CADDR3); 2941 *CMAP3 = 0; 2942 sched_unpin(); 2943} 2944 2945/* 2946 * pmap_copy_page copies the specified (machine independent) 2947 * page by mapping the page into virtual memory and using 2948 * bcopy to copy the page, one machine dependent page at a 2949 * time. 2950 */ 2951void 2952pmap_copy_page(vm_page_t src, vm_page_t dst) 2953{ 2954 struct sysmaps *sysmaps; 2955 2956 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2957 mtx_lock(&sysmaps->lock); 2958 if (*sysmaps->CMAP1) 2959 panic("pmap_copy_page: CMAP1 busy"); 2960 if (*sysmaps->CMAP2) 2961 panic("pmap_copy_page: CMAP2 busy"); 2962 sched_pin(); 2963 invlpg((u_int)sysmaps->CADDR1); 2964 invlpg((u_int)sysmaps->CADDR2); 2965 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A; 2966 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M; 2967 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 2968 *sysmaps->CMAP1 = 0; 2969 *sysmaps->CMAP2 = 0; 2970 sched_unpin(); 2971 mtx_unlock(&sysmaps->lock); 2972} 2973 2974/* 2975 * Returns true if the pmap's pv is one of the first 2976 * 16 pvs linked to from this page. This count may 2977 * be changed upwards or downwards in the future; it 2978 * is only necessary that true be returned for a small 2979 * subset of pmaps for proper page aging. 2980 */ 2981boolean_t 2982pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2983{ 2984 pv_entry_t pv; 2985 int loops = 0; 2986 2987 if (m->flags & PG_FICTITIOUS) 2988 return FALSE; 2989 2990 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2991 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2992 if (PV_PMAP(pv) == pmap) { 2993 return TRUE; 2994 } 2995 loops++; 2996 if (loops >= 16) 2997 break; 2998 } 2999 return (FALSE); 3000} 3001 3002/* 3003 * pmap_page_wired_mappings: 3004 * 3005 * Return the number of managed mappings to the given physical page 3006 * that are wired. 3007 */ 3008int 3009pmap_page_wired_mappings(vm_page_t m) 3010{ 3011 pv_entry_t pv; 3012 pt_entry_t *pte; 3013 pmap_t pmap; 3014 int count; 3015 3016 count = 0; 3017 if ((m->flags & PG_FICTITIOUS) != 0) 3018 return (count); 3019 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3020 sched_pin(); 3021 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3022 pmap = PV_PMAP(pv); 3023 PMAP_LOCK(pmap); 3024 pte = pmap_pte_quick(pmap, pv->pv_va); 3025 if ((*pte & PG_W) != 0) 3026 count++; 3027 PMAP_UNLOCK(pmap); 3028 } 3029 sched_unpin(); 3030 return (count); 3031} 3032 3033/* 3034 * Remove all pages from specified address space 3035 * this aids process exit speeds. Also, this code 3036 * is special cased for current process only, but 3037 * can have the more generic (and slightly slower) 3038 * mode enabled. This is much faster than pmap_remove 3039 * in the case of running down an entire address space. 3040 */ 3041void 3042pmap_remove_pages(pmap_t pmap) 3043{ 3044 pt_entry_t *pte, tpte; 3045 vm_page_t m, free = NULL; 3046 pv_entry_t pv; 3047 struct pv_chunk *pc, *npc; 3048 int field, idx; 3049 int32_t bit; 3050 uint32_t inuse, bitmask; 3051 int allfree; 3052 3053 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3054 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3055 return; 3056 } 3057 vm_page_lock_queues(); 3058 PMAP_LOCK(pmap); 3059 sched_pin(); 3060 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3061 allfree = 1; 3062 for (field = 0; field < _NPCM; field++) { 3063 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3064 while (inuse != 0) { 3065 bit = bsfl(inuse); 3066 bitmask = 1UL << bit; 3067 idx = field * 32 + bit; 3068 pv = &pc->pc_pventry[idx]; 3069 inuse &= ~bitmask; 3070 3071 pte = vtopte(pv->pv_va); 3072 tpte = *pte; 3073 3074 if (tpte == 0) { 3075 printf( 3076 "TPTE at %p IS ZERO @ VA %08x\n", 3077 pte, pv->pv_va); 3078 panic("bad pte"); 3079 } 3080 3081/* 3082 * We cannot remove wired pages from a process' mapping at this time 3083 */ 3084 if (tpte & PG_W) { 3085 allfree = 0; 3086 continue; 3087 } 3088 3089 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3090 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3091 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3092 m, (uintmax_t)m->phys_addr, 3093 (uintmax_t)tpte)); 3094 3095 KASSERT(m < &vm_page_array[vm_page_array_size], 3096 ("pmap_remove_pages: bad tpte %#jx", 3097 (uintmax_t)tpte)); 3098 3099 pmap->pm_stats.resident_count--; 3100 3101 pte_clear(pte); 3102 3103 /* 3104 * Update the vm_page_t clean/reference bits. 3105 */ 3106 if (tpte & PG_M) 3107 vm_page_dirty(m); 3108 3109 /* Mark free */ 3110 PV_STAT(pv_entry_frees++); 3111 PV_STAT(pv_entry_spare++); 3112 pv_entry_count--; 3113 pc->pc_map[field] |= bitmask; 3114 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3115 if (TAILQ_EMPTY(&m->md.pv_list)) 3116 vm_page_flag_clear(m, PG_WRITEABLE); 3117 3118 pmap_unuse_pt(pmap, pv->pv_va, &free); 3119 } 3120 } 3121 if (allfree) { 3122 PV_STAT(pv_entry_spare -= _NPCPV); 3123 PV_STAT(pc_chunk_count--); 3124 PV_STAT(pc_chunk_frees++); 3125 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3126 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3127 pmap_qremove((vm_offset_t)pc, 1); 3128 vm_page_unwire(m, 0); 3129 vm_page_free(m); 3130 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3131 } 3132 } 3133 sched_unpin(); 3134 pmap_invalidate_all(pmap); 3135 vm_page_unlock_queues(); 3136 PMAP_UNLOCK(pmap); 3137 pmap_free_zero_pages(free); 3138} 3139 3140/* 3141 * pmap_is_modified: 3142 * 3143 * Return whether or not the specified physical page was modified 3144 * in any physical maps. 3145 */ 3146boolean_t 3147pmap_is_modified(vm_page_t m) 3148{ 3149 pv_entry_t pv; 3150 pt_entry_t *pte; 3151 pmap_t pmap; 3152 boolean_t rv; 3153 3154 rv = FALSE; 3155 if (m->flags & PG_FICTITIOUS) 3156 return (rv); 3157 3158 sched_pin(); 3159 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3160 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3161 pmap = PV_PMAP(pv); 3162 PMAP_LOCK(pmap); 3163 pte = pmap_pte_quick(pmap, pv->pv_va); 3164 rv = (*pte & PG_M) != 0; 3165 PMAP_UNLOCK(pmap); 3166 if (rv) 3167 break; 3168 } 3169 sched_unpin(); 3170 return (rv); 3171} 3172 3173/* 3174 * pmap_is_prefaultable: 3175 * 3176 * Return whether or not the specified virtual address is elgible 3177 * for prefault. 3178 */ 3179boolean_t 3180pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3181{ 3182 pt_entry_t *pte; 3183 boolean_t rv; 3184 3185 rv = FALSE; 3186 PMAP_LOCK(pmap); 3187 if (*pmap_pde(pmap, addr)) { 3188 pte = vtopte(addr); 3189 rv = *pte == 0; 3190 } 3191 PMAP_UNLOCK(pmap); 3192 return (rv); 3193} 3194 3195/* 3196 * Clear the write and modified bits in each of the given page's mappings. 3197 */ 3198void 3199pmap_remove_write(vm_page_t m) 3200{ 3201 pv_entry_t pv; 3202 pmap_t pmap; 3203 pt_entry_t oldpte, *pte; 3204 3205 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3206 if ((m->flags & PG_FICTITIOUS) != 0 || 3207 (m->flags & PG_WRITEABLE) == 0) 3208 return; 3209 sched_pin(); 3210 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3211 pmap = PV_PMAP(pv); 3212 PMAP_LOCK(pmap); 3213 pte = pmap_pte_quick(pmap, pv->pv_va); 3214retry: 3215 oldpte = *pte; 3216 if ((oldpte & PG_RW) != 0) { 3217 /* 3218 * Regardless of whether a pte is 32 or 64 bits 3219 * in size, PG_RW and PG_M are among the least 3220 * significant 32 bits. 3221 */ 3222 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3223 oldpte & ~(PG_RW | PG_M))) 3224 goto retry; 3225 if ((oldpte & PG_M) != 0) 3226 vm_page_dirty(m); 3227 pmap_invalidate_page(pmap, pv->pv_va); 3228 } 3229 PMAP_UNLOCK(pmap); 3230 } 3231 vm_page_flag_clear(m, PG_WRITEABLE); 3232 sched_unpin(); 3233} 3234 3235/* 3236 * pmap_ts_referenced: 3237 * 3238 * Return a count of reference bits for a page, clearing those bits. 3239 * It is not necessary for every reference bit to be cleared, but it 3240 * is necessary that 0 only be returned when there are truly no 3241 * reference bits set. 3242 * 3243 * XXX: The exact number of bits to check and clear is a matter that 3244 * should be tested and standardized at some point in the future for 3245 * optimal aging of shared pages. 3246 */ 3247int 3248pmap_ts_referenced(vm_page_t m) 3249{ 3250 pv_entry_t pv, pvf, pvn; 3251 pmap_t pmap; 3252 pt_entry_t *pte; 3253 int rtval = 0; 3254 3255 if (m->flags & PG_FICTITIOUS) 3256 return (rtval); 3257 sched_pin(); 3258 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3259 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3260 pvf = pv; 3261 do { 3262 pvn = TAILQ_NEXT(pv, pv_list); 3263 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3264 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3265 pmap = PV_PMAP(pv); 3266 PMAP_LOCK(pmap); 3267 pte = pmap_pte_quick(pmap, pv->pv_va); 3268 if ((*pte & PG_A) != 0) { 3269 atomic_clear_int((u_int *)pte, PG_A); 3270 pmap_invalidate_page(pmap, pv->pv_va); 3271 rtval++; 3272 if (rtval > 4) 3273 pvn = NULL; 3274 } 3275 PMAP_UNLOCK(pmap); 3276 } while ((pv = pvn) != NULL && pv != pvf); 3277 } 3278 sched_unpin(); 3279 return (rtval); 3280} 3281 3282/* 3283 * Clear the modify bits on the specified physical page. 3284 */ 3285void 3286pmap_clear_modify(vm_page_t m) 3287{ 3288 pv_entry_t pv; 3289 pmap_t pmap; 3290 pt_entry_t *pte; 3291 3292 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3293 if ((m->flags & PG_FICTITIOUS) != 0) 3294 return; 3295 sched_pin(); 3296 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3297 pmap = PV_PMAP(pv); 3298 PMAP_LOCK(pmap); 3299 pte = pmap_pte_quick(pmap, pv->pv_va); 3300 if ((*pte & PG_M) != 0) { 3301 /* 3302 * Regardless of whether a pte is 32 or 64 bits 3303 * in size, PG_M is among the least significant 3304 * 32 bits. 3305 */ 3306 atomic_clear_int((u_int *)pte, PG_M); 3307 pmap_invalidate_page(pmap, pv->pv_va); 3308 } 3309 PMAP_UNLOCK(pmap); 3310 } 3311 sched_unpin(); 3312} 3313 3314/* 3315 * pmap_clear_reference: 3316 * 3317 * Clear the reference bit on the specified physical page. 3318 */ 3319void 3320pmap_clear_reference(vm_page_t m) 3321{ 3322 pv_entry_t pv; 3323 pmap_t pmap; 3324 pt_entry_t *pte; 3325 3326 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3327 if ((m->flags & PG_FICTITIOUS) != 0) 3328 return; 3329 sched_pin(); 3330 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3331 pmap = PV_PMAP(pv); 3332 PMAP_LOCK(pmap); 3333 pte = pmap_pte_quick(pmap, pv->pv_va); 3334 if ((*pte & PG_A) != 0) { 3335 /* 3336 * Regardless of whether a pte is 32 or 64 bits 3337 * in size, PG_A is among the least significant 3338 * 32 bits. 3339 */ 3340 atomic_clear_int((u_int *)pte, PG_A); 3341 pmap_invalidate_page(pmap, pv->pv_va); 3342 } 3343 PMAP_UNLOCK(pmap); 3344 } 3345 sched_unpin(); 3346} 3347 3348/* 3349 * Miscellaneous support routines follow 3350 */ 3351 3352/* 3353 * Map a set of physical memory pages into the kernel virtual 3354 * address space. Return a pointer to where it is mapped. This 3355 * routine is intended to be used for mapping device memory, 3356 * NOT real memory. 3357 */ 3358void * 3359pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3360{ 3361 vm_offset_t va, tmpva, offset; 3362 3363 offset = pa & PAGE_MASK; 3364 size = roundup(offset + size, PAGE_SIZE); 3365 pa = pa & PG_FRAME; 3366 3367 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3368 va = KERNBASE + pa; 3369 else 3370 va = kmem_alloc_nofault(kernel_map, size); 3371 if (!va) 3372 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3373 3374 for (tmpva = va; size > 0; ) { 3375 pmap_kenter_attr(tmpva, pa, mode); 3376 size -= PAGE_SIZE; 3377 tmpva += PAGE_SIZE; 3378 pa += PAGE_SIZE; 3379 } 3380 pmap_invalidate_range(kernel_pmap, va, tmpva); 3381 pmap_invalidate_cache(); 3382 return ((void *)(va + offset)); 3383} 3384 3385void * 3386pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3387{ 3388 3389 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3390} 3391 3392void * 3393pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3394{ 3395 3396 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3397} 3398 3399void 3400pmap_unmapdev(vm_offset_t va, vm_size_t size) 3401{ 3402 vm_offset_t base, offset, tmpva; 3403 3404 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3405 return; 3406 base = trunc_page(va); 3407 offset = va & PAGE_MASK; 3408 size = roundup(offset + size, PAGE_SIZE); 3409 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3410 pmap_kremove(tmpva); 3411 pmap_invalidate_range(kernel_pmap, va, tmpva); 3412 kmem_free(kernel_map, base, size); 3413} 3414 3415int 3416pmap_change_attr(va, size, mode) 3417 vm_offset_t va; 3418 vm_size_t size; 3419 int mode; 3420{ 3421 vm_offset_t base, offset, tmpva; 3422 pt_entry_t *pte; 3423 u_int opte, npte; 3424 pd_entry_t *pde; 3425 3426 base = trunc_page(va); 3427 offset = va & PAGE_MASK; 3428 size = roundup(offset + size, PAGE_SIZE); 3429 3430 /* Only supported on kernel virtual addresses. */ 3431 if (base <= VM_MAXUSER_ADDRESS) 3432 return (EINVAL); 3433 3434 /* 4MB pages and pages that aren't mapped aren't supported. */ 3435 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 3436 pde = pmap_pde(kernel_pmap, tmpva); 3437 if (*pde & PG_PS) 3438 return (EINVAL); 3439 if (*pde == 0) 3440 return (EINVAL); 3441 pte = vtopte(va); 3442 if (*pte == 0) 3443 return (EINVAL); 3444 } 3445 3446 /* 3447 * Ok, all the pages exist and are 4k, so run through them updating 3448 * their cache mode. 3449 */ 3450 for (tmpva = base; size > 0; ) { 3451 pte = vtopte(tmpva); 3452 3453 /* 3454 * The cache mode bits are all in the low 32-bits of the 3455 * PTE, so we can just spin on updating the low 32-bits. 3456 */ 3457 do { 3458 opte = *(u_int *)pte; 3459 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 3460 npte |= pmap_cache_bits(mode, 0); 3461 } while (npte != opte && 3462 !atomic_cmpset_int((u_int *)pte, opte, npte)); 3463 tmpva += PAGE_SIZE; 3464 size -= PAGE_SIZE; 3465 } 3466 3467 /* 3468 * Flush CPU caches to make sure any data isn't cached that shouldn't 3469 * be, etc. 3470 */ 3471 pmap_invalidate_range(kernel_pmap, base, tmpva); 3472 pmap_invalidate_cache(); 3473 return (0); 3474} 3475 3476/* 3477 * perform the pmap work for mincore 3478 */ 3479int 3480pmap_mincore(pmap_t pmap, vm_offset_t addr) 3481{ 3482 pt_entry_t *ptep, pte; 3483 vm_page_t m; 3484 int val = 0; 3485 3486 PMAP_LOCK(pmap); 3487 ptep = pmap_pte(pmap, addr); 3488 pte = (ptep != NULL) ? *ptep : 0; 3489 pmap_pte_release(ptep); 3490 PMAP_UNLOCK(pmap); 3491 3492 if (pte != 0) { 3493 vm_paddr_t pa; 3494 3495 val = MINCORE_INCORE; 3496 if ((pte & PG_MANAGED) == 0) 3497 return val; 3498 3499 pa = pte & PG_FRAME; 3500 3501 m = PHYS_TO_VM_PAGE(pa); 3502 3503 /* 3504 * Modified by us 3505 */ 3506 if (pte & PG_M) 3507 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER; 3508 else { 3509 /* 3510 * Modified by someone else 3511 */ 3512 vm_page_lock_queues(); 3513 if (m->dirty || pmap_is_modified(m)) 3514 val |= MINCORE_MODIFIED_OTHER; 3515 vm_page_unlock_queues(); 3516 } 3517 /* 3518 * Referenced by us 3519 */ 3520 if (pte & PG_A) 3521 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER; 3522 else { 3523 /* 3524 * Referenced by someone else 3525 */ 3526 vm_page_lock_queues(); 3527 if ((m->flags & PG_REFERENCED) || 3528 pmap_ts_referenced(m)) { 3529 val |= MINCORE_REFERENCED_OTHER; 3530 vm_page_flag_set(m, PG_REFERENCED); 3531 } 3532 vm_page_unlock_queues(); 3533 } 3534 } 3535 return val; 3536} 3537 3538void 3539pmap_activate(struct thread *td) 3540{ 3541 pmap_t pmap, oldpmap; 3542 u_int32_t cr3; 3543 3544 critical_enter(); 3545 pmap = vmspace_pmap(td->td_proc->p_vmspace); 3546 oldpmap = PCPU_GET(curpmap); 3547#if defined(SMP) 3548 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 3549 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 3550#else 3551 oldpmap->pm_active &= ~1; 3552 pmap->pm_active |= 1; 3553#endif 3554#ifdef PAE 3555 cr3 = vtophys(pmap->pm_pdpt); 3556#else 3557 cr3 = vtophys(pmap->pm_pdir); 3558#endif 3559 /* 3560 * pmap_activate is for the current thread on the current cpu 3561 */ 3562 td->td_pcb->pcb_cr3 = cr3; 3563 load_cr3(cr3); 3564 PCPU_SET(curpmap, pmap); 3565 critical_exit(); 3566} 3567 3568vm_offset_t 3569pmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size) 3570{ 3571 3572 if ((obj == NULL) || (size < NBPDR) || (obj->type != OBJT_DEVICE)) { 3573 return addr; 3574 } 3575 3576 addr = (addr + PDRMASK) & ~PDRMASK; 3577 return addr; 3578} 3579 3580 3581#if defined(PMAP_DEBUG) 3582pmap_pid_dump(int pid) 3583{ 3584 pmap_t pmap; 3585 struct proc *p; 3586 int npte = 0; 3587 int index; 3588 3589 sx_slock(&allproc_lock); 3590 FOREACH_PROC_IN_SYSTEM(p) { 3591 if (p->p_pid != pid) 3592 continue; 3593 3594 if (p->p_vmspace) { 3595 int i,j; 3596 index = 0; 3597 pmap = vmspace_pmap(p->p_vmspace); 3598 for (i = 0; i < NPDEPTD; i++) { 3599 pd_entry_t *pde; 3600 pt_entry_t *pte; 3601 vm_offset_t base = i << PDRSHIFT; 3602 3603 pde = &pmap->pm_pdir[i]; 3604 if (pde && pmap_pde_v(pde)) { 3605 for (j = 0; j < NPTEPG; j++) { 3606 vm_offset_t va = base + (j << PAGE_SHIFT); 3607 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 3608 if (index) { 3609 index = 0; 3610 printf("\n"); 3611 } 3612 sx_sunlock(&allproc_lock); 3613 return npte; 3614 } 3615 pte = pmap_pte(pmap, va); 3616 if (pte && pmap_pte_v(pte)) { 3617 pt_entry_t pa; 3618 vm_page_t m; 3619 pa = *pte; 3620 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 3621 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 3622 va, pa, m->hold_count, m->wire_count, m->flags); 3623 npte++; 3624 index++; 3625 if (index >= 2) { 3626 index = 0; 3627 printf("\n"); 3628 } else { 3629 printf(" "); 3630 } 3631 } 3632 } 3633 } 3634 } 3635 } 3636 } 3637 sx_sunlock(&allproc_lock); 3638 return npte; 3639} 3640#endif 3641 3642#if defined(DEBUG) 3643 3644static void pads(pmap_t pm); 3645void pmap_pvdump(vm_offset_t pa); 3646 3647/* print address space of pmap*/ 3648static void 3649pads(pmap_t pm) 3650{ 3651 int i, j; 3652 vm_paddr_t va; 3653 pt_entry_t *ptep; 3654 3655 if (pm == kernel_pmap) 3656 return; 3657 for (i = 0; i < NPDEPTD; i++) 3658 if (pm->pm_pdir[i]) 3659 for (j = 0; j < NPTEPG; j++) { 3660 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 3661 if (pm == kernel_pmap && va < KERNBASE) 3662 continue; 3663 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 3664 continue; 3665 ptep = pmap_pte(pm, va); 3666 if (pmap_pte_v(ptep)) 3667 printf("%x:%x ", va, *ptep); 3668 }; 3669 3670} 3671 3672void 3673pmap_pvdump(vm_paddr_t pa) 3674{ 3675 pv_entry_t pv; 3676 pmap_t pmap; 3677 vm_page_t m; 3678 3679 printf("pa %x", pa); 3680 m = PHYS_TO_VM_PAGE(pa); 3681 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3682 pmap = PV_PMAP(pv); 3683 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 3684 pads(pmap); 3685 } 3686 printf(" "); 3687} 3688#endif 3689