if_xlreg.h revision 49010
1191783Srmacklem/* 2191783Srmacklem * Copyright (c) 1997, 1998 3191783Srmacklem * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4191783Srmacklem * 5191783Srmacklem * Redistribution and use in source and binary forms, with or without 6191783Srmacklem * modification, are permitted provided that the following conditions 7191783Srmacklem * are met: 8191783Srmacklem * 1. Redistributions of source code must retain the above copyright 9191783Srmacklem * notice, this list of conditions and the following disclaimer. 10191783Srmacklem * 2. Redistributions in binary form must reproduce the above copyright 11191783Srmacklem * notice, this list of conditions and the following disclaimer in the 12191783Srmacklem * documentation and/or other materials provided with the distribution. 13191783Srmacklem * 3. All advertising materials mentioning features or use of this software 14191783Srmacklem * must display the following acknowledgement: 15191783Srmacklem * This product includes software developed by Bill Paul. 16191783Srmacklem * 4. Neither the name of the author nor the names of any co-contributors 17191783Srmacklem * may be used to endorse or promote products derived from this software 18191783Srmacklem * without specific prior written permission. 19191783Srmacklem * 20191783Srmacklem * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21191783Srmacklem * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22191783Srmacklem * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23191783Srmacklem * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24191783Srmacklem * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25191783Srmacklem * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26191783Srmacklem * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27191783Srmacklem * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28191783Srmacklem * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29191783Srmacklem * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30191783Srmacklem * THE POSSIBILITY OF SUCH DAMAGE. 31191783Srmacklem * 32191783Srmacklem * $Id: if_xlreg.h,v 1.17 1999/05/30 18:09:17 wpaul Exp $ 33191783Srmacklem */ 34191783Srmacklem 35191783Srmacklem#define XL_EE_READ 0x0080 /* read, 5 bit address */ 36191783Srmacklem#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 37191783Srmacklem#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 38223280Srmacklem#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 39223280Srmacklem#define XL_EE_BUSY 0x8000 40191783Srmacklem 41191783Srmacklem#define XL_EE_EADDR0 0x00 /* station address, first word */ 42191783Srmacklem#define XL_EE_EADDR1 0x01 /* station address, next word, */ 43191783Srmacklem#define XL_EE_EADDR2 0x02 /* station address, last word */ 44191783Srmacklem#define XL_EE_PRODID 0x03 /* product ID code */ 45191783Srmacklem#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 46191783Srmacklem#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 47191783Srmacklem#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 48191783Srmacklem#define XL_EE_MFG_ID 0x07 49191783Srmacklem#define XL_EE_PCI_PARM 0x08 50240238Skib#define XL_EE_ROM_ONFO 0x09 51191783Srmacklem#define XL_EE_OEM_ADR0 0x0A 52191783Srmacklem#define XL_EE_OEM_ADR1 0x0B 53191783Srmacklem#define XL_EE_OEM_ADR2 0x0C 54191783Srmacklem#define XL_EE_SOFTINFO1 0x0D 55191783Srmacklem#define XL_EE_COMPAT 0x0E 56191783Srmacklem#define XL_EE_SOFTINFO2 0x0F 57191783Srmacklem#define XL_EE_CAPS 0x10 /* capabilities word */ 58191783Srmacklem#define XL_EE_RSVD0 0x11 59191783Srmacklem#define XL_EE_ICFG_0 0x12 60191783Srmacklem#define XL_EE_ICFG_1 0x13 61223280Srmacklem#define XL_EE_RSVD1 0x14 62191783Srmacklem#define XL_EE_SOFTINFO3 0x15 63191783Srmacklem#define XL_EE_RSVD_2 0x16 64191783Srmacklem 65191783Srmacklem/* 66191783Srmacklem * Bits in the capabilities word 67220683Srmacklem */ 68220683Srmacklem#define XL_CAPS_PNP 0x0001 69191783Srmacklem#define XL_CAPS_FULL_DUPLEX 0x0002 70233730Skib#define XL_CAPS_LARGE_PKTS 0x0004 71191783Srmacklem#define XL_CAPS_SLAVE_DMA 0x0008 72191783Srmacklem#define XL_CAPS_SECOND_DMA 0x0010 73191783Srmacklem#define XL_CAPS_FULL_BM 0x0020 74191783Srmacklem#define XL_CAPS_FRAG_BM 0x0040 75191783Srmacklem#define XL_CAPS_CRC_PASSTHRU 0x0080 76249077Skib#define XL_CAPS_TXDONE 0x0100 77191783Srmacklem#define XL_CAPS_NO_TXLENGTH 0x0200 78191783Srmacklem#define XL_CAPS_RX_REPEAT 0x0400 79191783Srmacklem#define XL_CAPS_SNOOPING 0x0800 80191783Srmacklem#define XL_CAPS_100MBPS 0x1000 81191783Srmacklem#define XL_CAPS_PWRMGMT 0x2000 82191783Srmacklem 83191783Srmacklem#define XL_PACKET_SIZE 1536 84191783Srmacklem 85191783Srmacklem/* 86191783Srmacklem * Register layouts. 87191783Srmacklem */ 88191783Srmacklem#define XL_COMMAND 0x0E 89191783Srmacklem#define XL_STATUS 0x0E 90191783Srmacklem 91191783Srmacklem#define XL_TX_STATUS 0x1B 92191783Srmacklem#define XL_TX_FREE 0x1C 93191783Srmacklem#define XL_DMACTL 0x20 94191783Srmacklem#define XL_DOWNLIST_PTR 0x24 95191783Srmacklem#define XL_TX_FREETHRESH 0x2F 96191783Srmacklem#define XL_UPLIST_PTR 0x38 97191783Srmacklem#define XL_UPLIST_STATUS 0x30 98191783Srmacklem 99191783Srmacklem#define XL_PKTSTAT_UP_STALLED 0x00002000 100191783Srmacklem#define XL_PKTSTAT_UP_ERROR 0x00004000 101191783Srmacklem#define XL_PKTSTAT_UP_CMPLT 0x00008000 102191783Srmacklem 103191783Srmacklem#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 104191783Srmacklem#define XL_DMACTL_DOWN_STALLED 0x00000004 105191783Srmacklem#define XL_DMACTL_UP_CMPLT 0x00000008 106191783Srmacklem#define XL_DMACTL_DOWN_CMPLT 0x00000010 107191783Srmacklem#define XL_DMACTL_UP_RX_EARLY 0x00000020 108194425Salc#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 109191783Srmacklem#define XL_DMACTL_DOWN_INPROG 0x00000080 110191783Srmacklem#define XL_DMACTL_COUNTER_SPEED 0x00000100 111191783Srmacklem#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 112191783Srmacklem#define XL_DMACTL_TARGET_ABORT 0x40000000 113191783Srmacklem#define XL_DMACTL_MASTER_ABORT 0x80000000 114191783Srmacklem 115191783Srmacklem/* 116194425Salc * Command codes. Some command codes require that we wait for 117191783Srmacklem * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 118191783Srmacklem */ 119191783Srmacklem#define XL_CMD_RESET 0x0000 /* mustwait */ 120191783Srmacklem#define XL_CMD_WINSEL 0x0800 121191783Srmacklem#define XL_CMD_COAX_START 0x1000 122191783Srmacklem#define XL_CMD_RX_DISABLE 0x1800 123249077Skib#define XL_CMD_RX_ENABLE 0x2000 124191783Srmacklem#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 125191783Srmacklem#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 126191783Srmacklem#define XL_CMD_UP_UNSTALL 0x3001 127191783Srmacklem#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 128191783Srmacklem#define XL_CMD_DOWN_UNSTALL 0x3003 129191783Srmacklem#define XL_CMD_RX_DISCARD 0x4000 130191783Srmacklem#define XL_CMD_TX_ENABLE 0x4800 131191783Srmacklem#define XL_CMD_TX_DISABLE 0x5000 132191783Srmacklem#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 133191783Srmacklem#define XL_CMD_INTR_FAKE 0x6000 134191783Srmacklem#define XL_CMD_INTR_ACK 0x6800 135191783Srmacklem#define XL_CMD_INTR_ENB 0x7000 136191783Srmacklem#define XL_CMD_STAT_ENB 0x7800 137194425Salc#define XL_CMD_RX_SET_FILT 0x8000 138194425Salc#define XL_CMD_RX_SET_THRESH 0x8800 139194425Salc#define XL_CMD_TX_SET_THRESH 0x9000 140207669Salc#define XL_CMD_TX_SET_START 0x9800 141207669Salc#define XL_CMD_DMA_UP 0xA000 142194425Salc#define XL_CMD_DMA_STOP 0xA001 143207669Salc#define XL_CMD_STATS_ENABLE 0xA800 144207669Salc#define XL_CMD_STATS_DISABLE 0xB000 145191783Srmacklem#define XL_CMD_COAX_STOP 0xB800 146191783Srmacklem 147194425Salc#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 148191783Srmacklem#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 149194425Salc 150191783Srmacklem#define XL_HASH_SET 0x0400 151191783Srmacklem#define XL_HASHFILT_SIZE 256 152191783Srmacklem 153191783Srmacklem/* 154191783Srmacklem * status codes 155191783Srmacklem * Note that bits 15 to 13 indicate the currently visible register window 156191783Srmacklem * which may be anything from 0 to 7. 157191783Srmacklem */ 158191783Srmacklem#define XL_STAT_INTLATCH 0x0001 /* 0 */ 159191783Srmacklem#define XL_STAT_ADFAIL 0x0002 /* 1 */ 160191783Srmacklem#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 161191783Srmacklem#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 162191783Srmacklem#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 163191783Srmacklem#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 164191783Srmacklem#define XL_STAT_INTREQ 0x0040 /* 6 */ 165191783Srmacklem#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 166191783Srmacklem#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 167191783Srmacklem#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 168191783Srmacklem#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 169191783Srmacklem#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 170191783Srmacklem#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 171191783Srmacklem#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 172191783Srmacklem 173191783Srmacklem/* 174191783Srmacklem * Interrupts we normally want enabled. 175191783Srmacklem */ 176191783Srmacklem#define XL_INTRS \ 177191783Srmacklem (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 178191783Srmacklem XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 179191783Srmacklem 180191783Srmacklem/* 181207669Salc * Window 0 registers 182207669Salc */ 183191783Srmacklem#define XL_W0_EE_DATA 0x0C 184207669Salc#define XL_W0_EE_CMD 0x0A 185207669Salc#define XL_W0_RSRC_CFG 0x08 186191783Srmacklem#define XL_W0_ADDR_CFG 0x06 187191783Srmacklem#define XL_W0_CFG_CTRL 0x04 188194425Salc 189191783Srmacklem#define XL_W0_PROD_ID 0x02 190191783Srmacklem#define XL_W0_MFG_ID 0x00 191191783Srmacklem 192191783Srmacklem/* 193191783Srmacklem * Window 1 194191783Srmacklem */ 195191783Srmacklem 196191783Srmacklem#define XL_W1_TX_FIFO 0x10 197191783Srmacklem 198191783Srmacklem#define XL_W1_FREE_TX 0x0C 199191783Srmacklem#define XL_W1_TX_STATUS 0x0B 200191783Srmacklem#define XL_W1_TX_TIMER 0x0A 201191783Srmacklem#define XL_W1_RX_STATUS 0x08 202191783Srmacklem#define XL_W1_RX_FIFO 0x00 203191783Srmacklem 204191783Srmacklem/* 205191783Srmacklem * RX status codes 206191783Srmacklem */ 207191783Srmacklem#define XL_RXSTATUS_OVERRUN 0x01 208191783Srmacklem#define XL_RXSTATUS_RUNT 0x02 209192065Srmacklem#define XL_RXSTATUS_ALIGN 0x04 210192065Srmacklem#define XL_RXSTATUS_CRC 0x08 211191783Srmacklem#define XL_RXSTATUS_OVERSIZE 0x10 212191783Srmacklem#define XL_RXSTATUS_DRIBBLE 0x20 213191783Srmacklem 214191783Srmacklem/* 215191783Srmacklem * TX status codes 216192231Srmacklem */ 217192986Salc#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 218192231Srmacklem#define XL_TXSTATUS_OVERFLOW 0x04 219191783Srmacklem#define XL_TXSTATUS_MAXCOLS 0x08 220191783Srmacklem#define XL_TXSTATUS_UNDERRUN 0x10 221239554Skib#define XL_TXSTATUS_JABBER 0x20 222239554Skib#define XL_TXSTATUS_INTREQ 0x40 223239554Skib#define XL_TXSTATUS_COMPLETE 0x80 224239554Skib 225239554Skib/* 226239554Skib * Window 2 227239554Skib */ 228191783Srmacklem#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 229191783Srmacklem#define XL_W2_STATION_MASK_HI 0x0A 230191783Srmacklem#define XL_W2_STATION_MASK_MID 0x08 231239554Skib#define XL_W2_STATION_MASK_LO 0x06 232239554Skib#define XL_W2_STATION_ADDR_HI 0x04 233191783Srmacklem#define XL_W2_STATION_ADDR_MID 0x02 234191783Srmacklem#define XL_W2_STATION_ADDR_LO 0x00 235194425Salc 236191783Srmacklem#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 237191783Srmacklem#define XL_RESETOPT_D3RESETDIS 0x0008 238191783Srmacklem#define XL_RESETOPT_DISADVFD 0x0010 239191783Srmacklem#define XL_RESETOPT_DISADV100 0x0020 240191783Srmacklem#define XL_RESETOPT_DISAUTONEG 0x0040 241191783Srmacklem#define XL_RESETOPT_DEBUGMODE 0x0080 242191783Srmacklem#define XL_RESETOPT_FASTAUTO 0x0100 243191783Srmacklem#define XL_RESETOPT_FASTEE 0x0200 244191783Srmacklem#define XL_RESETOPT_FORCEDCONF 0x0400 245191783Srmacklem#define XL_RESETOPT_TESTPDTPDR 0x0800 246191783Srmacklem#define XL_RESETOPT_TEST100TX 0x1000 247191783Srmacklem#define XL_RESETOPT_TEST100RX 0x2000 248191783Srmacklem 249191783Srmacklem/* 250191783Srmacklem * Window 3 (fifo management) 251191783Srmacklem */ 252191783Srmacklem#define XL_W3_INTERNAL_CFG 0x00 253191783Srmacklem#define XL_W3_RESET_OPT 0x08 254191783Srmacklem#define XL_W3_FREE_TX 0x0C 255191783Srmacklem#define XL_W3_FREE_RX 0x0A 256191783Srmacklem#define XL_W3_MAC_CTRL 0x06 257191783Srmacklem 258191783Srmacklem#define XL_ICFG_CONNECTOR_MASK 0x00F00000 259191783Srmacklem#define XL_ICFG_CONNECTOR_BITS 20 260191783Srmacklem 261236096Srmacklem#define XL_ICFG_RAMSIZE_MASK 0x00000007 262236096Srmacklem#define XL_ICFG_RAMWIDTH 0x00000008 263236096Srmacklem#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 264236096Srmacklem#define XL_ICFG_DISABLE_BASSD 0x00000100 265236096Srmacklem#define XL_ICFG_RAMLOC 0x00000200 266191783Srmacklem#define XL_ICFG_RAMPART (0x00010000|0x00020000) 267191783Srmacklem#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 268191783Srmacklem#define XL_ICFG_AUTOSEL 0x01000000 269191783Srmacklem 270191783Srmacklem#define XL_XCVR_10BT 0x00 271191783Srmacklem#define XL_XCVR_AUI 0x01 272249077Skib#define XL_XCVR_RSVD_0 0x02 273191783Srmacklem#define XL_XCVR_COAX 0x03 274191783Srmacklem#define XL_XCVR_100BTX 0x04 275191783Srmacklem#define XL_XCVR_100BFX 0x05 276191783Srmacklem#define XL_XCVR_MII 0x06 277191783Srmacklem#define XL_XCVR_RSVD_1 0x07 278191783Srmacklem#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 279191783Srmacklem 280191783Srmacklem#define XL_MACCTRL_DEFER_EXT_END 0x0001 281191783Srmacklem#define XL_MACCTRL_DEFER_0 0x0002 282249077Skib#define XL_MACCTRL_DEFER_1 0x0004 283191783Srmacklem#define XL_MACCTRL_DEFER_2 0x0008 284249077Skib#define XL_MACCTRL_DEFER_3 0x0010 285191783Srmacklem#define XL_MACCTRL_DUPLEX 0x0020 286191783Srmacklem#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 287191783Srmacklem#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 288191783Srmacklem#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 289191783Srmacklem#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 290222586Skib 291191783Srmacklem/* 292191783Srmacklem * The 'reset options' register contains power-on reset values 293191783Srmacklem * loaded from the EEPROM. This includes the supported media 294191783Srmacklem * types on the card. It is also known as the media options register. 295191783Srmacklem */ 296191783Srmacklem#define XL_W3_MEDIA_OPT 0x08 297191783Srmacklem 298191783Srmacklem#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 299191783Srmacklem#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 300191783Srmacklem#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 301191783Srmacklem#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 302191783Srmacklem#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 303191783Srmacklem#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 304191783Srmacklem#define XL_MEDIAOPT_MII 0x0040 /* MII */ 305191783Srmacklem#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 306191783Srmacklem 307191783Srmacklem#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 308191783Srmacklem#define XL_MEDIAOPT_MASK 0x01FF 309191783Srmacklem 310191783Srmacklem/* 311191783Srmacklem * Window 4 (diagnostics) 312191783Srmacklem */ 313191783Srmacklem#define XL_W4_UPPERBYTESOK 0x0D 314191783Srmacklem#define XL_W4_BADSSD 0x0C 315191783Srmacklem#define XL_W4_MEDIA_STATUS 0x0A 316191783Srmacklem#define XL_W4_PHY_MGMT 0x08 317191783Srmacklem#define XL_W4_NET_DIAG 0x06 318191783Srmacklem#define XL_W4_FIFO_DIAG 0x04 319191783Srmacklem#define XL_W4_VCO_DIAG 0x02 320191783Srmacklem 321191783Srmacklem#define XL_W4_CTRLR_STAT 0x08 322191783Srmacklem#define XL_W4_TX_DIAG 0x00 323191783Srmacklem 324191783Srmacklem#define XL_MII_CLK 0x01 325191783Srmacklem#define XL_MII_DATA 0x02 326191783Srmacklem#define XL_MII_DIR 0x04 327191783Srmacklem 328207082Srmacklem#define XL_MEDIA_SQE 0x0008 329236096Srmacklem#define XL_MEDIA_10TP 0x00C0 330191783Srmacklem#define XL_MEDIA_LNK 0x0080 331191783Srmacklem#define XL_MEDIA_LNKBEAT 0x0800 332191783Srmacklem 333191783Srmacklem#define XL_MEDIASTAT_CRCSTRIP 0x0004 334233730Skib#define XL_MEDIASTAT_SQEENB 0x0008 335233730Skib#define XL_MEDIASTAT_COLDET 0x0010 336233730Skib#define XL_MEDIASTAT_CARRIER 0x0020 337233730Skib#define XL_MEDIASTAT_JABGUARD 0x0040 338233730Skib#define XL_MEDIASTAT_LINKBEAT 0x0080 339191783Srmacklem#define XL_MEDIASTAT_JABDETECT 0x0200 340191783Srmacklem#define XL_MEDIASTAT_POLREVERS 0x0400 341191783Srmacklem#define XL_MEDIASTAT_LINKDETECT 0x0800 342191783Srmacklem#define XL_MEDIASTAT_TXINPROG 0x1000 343191783Srmacklem#define XL_MEDIASTAT_DCENB 0x4000 344191783Srmacklem#define XL_MEDIASTAT_AUIDIS 0x8000 345191783Srmacklem 346191783Srmacklem#define XL_NETDIAG_TEST_LOWVOLT 0x0001 347191783Srmacklem#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 348191783Srmacklem#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 349191783Srmacklem#define XL_NETDIAG_STATS_ENABLED 0x0080 350191783Srmacklem#define XL_NETDIAG_TX_FATALERR 0x0100 351191783Srmacklem#define XL_NETDIAG_TRANSMITTING 0x0200 352191783Srmacklem#define XL_NETDIAG_RX_ENABLED 0x0400 353191783Srmacklem#define XL_NETDIAG_TX_ENABLED 0x0800 354191783Srmacklem#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 355191783Srmacklem#define XL_NETDIAG_MAC_LOOPBACK 0x2000 356191783Srmacklem#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 357191783Srmacklem#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 358191783Srmacklem 359191783Srmacklem/* 360191783Srmacklem * Window 5 361191783Srmacklem */ 362191783Srmacklem#define XL_W5_STAT_ENB 0x0C 363191783Srmacklem#define XL_W5_INTR_ENB 0x0A 364191783Srmacklem#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 365249077Skib#define XL_W5_RX_FILTER 0x08 366191783Srmacklem#define XL_W5_RX_EARLYTHRESH 0x06 367191783Srmacklem#define XL_W5_TX_AVAILTHRESH 0x02 368191783Srmacklem#define XL_W5_TX_STARTTHRESH 0x00 369191783Srmacklem 370191783Srmacklem/* 371191783Srmacklem * RX filter bits 372191783Srmacklem */ 373193955Srmacklem#define XL_RXFILTER_INDIVIDUAL 0x01 374193955Srmacklem#define XL_RXFILTER_ALLMULTI 0x02 375193955Srmacklem#define XL_RXFILTER_BROADCAST 0x04 376193955Srmacklem#define XL_RXFILTER_ALLFRAMES 0x08 377193955Srmacklem#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 378191783Srmacklem 379191783Srmacklem/* 380191783Srmacklem * Window 6 (stats) 381191783Srmacklem */ 382191783Srmacklem#define XL_W6_TX_BYTES_OK 0x0C 383191783Srmacklem#define XL_W6_RX_BYTES_OK 0x0A 384191783Srmacklem#define XL_W6_UPPER_FRAMES_OK 0x09 385191783Srmacklem#define XL_W6_DEFERRED 0x08 386191783Srmacklem#define XL_W6_RX_OK 0x07 387191783Srmacklem#define XL_W6_TX_OK 0x06 388191783Srmacklem#define XL_W6_RX_OVERRUN 0x05 389191783Srmacklem#define XL_W6_COL_LATE 0x04 390223280Srmacklem#define XL_W6_COL_SINGLE 0x03 391191783Srmacklem#define XL_W6_COL_MULTIPLE 0x02 392191783Srmacklem#define XL_W6_SQE_ERRORS 0x01 393191783Srmacklem#define XL_W6_CARRIER_LOST 0x00 394191783Srmacklem 395191783Srmacklem/* 396191783Srmacklem * Window 7 (bus master control) 397191783Srmacklem */ 398191783Srmacklem#define XL_W7_BM_ADDR 0x00 399191783Srmacklem#define XL_W7_BM_LEN 0x06 400191783Srmacklem#define XL_W7_BM_STATUS 0x0B 401191783Srmacklem#define XL_W7_BM_TIMEr 0x0A 402191783Srmacklem 403191783Srmacklem/* 404191783Srmacklem * bus master control registers 405191783Srmacklem */ 406191783Srmacklem#define XL_BM_PKTSTAT 0x20 407191783Srmacklem#define XL_BM_DOWNLISTPTR 0x24 408191783Srmacklem#define XL_BM_FRAGADDR 0x28 409191783Srmacklem#define XL_BM_FRAGLEN 0x2C 410191783Srmacklem#define XL_BM_TXFREETHRESH 0x2F 411191783Srmacklem#define XL_BM_UPPKTSTAT 0x30 412191783Srmacklem#define XL_BM_UPLISTPTR 0x38 413191783Srmacklem 414191783Srmacklem#define XL_LAST_FRAG 0x80000000 415191783Srmacklem 416191783Srmacklem/* 417249077Skib * Boomerang/Cyclone TX/RX list structure. 418191783Srmacklem * For the TX lists, bits 0 to 12 of the status word indicate 419191783Srmacklem * length. 420191783Srmacklem * This looks suspiciously like the ThunderLAN, doesn't it. 421191783Srmacklem */ 422191783Srmacklemstruct xl_frag { 423191783Srmacklem u_int32_t xl_addr; /* 63 addr/len pairs */ 424191783Srmacklem u_int32_t xl_len; 425191783Srmacklem}; 426191783Srmacklem 427191783Srmacklemstruct xl_list { 428191783Srmacklem u_int32_t xl_next; /* final entry has 0 nextptr */ 429191783Srmacklem u_int32_t xl_status; 430191783Srmacklem struct xl_frag xl_frag[63]; 431191783Srmacklem}; 432191783Srmacklem 433191783Srmacklemstruct xl_list_onefrag { 434191783Srmacklem u_int32_t xl_next; /* final entry has 0 nextptr */ 435191783Srmacklem u_int32_t xl_status; 436191783Srmacklem struct xl_frag xl_frag; 437220877Srmacklem}; 438191783Srmacklem 439209120Skib#define XL_MAXFRAGS 63 440191783Srmacklem#define XL_RX_LIST_CNT 128 441191783Srmacklem#define XL_TX_LIST_CNT 256 442191783Srmacklem#define XL_MIN_FRAMELEN 60 443191783Srmacklem 444191783Srmacklemstruct xl_list_data { 445191783Srmacklem struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 446191783Srmacklem struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 447191783Srmacklem unsigned char xl_pad[XL_MIN_FRAMELEN]; 448191783Srmacklem}; 449191783Srmacklem 450191783Srmacklemstruct xl_chain { 451191783Srmacklem struct xl_list *xl_ptr; 452191783Srmacklem struct mbuf *xl_mbuf; 453191783Srmacklem struct xl_chain *xl_next; 454191783Srmacklem}; 455191783Srmacklem 456220877Srmacklemstruct xl_chain_onefrag { 457191783Srmacklem struct xl_list_onefrag *xl_ptr; 458220877Srmacklem struct mbuf *xl_mbuf; 459249077Skib struct xl_chain_onefrag *xl_next; 460191783Srmacklem}; 461220877Srmacklem 462249077Skibstruct xl_chain_data { 463191783Srmacklem struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 464191783Srmacklem struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 465191783Srmacklem 466191783Srmacklem struct xl_chain_onefrag *xl_rx_head; 467191783Srmacklem 468231330Srmacklem struct xl_chain *xl_tx_head; 469191783Srmacklem struct xl_chain *xl_tx_tail; 470249077Skib struct xl_chain *xl_tx_free; 471191783Srmacklem}; 472191783Srmacklem 473191783Srmacklem#define XL_RXSTAT_LENMASK 0x00001FFF 474191783Srmacklem#define XL_RXSTAT_UP_ERROR 0x00004000 475191783Srmacklem#define XL_RXSTAT_UP_CMPLT 0x00008000 476191783Srmacklem#define XL_RXSTAT_UP_OVERRUN 0x00010000 477249077Skib#define XL_RXSTAT_RUNT 0x00020000 478191783Srmacklem#define XL_RXSTAT_ALIGN 0x00040000 479191783Srmacklem#define XL_RXSTAT_CRC 0x00080000 480249077Skib#define XL_RXSTAT_OVERSIZE 0x00100000 481191783Srmacklem#define XL_RXSTAT_DRIBBLE 0x00800000 482191783Srmacklem#define XL_RXSTAT_UP_OFLOW 0x01000000 483191783Srmacklem#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 484191783Srmacklem#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 485191783Srmacklem#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 486191783Srmacklem#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 487191783Srmacklem#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 488191783Srmacklem#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 489191783Srmacklem#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 490191783Srmacklem 491191783Srmacklem#define XL_TXSTAT_LENMASK 0x00001FFF 492191783Srmacklem#define XL_TXSTAT_CRCDIS 0x00002000 493191783Srmacklem#define XL_TXSTAT_TX_INTR 0x00008000 494191783Srmacklem#define XL_TXSTAT_DL_COMPLETE 0x00010000 495191783Srmacklem#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 496191783Srmacklem#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 497191783Srmacklem#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 498191783Srmacklem#define XL_TXSTAT_DL_INTR 0x80000000 499212217Srmacklem 500191783Srmacklem#define XL_CAPABILITY_BM 0x20 501191783Srmacklem 502191783Srmacklem 503191783Srmacklemstruct xl_type { 504191783Srmacklem u_int16_t xl_vid; 505191783Srmacklem u_int16_t xl_did; 506191783Srmacklem char *xl_name; 507191783Srmacklem}; 508191783Srmacklem 509191783Srmacklemstruct xl_mii_frame { 510191783Srmacklem u_int8_t mii_stdelim; 511191783Srmacklem u_int8_t mii_opcode; 512191783Srmacklem u_int8_t mii_phyaddr; 513191783Srmacklem u_int8_t mii_regaddr; 514191783Srmacklem u_int8_t mii_turnaround; 515191783Srmacklem u_int16_t mii_data; 516191783Srmacklem}; 517191783Srmacklem 518191783Srmacklem/* 519191783Srmacklem * MII constants 520191783Srmacklem */ 521191783Srmacklem#define XL_MII_STARTDELIM 0x01 522191783Srmacklem#define XL_MII_READOP 0x02 523191783Srmacklem#define XL_MII_WRITEOP 0x01 524191783Srmacklem#define XL_MII_TURNAROUND 0x02 525191783Srmacklem 526191783Srmacklem/* 527191783Srmacklem * The 3C905B adapters implement a few features that we want to 528191783Srmacklem * take advantage of, namely the multicast hash filter. With older 529191783Srmacklem * chips, you only have the option of turning on reception of all 530191783Srmacklem * multicast frames, which is kind of lame. 531191783Srmacklem */ 532191783Srmacklem#define XL_TYPE_905B 1 533191783Srmacklem#define XL_TYPE_90X 2 534191783Srmacklem 535191783Srmacklem#define XL_FLAG_FORCEDELAY 1 536191783Srmacklem#define XL_FLAG_SCHEDDELAY 2 537191783Srmacklem#define XL_FLAG_DELAYTIMEO 3 538191783Srmacklem 539191783Srmacklemstruct xl_softc { 540191783Srmacklem struct arpcom arpcom; /* interface info */ 541207082Srmacklem struct ifmedia ifmedia; /* media info */ 542191783Srmacklem bus_space_handle_t xl_bhandle; 543191783Srmacklem bus_space_tag_t xl_btag; 544191783Srmacklem void *xl_intrhand; 545191783Srmacklem struct resource *xl_irq; 546191783Srmacklem struct resource *xl_res; 547191783Srmacklem struct xl_type *xl_info; /* 3Com adapter info */ 548191783Srmacklem struct xl_type *xl_pinfo; /* phy info */ 549191783Srmacklem u_int8_t xl_unit; /* interface number */ 550191783Srmacklem u_int8_t xl_type; 551191783Srmacklem u_int8_t xl_phy_addr; /* PHY address */ 552191783Srmacklem u_int32_t xl_xcvr; 553191783Srmacklem u_int16_t xl_media; 554191783Srmacklem u_int16_t xl_caps; 555191783Srmacklem u_int8_t xl_tx_pend; /* TX pending */ 556191783Srmacklem u_int8_t xl_want_auto; 557191783Srmacklem u_int8_t xl_autoneg; 558233353Skib u_int8_t xl_stats_no_timeout; 559191783Srmacklem u_int16_t xl_tx_thresh; 560191783Srmacklem caddr_t xl_ldata_ptr; 561191783Srmacklem struct xl_list_data *xl_ldata; 562191783Srmacklem struct xl_chain_data xl_cdata; 563191783Srmacklem struct callout_handle xl_stat_ch; 564191783Srmacklem}; 565191783Srmacklem 566191783Srmacklem#define xl_rx_goodframes(x) \ 567191783Srmacklem ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 568191783Srmacklem 569191783Srmacklem#define xl_tx_goodframes(x) \ 570207082Srmacklem ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 571191783Srmacklem 572191783Srmacklemstruct xl_stats { 573191783Srmacklem u_int8_t xl_carrier_lost; 574191783Srmacklem u_int8_t xl_sqe_errs; 575191783Srmacklem u_int8_t xl_tx_multi_collision; 576191783Srmacklem u_int8_t xl_tx_single_collision; 577233353Skib u_int8_t xl_tx_late_collision; 578191783Srmacklem u_int8_t xl_rx_overrun; 579191783Srmacklem u_int8_t xl_tx_frames_ok; 580191783Srmacklem u_int8_t xl_rx_frames_ok; 581191783Srmacklem u_int8_t xl_tx_deferred; 582191783Srmacklem u_int8_t xl_upper_frames_ok; 583191783Srmacklem u_int16_t xl_rx_bytes_ok; 584191783Srmacklem u_int16_t xl_tx_bytes_ok; 585191783Srmacklem u_int16_t status; 586191783Srmacklem}; 587191783Srmacklem 588191783Srmacklem/* 589191783Srmacklem * register space access macros 590191783Srmacklem */ 591191783Srmacklem#define CSR_WRITE_4(sc, reg, val) \ 592191783Srmacklem bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 593191783Srmacklem#define CSR_WRITE_2(sc, reg, val) \ 594191783Srmacklem bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 595191783Srmacklem#define CSR_WRITE_1(sc, reg, val) \ 596207082Srmacklem bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 597191783Srmacklem 598191783Srmacklem#define CSR_READ_4(sc, reg) \ 599191783Srmacklem bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 600191783Srmacklem#define CSR_READ_2(sc, reg) \ 601191783Srmacklem bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 602191783Srmacklem#define CSR_READ_1(sc, reg) \ 603191783Srmacklem bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 604191783Srmacklem 605191783Srmacklem#define XL_SEL_WIN(x) \ 606191783Srmacklem CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 607191783Srmacklem#define XL_TIMEOUT 1000 608191783Srmacklem 609191783Srmacklem/* 610191783Srmacklem * General constants that are fun to know. 611191783Srmacklem * 612191783Srmacklem * 3Com PCI vendor ID 613191783Srmacklem */ 614191783Srmacklem#define TC_VENDORID 0x10B7 615191783Srmacklem 616191783Srmacklem/* 617191783Srmacklem * 3Com chip device IDs. 618191783Srmacklem */ 619191783Srmacklem#define TC_DEVICEID_BOOMERANG_10BT 0x9000 620191783Srmacklem#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 621191783Srmacklem#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 622191783Srmacklem#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 623191783Srmacklem#define TC_DEVICEID_KRAKATOA_10BT 0x9004 624191783Srmacklem#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 625207082Srmacklem#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 626191783Srmacklem#define TC_DEVICEID_CYCLONE_10FL 0x900A 627191783Srmacklem#define TC_DEVICEID_HURRICANE_10_100BT 0x9055 628191783Srmacklem#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 629191783Srmacklem#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 630191783Srmacklem#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 631191783Srmacklem#define TC_DEVICEID_TORNADO_10_100BT 0x9200 632191783Srmacklem#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 633191783Srmacklem#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 634191783Srmacklem 635191783Srmacklem/* 636191783Srmacklem * Texas Instruments PHY identifiers 637191783Srmacklem * 638191783Srmacklem * The ThunderLAN manual has a curious and confusing error in it. 639191783Srmacklem * In chapter 7, which describes PHYs, it says that TI PHYs have 640191783Srmacklem * the following ID codes, where xx denotes a revision: 641191783Srmacklem * 642191783Srmacklem * 0x4000501xx internal 10baseT PHY 643191783Srmacklem * 0x4000502xx TNETE211 100VG-AnyLan PMI 644191783Srmacklem * 645191783Srmacklem * The problem here is that these are not valid 32-bit hex numbers: 646191783Srmacklem * there's one digit too many. My guess is that they mean the internal 647191783Srmacklem * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these 648191783Srmacklem * are the only numbers that make sense. 649191783Srmacklem */ 650191783Srmacklem#define TI_PHY_VENDORID 0x4000 651191783Srmacklem#define TI_PHY_10BT 0x501F 652191783Srmacklem#define TI_PHY_100VGPMI 0x502F 653191783Srmacklem 654191783Srmacklem/* 655191783Srmacklem * These ID values are for the NS DP83840A 10/100 PHY 656191783Srmacklem */ 657191783Srmacklem#define NS_PHY_VENDORID 0x2000 658191783Srmacklem#define NS_PHY_83840A 0x5C0F 659191783Srmacklem 660191783Srmacklem/* 661191783Srmacklem * Level 1 10/100 PHY 662191783Srmacklem */ 663191783Srmacklem#define LEVEL1_PHY_VENDORID 0x7810 664191783Srmacklem#define LEVEL1_PHY_LXT970 0x000F 665191783Srmacklem 666191783Srmacklem/* 667191783Srmacklem * Intel 82555 10/100 PHY 668191783Srmacklem */ 669191783Srmacklem#define INTEL_PHY_VENDORID 0x0A28 670191783Srmacklem#define INTEL_PHY_82555 0x015F 671191783Srmacklem 672191783Srmacklem/* 673191783Srmacklem * SEEQ 80220 10/100 PHY 674191783Srmacklem */ 675191783Srmacklem#define SEEQ_PHY_VENDORID 0x0016 676191783Srmacklem#define SEEQ_PHY_80220 0xF83F 677191783Srmacklem 678191783Srmacklem 679191783Srmacklem/* 680191783Srmacklem * PCI low memory base and low I/O base register, and 681191783Srmacklem * other PCI registers. Note: some are only available on 682191783Srmacklem * the 3c905B, in particular those that related to power management. 683191783Srmacklem */ 684191783Srmacklem 685191783Srmacklem#define XL_PCI_VENDOR_ID 0x00 686191783Srmacklem#define XL_PCI_DEVICE_ID 0x02 687191783Srmacklem#define XL_PCI_COMMAND 0x04 688191783Srmacklem#define XL_PCI_STATUS 0x06 689191783Srmacklem#define XL_PCI_CLASSCODE 0x09 690191783Srmacklem#define XL_PCI_LATENCY_TIMER 0x0D 691191783Srmacklem#define XL_PCI_HEADER_TYPE 0x0E 692191783Srmacklem#define XL_PCI_LOIO 0x10 693191783Srmacklem#define XL_PCI_LOMEM 0x14 694191783Srmacklem#define XL_PCI_BIOSROM 0x30 695191783Srmacklem#define XL_PCI_INTLINE 0x3C 696191783Srmacklem#define XL_PCI_INTPIN 0x3D 697191783Srmacklem#define XL_PCI_MINGNT 0x3E 698191783Srmacklem#define XL_PCI_MINLAT 0x0F 699191783Srmacklem#define XL_PCI_RESETOPT 0x48 700191783Srmacklem#define XL_PCI_EEPROM_DATA 0x4C 701191783Srmacklem 702239852Skib/* 3c905B-only registers */ 703191783Srmacklem#define XL_PCI_CAPID 0xDC /* 8 bits */ 704191783Srmacklem#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 705191783Srmacklem#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 706191783Srmacklem#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 707191783Srmacklem 708191783Srmacklem#define XL_PSTATE_MASK 0x0003 709191783Srmacklem#define XL_PSTATE_D0 0x0000 710191783Srmacklem#define XL_PSTATE_D1 0x0002 711191783Srmacklem#define XL_PSTATE_D2 0x0002 712191783Srmacklem#define XL_PSTATE_D3 0x0003 713249077Skib#define XL_PME_EN 0x0010 714191783Srmacklem#define XL_PME_STATUS 0x8000 715249077Skib 716249077Skib#define PHY_UNKNOWN 6 717191783Srmacklem 718191783Srmacklem#define XL_PHYADDR_MIN 0x00 719249077Skib#define XL_PHYADDR_MAX 0x1F 720191783Srmacklem 721191783Srmacklem#define XL_PHY_GENCTL 0x00 722191783Srmacklem#define XL_PHY_GENSTS 0x01 723191783Srmacklem#define XL_PHY_VENID 0x02 724191783Srmacklem#define XL_PHY_DEVID 0x03 725191783Srmacklem#define XL_PHY_ANAR 0x04 726191783Srmacklem#define XL_PHY_LPAR 0x05 727191783Srmacklem#define XL_PHY_ANEXP 0x06 728191783Srmacklem 729191783Srmacklem#define PHY_ANAR_NEXTPAGE 0x8000 730191783Srmacklem#define PHY_ANAR_RSVD0 0x4000 731191783Srmacklem#define PHY_ANAR_TLRFLT 0x2000 732191783Srmacklem#define PHY_ANAR_RSVD1 0x1000 733191783Srmacklem#define PHY_ANAR_RSVD2 0x0800 734191783Srmacklem#define PHY_ANAR_RSVD3 0x0400 735249077Skib#define PHY_ANAR_100BT4 0x0200 736191783Srmacklem#define PHY_ANAR_100BTXFULL 0x0100 737191783Srmacklem#define PHY_ANAR_100BTXHALF 0x0080 738191783Srmacklem#define PHY_ANAR_10BTFULL 0x0040 739191783Srmacklem#define PHY_ANAR_10BTHALF 0x0020 740191783Srmacklem#define PHY_ANAR_PROTO4 0x0010 741191783Srmacklem#define PHY_ANAR_PROTO3 0x0008 742191783Srmacklem#define PHY_ANAR_PROTO2 0x0004 743191783Srmacklem#define PHY_ANAR_PROTO1 0x0002 744191783Srmacklem#define PHY_ANAR_PROTO0 0x0001 745233353Skib 746233353Skib/* 747191783Srmacklem * These are the register definitions for the PHY (physical layer 748191783Srmacklem * interface chip). 749191783Srmacklem */ 750191783Srmacklem/* 751191783Srmacklem * PHY BMCR Basic Mode Control Register 752191783Srmacklem */ 753191783Srmacklem#define PHY_BMCR 0x00 754191783Srmacklem#define PHY_BMCR_RESET 0x8000 755191783Srmacklem#define PHY_BMCR_LOOPBK 0x4000 756191783Srmacklem#define PHY_BMCR_SPEEDSEL 0x2000 757191783Srmacklem#define PHY_BMCR_AUTONEGENBL 0x1000 758207082Srmacklem#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 759249077Skib#define PHY_BMCR_ISOLATE 0x0400 760191783Srmacklem#define PHY_BMCR_AUTONEGRSTR 0x0200 761191783Srmacklem#define PHY_BMCR_DUPLEX 0x0100 762191783Srmacklem#define PHY_BMCR_COLLTEST 0x0080 763191783Srmacklem#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 764191783Srmacklem#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 765191783Srmacklem#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 766191783Srmacklem#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 767191783Srmacklem#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 768191783Srmacklem#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 769249077Skib#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 770191783Srmacklem/* 771191783Srmacklem * RESET: 1 == software reset, 0 == normal operation 772191783Srmacklem * Resets status and control registers to default values. 773191783Srmacklem * Relatches all hardware config values. 774191783Srmacklem * 775191783Srmacklem * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 776191783Srmacklem * 777191783Srmacklem * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 778249077Skib * Link speed is selected byt his bit or if auto-negotiation if bit 779191783Srmacklem * 12 (AUTONEGENBL) is set (in which case the value of this register 780191783Srmacklem * is ignored). 781191783Srmacklem * 782249077Skib * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 783249077Skib * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 784191783Srmacklem * determine speed and mode. Should be cleared and then set if PHY configured 785249077Skib * for no autoneg on startup. 786191783Srmacklem * 787191783Srmacklem * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 788191783Srmacklem * 789191783Srmacklem * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 790191783Srmacklem * 791191783Srmacklem * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 792191783Srmacklem * 793191783Srmacklem * COLLTEST: 1 == collision test enabled, 0 == normal operation 794233353Skib */ 795233353Skib 796191783Srmacklem/* 797191783Srmacklem * PHY, BMSR Basic Mode Status Register 798191783Srmacklem */ 799191783Srmacklem#define PHY_BMSR 0x01 800191783Srmacklem#define PHY_BMSR_100BT4 0x8000 801191783Srmacklem#define PHY_BMSR_100BTXFULL 0x4000 802191783Srmacklem#define PHY_BMSR_100BTXHALF 0x2000 803191783Srmacklem#define PHY_BMSR_10BTFULL 0x1000 804191783Srmacklem#define PHY_BMSR_10BTHALF 0x0800 805191783Srmacklem#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 806191783Srmacklem#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 807191783Srmacklem#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 808232682Srmacklem#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 809232682Srmacklem#define PHY_BMSR_MFPRESUP 0x0040 810232682Srmacklem#define PHY_BMSR_AUTONEGCOMP 0x0020 811232682Srmacklem#define PHY_BMSR_REMFAULT 0x0010 812232682Srmacklem#define PHY_BMSR_CANAUTONEG 0x0008 813232682Srmacklem#define PHY_BMSR_LINKSTAT 0x0004 814232682Srmacklem#define PHY_BMSR_JABBER 0x0002 815232682Srmacklem#define PHY_BMSR_EXTENDED 0x0001 816232682Srmacklem 817232682Srmacklem#ifdef __alpha__ 818232682Srmacklem#undef vtophys 819232682Srmacklem#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 820232682Srmacklem 821232682Srmacklem#endif 822232682Srmacklem 823191783Srmacklem#ifndef IFM_10_FL 824191783Srmacklem#define IFM_10_FL 13 /* 10baseFL - Fiber */ 825191783Srmacklem#endif 826191783Srmacklem