1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD$*/ 32221167Sgnn 33221167Sgnn#ifndef VXGE_HAL_SRPCIM_REGS_H 34221167Sgnn#define VXGE_HAL_SRPCIM_REGS_H 35221167Sgnn 36221167Sgnn__EXTERN_BEGIN_DECLS 37221167Sgnn 38221167Sgnntypedef struct vxge_hal_srpcim_reg_t { 39221167Sgnn 40221167Sgnn/* 0x00000 */ u64 tim_mr2sr_resource_assignment_vh; 41221167Sgnn#define VXGE_HAL_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val)\ 42221167Sgnn vBIT(val, 0, 32) 43221167Sgnn u8 unused00100[0x00100 - 0x00008]; 44221167Sgnn 45221167Sgnn/* 0x00100 */ u64 srpcim_pcipif_int_status; 46221167Sgnn#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_INT mBIT(3) 47221167Sgnn#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT mBIT(7) 48221167Sgnn#define VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT\ 49221167Sgnn mBIT(11) 50221167Sgnn/* 0x00108 */ u64 srpcim_pcipif_int_mask; 51221167Sgnn/* 0x00110 */ u64 mrpcim_msg_reg; 52221167Sgnn#define VXGE_HAL_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT mBIT(3) 53221167Sgnn/* 0x00118 */ u64 mrpcim_msg_mask; 54221167Sgnn/* 0x00120 */ u64 mrpcim_msg_alarm; 55221167Sgnn/* 0x00128 */ u64 vpath_msg_reg; 56221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT mBIT(0) 57221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT mBIT(1) 58221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT mBIT(2) 59221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT mBIT(3) 60221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT mBIT(4) 61221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT mBIT(5) 62221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT mBIT(6) 63221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT mBIT(7) 64221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT mBIT(8) 65221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT mBIT(9) 66221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT mBIT(10) 67221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT mBIT(11) 68221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT mBIT(12) 69221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT mBIT(13) 70221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT mBIT(14) 71221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT mBIT(15) 72221167Sgnn#define VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT mBIT(16) 73221167Sgnn/* 0x00130 */ u64 vpath_msg_mask; 74221167Sgnn/* 0x00138 */ u64 vpath_msg_alarm; 75221167Sgnn u8 unused00158[0x00158 - 0x00140]; 76221167Sgnn 77221167Sgnn/* 0x00158 */ u64 vf_bargrp_no; 78221167Sgnn#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR0(val) vBIT(val, 11, 5) 79221167Sgnn#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR1(val) vBIT(val, 19, 5) 80221167Sgnn#define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR2(val) vBIT(val, 26, 6) 81221167Sgnn#define VXGE_HAL_VF_BARGRP_NO_FIRST_VF_OFFSET(val) vBIT(val, 32, 4) 82221167Sgnn#define VXGE_HAL_VF_BARGRP_NO_MASK(val) vBIT(val, 36, 4) 83221167Sgnn/* 0x00160 */ u64 srpcim_to_mrpcim_wmsg; 84221167Sgnn#define VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val)\ 85221167Sgnn vBIT(val, 0, 64) 86221167Sgnn/* 0x00168 */ u64 srpcim_to_mrpcim_wmsg_trig; 87221167Sgnn#define VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG mBIT(0) 88221167Sgnn/* 0x00170 */ u64 mrpcim_to_srpcim_rmsg; 89221167Sgnn#define VXGE_HAL_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val)\ 90221167Sgnn vBIT(val, 0, 64) 91221167Sgnn/* 0x00178 */ u64 vpath_to_srpcim_rmsg_sel; 92221167Sgnn#define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SEL_SEL(val) vBIT(val, 0, 5) 93221167Sgnn/* 0x00180 */ u64 vpath_to_srpcim_rmsg; 94221167Sgnn#define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val)\ 95221167Sgnn vBIT(val, 0, 64) 96221167Sgnn u8 unused00200[0x00200 - 0x00188]; 97221167Sgnn 98221167Sgnn/* 0x00200 */ u64 srpcim_general_int_status; 99221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT mBIT(0) 100221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PCI_INT mBIT(3) 101221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT mBIT(7) 102221167Sgnn u8 unused00210[0x00210 - 0x00208]; 103221167Sgnn 104221167Sgnn/* 0x00210 */ u64 srpcim_general_int_mask; 105221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PIC_INT mBIT(0) 106221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT mBIT(3) 107221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_INT_MASK_XMAC_INT mBIT(7) 108221167Sgnn u8 unused00220[0x00220 - 0x00218]; 109221167Sgnn 110221167Sgnn/* 0x00220 */ u64 srpcim_ppif_int_status; 111221167Sgnn#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_SRPCIM_GEN_ERRORS_INT\ 112221167Sgnn mBIT(3) 113221167Sgnn#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM mBIT(7) 114221167Sgnn#define VXGE_HAL_SRPCIM_PPIF_INT_STATUS_VPATH_TO_SRPCIM_ALARM_INT mBIT(11) 115221167Sgnn/* 0x00228 */ u64 srpcim_ppif_int_mask; 116221167Sgnn/* 0x00230 */ u64 srpcim_gen_errors_reg; 117221167Sgnn#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR mBIT(3) 118221167Sgnn#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR mBIT(7) 119221167Sgnn#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR mBIT(11) 120221167Sgnn#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT mBIT(15) 121221167Sgnn#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET mBIT(19) 122221167Sgnn#define VXGE_HAL_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS mBIT(23) 123221167Sgnn/* 0x00238 */ u64 srpcim_gen_errors_mask; 124221167Sgnn/* 0x00240 */ u64 srpcim_gen_errors_alarm; 125221167Sgnn/* 0x00248 */ u64 mrpcim_to_srpcim_alarm_reg; 126221167Sgnn#define VXGE_HAL_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM mBIT(3) 127221167Sgnn/* 0x00250 */ u64 mrpcim_to_srpcim_alarm_mask; 128221167Sgnn/* 0x00258 */ u64 mrpcim_to_srpcim_alarm_alarm; 129221167Sgnn/* 0x00260 */ u64 vpath_to_srpcim_alarm_reg; 130221167Sgnn#define VXGE_HAL_VPATH_TO_SRPCIM_ALARM_REG_PPIF_VPATH_TO_SRPCIM_ALARM(val)\ 131221167Sgnn vBIT(val, 0, 17) 132221167Sgnn/* 0x00268 */ u64 vpath_to_srpcim_alarm_mask; 133221167Sgnn/* 0x00270 */ u64 vpath_to_srpcim_alarm_alarm; 134221167Sgnn u8 unused00280[0x00280 - 0x00278]; 135221167Sgnn 136221167Sgnn/* 0x00280 */ u64 pf_sw_reset; 137221167Sgnn#define VXGE_HAL_PF_SW_RESET_PF_SW_RESET(val) vBIT(val, 0, 8) 138221167Sgnn/* 0x00288 */ u64 srpcim_general_cfg1; 139221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN mBIT(19) 140221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN mBIT(23) 141221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN mBIT(27) 142221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN mBIT(31) 143221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN mBIT(35) 144221167Sgnn#define VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN mBIT(39) 145221167Sgnn/* 0x00290 */ u64 srpcim_interrupt_cfg1; 146221167Sgnn#define VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vBIT(val, 1, 7) 147221167Sgnn#define VXGE_HAL_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vBIT(val, 9, 3) 148221167Sgnn/* 0x00298 */ u64 srpcim_interrupt_cfg2; 149221167Sgnn#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_MSIX_FOR_SCHED_INT(val)\ 150221167Sgnn vBIT(val, 1, 7) 151221167Sgnn#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_ONE_SHOT mBIT(11) 152221167Sgnn#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_TIMER_EN mBIT(15) 153221167Sgnn#define VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_INT_PERIOD(val) vBIT(val, 32, 32) 154221167Sgnn u8 unused002a8[0x002a8 - 0x002a0]; 155221167Sgnn 156221167Sgnn/* 0x002a8 */ u64 srpcim_clear_msix_mask; 157221167Sgnn#define VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK mBIT(0) 158221167Sgnn/* 0x002b0 */ u64 srpcim_set_msix_mask; 159221167Sgnn#define VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK mBIT(0) 160221167Sgnn/* 0x002b8 */ u64 srpcim_clr_msix_one_shot; 161221167Sgnn#define VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT mBIT(0) 162221167Sgnn/* 0x002c0 */ u64 srpcim_rst_in_prog; 163221167Sgnn#define VXGE_HAL_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG mBIT(7) 164221167Sgnn/* 0x002c8 */ u64 srpcim_reg_modified; 165221167Sgnn#define VXGE_HAL_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED mBIT(7) 166221167Sgnn/* 0x002d0 */ u64 tgt_pf_illegal_access; 167221167Sgnn#define VXGE_HAL_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vBIT(val, 1, 7) 168221167Sgnn/* 0x002d8 */ u64 srpcim_msix_status; 169221167Sgnn#define VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK mBIT(3) 170221167Sgnn#define VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR mBIT(7) 171221167Sgnn u8 unused00318[0x00318 - 0x002e0]; 172221167Sgnn 173221167Sgnn/* 0x00318 */ u64 usdc_vpl; 174221167Sgnn#define VXGE_HAL_USDC_VPL_SGRP_OWN(val) vBIT(val, 0, 32) 175221167Sgnn u8 unused00600[0x00600 - 0x00320]; 176221167Sgnn 177221167Sgnn/* 0x00600 */ u64 one_cfg_sr_copy; 178221167Sgnn#define VXGE_HAL_ONE_CFG_SR_COPY_ONE_CFG_RDY mBIT(7) 179221167Sgnn/* 0x00608 */ u64 sgrp_allocated; 180221167Sgnn#define VXGE_HAL_SGRP_ALLOCATED_SGRP_ALLOC(val) vBIT(val, 0, 64) 181221167Sgnn/* 0x00610 */ u64 sgrp_iwarp_lro_allocated; 182221167Sgnn#define VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_ENABLE_IWARP mBIT(7) 183221167Sgnn#define VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_LAST_IWARP_SGRP(val) vBIT(val, 11, 5) 184221167Sgnn u8 unused00880[0x00880 - 0x00618]; 185221167Sgnn 186221167Sgnn/* 0x00880 */ u64 xgmac_sr_int_status; 187221167Sgnn#define VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT mBIT(3) 188221167Sgnn/* 0x00888 */ u64 xgmac_sr_int_mask; 189221167Sgnn/* 0x00890 */ u64 asic_ntwk_sr_err_reg; 190221167Sgnn#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT mBIT(3) 191221167Sgnn#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK mBIT(7) 192221167Sgnn#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED\ 193221167Sgnn mBIT(11) 194221167Sgnn#define VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED mBIT(15) 195221167Sgnn/* 0x00898 */ u64 asic_ntwk_sr_err_mask; 196221167Sgnn/* 0x008a0 */ u64 asic_ntwk_sr_err_alarm; 197221167Sgnn u8 unused008c0[0x008c0 - 0x008a8]; 198221167Sgnn 199221167Sgnn/* 0x008c0 */ u64 xmac_vsport_choices_sr_clone; 200221167Sgnn#define VXGE_HAL_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val)\ 201221167Sgnn vBIT(val, 0, 17) 202221167Sgnn u8 unused00900[0x00900 - 0x008c8]; 203221167Sgnn 204221167Sgnn/* 0x00900 */ u64 mr_rqa_top_prty_for_vh; 205221167Sgnn#define VXGE_HAL_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val)\ 206221167Sgnn vBIT(val, 59, 5) 207221167Sgnn/* 0x00908 */ u64 umq_vh_data_list_empty; 208221167Sgnn#define VXGE_HAL_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY mBIT(0) 209221167Sgnn/* 0x00910 */ u64 wde_cfg; 210221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_START mBIT(0) 211221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_END mBIT(1) 212221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_FORCE_QB_START mBIT(2) 213221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_FORCE_QB_END mBIT(3) 214221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_START mBIT(4) 215221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_END mBIT(5) 216221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_MWB_OPT_EN mBIT(6) 217221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_QB_OPT_EN mBIT(7) 218221167Sgnn#define VXGE_HAL_WDE_CFG_NS0_MPSB_OPT_EN mBIT(8) 219221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_START mBIT(9) 220221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_END mBIT(10) 221221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_FORCE_QB_START mBIT(11) 222221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_FORCE_QB_END mBIT(12) 223221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_START mBIT(13) 224221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_END mBIT(14) 225221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_MWB_OPT_EN mBIT(15) 226221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_QB_OPT_EN mBIT(16) 227221167Sgnn#define VXGE_HAL_WDE_CFG_NS1_MPSB_OPT_EN mBIT(17) 228221167Sgnn#define VXGE_HAL_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR mBIT(19) 229221167Sgnn#define VXGE_HAL_WDE_CFG_ALIGNMENT_PREFERENCE(val) vBIT(val, 30, 2) 230221167Sgnn#define VXGE_HAL_WDE_CFG_MEM_WORD_SIZE(val) vBIT(val, 46, 2) 231221167Sgnn 232221167Sgnn} vxge_hal_srpcim_reg_t; 233221167Sgnn 234221167Sgnn__EXTERN_END_DECLS 235221167Sgnn 236221167Sgnn#endif /* VXGE_HAL_SRPCIM_REGS_H */ 237