1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD$*/ 32221167Sgnn 33221167Sgnn#ifndef VXGE_HAL_DEVICE_H 34221167Sgnn#define VXGE_HAL_DEVICE_H 35221167Sgnn 36221167Sgnn__EXTERN_BEGIN_DECLS 37221167Sgnn 38221167Sgnnstruct __hal_mrpcim_t; 39221167Sgnnstruct __hal_srpcim_t; 40221167Sgnn 41221167Sgnn/* 42221167Sgnn * vxge_hal_vpd_data_t 43221167Sgnn * 44221167Sgnn * Represents vpd capabilty structure 45221167Sgnn */ 46221167Sgnntypedef struct vxge_hal_vpd_data_t { 47221167Sgnn u8 product_name[VXGE_HAL_VPD_LEN]; 48221167Sgnn u8 serial_num[VXGE_HAL_VPD_LEN]; 49221167Sgnn} vxge_hal_vpd_data_t; 50221167Sgnn 51221167Sgnn#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 52221167Sgnn/* 53221167Sgnn * __hal_tracebuf_t 54221167Sgnn * 55221167Sgnn * HAL trace buffer object. 56221167Sgnn */ 57221167Sgnntypedef struct __hal_tracebuf_t { 58221167Sgnn u8 *data; 59221167Sgnn u64 wrapped_count; 60221167Sgnn volatile u32 offset; 61221167Sgnn u32 size; 62221167Sgnn} __hal_tracebuf_t; 63221167Sgnn#endif 64221167Sgnn 65221167Sgnn/* 66221167Sgnn * __hal_msix_map_t 67221167Sgnn * 68221167Sgnn * HAL msix to vpath map. 69221167Sgnn */ 70221167Sgnntypedef struct __hal_msix_map_t { 71221167Sgnn u32 vp_id; 72221167Sgnn u32 int_num; 73221167Sgnn} __hal_msix_map_t; 74221167Sgnn 75221167Sgnn/* 76221167Sgnn * __hal_device_t 77221167Sgnn * 78221167Sgnn * HAL device object. Represents X3100. 79221167Sgnn */ 80221167Sgnntypedef struct __hal_device_t { 81221167Sgnn vxge_hal_device_t header; 82221167Sgnn u32 host_type; 83221167Sgnn u32 vh_id; 84221167Sgnn u32 func_id; 85221167Sgnn u32 srpcim_id; 86221167Sgnn u32 access_rights; 87221167Sgnn#define VXGE_HAL_DEVICE_ACCESS_RIGHT_VPATH 0x1 88221167Sgnn#define VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM 0x2 89221167Sgnn#define VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM 0x4 90221167Sgnn u32 ifmsg_seqno; 91221167Sgnn u32 manager_up; 92221167Sgnn vxge_hal_pci_config_t pci_config_space; 93221167Sgnn vxge_hal_pci_config_t pci_config_space_bios; 94221167Sgnn vxge_hal_pci_caps_offset_t pci_caps; 95221167Sgnn vxge_hal_pci_e_caps_offset_t pci_e_caps; 96221167Sgnn vxge_hal_pci_e_ext_caps_offset_t pci_e_ext_caps; 97221167Sgnn vxge_hal_legacy_reg_t *legacy_reg; 98221167Sgnn vxge_hal_toc_reg_t *toc_reg; 99221167Sgnn vxge_hal_common_reg_t *common_reg; 100221167Sgnn vxge_hal_memrepair_reg_t *memrepair_reg; 101221167Sgnn vxge_hal_pcicfgmgmt_reg_t 102221167Sgnn *pcicfgmgmt_reg[VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES]; 103221167Sgnn vxge_hal_mrpcim_reg_t *mrpcim_reg; 104221167Sgnn vxge_hal_srpcim_reg_t 105221167Sgnn *srpcim_reg[VXGE_HAL_TITAN_SRPCIM_REG_SPACES]; 106221167Sgnn vxge_hal_vpmgmt_reg_t 107221167Sgnn *vpmgmt_reg[VXGE_HAL_TITAN_VPMGMT_REG_SPACES]; 108221167Sgnn vxge_hal_vpath_reg_t 109221167Sgnn *vpath_reg[VXGE_HAL_TITAN_VPATH_REG_SPACES]; 110221167Sgnn u8 *kdfc; 111221167Sgnn u8 *usdc; 112221167Sgnn __hal_virtualpath_t 113221167Sgnn virtual_paths[VXGE_HAL_MAX_VIRTUAL_PATHS]; 114221167Sgnn u64 vpath_assignments; 115221167Sgnn u64 vpaths_deployed; 116221167Sgnn u32 first_vp_id; 117221167Sgnn u64 tim_int_mask0[4]; 118221167Sgnn u32 tim_int_mask1[4]; 119221167Sgnn __hal_msix_map_t 120221167Sgnn msix_map[VXGE_HAL_MAX_VIRTUAL_PATHS * VXGE_HAL_VPATH_MSIX_MAX]; 121221167Sgnn struct __hal_srpcim_t *srpcim; 122221167Sgnn struct __hal_mrpcim_t *mrpcim; 123221167Sgnn __hal_blockpool_t block_pool; 124221167Sgnn vxge_list_t pending_channel_list; 125221167Sgnn spinlock_t pending_channel_lock; 126221167Sgnn vxge_hal_device_stats_t stats; 127221167Sgnn volatile u32 msix_enabled; 128221167Sgnn volatile u32 hw_is_initialized; 129221167Sgnn volatile int device_resetting; 130221167Sgnn volatile int is_promisc; 131221167Sgnn int tti_enabled; 132221167Sgnn spinlock_t titan_post_lock; 133221167Sgnn u32 mtu_first_time_set; 134221167Sgnn char *dump_buf; 135221167Sgnn#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 136221167Sgnn __hal_tracebuf_t trace_buf; 137221167Sgnn#endif 138221167Sgnn volatile u32 in_poll; 139221167Sgnn u32 d_err_mask; 140221167Sgnn u32 d_info_mask; 141221167Sgnn u32 d_trace_mask; 142221167Sgnn} __hal_device_t; 143221167Sgnn 144221167Sgnn/* 145221167Sgnn * I2C device id. Used in I2C control register for accessing EEPROM device 146221167Sgnn * memory. 147221167Sgnn */ 148221167Sgnn#define VXGE_DEV_ID 5 149221167Sgnn 150221167Sgnn#define VXGE_HAL_DEVICE_MANAGER_STATE_SET(hldev, wmsg) { \ 151221167Sgnn ((__hal_device_t *)hldev)->manager_up = \ 152221167Sgnn __hal_ifmsg_is_manager_up(wmsg); \ 153221167Sgnn} 154221167Sgnn 155221167Sgnn#define VXGE_HAL_DEVICE_LINK_STATE_SET(hldev, ls) { \ 156221167Sgnn ((vxge_hal_device_t *)hldev)->link_state = ls; \ 157221167Sgnn} 158221167Sgnn 159221167Sgnn#define VXGE_HAL_DEVICE_DATA_RATE_SET(hldev, dr) { \ 160221167Sgnn ((vxge_hal_device_t *)hldev)->data_rate = dr; \ 161221167Sgnn} 162221167Sgnn 163221167Sgnn#define VXGE_HAL_DEVICE_TIM_INT_MASK_SET(hldev, i) { \ 164221167Sgnn if (i < 16) { \ 165221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask0[0] |= \ 166221167Sgnn vBIT(0x8, (i*4), 4); \ 167221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask0[1] |= \ 168221167Sgnn vBIT(0x4, (i*4), 4); \ 169221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask0[3] |= \ 170221167Sgnn vBIT(0x1, (i*4), 4); \ 171221167Sgnn } else { \ 172221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0x80000000; \ 173221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0x40000000; \ 174221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0x10000000; \ 175221167Sgnn } \ 176221167Sgnn} 177221167Sgnn 178221167Sgnn#define VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(hldev, i) { \ 179221167Sgnn if (i < 16) { \ 180221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask0[0] &= \ 181221167Sgnn ~vBIT(0x8, (i*4), 4); \ 182221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask0[1] &= \ 183221167Sgnn ~vBIT(0x4, (i*4), 4); \ 184221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask0[3] &= \ 185221167Sgnn ~vBIT(0x1, (i*4), 4); \ 186221167Sgnn } else { \ 187221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0; \ 188221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0; \ 189221167Sgnn ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0; \ 190221167Sgnn } \ 191221167Sgnn} 192221167Sgnn 193221167Sgnn/* ========================== PRIVATE API ================================= */ 194221167Sgnn 195221167Sgnnvoid 196221167Sgnnvxge_hal_pio_mem_write32_upper(pci_dev_h pdev, 197221167Sgnn pci_reg_h regh, 198221167Sgnn u32 val, 199221167Sgnn void *addr); 200221167Sgnn 201221167Sgnnvoid 202221167Sgnnvxge_hal_pio_mem_write32_lower(pci_dev_h pdev, 203221167Sgnn pci_reg_h regh, 204221167Sgnn u32 val, 205221167Sgnn void *addr); 206221167Sgnn 207221167Sgnnvoid 208221167Sgnn__hal_device_event_queued(void *data, 209221167Sgnn u32 event_type); 210221167Sgnn 211221167Sgnnvoid 212221167Sgnn__hal_device_pci_caps_list_process(__hal_device_t *hldev); 213221167Sgnn 214221167Sgnnvoid 215221167Sgnn__hal_device_pci_e_init(__hal_device_t *hldev); 216221167Sgnn 217221167Sgnnvxge_hal_status_e 218221167Sgnnvxge_hal_device_register_poll(pci_dev_h pdev, 219221167Sgnn pci_reg_h regh, 220221167Sgnn u64 *reg, 221221167Sgnn u32 op, 222221167Sgnn u64 mask, 223221167Sgnn u32 max_millis); 224221167Sgnn 225221167Sgnnvxge_hal_status_e 226221167Sgnn__hal_device_register_stall(pci_dev_h pdev, 227221167Sgnn pci_reg_h regh, 228221167Sgnn u64 *reg, 229221167Sgnn u32 op, 230221167Sgnn u64 mask, 231221167Sgnn u32 max_millis); 232221167Sgnn 233221167Sgnnvxge_hal_status_e 234221167Sgnn__hal_device_reg_addr_get(__hal_device_t *hldev); 235221167Sgnn 236221167Sgnnvoid 237221167Sgnn__hal_device_id_get(__hal_device_t *hldev); 238221167Sgnn 239221167Sgnnu32 240221167Sgnn__hal_device_access_rights_get(u32 host_type, u32 func_id); 241221167Sgnn 242221167Sgnnvoid 243221167Sgnn__hal_device_host_info_get(__hal_device_t *hldev); 244221167Sgnn 245221167Sgnnvxge_hal_status_e 246221167Sgnn__hal_device_hw_initialize(__hal_device_t *hldev); 247221167Sgnn 248221167Sgnnvxge_hal_status_e 249221167Sgnn__hal_device_reset(__hal_device_t *hldev); 250221167Sgnn 251221167Sgnnvxge_hal_status_e 252221167Sgnn__hal_device_handle_link_up_ind(__hal_device_t *hldev); 253221167Sgnn 254221167Sgnnvxge_hal_status_e 255221167Sgnn__hal_device_handle_link_down_ind(__hal_device_t *hldev); 256221167Sgnn 257221167Sgnnvoid 258221167Sgnn__hal_device_handle_error( 259221167Sgnn __hal_device_t *hldev, 260221167Sgnn u32 vp_id, 261221167Sgnn vxge_hal_event_e type); 262221167Sgnn 263221167Sgnn__EXTERN_END_DECLS 264221167Sgnn 265221167Sgnn#endif /* VXGE_HAL_DEVICE_H */ 266