if_uralreg.h revision 184610 
1/*	$FreeBSD: head/sys/dev/usb2/wlan/if_ural2_reg.h 184610 2008-11-04 02:31:03Z alfred $	*/
2
3/*-
4 * Copyright (c) 2005, 2006
5 *	Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define	RAL_NOISE_FLOOR		-95
21#define	RAL_RSSI_CORR		120
22
23#define	RAL_RX_DESC_SIZE	(sizeof (struct ural_rx_desc))
24#define	RAL_TX_DESC_SIZE	(sizeof (struct ural_tx_desc))
25#define	RAL_FRAME_SIZE		0x780	/* NOTE: using 0x980 does not work */
26#if (RAL_FRAME_SIZE % 0x80)
27#error "Invalid RAL_FRAME_SIZE"
28#endif
29
30#define	RAL_CONFIG_NO	1
31#define	RAL_IFACE_INDEX 0
32
33#define	RAL_VENDOR_REQUEST	0x01
34#define	RAL_WRITE_MAC		0x02
35#define	RAL_READ_MAC		0x03
36#define	RAL_WRITE_MULTI_MAC	0x06
37#define	RAL_READ_MULTI_MAC	0x07
38#define	RAL_READ_EEPROM		0x09
39
40/* MAC registers. */
41#define	RAL_MAC_CSR0	0x0400		/* ASIC Version */
42#define	RAL_MAC_CSR1	0x0402		/* System control */
43#define	RAL_MAC_CSR2	0x0404		/* MAC addr0 */
44#define	RAL_MAC_CSR3	0x0406		/* MAC addr1 */
45#define	RAL_MAC_CSR4	0x0408		/* MAC addr2 */
46#define	RAL_MAC_CSR5	0x040a		/* BSSID0 */
47#define	RAL_MAC_CSR6	0x040c		/* BSSID1 */
48#define	RAL_MAC_CSR7	0x040e		/* BSSID2 */
49#define	RAL_MAC_CSR8	0x0410		/* Max frame length */
50#define	RAL_MAC_CSR9	0x0412		/* Timer control */
51#define	RAL_MAC_CSR10	0x0414		/* Slot time */
52#define	RAL_MAC_CSR11	0x0416		/* IFS */
53#define	RAL_MAC_CSR12	0x0418		/* EIFS */
54#define	RAL_MAC_CSR13	0x041a		/* Power mode0 */
55#define	RAL_MAC_CSR14	0x041c		/* Power mode1 */
56#define	RAL_MAC_CSR15	0x041e		/* Power saving transition0 */
57#define	RAL_MAC_CSR16	0x0420		/* Power saving transition1 */
58#define	RAL_MAC_CSR17	0x0422		/* Power state control */
59#define	RAL_MAC_CSR18	0x0424		/* Auto wake-up control */
60#define	RAL_MAC_CSR19	0x0426		/* GPIO control */
61#define	RAL_MAC_CSR20	0x0428		/* LED control0 */
62#define	RAL_MAC_CSR22	0x042c		/* XXX not documented */
63
64/* Tx/Rx Registers. */
65#define	RAL_TXRX_CSR0	0x0440		/* Security control */
66#define	RAL_TXRX_CSR2	0x0444		/* Rx control */
67#define	RAL_TXRX_CSR5	0x044a		/* CCK Tx BBP ID0 */
68#define	RAL_TXRX_CSR6	0x044c		/* CCK Tx BBP ID1 */
69#define	RAL_TXRX_CSR7	0x044e		/* OFDM Tx BBP ID0 */
70#define	RAL_TXRX_CSR8	0x0450		/* OFDM Tx BBP ID1 */
71#define	RAL_TXRX_CSR10	0x0454		/* Auto responder control */
72#define	RAL_TXRX_CSR11	0x0456		/* Auto responder basic rate */
73#define	RAL_TXRX_CSR18	0x0464		/* Beacon interval */
74#define	RAL_TXRX_CSR19	0x0466		/* Beacon/sync control */
75#define	RAL_TXRX_CSR20	0x0468		/* Beacon alignment */
76#define	RAL_TXRX_CSR21	0x046a		/* XXX not documented */
77
78/* Security registers. */
79#define	RAL_SEC_CSR0	0x0480		/* Shared key 0, word 0 */
80
81/* PHY registers. */
82#define	RAL_PHY_CSR2	0x04c4		/* Tx MAC configuration */
83#define	RAL_PHY_CSR4	0x04c8		/* Interface configuration */
84#define	RAL_PHY_CSR5	0x04ca		/* BBP Pre-Tx CCK */
85#define	RAL_PHY_CSR6	0x04cc		/* BBP Pre-Tx OFDM */
86#define	RAL_PHY_CSR7	0x04ce		/* BBP serial control */
87#define	RAL_PHY_CSR8	0x04d0		/* BBP serial status */
88#define	RAL_PHY_CSR9	0x04d2		/* RF serial control0 */
89#define	RAL_PHY_CSR10	0x04d4		/* RF serial control1 */
90
91/* Statistics registers. */
92#define	RAL_STA_CSR0	0x04e0		/* FCS error */
93
94#define	RAL_DISABLE_RX		(1 << 0)
95#define	RAL_DROP_CRC		(1 << 1)
96#define	RAL_DROP_PHY		(1 << 2)
97#define	RAL_DROP_CTL		(1 << 3)
98#define	RAL_DROP_NOT_TO_ME	(1 << 4)
99#define	RAL_DROP_TODS		(1 << 5)
100#define	RAL_DROP_BAD_VERSION	(1 << 6)
101#define	RAL_DROP_MULTICAST	(1 << 9)
102#define	RAL_DROP_BROADCAST	(1 << 10)
103
104#define	RAL_SHORT_PREAMBLE	(1 << 2)
105
106#define	RAL_RESET_ASIC	(1 << 0)
107#define	RAL_RESET_BBP	(1 << 1)
108#define	RAL_HOST_READY	(1 << 2)
109
110#define	RAL_ENABLE_TSF			(1 << 0)
111#define	RAL_ENABLE_TSF_SYNC(x)		(((x) & 0x3) << 1)
112#define	RAL_ENABLE_TBCN			(1 << 3)
113#define	RAL_ENABLE_BEACON_GENERATOR	(1 << 4)
114
115#define	RAL_RF_AWAKE	(3 << 7)
116#define	RAL_BBP_AWAKE	(3 << 5)
117
118#define	RAL_BBP_WRITE	(1 << 15)
119#define	RAL_BBP_BUSY	(1 << 0)
120
121#define	RAL_RF1_AUTOTUNE	0x08000
122#define	RAL_RF3_AUTOTUNE	0x00040
123
124#define	RAL_RF_2522	0x00
125#define	RAL_RF_2523	0x01
126#define	RAL_RF_2524	0x02
127#define	RAL_RF_2525	0x03
128#define	RAL_RF_2525E	0x04
129#define	RAL_RF_2526	0x05
130/* dual-band RF */
131#define	RAL_RF_5222	0x10
132
133#define	RAL_BBP_VERSION	0
134#define	RAL_BBP_TX	2
135#define	RAL_BBP_RX	14
136
137#define	RAL_BBP_ANTA		0x00
138#define	RAL_BBP_DIVERSITY	0x01
139#define	RAL_BBP_ANTB		0x02
140#define	RAL_BBP_ANTMASK		0x03
141#define	RAL_BBP_FLIPIQ		0x04
142
143#define	RAL_JAPAN_FILTER	0x08
144
145#define	RAL_RF_LOBUSY		(1 << 15)
146#define	RAL_RF_BUSY		(1 << 31)
147#define	RAL_RF_20BIT		(20 << 24)
148
149#define	RAL_RF1			0
150#define	RAL_RF2			2
151#define	RAL_RF3			1
152#define	RAL_RF4			3
153
154#define	RAL_EEPROM_ADDRESS	0x0004
155#define	RAL_EEPROM_TXPOWER	0x003c
156#define	RAL_EEPROM_CONFIG0	0x0016
157#define	RAL_EEPROM_BBP_BASE	0x001c
158
159struct ural_tx_desc {
160	uint32_t flags;
161#define	RAL_TX_PACKET_ID(x)     ((x) & 0xf)
162#define	RAL_TX_RETRY(x)		((x) << 4)
163#define	RAL_TX_MORE_FRAG	(1 << 8)
164#define	RAL_TX_ACK		(1 << 9)
165#define	RAL_TX_TIMESTAMP	(1 << 10)
166#define	RAL_TX_OFDM		(1 << 11)
167#define	RAL_TX_NEWSEQ		(1 << 12)
168#define	RAL_TX_IFS_MASK		0x00006000
169#define	RAL_TX_IFS_BACKOFF	(0 << 13)
170#define	RAL_TX_IFS_SIFS		(1 << 13)
171#define	RAL_TX_IFS_NEWBACKOFF	(2 << 13)
172#define	RAL_TX_IFS_NONE		(3 << 13)
173	uint16_t wme;
174#define	RAL_LOGCWMAX(x)		(((x) & 0xf) << 12)
175#define	RAL_LOGCWMIN(x)		(((x) & 0xf) << 8)
176#define	RAL_AIFSN(x)		(((x) & 0x3) << 6)
177#define	RAL_IVOFFSET(x)		(((x) & 0x3f))
178	uint16_t reserved1;
179	uint8_t	plcp_signal;
180	uint8_t	plcp_service;
181#define	RAL_PLCP_LENGEXT	0x80
182	uint8_t	plcp_length_lo;
183	uint8_t	plcp_length_hi;
184	uint32_t iv;
185	uint32_t eiv;
186} __packed;
187
188struct ural_rx_desc {
189	uint32_t flags;
190#define	RAL_RX_CRC_ERROR	(1 << 5)
191#define	RAL_RX_OFDM		(1 << 6)
192#define	RAL_RX_PHY_ERROR	(1 << 7)
193	uint8_t	rssi;
194	uint8_t	rate;
195	uint16_t reserved;
196	uint32_t iv;
197	uint32_t eiv;
198} __packed;
199