1190688Sweongyo/* $OpenBSD: if_uathreg.h,v 1.2 2006/09/18 16:34:23 damien Exp $ */ 2190688Sweongyo/* $FreeBSD$ */ 3190688Sweongyo 4190688Sweongyo/*- 5190688Sweongyo * Copyright (c) 2006 6190688Sweongyo * Damien Bergamini <damien.bergamini@free.fr> 7190688Sweongyo * Copyright (c) 2006 Sam Leffler, Errno Consulting 8190688Sweongyo * 9190688Sweongyo * Permission to use, copy, modify, and distribute this software for any 10190688Sweongyo * purpose with or without fee is hereby granted, provided that the above 11190688Sweongyo * copyright notice and this permission notice appear in all copies. 12190688Sweongyo * 13190688Sweongyo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14190688Sweongyo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15190688Sweongyo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16190688Sweongyo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17190688Sweongyo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18190688Sweongyo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19190688Sweongyo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20190688Sweongyo */ 21190688Sweongyo 22190688Sweongyo#define UATH_CONFIG_INDEX 0 23190688Sweongyo#define UATH_IFACE_INDEX 0 24190688Sweongyo 25190688Sweongyo/* all fields are big endian */ 26190688Sweongyostruct uath_fwblock { 27190688Sweongyo uint32_t flags; 28190688Sweongyo#define UATH_WRITE_BLOCK (1 << 4) 29190688Sweongyo 30190688Sweongyo uint32_t len; 31190688Sweongyo#define UATH_MAX_FWBLOCK_SIZE 2048 32190688Sweongyo 33190688Sweongyo uint32_t total; 34190688Sweongyo uint32_t remain; 35190688Sweongyo uint32_t rxtotal; 36190688Sweongyo uint32_t pad[123]; 37190688Sweongyo} __packed; 38190688Sweongyo 39190688Sweongyo#define UATH_MAX_CMDSZ 512 40190688Sweongyo 41190688Sweongyo/* 42190688Sweongyo * Messages are passed in Target Endianness. All fixed-size 43190688Sweongyo * fields of a WDS Control Message are treated as 32-bit 44190688Sweongyo * values and Control Msgs are guaranteed to be 32-bit aligned. 45190688Sweongyo * 46190688Sweongyo * The format of a WDS Control Message is as follows: 47190688Sweongyo * Message Length 32 bits 48190688Sweongyo * Message Opcode 32 bits 49190688Sweongyo * Message ID 32 bits 50190688Sweongyo * parameter 1 51190688Sweongyo * parameter 2 52190688Sweongyo * ... 53190688Sweongyo * 54190688Sweongyo * A variable-length parameter, or a parmeter that is larger than 55190688Sweongyo * 32 bits is passed as <length, data> pair, where length is a 56190688Sweongyo * 32-bit quantity and data is padded to 32 bits. 57190688Sweongyo */ 58190688Sweongyostruct uath_cmd_hdr { 59190688Sweongyo uint32_t len; /* msg length including header */ 60190688Sweongyo uint32_t code; /* operation code */ 61190688Sweongyo/* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */ 62190688Sweongyo/* messages from Host -> Target */ 63190688Sweongyo#define WDCMSG_HOST_AVAILABLE 0x01 64190688Sweongyo#define WDCMSG_BIND 0x02 65190688Sweongyo#define WDCMSG_TARGET_RESET 0x03 66190688Sweongyo#define WDCMSG_TARGET_GET_CAPABILITY 0x04 67190688Sweongyo#define WDCMSG_TARGET_SET_CONFIG 0x05 68190688Sweongyo#define WDCMSG_TARGET_GET_STATUS 0x06 69190688Sweongyo#define WDCMSG_TARGET_GET_STATS 0x07 70190688Sweongyo#define WDCMSG_TARGET_START 0x08 71190688Sweongyo#define WDCMSG_TARGET_STOP 0x09 72190688Sweongyo#define WDCMSG_TARGET_ENABLE 0x0a 73190688Sweongyo#define WDCMSG_TARGET_DISABLE 0x0b 74190688Sweongyo#define WDCMSG_CREATE_CONNECTION 0x0c 75190688Sweongyo#define WDCMSG_UPDATE_CONNECT_ATTR 0x0d 76190688Sweongyo#define WDCMSG_DELETE_CONNECT 0x0e 77190688Sweongyo#define WDCMSG_SEND 0x0f 78190688Sweongyo#define WDCMSG_FLUSH 0x10 79190688Sweongyo/* messages from Target -> Host */ 80190688Sweongyo#define WDCMSG_STATS_UPDATE 0x11 81190688Sweongyo#define WDCMSG_BMISS 0x12 82190688Sweongyo#define WDCMSG_DEVICE_AVAIL 0x13 83190688Sweongyo#define WDCMSG_SEND_COMPLETE 0x14 84190688Sweongyo#define WDCMSG_DATA_AVAIL 0x15 85190688Sweongyo#define WDCMSG_SET_PWR_MODE 0x16 86190688Sweongyo#define WDCMSG_BMISS_ACK 0x17 87190688Sweongyo#define WDCMSG_SET_LED_STEADY 0x18 88190688Sweongyo#define WDCMSG_SET_LED_BLINK 0x19 89190688Sweongyo/* more messages */ 90190688Sweongyo#define WDCMSG_SETUP_BEACON_DESC 0x1a 91190688Sweongyo#define WDCMSG_BEACON_INIT 0x1b 92190688Sweongyo#define WDCMSG_RESET_KEY_CACHE 0x1c 93190688Sweongyo#define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d 94190688Sweongyo#define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e 95190688Sweongyo#define WDCMSG_SET_DECOMP_MASK 0x1f 96190688Sweongyo#define WDCMSG_SET_REGULATORY_DOMAIN 0x20 97190688Sweongyo#define WDCMSG_SET_LED_STATE 0x21 98190688Sweongyo#define WDCMSG_WRITE_ASSOCID 0x22 99190688Sweongyo#define WDCMSG_SET_STA_BEACON_TIMERS 0x23 100190688Sweongyo#define WDCMSG_GET_TSF 0x24 101190688Sweongyo#define WDCMSG_RESET_TSF 0x25 102190688Sweongyo#define WDCMSG_SET_ADHOC_MODE 0x26 103190688Sweongyo#define WDCMSG_SET_BASIC_RATE 0x27 104190688Sweongyo#define WDCMSG_MIB_CONTROL 0x28 105190688Sweongyo#define WDCMSG_GET_CHANNEL_DATA 0x29 106190688Sweongyo#define WDCMSG_GET_CUR_RSSI 0x2a 107190688Sweongyo#define WDCMSG_SET_ANTENNA_SWITCH 0x2b 108190688Sweongyo#define WDCMSG_USE_SHORT_SLOT_TIME 0x2f 109190688Sweongyo#define WDCMSG_SET_POWER_MODE 0x30 110190688Sweongyo#define WDCMSG_SETUP_PSPOLL_DESC 0x31 111190688Sweongyo#define WDCMSG_SET_RX_MULTICAST_FILTER 0x32 112190688Sweongyo#define WDCMSG_RX_FILTER 0x33 113190688Sweongyo#define WDCMSG_PER_CALIBRATION 0x34 114190688Sweongyo#define WDCMSG_RESET 0x35 115190688Sweongyo#define WDCMSG_DISABLE 0x36 116190688Sweongyo#define WDCMSG_PHY_DISABLE 0x37 117190688Sweongyo#define WDCMSG_SET_TX_POWER_LIMIT 0x38 118190688Sweongyo#define WDCMSG_SET_TX_QUEUE_PARAMS 0x39 119190688Sweongyo#define WDCMSG_SETUP_TX_QUEUE 0x3a 120190688Sweongyo#define WDCMSG_RELEASE_TX_QUEUE 0x3b 121190688Sweongyo#define WDCMSG_SET_DEFAULT_KEY 0x43 122190688Sweongyo uint32_t msgid; /* msg id (supplied by host) */ 123190688Sweongyo uint32_t magic; /* response desired/target status */ 124190688Sweongyo uint32_t debug[4]; /* debug data area */ 125190688Sweongyo /* msg data follows */ 126190688Sweongyo} __packed; 127190688Sweongyo 128190688Sweongyostruct uath_chunk { 129190688Sweongyo uint8_t seqnum; /* sequence number for ordering */ 130190688Sweongyo uint8_t flags; 131190688Sweongyo#define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */ 132190688Sweongyo#define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */ 133190688Sweongyo#define UATH_CFLAGS_DEBUG 0x04 /* for debugging */ 134190688Sweongyo uint16_t length; /* chunk size in bytes */ 135190688Sweongyo /* chunk data follows */ 136190688Sweongyo} __packed; 137190688Sweongyo 138190688Sweongyo#define UATH_RX_DUMMYSIZE 4 139190688Sweongyo 140190688Sweongyo/* 141190688Sweongyo * Message format for a WDCMSG_DATA_AVAIL message from Target to Host. 142190688Sweongyo */ 143190688Sweongyostruct uath_rx_desc { 144190688Sweongyo uint32_t len; /* msg length including header */ 145190688Sweongyo uint32_t code; /* WDCMSG_DATA_AVAIL */ 146190688Sweongyo uint32_t gennum; /* generation number */ 147190688Sweongyo uint32_t status; /* start of RECEIVE_INFO */ 148190688Sweongyo#define UATH_STATUS_OK 0 149190688Sweongyo#define UATH_STATUS_STOP_IN_PROGRESS 1 150190688Sweongyo#define UATH_STATUS_CRC_ERR 2 151190688Sweongyo#define UATH_STATUS_PHY_ERR 3 152190688Sweongyo#define UATH_STATUS_DECRYPT_CRC_ERR 4 153190688Sweongyo#define UATH_STATUS_DECRYPT_MIC_ERR 5 154190688Sweongyo#define UATH_STATUS_DECOMP_ERR 6 155190688Sweongyo#define UATH_STATUS_KEY_ERR 7 156190688Sweongyo#define UATH_STATUS_ERR 8 157190688Sweongyo uint32_t tstamp_low; /* low-order 32-bits of rx timestamp */ 158190688Sweongyo uint32_t tstamp_high; /* high-order 32-bits of rx timestamp */ 159190688Sweongyo uint32_t framelen; /* frame length */ 160190688Sweongyo uint32_t rate; /* rx rate code */ 161190688Sweongyo uint32_t antenna; 162190688Sweongyo int32_t rssi; 163190688Sweongyo uint32_t channel; 164190688Sweongyo uint32_t phyerror; 165190688Sweongyo uint32_t connix; /* key table ix for bss traffic */ 166190688Sweongyo uint32_t decrypterror; 167190688Sweongyo uint32_t keycachemiss; 168190688Sweongyo uint32_t pad; /* XXX? */ 169190688Sweongyo} __packed; 170190688Sweongyo 171190688Sweongyostruct uath_tx_desc { 172190688Sweongyo uint32_t msglen; 173190688Sweongyo uint32_t msgid; /* msg id (supplied by host) */ 174190688Sweongyo uint32_t type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */ 175190688Sweongyo uint32_t txqid; /* tx queue id and flags */ 176190688Sweongyo#define UATH_TXQID_MASK 0x0f 177190688Sweongyo#define UATH_TXQID_MINRATE 0x10 /* use min tx rate */ 178190688Sweongyo#define UATH_TXQID_FF 0x20 /* content is fast frame */ 179190688Sweongyo uint32_t connid; /* tx connection id */ 180190688Sweongyo#define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */ 181190688Sweongyo uint32_t flags; /* non-zero if response desired */ 182190688Sweongyo#define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */ 183190688Sweongyo uint32_t buflen; /* payload length */ 184190688Sweongyo} __packed; 185190688Sweongyo 186190688Sweongyostruct uath_cmd_host_available { 187190688Sweongyo uint32_t sw_ver_major; 188190688Sweongyo uint32_t sw_ver_minor; 189190688Sweongyo uint32_t sw_ver_patch; 190190688Sweongyo uint32_t sw_ver_build; 191190688Sweongyo} __packed; 192190688Sweongyo#define ATH_SW_VER_MAJOR 1 193190688Sweongyo#define ATH_SW_VER_MINOR 5 194190688Sweongyo#define ATH_SW_VER_PATCH 0 195190688Sweongyo#define ATH_SW_VER_BUILD 9999 196190688Sweongyo 197190688Sweongyostruct uath_cmd_bind { 198190688Sweongyo uint32_t targethandle; 199190688Sweongyo uint32_t hostapiversion; 200190688Sweongyo} __packed; 201190688Sweongyo 202190688Sweongyo/* structure for command WDCMSG_RESET */ 203190688Sweongyostruct uath_cmd_reset { 204190688Sweongyo uint32_t flags; /* channel flags */ 205190688Sweongyo#define UATH_CHAN_TURBO 0x0100 206190688Sweongyo#define UATH_CHAN_CCK 0x0200 207190688Sweongyo#define UATH_CHAN_OFDM 0x0400 208190688Sweongyo#define UATH_CHAN_2GHZ 0x1000 209190688Sweongyo#define UATH_CHAN_5GHZ 0x2000 210190688Sweongyo uint32_t freq; /* channel frequency */ 211190688Sweongyo uint32_t maxrdpower; 212190688Sweongyo uint32_t cfgctl; 213190688Sweongyo uint32_t twiceantennareduction; 214190688Sweongyo uint32_t channelchange; 215190688Sweongyo uint32_t keeprccontent; 216190688Sweongyo} __packed; 217190688Sweongyo 218190688Sweongyo/* structure for commands UATH_CMD_READ_MAC and UATH_CMD_READ_EEPROM */ 219190688Sweongyostruct uath_read_mac { 220190688Sweongyo uint32_t len; 221190688Sweongyo uint8_t data[32]; 222190688Sweongyo} __packed; 223190688Sweongyo 224190688Sweongyo/* structure for command UATH_CMD_WRITE_MAC */ 225190688Sweongyostruct uath_write_mac { 226190688Sweongyo uint32_t reg; 227190688Sweongyo uint32_t len; 228190688Sweongyo uint8_t data[32]; 229190688Sweongyo} __packed; 230190688Sweongyo 231190688Sweongyo/* structure for command UATH_CMD_STA_JOIN */ 232190688Sweongyostruct uath_cmd_join_bss { 233190688Sweongyo uint32_t bssid; /* NB: use zero */ 234190688Sweongyo uint32_t bssmac[2]; /* bssid mac address */ 235190688Sweongyo uint32_t bsstype; 236190688Sweongyo uint32_t wlanmode; 237190688Sweongyo uint32_t beaconinterval; 238190688Sweongyo uint32_t dtiminterval; 239190688Sweongyo uint32_t cfpinterval; 240190688Sweongyo uint32_t atimwindow; 241190688Sweongyo uint32_t defaultrateix; 242190688Sweongyo uint32_t shortslottime11g; 243190688Sweongyo uint32_t sleepduration; 244190688Sweongyo uint32_t bmissthreshold; 245190688Sweongyo uint32_t tcppowerlimit; 246190688Sweongyo uint32_t quietduration; 247190688Sweongyo uint32_t quietoffset; 248190688Sweongyo uint32_t quietackctsallow; 249190688Sweongyo uint32_t bssdefaultkey; /* XXX? */ 250190688Sweongyo} __packed; 251190688Sweongyo 252190688Sweongyostruct uath_cmd_assoc_bss { 253190688Sweongyo uint32_t bssid; 254190688Sweongyo uint32_t associd; 255190688Sweongyo} __packed; 256190688Sweongyo 257190688Sweongyostruct uath_cmd_start_bss { 258190688Sweongyo uint32_t bssid; 259190688Sweongyo} __packed; 260190688Sweongyo 261190688Sweongyo/* structure for command UATH_CMD_0C */ 262190688Sweongyostruct uath_cmd_0c { 263190688Sweongyo uint32_t magic1; 264190688Sweongyo uint32_t magic2; 265190688Sweongyo uint32_t magic3; 266190688Sweongyo} __packed; 267190688Sweongyo 268190688Sweongyostruct uath_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */ 269190688Sweongyo uint32_t lednum; 270190688Sweongyo#define UATH_LED_LINK 0 271190688Sweongyo#define UATH_LED_ACTIVITY 1 272190688Sweongyo uint32_t ledmode; 273190688Sweongyo#define UATH_LED_OFF 0 274190688Sweongyo#define UATH_LED_ON 1 275190688Sweongyo} __packed; 276190688Sweongyo 277190688Sweongyostruct uath_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */ 278190688Sweongyo uint32_t lednum; 279190688Sweongyo uint32_t ledmode; 280190688Sweongyo uint32_t blinkrate; 281190688Sweongyo uint32_t slowmode; 282190688Sweongyo} __packed; 283190688Sweongyo 284190688Sweongyostruct uath_cmd_ledstate { /* WDCMSG_SET_LED_STATE */ 285190688Sweongyo uint32_t connected; 286190688Sweongyo} __packed; 287190688Sweongyo 288190688Sweongyostruct uath_connkey_rec { 289190688Sweongyo uint8_t bssid[IEEE80211_ADDR_LEN]; 290190688Sweongyo uint32_t keyiv; 291190688Sweongyo uint32_t extkeyiv; 292190688Sweongyo uint16_t keyflags; 293190688Sweongyo uint16_t keylen; 294190688Sweongyo uint16_t keytype; /* WEP, TKIP or AES */ 295190688Sweongyo /* As far as I know, MIPS 4Kp is 32-bit processor */ 296190688Sweongyo uint32_t priv; 297190688Sweongyo uint8_t keyval[32]; 298190688Sweongyo uint16_t aes_keylen; 299190688Sweongyo uint8_t aes_keyval[16]; 300190688Sweongyo uint8_t mic_txkeyval[8]; 301190688Sweongyo uint8_t mic_rxkeyval[8]; 302190688Sweongyo int64_t keyrsc[17]; 303190688Sweongyo int32_t keytsc[17]; 304190688Sweongyo int32_t keyexttsc[17]; 305190688Sweongyo} __packed; 306190688Sweongyo 307190688Sweongyo/* structure for command UATH_CMD_CRYPTO */ 308190688Sweongyostruct uath_cmd_crypto { 309190688Sweongyo uint32_t keyidx; 310190688Sweongyo#define UATH_DEFAULT_KEY 6 311190688Sweongyo uint32_t xorkey; 312190688Sweongyo uint32_t size; 313190688Sweongyo struct uath_connkey_rec rec; 314190688Sweongyo} __packed; 315190688Sweongyo 316190688Sweongyostruct uath_cmd_rateset { 317190688Sweongyo uint8_t length; 318190688Sweongyo#define UATH_MAX_NRATES 32 319190688Sweongyo uint8_t set[UATH_MAX_NRATES]; 320190688Sweongyo}; 321190688Sweongyo 322190688Sweongyo/* structure for command WDCMSG_SET_BASIC_RATE */ 323190688Sweongyostruct uath_cmd_rates { 324190688Sweongyo uint32_t connid; 325190688Sweongyo uint32_t keeprccontent; 326190688Sweongyo uint32_t size; 327190688Sweongyo struct uath_cmd_rateset rateset; 328190688Sweongyo} __packed; 329190688Sweongyo 330190688Sweongyoenum { 331190688Sweongyo WLAN_MODE_NONE = 0, 332190688Sweongyo WLAN_MODE_11b, 333190688Sweongyo WLAN_MODE_11a, 334190688Sweongyo WLAN_MODE_11g, 335190688Sweongyo WLAN_MODE_11a_TURBO, 336190688Sweongyo WLAN_MODE_11g_TURBO, 337190688Sweongyo WLAN_MODE_11a_TURBO_PRIME, 338190688Sweongyo WLAN_MODE_11g_TURBO_PRIME, 339190688Sweongyo WLAN_MODE_11a_XR, 340190688Sweongyo WLAN_MODE_11g_XR, 341190688Sweongyo}; 342190688Sweongyo 343190688Sweongyostruct uath_cmd_connection_attr { 344190688Sweongyo uint32_t longpreambleonly; 345190688Sweongyo struct uath_cmd_rateset rateset; 346190688Sweongyo uint32_t wlanmode; 347190688Sweongyo} __packed; 348190688Sweongyo 349190688Sweongyo/* structure for command WDCMSG_CREATE_CONNECTION */ 350190688Sweongyostruct uath_cmd_create_connection { 351190688Sweongyo uint32_t connid; 352190688Sweongyo uint32_t bssid; 353190688Sweongyo uint32_t size; 354190688Sweongyo struct uath_cmd_connection_attr connattr; 355190688Sweongyo} __packed; 356190688Sweongyo 357190688Sweongyostruct uath_cmd_txq_setparams { /* WDCMSG_SET_TX_QUEUE_PARAMS */ 358190688Sweongyo uint32_t qnum; 359190688Sweongyo uint32_t aifs; 360190688Sweongyo uint32_t logcwmin; 361190688Sweongyo uint32_t logcwmax; 362190688Sweongyo uint32_t bursttime; 363190688Sweongyo uint32_t qflags; 364190688Sweongyo} __packed; 365190688Sweongyo 366190688Sweongyostruct uath_cmd_txq_attr { 367190688Sweongyo uint32_t priority; 368190688Sweongyo uint32_t aifs; 369190688Sweongyo uint32_t logcwmin; 370190688Sweongyo uint32_t logcwmax; 371190688Sweongyo uint32_t bursttime; 372190688Sweongyo uint32_t mode; 373190688Sweongyo uint32_t qflags; 374190688Sweongyo} __packed; 375190688Sweongyo 376190688Sweongyostruct uath_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */ 377190688Sweongyo uint32_t qid; 378190688Sweongyo uint32_t len; 379190688Sweongyo struct uath_cmd_txq_attr attr; 380190688Sweongyo} __packed; 381190688Sweongyo 382190688Sweongyostruct uath_cmd_stoptxdma { /* WDCMSG_STOP_TX_DMA */ 383190688Sweongyo uint32_t qnum; 384190688Sweongyo uint32_t msec; 385190688Sweongyo} __packed; 386190688Sweongyo 387190688Sweongyo/* structure for command UATH_CMD_31 */ 388190688Sweongyostruct uath_cmd_31 { 389190688Sweongyo uint32_t magic1; 390190688Sweongyo uint32_t magic2; 391190688Sweongyo} __packed; 392190688Sweongyo 393190688Sweongyostruct uath_cmd_rx_filter { /* WDCMSG_RX_FILTER */ 394190688Sweongyo uint32_t bits; 395190688Sweongyo#define UATH_FILTER_RX_UCAST 0x00000001 396190688Sweongyo#define UATH_FILTER_RX_MCAST 0x00000002 397190688Sweongyo#define UATH_FILTER_RX_BCAST 0x00000004 398190688Sweongyo#define UATH_FILTER_RX_CONTROL 0x00000008 399190688Sweongyo#define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */ 400190688Sweongyo#define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */ 401190688Sweongyo#define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */ 402190688Sweongyo#define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */ 403190688Sweongyo#define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */ 404190688Sweongyo#define UATH_FILTER_RX_PROBE_REQ 0x00000800 405190688Sweongyo uint32_t op; 406190688Sweongyo#define UATH_FILTER_OP_INIT 0x0 407190688Sweongyo#define UATH_FILTER_OP_SET 0x1 408190688Sweongyo#define UATH_FILTER_OP_CLEAR 0x2 409190688Sweongyo#define UATH_FILTER_OP_TEMP 0x3 410190688Sweongyo#define UATH_FILTER_OP_RESTORE 0x4 411190688Sweongyo} __packed; 412190688Sweongyo 413190688Sweongyostruct uath_cmd_rx_mcast_filter { /* WDCMSG_SET_RX_MCAST_FILTER */ 414190688Sweongyo uint32_t filter0; 415190688Sweongyo uint32_t filter1; 416190688Sweongyo} __packed; 417190688Sweongyo 418190688Sweongyostruct uath_cmd_set_associd { /* WDCMSG_WRITE_ASSOCID */ 419190688Sweongyo uint32_t defaultrateix; 420190688Sweongyo uint32_t associd; 421190688Sweongyo uint32_t timoffset; 422190688Sweongyo uint32_t turboprime; 423190688Sweongyo uint32_t bssid[2]; 424190688Sweongyo} __packed; 425190688Sweongyo 426190688Sweongyostruct uath_cmd_set_stabeacon_timers { /* WDCMSG_SET_STA_BEACON_TIMERS */ 427190688Sweongyo uint32_t nexttbtt; 428190688Sweongyo uint32_t nextdtim; 429190688Sweongyo uint32_t nextcfp; 430190688Sweongyo uint32_t beaconperiod; 431190688Sweongyo uint32_t dtimperiod; 432190688Sweongyo uint32_t cfpperiod; 433190688Sweongyo uint32_t cfpduration; 434190688Sweongyo uint32_t sleepduration; 435190688Sweongyo uint32_t bsmissthreshold; 436190688Sweongyo} __packed; 437190688Sweongyo 438190688Sweongyoenum { 439190688Sweongyo CFG_NONE, /* Sentinal to indicate "no config" */ 440190688Sweongyo CFG_REG_DOMAIN, /* Regulatory Domain */ 441190688Sweongyo CFG_RATE_CONTROL_ENABLE, 442190688Sweongyo CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */ 443190688Sweongyo CFG_HW_TX_RETRIES, 444190688Sweongyo CFG_SW_TX_RETRIES, 445190688Sweongyo CFG_SLOW_CLOCK_ENABLE, 446190688Sweongyo CFG_COMP_PROC, 447190688Sweongyo CFG_USER_RTS_THRESHOLD, 448190688Sweongyo CFG_XR2NORM_RATE_THRESHOLD, 449190688Sweongyo CFG_XRMODE_SWITCH_COUNT, 450190688Sweongyo CFG_PROTECTION_TYPE, 451190688Sweongyo CFG_BURST_SEQ_THRESHOLD, 452190688Sweongyo CFG_ABOLT, 453190688Sweongyo CFG_IQ_LOG_COUNT_MAX, 454190688Sweongyo CFG_MODE_CTS, 455190688Sweongyo CFG_WME_ENABLED, 456190688Sweongyo CFG_GPRS_CBR_PERIOD, 457190688Sweongyo CFG_SERVICE_TYPE, 458190688Sweongyo /* MAC Address to use. Overrides EEPROM */ 459190688Sweongyo CFG_MAC_ADDR, 460190688Sweongyo CFG_DEBUG_EAR, 461190688Sweongyo CFG_INIT_REGS, 462190688Sweongyo /* An ID for use in error & debug messages */ 463190688Sweongyo CFG_DEBUG_ID, 464190688Sweongyo CFG_COMP_WIN_SZ, 465190688Sweongyo CFG_DIVERSITY_CTL, 466190688Sweongyo CFG_TP_SCALE, 467190688Sweongyo CFG_TPC_HALF_DBM5, 468190688Sweongyo CFG_TPC_HALF_DBM2, 469190688Sweongyo CFG_OVERRD_TX_POWER, 470190688Sweongyo CFG_USE_32KHZ_CLOCK, 471190688Sweongyo CFG_GMODE_PROTECTION, 472190688Sweongyo CFG_GMODE_PROTECT_RATE_INDEX, 473190688Sweongyo CFG_GMODE_NON_ERP_PREAMBLE, 474190688Sweongyo CFG_WDC_TRANSPORT_CHUNK_SIZE, 475190688Sweongyo}; 476190688Sweongyo 477190688Sweongyoenum { 478190688Sweongyo /* Sentinal to indicate "no capability" */ 479190688Sweongyo CAP_NONE, 480190688Sweongyo CAP_ALL, /* ALL capabilities */ 481190688Sweongyo CAP_TARGET_VERSION, 482190688Sweongyo CAP_TARGET_REVISION, 483190688Sweongyo CAP_MAC_VERSION, 484190688Sweongyo CAP_MAC_REVISION, 485190688Sweongyo CAP_PHY_REVISION, 486190688Sweongyo CAP_ANALOG_5GHz_REVISION, 487190688Sweongyo CAP_ANALOG_2GHz_REVISION, 488190688Sweongyo /* Target supports WDC message debug features */ 489190688Sweongyo CAP_DEBUG_WDCMSG_SUPPORT, 490190688Sweongyo 491190688Sweongyo CAP_REG_DOMAIN, 492190688Sweongyo CAP_COUNTRY_CODE, 493190688Sweongyo CAP_REG_CAP_BITS, 494190688Sweongyo 495190688Sweongyo CAP_WIRELESS_MODES, 496190688Sweongyo CAP_CHAN_SPREAD_SUPPORT, 497190688Sweongyo CAP_SLEEP_AFTER_BEACON_BROKEN, 498190688Sweongyo CAP_COMPRESS_SUPPORT, 499190688Sweongyo CAP_BURST_SUPPORT, 500190688Sweongyo CAP_FAST_FRAMES_SUPPORT, 501190688Sweongyo CAP_CHAP_TUNING_SUPPORT, 502190688Sweongyo CAP_TURBOG_SUPPORT, 503190688Sweongyo CAP_TURBO_PRIME_SUPPORT, 504190688Sweongyo CAP_DEVICE_TYPE, 505190688Sweongyo CAP_XR_SUPPORT, 506190688Sweongyo CAP_WME_SUPPORT, 507190688Sweongyo CAP_TOTAL_QUEUES, 508190688Sweongyo CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */ 509190688Sweongyo 510190688Sweongyo CAP_LOW_5GHZ_CHAN, 511190688Sweongyo CAP_HIGH_5GHZ_CHAN, 512190688Sweongyo CAP_LOW_2GHZ_CHAN, 513190688Sweongyo CAP_HIGH_2GHZ_CHAN, 514190688Sweongyo 515190688Sweongyo CAP_MIC_AES_CCM, 516190688Sweongyo CAP_MIC_CKIP, 517190688Sweongyo CAP_MIC_TKIP, 518190688Sweongyo CAP_MIC_TKIP_WME, 519190688Sweongyo CAP_CIPHER_AES_CCM, 520190688Sweongyo CAP_CIPHER_CKIP, 521190688Sweongyo CAP_CIPHER_TKIP, 522190688Sweongyo 523190688Sweongyo CAP_TWICE_ANTENNAGAIN_5G, 524190688Sweongyo CAP_TWICE_ANTENNAGAIN_2G, 525190688Sweongyo}; 526190688Sweongyo 527190688Sweongyoenum { 528190688Sweongyo ST_NONE, /* Sentinal to indicate "no status" */ 529190688Sweongyo ST_ALL, 530190688Sweongyo ST_SERVICE_TYPE, 531190688Sweongyo ST_WLAN_MODE, 532190688Sweongyo ST_FREQ, 533190688Sweongyo ST_BAND, 534190688Sweongyo ST_LAST_RSSI, 535190688Sweongyo ST_PS_FRAMES_DROPPED, 536190688Sweongyo ST_CACHED_DEF_ANT, 537190688Sweongyo ST_COUNT_OTHER_RX_ANT, 538190688Sweongyo ST_USE_FAST_DIVERSITY, 539190688Sweongyo ST_MAC_ADDR, 540190688Sweongyo ST_RX_GENERATION_NUM, 541190688Sweongyo ST_TX_QUEUE_DEPTH, 542190688Sweongyo ST_SERIAL_NUMBER, 543190688Sweongyo ST_WDC_TRANSPORT_CHUNK_SIZE, 544190688Sweongyo}; 545190688Sweongyo 546190688Sweongyoenum { 547190688Sweongyo BSS_ATTR_BEACON_INTERVAL, 548190688Sweongyo BSS_ATTR_DTIM_INTERVAL, 549190688Sweongyo BSS_ATTR_CFP_INTERVAL, 550190688Sweongyo BSS_ATTR_CFP_MAX_DURATION, 551190688Sweongyo BSS_ATTR_ATIM_WINDOW, 552190688Sweongyo BSS_ATTR_DEFAULT_RATE_INDEX, 553190688Sweongyo BSS_ATTR_SHORT_SLOT_TIME_11g, 554190688Sweongyo BSS_ATTR_SLEEP_DURATION, 555190688Sweongyo BSS_ATTR_BMISS_THRESHOLD, 556190688Sweongyo BSS_ATTR_TPC_POWER_LIMIT, 557190688Sweongyo BSS_ATTR_BSS_KEY_UPDATE, 558190688Sweongyo}; 559190688Sweongyo 560190688Sweongyostruct uath_cmd_update_bss_attribute { 561190688Sweongyo uint32_t bssid; 562190688Sweongyo uint32_t attribute; /* BSS_ATTR_BEACON_INTERVAL, et al. */ 563190688Sweongyo uint32_t cfgsize; /* should be zero 0 */ 564190688Sweongyo uint32_t cfgdata; 565190688Sweongyo}; 566190688Sweongyo 567190688Sweongyostruct uath_cmd_update_bss_attribute_key { 568190688Sweongyo uint32_t bssid; 569190688Sweongyo uint32_t attribute; /* BSS_ATTR_BSS_KEY_UPDATE */ 570190688Sweongyo uint32_t cfgsize; /* size of remaining data */ 571190688Sweongyo uint32_t bsskeyix; 572190688Sweongyo uint32_t isdefaultkey; 573190688Sweongyo uint32_t keyiv; /* IV generation control */ 574190688Sweongyo uint32_t extkeyiv; /* extended IV for TKIP & CCM */ 575190688Sweongyo uint32_t keyflags; 576190688Sweongyo uint32_t keytype; 577190688Sweongyo uint32_t initvalue; /* XXX */ 578190688Sweongyo uint32_t keyval[4]; 579190688Sweongyo uint32_t mictxkeyval[2]; 580190688Sweongyo uint32_t micrxkeyval[2]; 581190688Sweongyo uint32_t keyrsc[2]; 582190688Sweongyo}; 583190688Sweongyo 584190688Sweongyoenum { 585190688Sweongyo TARGET_DEVICE_AWAKE, 586190688Sweongyo TARGET_DEVICE_SLEEP, 587190688Sweongyo TARGET_DEVICE_PWRDN, 588190688Sweongyo TARGET_DEVICE_PWRSAVE, 589190688Sweongyo TARGET_DEVICE_SUSPEND, 590190688Sweongyo TARGET_DEVICE_RESUME, 591190688Sweongyo}; 592190688Sweongyo 593190688Sweongyo#define UATH_MAX_TXBUFSZ \ 594190688Sweongyo (sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc) + \ 595190688Sweongyo IEEE80211_MAX_LEN) 596190688Sweongyo 597190688Sweongyo/* 598190688Sweongyo * it's not easy to measure how the chunk is passed into the host if the target 599190688Sweongyo * passed the multi-chunks so just we check a minimal size we can imagine. 600190688Sweongyo */ 601190688Sweongyo#define UATH_MIN_RXBUFSZ (sizeof(struct uath_chunk)) 602