1203134Sthompsa/* $OpenBSD: rt2860reg.h,v 1.19 2009/05/18 19:25:07 damien Exp $ */ 2203134Sthompsa 3203134Sthompsa/*- 4203134Sthompsa * Copyright (c) 2007 5203134Sthompsa * Damien Bergamini <damien.bergamini@free.fr> 6203134Sthompsa * 7203134Sthompsa * Permission to use, copy, modify, and distribute this software for any 8203134Sthompsa * purpose with or without fee is hereby granted, provided that the above 9203134Sthompsa * copyright notice and this permission notice appear in all copies. 10203134Sthompsa * 11203134Sthompsa * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12203134Sthompsa * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13203134Sthompsa * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14203134Sthompsa * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15203134Sthompsa * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16203134Sthompsa * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17203134Sthompsa * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18203134Sthompsa * 19203134Sthompsa * $FreeBSD$ 20203134Sthompsa */ 21203134Sthompsa 22203134Sthompsa#ifndef _IF_RUNREG_H_ 23203134Sthompsa#define _IF_RUNREG_H_ 24203134Sthompsa 25261868Skevlo#define RT2860_CONFIG_NO 1 26261868Skevlo#define RT2860_IFACE_INDEX 0 27203134Sthompsa 28261868Skevlo#define RT3070_OPT_14 0x0114 29203134Sthompsa 30203134Sthompsa/* SCH/DMA registers */ 31261868Skevlo#define RT2860_INT_STATUS 0x0200 32261868Skevlo#define RT2860_INT_MASK 0x0204 33261868Skevlo#define RT2860_WPDMA_GLO_CFG 0x0208 34261868Skevlo#define RT2860_WPDMA_RST_IDX 0x020c 35261868Skevlo#define RT2860_DELAY_INT_CFG 0x0210 36261868Skevlo#define RT2860_WMM_AIFSN_CFG 0x0214 37261868Skevlo#define RT2860_WMM_CWMIN_CFG 0x0218 38261868Skevlo#define RT2860_WMM_CWMAX_CFG 0x021c 39261868Skevlo#define RT2860_WMM_TXOP0_CFG 0x0220 40261868Skevlo#define RT2860_WMM_TXOP1_CFG 0x0224 41261868Skevlo#define RT2860_GPIO_CTRL 0x0228 42261868Skevlo#define RT2860_MCU_CMD_REG 0x022c 43261868Skevlo#define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 44261868Skevlo#define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 45261868Skevlo#define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 46261868Skevlo#define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 47261868Skevlo#define RT2860_RX_BASE_PTR 0x0290 48261868Skevlo#define RT2860_RX_MAX_CNT 0x0294 49261868Skevlo#define RT2860_RX_CALC_IDX 0x0298 50261868Skevlo#define RT2860_FS_DRX_IDX 0x029c 51261868Skevlo#define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 52261868Skevlo#define RT2860_US_CYC_CNT 0x02a4 53203134Sthompsa 54203134Sthompsa/* PBF registers */ 55261868Skevlo#define RT2860_SYS_CTRL 0x0400 56261868Skevlo#define RT2860_HOST_CMD 0x0404 57261868Skevlo#define RT2860_PBF_CFG 0x0408 58261868Skevlo#define RT2860_MAX_PCNT 0x040c 59261868Skevlo#define RT2860_BUF_CTRL 0x0410 60261868Skevlo#define RT2860_MCU_INT_STA 0x0414 61261868Skevlo#define RT2860_MCU_INT_ENA 0x0418 62261868Skevlo#define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 63261868Skevlo#define RT2860_RX0Q_IO 0x0424 64261868Skevlo#define RT2860_BCN_OFFSET0 0x042c 65261868Skevlo#define RT2860_BCN_OFFSET1 0x0430 66261868Skevlo#define RT2860_TXRXQ_STA 0x0434 67261868Skevlo#define RT2860_TXRXQ_PCNT 0x0438 68261868Skevlo#define RT2860_PBF_DBG 0x043c 69261868Skevlo#define RT2860_CAP_CTRL 0x0440 70203134Sthompsa 71203134Sthompsa/* RT3070 registers */ 72261868Skevlo#define RT3070_RF_CSR_CFG 0x0500 73261868Skevlo#define RT3070_EFUSE_CTRL 0x0580 74261868Skevlo#define RT3070_EFUSE_DATA0 0x0590 75261868Skevlo#define RT3070_EFUSE_DATA1 0x0594 76261868Skevlo#define RT3070_EFUSE_DATA2 0x0598 77261868Skevlo#define RT3070_EFUSE_DATA3 0x059c 78261868Skevlo#define RT3070_LDO_CFG0 0x05d4 79261868Skevlo#define RT3070_GPIO_SWITCH 0x05dc 80203134Sthompsa 81259453Shselasky/* RT5592 registers */ 82261868Skevlo#define RT5592_DEBUG_INDEX 0x05e8 83259453Shselasky 84203134Sthompsa/* MAC registers */ 85261868Skevlo#define RT2860_ASIC_VER_ID 0x1000 86261868Skevlo#define RT2860_MAC_SYS_CTRL 0x1004 87261868Skevlo#define RT2860_MAC_ADDR_DW0 0x1008 88261868Skevlo#define RT2860_MAC_ADDR_DW1 0x100c 89261868Skevlo#define RT2860_MAC_BSSID_DW0 0x1010 90261868Skevlo#define RT2860_MAC_BSSID_DW1 0x1014 91261868Skevlo#define RT2860_MAX_LEN_CFG 0x1018 92261868Skevlo#define RT2860_BBP_CSR_CFG 0x101c 93261868Skevlo#define RT2860_RF_CSR_CFG0 0x1020 94261868Skevlo#define RT2860_RF_CSR_CFG1 0x1024 95261868Skevlo#define RT2860_RF_CSR_CFG2 0x1028 96261868Skevlo#define RT2860_LED_CFG 0x102c 97203134Sthompsa 98203134Sthompsa/* undocumented registers */ 99261868Skevlo#define RT2860_DEBUG 0x10f4 100203134Sthompsa 101203134Sthompsa/* MAC Timing control registers */ 102261868Skevlo#define RT2860_XIFS_TIME_CFG 0x1100 103261868Skevlo#define RT2860_BKOFF_SLOT_CFG 0x1104 104261868Skevlo#define RT2860_NAV_TIME_CFG 0x1108 105261868Skevlo#define RT2860_CH_TIME_CFG 0x110c 106261868Skevlo#define RT2860_PBF_LIFE_TIMER 0x1110 107261868Skevlo#define RT2860_BCN_TIME_CFG 0x1114 108261868Skevlo#define RT2860_TBTT_SYNC_CFG 0x1118 109261868Skevlo#define RT2860_TSF_TIMER_DW0 0x111c 110261868Skevlo#define RT2860_TSF_TIMER_DW1 0x1120 111261868Skevlo#define RT2860_TBTT_TIMER 0x1124 112261868Skevlo#define RT2860_INT_TIMER_CFG 0x1128 113261868Skevlo#define RT2860_INT_TIMER_EN 0x112c 114261868Skevlo#define RT2860_CH_IDLE_TIME 0x1130 115203134Sthompsa 116203134Sthompsa/* MAC Power Save configuration registers */ 117261868Skevlo#define RT2860_MAC_STATUS_REG 0x1200 118261868Skevlo#define RT2860_PWR_PIN_CFG 0x1204 119261868Skevlo#define RT2860_AUTO_WAKEUP_CFG 0x1208 120203134Sthompsa 121203134Sthompsa/* MAC TX configuration registers */ 122261868Skevlo#define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 123261868Skevlo#define RT2860_EDCA_TID_AC_MAP 0x1310 124261868Skevlo#define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 125261868Skevlo#define RT2860_TX_PIN_CFG 0x1328 126261868Skevlo#define RT2860_TX_BAND_CFG 0x132c 127261868Skevlo#define RT2860_TX_SW_CFG0 0x1330 128261868Skevlo#define RT2860_TX_SW_CFG1 0x1334 129261868Skevlo#define RT2860_TX_SW_CFG2 0x1338 130261868Skevlo#define RT2860_TXOP_THRES_CFG 0x133c 131261868Skevlo#define RT2860_TXOP_CTRL_CFG 0x1340 132261868Skevlo#define RT2860_TX_RTS_CFG 0x1344 133261868Skevlo#define RT2860_TX_TIMEOUT_CFG 0x1348 134261868Skevlo#define RT2860_TX_RTY_CFG 0x134c 135261868Skevlo#define RT2860_TX_LINK_CFG 0x1350 136261868Skevlo#define RT2860_HT_FBK_CFG0 0x1354 137261868Skevlo#define RT2860_HT_FBK_CFG1 0x1358 138261868Skevlo#define RT2860_LG_FBK_CFG0 0x135c 139261868Skevlo#define RT2860_LG_FBK_CFG1 0x1360 140261868Skevlo#define RT2860_CCK_PROT_CFG 0x1364 141261868Skevlo#define RT2860_OFDM_PROT_CFG 0x1368 142261868Skevlo#define RT2860_MM20_PROT_CFG 0x136c 143261868Skevlo#define RT2860_MM40_PROT_CFG 0x1370 144261868Skevlo#define RT2860_GF20_PROT_CFG 0x1374 145261868Skevlo#define RT2860_GF40_PROT_CFG 0x1378 146261868Skevlo#define RT2860_EXP_CTS_TIME 0x137c 147261868Skevlo#define RT2860_EXP_ACK_TIME 0x1380 148203134Sthompsa 149203134Sthompsa/* MAC RX configuration registers */ 150261868Skevlo#define RT2860_RX_FILTR_CFG 0x1400 151261868Skevlo#define RT2860_AUTO_RSP_CFG 0x1404 152261868Skevlo#define RT2860_LEGACY_BASIC_RATE 0x1408 153261868Skevlo#define RT2860_HT_BASIC_RATE 0x140c 154261868Skevlo#define RT2860_HT_CTRL_CFG 0x1410 155261868Skevlo#define RT2860_SIFS_COST_CFG 0x1414 156261868Skevlo#define RT2860_RX_PARSER_CFG 0x1418 157203134Sthompsa 158203134Sthompsa/* MAC Security configuration registers */ 159261868Skevlo#define RT2860_TX_SEC_CNT0 0x1500 160261868Skevlo#define RT2860_RX_SEC_CNT0 0x1504 161261868Skevlo#define RT2860_CCMP_FC_MUTE 0x1508 162203134Sthompsa 163203134Sthompsa/* MAC HCCA/PSMP configuration registers */ 164261868Skevlo#define RT2860_TXOP_HLDR_ADDR0 0x1600 165261868Skevlo#define RT2860_TXOP_HLDR_ADDR1 0x1604 166261868Skevlo#define RT2860_TXOP_HLDR_ET 0x1608 167261868Skevlo#define RT2860_QOS_CFPOLL_RA_DW0 0x160c 168261868Skevlo#define RT2860_QOS_CFPOLL_A1_DW1 0x1610 169261868Skevlo#define RT2860_QOS_CFPOLL_QC 0x1614 170203134Sthompsa 171203134Sthompsa/* MAC Statistics Counters */ 172261868Skevlo#define RT2860_RX_STA_CNT0 0x1700 173261868Skevlo#define RT2860_RX_STA_CNT1 0x1704 174261868Skevlo#define RT2860_RX_STA_CNT2 0x1708 175261868Skevlo#define RT2860_TX_STA_CNT0 0x170c 176261868Skevlo#define RT2860_TX_STA_CNT1 0x1710 177261868Skevlo#define RT2860_TX_STA_CNT2 0x1714 178261868Skevlo#define RT2860_TX_STAT_FIFO 0x1718 179203134Sthompsa 180203134Sthompsa/* RX WCID search table */ 181261868Skevlo#define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 182203134Sthompsa 183261868Skevlo#define RT2860_FW_BASE 0x2000 184261868Skevlo#define RT2870_FW_BASE 0x3000 185203134Sthompsa 186203134Sthompsa/* Pair-wise key table */ 187261868Skevlo#define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 188203134Sthompsa 189203134Sthompsa/* IV/EIV table */ 190261868Skevlo#define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 191203134Sthompsa 192203134Sthompsa/* WCID attribute table */ 193261868Skevlo#define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 194203134Sthompsa 195203134Sthompsa/* Shared Key Table */ 196261868Skevlo#define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 197203134Sthompsa 198203134Sthompsa/* Shared Key Mode */ 199261868Skevlo#define RT2860_SKEY_MODE_0_7 0x7000 200261868Skevlo#define RT2860_SKEY_MODE_8_15 0x7004 201261868Skevlo#define RT2860_SKEY_MODE_16_23 0x7008 202261868Skevlo#define RT2860_SKEY_MODE_24_31 0x700c 203203134Sthompsa 204203134Sthompsa/* Shared Memory between MCU and host */ 205261868Skevlo#define RT2860_H2M_MAILBOX 0x7010 206261868Skevlo#define RT2860_H2M_MAILBOX_CID 0x7014 207261868Skevlo#define RT2860_H2M_MAILBOX_STATUS 0x701c 208261868Skevlo#define RT2860_H2M_INTSRC 0x7024 209261868Skevlo#define RT2860_H2M_BBPAGENT 0x7028 210261868Skevlo#define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 211203134Sthompsa 212203134Sthompsa 213203134Sthompsa/* possible flags for register RT2860_PCI_EECTRL */ 214261868Skevlo#define RT2860_C (1 << 0) 215261868Skevlo#define RT2860_S (1 << 1) 216261868Skevlo#define RT2860_D (1 << 2) 217261868Skevlo#define RT2860_SHIFT_D 2 218261868Skevlo#define RT2860_Q (1 << 3) 219261868Skevlo#define RT2860_SHIFT_Q 3 220203134Sthompsa 221203134Sthompsa/* possible flags for registers INT_STATUS/INT_MASK */ 222261868Skevlo#define RT2860_TX_COHERENT (1 << 17) 223261868Skevlo#define RT2860_RX_COHERENT (1 << 16) 224261868Skevlo#define RT2860_MAC_INT_4 (1 << 15) 225261868Skevlo#define RT2860_MAC_INT_3 (1 << 14) 226261868Skevlo#define RT2860_MAC_INT_2 (1 << 13) 227261868Skevlo#define RT2860_MAC_INT_1 (1 << 12) 228261868Skevlo#define RT2860_MAC_INT_0 (1 << 11) 229261868Skevlo#define RT2860_TX_RX_COHERENT (1 << 10) 230261868Skevlo#define RT2860_MCU_CMD_INT (1 << 9) 231261868Skevlo#define RT2860_TX_DONE_INT5 (1 << 8) 232261868Skevlo#define RT2860_TX_DONE_INT4 (1 << 7) 233261868Skevlo#define RT2860_TX_DONE_INT3 (1 << 6) 234261868Skevlo#define RT2860_TX_DONE_INT2 (1 << 5) 235261868Skevlo#define RT2860_TX_DONE_INT1 (1 << 4) 236261868Skevlo#define RT2860_TX_DONE_INT0 (1 << 3) 237261868Skevlo#define RT2860_RX_DONE_INT (1 << 2) 238261868Skevlo#define RT2860_TX_DLY_INT (1 << 1) 239261868Skevlo#define RT2860_RX_DLY_INT (1 << 0) 240203134Sthompsa 241203134Sthompsa/* possible flags for register WPDMA_GLO_CFG */ 242261868Skevlo#define RT2860_HDR_SEG_LEN_SHIFT 8 243261868Skevlo#define RT2860_BIG_ENDIAN (1 << 7) 244261868Skevlo#define RT2860_TX_WB_DDONE (1 << 6) 245261868Skevlo#define RT2860_WPDMA_BT_SIZE_SHIFT 4 246261868Skevlo#define RT2860_WPDMA_BT_SIZE16 0 247261868Skevlo#define RT2860_WPDMA_BT_SIZE32 1 248261868Skevlo#define RT2860_WPDMA_BT_SIZE64 2 249261868Skevlo#define RT2860_WPDMA_BT_SIZE128 3 250261868Skevlo#define RT2860_RX_DMA_BUSY (1 << 3) 251261868Skevlo#define RT2860_RX_DMA_EN (1 << 2) 252261868Skevlo#define RT2860_TX_DMA_BUSY (1 << 1) 253261868Skevlo#define RT2860_TX_DMA_EN (1 << 0) 254203134Sthompsa 255203134Sthompsa/* possible flags for register DELAY_INT_CFG */ 256261868Skevlo#define RT2860_TXDLY_INT_EN (1U << 31) 257261868Skevlo#define RT2860_TXMAX_PINT_SHIFT 24 258261868Skevlo#define RT2860_TXMAX_PTIME_SHIFT 16 259261868Skevlo#define RT2860_RXDLY_INT_EN (1 << 15) 260261868Skevlo#define RT2860_RXMAX_PINT_SHIFT 8 261261868Skevlo#define RT2860_RXMAX_PTIME_SHIFT 0 262203134Sthompsa 263203134Sthompsa/* possible flags for register GPIO_CTRL */ 264261868Skevlo#define RT2860_GPIO_D_SHIFT 8 265261868Skevlo#define RT2860_GPIO_O_SHIFT 0 266203134Sthompsa 267203134Sthompsa/* possible flags for register USB_DMA_CFG */ 268261868Skevlo#define RT2860_USB_TX_BUSY (1U << 31) 269261868Skevlo#define RT2860_USB_RX_BUSY (1 << 30) 270261868Skevlo#define RT2860_USB_EPOUT_VLD_SHIFT 24 271261868Skevlo#define RT2860_USB_TX_EN (1 << 23) 272261868Skevlo#define RT2860_USB_RX_EN (1 << 22) 273261868Skevlo#define RT2860_USB_RX_AGG_EN (1 << 21) 274261868Skevlo#define RT2860_USB_TXOP_HALT (1 << 20) 275261868Skevlo#define RT2860_USB_TX_CLEAR (1 << 19) 276261868Skevlo#define RT2860_USB_PHY_WD_EN (1 << 16) 277261868Skevlo#define RT2860_USB_PHY_MAN_RST (1 << 15) 278261868Skevlo#define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 279261868Skevlo#define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 280203134Sthompsa 281203134Sthompsa/* possible flags for register US_CYC_CNT */ 282261868Skevlo#define RT2860_TEST_EN (1 << 24) 283261868Skevlo#define RT2860_TEST_SEL_SHIFT 16 284261868Skevlo#define RT2860_BT_MODE_EN (1 << 8) 285261868Skevlo#define RT2860_US_CYC_CNT_SHIFT 0 286203134Sthompsa 287203134Sthompsa/* possible flags for register SYS_CTRL */ 288261868Skevlo#define RT2860_HST_PM_SEL (1 << 16) 289261868Skevlo#define RT2860_CAP_MODE (1 << 14) 290261868Skevlo#define RT2860_PME_OEN (1 << 13) 291261868Skevlo#define RT2860_CLKSELECT (1 << 12) 292261868Skevlo#define RT2860_PBF_CLK_EN (1 << 11) 293261868Skevlo#define RT2860_MAC_CLK_EN (1 << 10) 294261868Skevlo#define RT2860_DMA_CLK_EN (1 << 9) 295261868Skevlo#define RT2860_MCU_READY (1 << 7) 296261868Skevlo#define RT2860_ASY_RESET (1 << 4) 297261868Skevlo#define RT2860_PBF_RESET (1 << 3) 298261868Skevlo#define RT2860_MAC_RESET (1 << 2) 299261868Skevlo#define RT2860_DMA_RESET (1 << 1) 300261868Skevlo#define RT2860_MCU_RESET (1 << 0) 301203134Sthompsa 302203134Sthompsa/* possible values for register HOST_CMD */ 303261868Skevlo#define RT2860_MCU_CMD_SLEEP 0x30 304261868Skevlo#define RT2860_MCU_CMD_WAKEUP 0x31 305261868Skevlo#define RT2860_MCU_CMD_LEDS 0x50 306261868Skevlo#define RT2860_MCU_CMD_LED_RSSI 0x51 307261868Skevlo#define RT2860_MCU_CMD_LED1 0x52 308261868Skevlo#define RT2860_MCU_CMD_LED2 0x53 309261868Skevlo#define RT2860_MCU_CMD_LED3 0x54 310261868Skevlo#define RT2860_MCU_CMD_RFRESET 0x72 311261868Skevlo#define RT2860_MCU_CMD_ANTSEL 0x73 312261868Skevlo#define RT2860_MCU_CMD_BBP 0x80 313261868Skevlo#define RT2860_MCU_CMD_PSLEVEL 0x83 314203134Sthompsa 315203134Sthompsa/* possible flags for register PBF_CFG */ 316261868Skevlo#define RT2860_TX1Q_NUM_SHIFT 21 317261868Skevlo#define RT2860_TX2Q_NUM_SHIFT 16 318261868Skevlo#define RT2860_NULL0_MODE (1 << 15) 319261868Skevlo#define RT2860_NULL1_MODE (1 << 14) 320261868Skevlo#define RT2860_RX_DROP_MODE (1 << 13) 321261868Skevlo#define RT2860_TX0Q_MANUAL (1 << 12) 322261868Skevlo#define RT2860_TX1Q_MANUAL (1 << 11) 323261868Skevlo#define RT2860_TX2Q_MANUAL (1 << 10) 324261868Skevlo#define RT2860_RX0Q_MANUAL (1 << 9) 325261868Skevlo#define RT2860_HCCA_EN (1 << 8) 326261868Skevlo#define RT2860_TX0Q_EN (1 << 4) 327261868Skevlo#define RT2860_TX1Q_EN (1 << 3) 328261868Skevlo#define RT2860_TX2Q_EN (1 << 2) 329261868Skevlo#define RT2860_RX0Q_EN (1 << 1) 330203134Sthompsa 331203134Sthompsa/* possible flags for register BUF_CTRL */ 332261868Skevlo#define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 333261868Skevlo#define RT2860_NULL0_KICK (1 << 7) 334261868Skevlo#define RT2860_NULL1_KICK (1 << 6) 335261868Skevlo#define RT2860_BUF_RESET (1 << 5) 336261868Skevlo#define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 337261868Skevlo#define RT2860_READ_RX0Q (1 << 0) 338203134Sthompsa 339203134Sthompsa/* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 340261868Skevlo#define RT2860_MCU_MAC_INT_8 (1 << 24) 341261868Skevlo#define RT2860_MCU_MAC_INT_7 (1 << 23) 342261868Skevlo#define RT2860_MCU_MAC_INT_6 (1 << 22) 343261868Skevlo#define RT2860_MCU_MAC_INT_4 (1 << 20) 344261868Skevlo#define RT2860_MCU_MAC_INT_3 (1 << 19) 345261868Skevlo#define RT2860_MCU_MAC_INT_2 (1 << 18) 346261868Skevlo#define RT2860_MCU_MAC_INT_1 (1 << 17) 347261868Skevlo#define RT2860_MCU_MAC_INT_0 (1 << 16) 348261868Skevlo#define RT2860_DTX0_INT (1 << 11) 349261868Skevlo#define RT2860_DTX1_INT (1 << 10) 350261868Skevlo#define RT2860_DTX2_INT (1 << 9) 351261868Skevlo#define RT2860_DRX0_INT (1 << 8) 352261868Skevlo#define RT2860_HCMD_INT (1 << 7) 353261868Skevlo#define RT2860_N0TX_INT (1 << 6) 354261868Skevlo#define RT2860_N1TX_INT (1 << 5) 355261868Skevlo#define RT2860_BCNTX_INT (1 << 4) 356261868Skevlo#define RT2860_MTX0_INT (1 << 3) 357261868Skevlo#define RT2860_MTX1_INT (1 << 2) 358261868Skevlo#define RT2860_MTX2_INT (1 << 1) 359261868Skevlo#define RT2860_MRX0_INT (1 << 0) 360203134Sthompsa 361203134Sthompsa/* possible flags for register TXRXQ_PCNT */ 362261868Skevlo#define RT2860_RX0Q_PCNT_MASK 0xff000000 363261868Skevlo#define RT2860_TX2Q_PCNT_MASK 0x00ff0000 364261868Skevlo#define RT2860_TX1Q_PCNT_MASK 0x0000ff00 365261868Skevlo#define RT2860_TX0Q_PCNT_MASK 0x000000ff 366203134Sthompsa 367203134Sthompsa/* possible flags for register CAP_CTRL */ 368261868Skevlo#define RT2860_CAP_ADC_FEQ (1U << 31) 369261868Skevlo#define RT2860_CAP_START (1 << 30) 370261868Skevlo#define RT2860_MAN_TRIG (1 << 29) 371261868Skevlo#define RT2860_TRIG_OFFSET_SHIFT 16 372261868Skevlo#define RT2860_START_ADDR_SHIFT 0 373203134Sthompsa 374203134Sthompsa/* possible flags for register RF_CSR_CFG */ 375261868Skevlo#define RT3070_RF_KICK (1 << 17) 376261868Skevlo#define RT3070_RF_WRITE (1 << 16) 377203134Sthompsa 378203134Sthompsa/* possible flags for register EFUSE_CTRL */ 379261868Skevlo#define RT3070_SEL_EFUSE (1U << 31) 380261868Skevlo#define RT3070_EFSROM_KICK (1 << 30) 381261868Skevlo#define RT3070_EFSROM_AIN_MASK 0x03ff0000 382261868Skevlo#define RT3070_EFSROM_AIN_SHIFT 16 383261868Skevlo#define RT3070_EFSROM_MODE_MASK 0x000000c0 384261868Skevlo#define RT3070_EFUSE_AOUT_MASK 0x0000003f 385203134Sthompsa 386259453Shselasky/* possible flag for register DEBUG_INDEX */ 387261868Skevlo#define RT5592_SEL_XTAL (1U << 31) 388259453Shselasky 389203134Sthompsa/* possible flags for register MAC_SYS_CTRL */ 390261868Skevlo#define RT2860_RX_TS_EN (1 << 7) 391261868Skevlo#define RT2860_WLAN_HALT_EN (1 << 6) 392261868Skevlo#define RT2860_PBF_LOOP_EN (1 << 5) 393261868Skevlo#define RT2860_CONT_TX_TEST (1 << 4) 394261868Skevlo#define RT2860_MAC_RX_EN (1 << 3) 395261868Skevlo#define RT2860_MAC_TX_EN (1 << 2) 396261868Skevlo#define RT2860_BBP_HRST (1 << 1) 397261868Skevlo#define RT2860_MAC_SRST (1 << 0) 398203134Sthompsa 399203134Sthompsa/* possible flags for register MAC_BSSID_DW1 */ 400261868Skevlo#define RT2860_MULTI_BCN_NUM_SHIFT 18 401261868Skevlo#define RT2860_MULTI_BSSID_MODE_SHIFT 16 402203134Sthompsa 403203134Sthompsa/* possible flags for register MAX_LEN_CFG */ 404261868Skevlo#define RT2860_MIN_MPDU_LEN_SHIFT 16 405261868Skevlo#define RT2860_MAX_PSDU_LEN_SHIFT 12 406261868Skevlo#define RT2860_MAX_PSDU_LEN8K 0 407261868Skevlo#define RT2860_MAX_PSDU_LEN16K 1 408261868Skevlo#define RT2860_MAX_PSDU_LEN32K 2 409261868Skevlo#define RT2860_MAX_PSDU_LEN64K 3 410261868Skevlo#define RT2860_MAX_MPDU_LEN_SHIFT 0 411203134Sthompsa 412203134Sthompsa/* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 413261868Skevlo#define RT2860_BBP_RW_PARALLEL (1 << 19) 414261868Skevlo#define RT2860_BBP_PAR_DUR_112_5 (1 << 18) 415261868Skevlo#define RT2860_BBP_CSR_KICK (1 << 17) 416261868Skevlo#define RT2860_BBP_CSR_READ (1 << 16) 417261868Skevlo#define RT2860_BBP_ADDR_SHIFT 8 418261868Skevlo#define RT2860_BBP_DATA_SHIFT 0 419203134Sthompsa 420203134Sthompsa/* possible flags for register RF_CSR_CFG0 */ 421261868Skevlo#define RT2860_RF_REG_CTRL (1U << 31) 422261868Skevlo#define RT2860_RF_LE_SEL1 (1 << 30) 423261868Skevlo#define RT2860_RF_LE_STBY (1 << 29) 424261868Skevlo#define RT2860_RF_REG_WIDTH_SHIFT 24 425261868Skevlo#define RT2860_RF_REG_0_SHIFT 0 426203134Sthompsa 427203134Sthompsa/* possible flags for register RF_CSR_CFG1 */ 428261868Skevlo#define RT2860_RF_DUR_5 (1 << 24) 429261868Skevlo#define RT2860_RF_REG_1_SHIFT 0 430203134Sthompsa 431203134Sthompsa/* possible flags for register LED_CFG */ 432261868Skevlo#define RT2860_LED_POL (1 << 30) 433261868Skevlo#define RT2860_Y_LED_MODE_SHIFT 28 434261868Skevlo#define RT2860_G_LED_MODE_SHIFT 26 435261868Skevlo#define RT2860_R_LED_MODE_SHIFT 24 436261868Skevlo#define RT2860_LED_MODE_OFF 0 437261868Skevlo#define RT2860_LED_MODE_BLINK_TX 1 438261868Skevlo#define RT2860_LED_MODE_SLOW_BLINK 2 439261868Skevlo#define RT2860_LED_MODE_ON 3 440261868Skevlo#define RT2860_SLOW_BLK_TIME_SHIFT 16 441261868Skevlo#define RT2860_LED_OFF_TIME_SHIFT 8 442261868Skevlo#define RT2860_LED_ON_TIME_SHIFT 0 443203134Sthompsa 444203134Sthompsa/* possible flags for register XIFS_TIME_CFG */ 445261868Skevlo#define RT2860_BB_RXEND_EN (1 << 29) 446261868Skevlo#define RT2860_EIFS_TIME_SHIFT 20 447261868Skevlo#define RT2860_OFDM_XIFS_TIME_SHIFT 16 448261868Skevlo#define RT2860_OFDM_SIFS_TIME_SHIFT 8 449261868Skevlo#define RT2860_CCK_SIFS_TIME_SHIFT 0 450203134Sthompsa 451203134Sthompsa/* possible flags for register BKOFF_SLOT_CFG */ 452261868Skevlo#define RT2860_CC_DELAY_TIME_SHIFT 8 453261868Skevlo#define RT2860_SLOT_TIME 0 454203134Sthompsa 455203134Sthompsa/* possible flags for register NAV_TIME_CFG */ 456261868Skevlo#define RT2860_NAV_UPD (1U << 31) 457261868Skevlo#define RT2860_NAV_UPD_VAL_SHIFT 16 458261868Skevlo#define RT2860_NAV_CLR_EN (1 << 15) 459261868Skevlo#define RT2860_NAV_TIMER_SHIFT 0 460203134Sthompsa 461203134Sthompsa/* possible flags for register CH_TIME_CFG */ 462261868Skevlo#define RT2860_EIFS_AS_CH_BUSY (1 << 4) 463261868Skevlo#define RT2860_NAV_AS_CH_BUSY (1 << 3) 464261868Skevlo#define RT2860_RX_AS_CH_BUSY (1 << 2) 465261868Skevlo#define RT2860_TX_AS_CH_BUSY (1 << 1) 466261868Skevlo#define RT2860_CH_STA_TIMER_EN (1 << 0) 467203134Sthompsa 468203134Sthompsa/* possible values for register BCN_TIME_CFG */ 469261868Skevlo#define RT2860_TSF_INS_COMP_SHIFT 24 470261868Skevlo#define RT2860_BCN_TX_EN (1 << 20) 471261868Skevlo#define RT2860_TBTT_TIMER_EN (1 << 19) 472261868Skevlo#define RT2860_TSF_SYNC_MODE_SHIFT 17 473261868Skevlo#define RT2860_TSF_SYNC_MODE_DIS 0 474261868Skevlo#define RT2860_TSF_SYNC_MODE_STA 1 475261868Skevlo#define RT2860_TSF_SYNC_MODE_IBSS 2 476261868Skevlo#define RT2860_TSF_SYNC_MODE_HOSTAP 3 477261868Skevlo#define RT2860_TSF_TIMER_EN (1 << 16) 478261868Skevlo#define RT2860_BCN_INTVAL_SHIFT 0 479203134Sthompsa 480203134Sthompsa/* possible flags for register TBTT_SYNC_CFG */ 481261868Skevlo#define RT2860_BCN_CWMIN_SHIFT 20 482261868Skevlo#define RT2860_BCN_AIFSN_SHIFT 16 483261868Skevlo#define RT2860_BCN_EXP_WIN_SHIFT 8 484261868Skevlo#define RT2860_TBTT_ADJUST_SHIFT 0 485203134Sthompsa 486203134Sthompsa/* possible flags for register INT_TIMER_CFG */ 487261868Skevlo#define RT2860_GP_TIMER_SHIFT 16 488261868Skevlo#define RT2860_PRE_TBTT_TIMER_SHIFT 0 489203134Sthompsa 490203134Sthompsa/* possible flags for register INT_TIMER_EN */ 491261868Skevlo#define RT2860_GP_TIMER_EN (1 << 1) 492261868Skevlo#define RT2860_PRE_TBTT_INT_EN (1 << 0) 493203134Sthompsa 494203134Sthompsa/* possible flags for register MAC_STATUS_REG */ 495261868Skevlo#define RT2860_RX_STATUS_BUSY (1 << 1) 496261868Skevlo#define RT2860_TX_STATUS_BUSY (1 << 0) 497203134Sthompsa 498203134Sthompsa/* possible flags for register PWR_PIN_CFG */ 499261868Skevlo#define RT2860_IO_ADDA_PD (1 << 3) 500261868Skevlo#define RT2860_IO_PLL_PD (1 << 2) 501261868Skevlo#define RT2860_IO_RA_PE (1 << 1) 502261868Skevlo#define RT2860_IO_RF_PE (1 << 0) 503203134Sthompsa 504203134Sthompsa/* possible flags for register AUTO_WAKEUP_CFG */ 505261868Skevlo#define RT2860_AUTO_WAKEUP_EN (1 << 15) 506261868Skevlo#define RT2860_SLEEP_TBTT_NUM_SHIFT 8 507261868Skevlo#define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 508203134Sthompsa 509203134Sthompsa/* possible flags for register TX_PIN_CFG */ 510261868Skevlo#define RT2860_TRSW_POL (1 << 19) 511261868Skevlo#define RT2860_TRSW_EN (1 << 18) 512261868Skevlo#define RT2860_RFTR_POL (1 << 17) 513261868Skevlo#define RT2860_RFTR_EN (1 << 16) 514261868Skevlo#define RT2860_LNA_PE_G1_POL (1 << 15) 515261868Skevlo#define RT2860_LNA_PE_A1_POL (1 << 14) 516261868Skevlo#define RT2860_LNA_PE_G0_POL (1 << 13) 517261868Skevlo#define RT2860_LNA_PE_A0_POL (1 << 12) 518261868Skevlo#define RT2860_LNA_PE_G1_EN (1 << 11) 519261868Skevlo#define RT2860_LNA_PE_A1_EN (1 << 10) 520261868Skevlo#define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 521261868Skevlo#define RT2860_LNA_PE_G0_EN (1 << 9) 522261868Skevlo#define RT2860_LNA_PE_A0_EN (1 << 8) 523261868Skevlo#define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 524261868Skevlo#define RT2860_PA_PE_G1_POL (1 << 7) 525261868Skevlo#define RT2860_PA_PE_A1_POL (1 << 6) 526261868Skevlo#define RT2860_PA_PE_G0_POL (1 << 5) 527261868Skevlo#define RT2860_PA_PE_A0_POL (1 << 4) 528261868Skevlo#define RT2860_PA_PE_G1_EN (1 << 3) 529261868Skevlo#define RT2860_PA_PE_A1_EN (1 << 2) 530261868Skevlo#define RT2860_PA_PE_G0_EN (1 << 1) 531261868Skevlo#define RT2860_PA_PE_A0_EN (1 << 0) 532203134Sthompsa 533203134Sthompsa/* possible flags for register TX_BAND_CFG */ 534261868Skevlo#define RT2860_5G_BAND_SEL_N (1 << 2) 535261868Skevlo#define RT2860_5G_BAND_SEL_P (1 << 1) 536261868Skevlo#define RT2860_TX_BAND_SEL (1 << 0) 537203134Sthompsa 538203134Sthompsa/* possible flags for register TX_SW_CFG0 */ 539261868Skevlo#define RT2860_DLY_RFTR_EN_SHIFT 24 540261868Skevlo#define RT2860_DLY_TRSW_EN_SHIFT 16 541261868Skevlo#define RT2860_DLY_PAPE_EN_SHIFT 8 542261868Skevlo#define RT2860_DLY_TXPE_EN_SHIFT 0 543203134Sthompsa 544203134Sthompsa/* possible flags for register TX_SW_CFG1 */ 545261868Skevlo#define RT2860_DLY_RFTR_DIS_SHIFT 16 546261868Skevlo#define RT2860_DLY_TRSW_DIS_SHIFT 8 547261868Skevlo#define RT2860_DLY_PAPE_DIS SHIFT 0 548203134Sthompsa 549203134Sthompsa/* possible flags for register TX_SW_CFG2 */ 550261868Skevlo#define RT2860_DLY_LNA_EN_SHIFT 24 551261868Skevlo#define RT2860_DLY_LNA_DIS_SHIFT 16 552261868Skevlo#define RT2860_DLY_DAC_EN_SHIFT 8 553261868Skevlo#define RT2860_DLY_DAC_DIS_SHIFT 0 554203134Sthompsa 555203134Sthompsa/* possible flags for register TXOP_THRES_CFG */ 556261868Skevlo#define RT2860_TXOP_REM_THRES_SHIFT 24 557261868Skevlo#define RT2860_CF_END_THRES_SHIFT 16 558261868Skevlo#define RT2860_RDG_IN_THRES 8 559261868Skevlo#define RT2860_RDG_OUT_THRES 0 560203134Sthompsa 561203134Sthompsa/* possible flags for register TXOP_CTRL_CFG */ 562261868Skevlo#define RT2860_EXT_CW_MIN_SHIFT 16 563261868Skevlo#define RT2860_EXT_CCA_DLY_SHIFT 8 564261868Skevlo#define RT2860_EXT_CCA_EN (1 << 7) 565261868Skevlo#define RT2860_LSIG_TXOP_EN (1 << 6) 566261868Skevlo#define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) 567261868Skevlo#define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) 568261868Skevlo#define RT2860_TXOP_TRUN_EN_RATE (1 << 2) 569261868Skevlo#define RT2860_TXOP_TRUN_EN_AC (1 << 1) 570261868Skevlo#define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) 571203134Sthompsa 572203134Sthompsa/* possible flags for register TX_RTS_CFG */ 573261868Skevlo#define RT2860_RTS_FBK_EN (1 << 24) 574261868Skevlo#define RT2860_RTS_THRES_SHIFT 8 575261868Skevlo#define RT2860_RTS_RTY_LIMIT_SHIFT 0 576203134Sthompsa 577203134Sthompsa/* possible flags for register TX_TIMEOUT_CFG */ 578261868Skevlo#define RT2860_TXOP_TIMEOUT_SHIFT 16 579261868Skevlo#define RT2860_RX_ACK_TIMEOUT_SHIFT 8 580261868Skevlo#define RT2860_MPDU_LIFE_TIME_SHIFT 4 581203134Sthompsa 582203134Sthompsa/* possible flags for register TX_RTY_CFG */ 583261868Skevlo#define RT2860_TX_AUTOFB_EN (1 << 30) 584261868Skevlo#define RT2860_AGG_RTY_MODE_TIMER (1 << 29) 585261868Skevlo#define RT2860_NAG_RTY_MODE_TIMER (1 << 28) 586261868Skevlo#define RT2860_LONG_RTY_THRES_SHIFT 16 587261868Skevlo#define RT2860_LONG_RTY_LIMIT_SHIFT 8 588261868Skevlo#define RT2860_SHORT_RTY_LIMIT_SHIFT 0 589203134Sthompsa 590203134Sthompsa/* possible flags for register TX_LINK_CFG */ 591261868Skevlo#define RT2860_REMOTE_MFS_SHIFT 24 592261868Skevlo#define RT2860_REMOTE_MFB_SHIFT 16 593261868Skevlo#define RT2860_TX_CFACK_EN (1 << 12) 594261868Skevlo#define RT2860_TX_RDG_EN (1 << 11) 595261868Skevlo#define RT2860_TX_MRQ_EN (1 << 10) 596261868Skevlo#define RT2860_REMOTE_UMFS_EN (1 << 9) 597261868Skevlo#define RT2860_TX_MFB_EN (1 << 8) 598261868Skevlo#define RT2860_REMOTE_MFB_LT_SHIFT 0 599203134Sthompsa 600203134Sthompsa/* possible flags for registers *_PROT_CFG */ 601261868Skevlo#define RT2860_RTSTH_EN (1 << 26) 602261868Skevlo#define RT2860_TXOP_ALLOW_GF40 (1 << 25) 603261868Skevlo#define RT2860_TXOP_ALLOW_GF20 (1 << 24) 604261868Skevlo#define RT2860_TXOP_ALLOW_MM40 (1 << 23) 605261868Skevlo#define RT2860_TXOP_ALLOW_MM20 (1 << 22) 606261868Skevlo#define RT2860_TXOP_ALLOW_OFDM (1 << 21) 607261868Skevlo#define RT2860_TXOP_ALLOW_CCK (1 << 20) 608261868Skevlo#define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 609261868Skevlo#define RT2860_PROT_NAV_SHORT (1 << 18) 610261868Skevlo#define RT2860_PROT_NAV_LONG (2 << 18) 611261868Skevlo#define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 612261868Skevlo#define RT2860_PROT_CTRL_CTS (2 << 16) 613203134Sthompsa 614203134Sthompsa/* possible flags for registers EXP_{CTS,ACK}_TIME */ 615261868Skevlo#define RT2860_EXP_OFDM_TIME_SHIFT 16 616261868Skevlo#define RT2860_EXP_CCK_TIME_SHIFT 0 617203134Sthompsa 618203134Sthompsa/* possible flags for register RX_FILTR_CFG */ 619261868Skevlo#define RT2860_DROP_CTRL_RSV (1 << 16) 620261868Skevlo#define RT2860_DROP_BAR (1 << 15) 621261868Skevlo#define RT2860_DROP_BA (1 << 14) 622261868Skevlo#define RT2860_DROP_PSPOLL (1 << 13) 623261868Skevlo#define RT2860_DROP_RTS (1 << 12) 624261868Skevlo#define RT2860_DROP_CTS (1 << 11) 625261868Skevlo#define RT2860_DROP_ACK (1 << 10) 626261868Skevlo#define RT2860_DROP_CFEND (1 << 9) 627261868Skevlo#define RT2860_DROP_CFACK (1 << 8) 628261868Skevlo#define RT2860_DROP_DUPL (1 << 7) 629261868Skevlo#define RT2860_DROP_BC (1 << 6) 630261868Skevlo#define RT2860_DROP_MC (1 << 5) 631261868Skevlo#define RT2860_DROP_VER_ERR (1 << 4) 632261868Skevlo#define RT2860_DROP_NOT_MYBSS (1 << 3) 633261868Skevlo#define RT2860_DROP_UC_NOME (1 << 2) 634261868Skevlo#define RT2860_DROP_PHY_ERR (1 << 1) 635261868Skevlo#define RT2860_DROP_CRC_ERR (1 << 0) 636203134Sthompsa 637203134Sthompsa/* possible flags for register AUTO_RSP_CFG */ 638261868Skevlo#define RT2860_CTRL_PWR_BIT (1 << 7) 639261868Skevlo#define RT2860_BAC_ACK_POLICY (1 << 6) 640261868Skevlo#define RT2860_CCK_SHORT_EN (1 << 4) 641261868Skevlo#define RT2860_CTS_40M_REF_EN (1 << 3) 642261868Skevlo#define RT2860_CTS_40M_MODE_EN (1 << 2) 643261868Skevlo#define RT2860_BAC_ACKPOLICY_EN (1 << 1) 644261868Skevlo#define RT2860_AUTO_RSP_EN (1 << 0) 645203134Sthompsa 646203134Sthompsa/* possible flags for register SIFS_COST_CFG */ 647261868Skevlo#define RT2860_OFDM_SIFS_COST_SHIFT 8 648261868Skevlo#define RT2860_CCK_SIFS_COST_SHIFT 0 649203134Sthompsa 650203134Sthompsa/* possible flags for register TXOP_HLDR_ET */ 651261868Skevlo#define RT2860_TXOP_ETM1_EN (1 << 25) 652261868Skevlo#define RT2860_TXOP_ETM0_EN (1 << 24) 653261868Skevlo#define RT2860_TXOP_ETM_THRES_SHIFT 16 654261868Skevlo#define RT2860_TXOP_ETO_EN (1 << 8) 655261868Skevlo#define RT2860_TXOP_ETO_THRES_SHIFT 1 656261868Skevlo#define RT2860_PER_RX_RST_EN (1 << 0) 657203134Sthompsa 658203134Sthompsa/* possible flags for register TX_STAT_FIFO */ 659261868Skevlo#define RT2860_TXQ_MCS_SHIFT 16 660261868Skevlo#define RT2860_TXQ_WCID_SHIFT 8 661261868Skevlo#define RT2860_TXQ_ACKREQ (1 << 7) 662261868Skevlo#define RT2860_TXQ_AGG (1 << 6) 663261868Skevlo#define RT2860_TXQ_OK (1 << 5) 664261868Skevlo#define RT2860_TXQ_PID_SHIFT 1 665261868Skevlo#define RT2860_TXQ_VLD (1 << 0) 666203134Sthompsa 667203134Sthompsa/* possible flags for register WCID_ATTR */ 668261868Skevlo#define RT2860_MODE_NOSEC 0 669261868Skevlo#define RT2860_MODE_WEP40 1 670261868Skevlo#define RT2860_MODE_WEP104 2 671261868Skevlo#define RT2860_MODE_TKIP 3 672261868Skevlo#define RT2860_MODE_AES_CCMP 4 673261868Skevlo#define RT2860_MODE_CKIP40 5 674261868Skevlo#define RT2860_MODE_CKIP104 6 675261868Skevlo#define RT2860_MODE_CKIP128 7 676261868Skevlo#define RT2860_RX_PKEY_EN (1 << 0) 677203134Sthompsa 678203134Sthompsa/* possible flags for register H2M_MAILBOX */ 679261868Skevlo#define RT2860_H2M_BUSY (1 << 24) 680261868Skevlo#define RT2860_TOKEN_NO_INTR 0xff 681203134Sthompsa 682203134Sthompsa/* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 683261868Skevlo#define RT2860_LED_RADIO (1 << 13) 684261868Skevlo#define RT2860_LED_LINK_2GHZ (1 << 14) 685261868Skevlo#define RT2860_LED_LINK_5GHZ (1 << 15) 686203134Sthompsa 687203134Sthompsa/* possible flags for RT3020 RF register 1 */ 688261868Skevlo#define RT3070_RF_BLOCK (1 << 0) 689261868Skevlo#define RT3070_PLL_PD (1 << 1) 690261868Skevlo#define RT3070_RX0_PD (1 << 2) 691261868Skevlo#define RT3070_TX0_PD (1 << 3) 692261868Skevlo#define RT3070_RX1_PD (1 << 4) 693261868Skevlo#define RT3070_TX1_PD (1 << 5) 694261868Skevlo#define RT3070_RX2_PD (1 << 6) 695261868Skevlo#define RT3070_TX2_PD (1 << 7) 696203134Sthompsa 697203134Sthompsa/* possible flags for RT3020 RF register 15 */ 698261868Skevlo#define RT3070_TX_LO2 (1 << 3) 699203134Sthompsa 700203134Sthompsa/* possible flags for RT3020 RF register 17 */ 701261868Skevlo#define RT3070_TX_LO1 (1 << 3) 702203134Sthompsa 703203134Sthompsa/* possible flags for RT3020 RF register 20 */ 704261868Skevlo#define RT3070_RX_LO1 (1 << 3) 705203134Sthompsa 706203134Sthompsa/* possible flags for RT3020 RF register 21 */ 707261868Skevlo#define RT3070_RX_LO2 (1 << 3) 708203134Sthompsa 709261868Skevlo/* possible flags for RT3053 RF register 18 */ 710261868Skevlo#define RT3593_AUTOTUNE_BYPASS (1 << 6) 711261868Skevlo 712261868Skevlo/* possible flags for RT3053 RF register 50 */ 713261868Skevlo#define RT3593_TX_LO2 (1 << 4) 714261868Skevlo 715261868Skevlo/* possible flags for RT3053 RF register 51 */ 716261868Skevlo#define RT3593_TX_LO1 (1 << 4) 717261868Skevlo 718259453Shselasky/* Possible flags for RT5390 RF register 2. */ 719259453Shselasky#define RT5390_RESCAL (1 << 7) 720203134Sthompsa 721259453Shselasky/* Possible flags for RT5390 RF register 3. */ 722259453Shselasky#define RT5390_VCOCAL (1 << 7) 723259453Shselasky 724259453Shselasky/* Possible flags for RT5390 RF register 38. */ 725259453Shselasky#define RT5390_RX_LO1 (1 << 5) 726259453Shselasky 727259453Shselasky/* Possible flags for RT5390 RF register 39. */ 728259453Shselasky#define RT5390_RX_LO2 (1 << 7) 729259453Shselasky 730259453Shselasky/* Possible flags for RT5390 BBP register 4. */ 731259453Shselasky#define RT5390_MAC_IF_CTRL (1 << 6) 732259453Shselasky 733259453Shselasky/* Possible flags for RT5390 BBP register 105. */ 734259453Shselasky#define RT5390_MLD (1 << 2) 735259453Shselasky#define RT5390_EN_SIG_MODULATION (1 << 3) 736259453Shselasky 737203134Sthompsa/* RT2860 TX descriptor */ 738203134Sthompsastruct rt2860_txd { 739203134Sthompsa uint32_t sdp0; /* Segment Data Pointer 0 */ 740203134Sthompsa uint16_t sdl1; /* Segment Data Length 1 */ 741261868Skevlo#define RT2860_TX_BURST (1 << 15) 742261868Skevlo#define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 743203134Sthompsa 744203134Sthompsa uint16_t sdl0; /* Segment Data Length 0 */ 745261868Skevlo#define RT2860_TX_DDONE (1 << 15) 746261868Skevlo#define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 747203134Sthompsa 748203134Sthompsa uint32_t sdp1; /* Segment Data Pointer 1 */ 749203134Sthompsa uint8_t reserved[3]; 750203134Sthompsa uint8_t flags; 751261868Skevlo#define RT2860_TX_QSEL_SHIFT 1 752261868Skevlo#define RT2860_TX_QSEL_MGMT (0 << 1) 753261868Skevlo#define RT2860_TX_QSEL_HCCA (1 << 1) 754261868Skevlo#define RT2860_TX_QSEL_EDCA (2 << 1) 755261868Skevlo#define RT2860_TX_WIV (1 << 0) 756203134Sthompsa} __packed; 757203134Sthompsa 758203134Sthompsa/* RT2870 TX descriptor */ 759203134Sthompsastruct rt2870_txd { 760203134Sthompsa uint16_t len; 761203134Sthompsa uint8_t pad; 762203134Sthompsa uint8_t flags; 763203134Sthompsa} __packed; 764203134Sthompsa 765203134Sthompsa/* TX Wireless Information */ 766203134Sthompsastruct rt2860_txwi { 767203134Sthompsa uint8_t flags; 768261868Skevlo#define RT2860_TX_MPDU_DSITY_SHIFT 5 769261868Skevlo#define RT2860_TX_AMPDU (1 << 4) 770261868Skevlo#define RT2860_TX_TS (1 << 3) 771261868Skevlo#define RT2860_TX_CFACK (1 << 2) 772261868Skevlo#define RT2860_TX_MMPS (1 << 1) 773261868Skevlo#define RT2860_TX_FRAG (1 << 0) 774203134Sthompsa 775203134Sthompsa uint8_t txop; 776261868Skevlo#define RT2860_TX_TXOP_HT 0 777261868Skevlo#define RT2860_TX_TXOP_PIFS 1 778261868Skevlo#define RT2860_TX_TXOP_SIFS 2 779261868Skevlo#define RT2860_TX_TXOP_BACKOFF 3 780203134Sthompsa 781203134Sthompsa uint16_t phy; 782261868Skevlo#define RT2860_PHY_MODE 0xc000 783261868Skevlo#define RT2860_PHY_CCK (0 << 14) 784261868Skevlo#define RT2860_PHY_OFDM (1 << 14) 785261868Skevlo#define RT2860_PHY_HT (2 << 14) 786261868Skevlo#define RT2860_PHY_HT_GF (3 << 14) 787261868Skevlo#define RT2860_PHY_SGI (1 << 8) 788261868Skevlo#define RT2860_PHY_BW40 (1 << 7) 789261868Skevlo#define RT2860_PHY_MCS 0x7f 790261868Skevlo#define RT2860_PHY_SHPRE (1 << 3) 791203134Sthompsa 792203134Sthompsa uint8_t xflags; 793261868Skevlo#define RT2860_TX_BAWINSIZE_SHIFT 2 794261868Skevlo#define RT2860_TX_NSEQ (1 << 1) 795261868Skevlo#define RT2860_TX_ACK (1 << 0) 796203134Sthompsa 797203134Sthompsa uint8_t wcid; /* Wireless Client ID */ 798203134Sthompsa uint16_t len; 799261868Skevlo#define RT2860_TX_PID_SHIFT 12 800203134Sthompsa 801203134Sthompsa uint32_t iv; 802203134Sthompsa uint32_t eiv; 803203134Sthompsa} __packed; 804203134Sthompsa 805203134Sthompsa/* RT2860 RX descriptor */ 806203134Sthompsastruct rt2860_rxd { 807203134Sthompsa uint32_t sdp0; 808203134Sthompsa uint16_t sdl1; /* unused */ 809203134Sthompsa uint16_t sdl0; 810261868Skevlo#define RT2860_RX_DDONE (1 << 15) 811261868Skevlo#define RT2860_RX_LS0 (1 << 14) 812203134Sthompsa 813203134Sthompsa uint32_t sdp1; /* unused */ 814203134Sthompsa uint32_t flags; 815261868Skevlo#define RT2860_RX_DEC (1 << 16) 816261868Skevlo#define RT2860_RX_AMPDU (1 << 15) 817261868Skevlo#define RT2860_RX_L2PAD (1 << 14) 818261868Skevlo#define RT2860_RX_RSSI (1 << 13) 819261868Skevlo#define RT2860_RX_HTC (1 << 12) 820261868Skevlo#define RT2860_RX_AMSDU (1 << 11) 821261868Skevlo#define RT2860_RX_MICERR (1 << 10) 822261868Skevlo#define RT2860_RX_ICVERR (1 << 9) 823261868Skevlo#define RT2860_RX_CRCERR (1 << 8) 824261868Skevlo#define RT2860_RX_MYBSS (1 << 7) 825261868Skevlo#define RT2860_RX_BC (1 << 6) 826261868Skevlo#define RT2860_RX_MC (1 << 5) 827261868Skevlo#define RT2860_RX_UC2ME (1 << 4) 828261868Skevlo#define RT2860_RX_FRAG (1 << 3) 829261868Skevlo#define RT2860_RX_NULL (1 << 2) 830261868Skevlo#define RT2860_RX_DATA (1 << 1) 831261868Skevlo#define RT2860_RX_BA (1 << 0) 832203134Sthompsa} __packed; 833203134Sthompsa 834203134Sthompsa/* RT2870 RX descriptor */ 835203134Sthompsastruct rt2870_rxd { 836203134Sthompsa /* single 32-bit field */ 837203134Sthompsa uint32_t flags; 838203134Sthompsa} __packed; 839203134Sthompsa 840203134Sthompsa/* RX Wireless Information */ 841203134Sthompsastruct rt2860_rxwi { 842203134Sthompsa uint8_t wcid; 843203134Sthompsa uint8_t keyidx; 844261868Skevlo#define RT2860_RX_UDF_SHIFT 5 845261868Skevlo#define RT2860_RX_BSS_IDX_SHIFT 2 846203134Sthompsa 847203134Sthompsa uint16_t len; 848261868Skevlo#define RT2860_RX_TID_SHIFT 12 849203134Sthompsa 850203134Sthompsa uint16_t seq; 851203134Sthompsa uint16_t phy; 852203134Sthompsa uint8_t rssi[3]; 853203134Sthompsa uint8_t reserved1; 854203134Sthompsa uint8_t snr[2]; 855203134Sthompsa uint16_t reserved2; 856203134Sthompsa} __packed; 857203134Sthompsa 858261868Skevlo#define RT2860_RF_2820 0x0001 /* 2T3R */ 859261868Skevlo#define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ 860261868Skevlo#define RT2860_RF_2720 0x0003 /* 1T2R */ 861261868Skevlo#define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ 862261868Skevlo#define RT3070_RF_3020 0x0005 /* 1T1R */ 863261868Skevlo#define RT3070_RF_2020 0x0006 /* b/g */ 864261868Skevlo#define RT3070_RF_3021 0x0007 /* 1T2R */ 865261868Skevlo#define RT3070_RF_3022 0x0008 /* 2T2R */ 866261868Skevlo#define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ 867261868Skevlo#define RT3593_RF_3053 0x000d /* dual-band 3T3R */ 868261868Skevlo#define RT5592_RF_5592 0x000f /* dual-band 2T2R */ 869261868Skevlo#define RT5390_RF_5370 0x5370 /* 1T1R */ 870261868Skevlo#define RT5390_RF_5372 0x5372 /* 2T2R */ 871203134Sthompsa 872203134Sthompsa/* USB commands for RT2870 only */ 873261868Skevlo#define RT2870_RESET 1 874261868Skevlo#define RT2870_WRITE_2 2 875261868Skevlo#define RT2870_WRITE_REGION_1 6 876261868Skevlo#define RT2870_READ_REGION_1 7 877261868Skevlo#define RT2870_EEPROM_READ 9 878203134Sthompsa 879261868Skevlo#define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 880203134Sthompsa 881261868Skevlo#define RT2860_EEPROM_VERSION 0x01 882261868Skevlo#define RT2860_EEPROM_MAC01 0x02 883261868Skevlo#define RT2860_EEPROM_MAC23 0x03 884261868Skevlo#define RT2860_EEPROM_MAC45 0x04 885261868Skevlo#define RT2860_EEPROM_PCIE_PSLEVEL 0x11 886261868Skevlo#define RT2860_EEPROM_REV 0x12 887261868Skevlo#define RT2860_EEPROM_ANTENNA 0x1a 888261868Skevlo#define RT2860_EEPROM_CONFIG 0x1b 889261868Skevlo#define RT2860_EEPROM_COUNTRY 0x1c 890261868Skevlo#define RT2860_EEPROM_FREQ_LEDS 0x1d 891261868Skevlo#define RT2860_EEPROM_LED1 0x1e 892261868Skevlo#define RT2860_EEPROM_LED2 0x1f 893261868Skevlo#define RT2860_EEPROM_LED3 0x20 894261868Skevlo#define RT2860_EEPROM_LNA 0x22 895261868Skevlo#define RT2860_EEPROM_RSSI1_2GHZ 0x23 896261868Skevlo#define RT2860_EEPROM_RSSI2_2GHZ 0x24 897261868Skevlo#define RT2860_EEPROM_RSSI1_5GHZ 0x25 898261868Skevlo#define RT2860_EEPROM_RSSI2_5GHZ 0x26 899261868Skevlo#define RT2860_EEPROM_DELTAPWR 0x28 900261868Skevlo#define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 901261868Skevlo#define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 902261868Skevlo#define RT2860_EEPROM_TSSI1_2GHZ 0x37 903261868Skevlo#define RT2860_EEPROM_TSSI2_2GHZ 0x38 904261868Skevlo#define RT2860_EEPROM_TSSI3_2GHZ 0x39 905261868Skevlo#define RT2860_EEPROM_TSSI4_2GHZ 0x3a 906261868Skevlo#define RT2860_EEPROM_TSSI5_2GHZ 0x3b 907261868Skevlo#define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 908261868Skevlo#define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 909261868Skevlo#define RT2860_EEPROM_TSSI1_5GHZ 0x6a 910261868Skevlo#define RT2860_EEPROM_TSSI2_5GHZ 0x6b 911261868Skevlo#define RT2860_EEPROM_TSSI3_5GHZ 0x6c 912261868Skevlo#define RT2860_EEPROM_TSSI4_5GHZ 0x6d 913261868Skevlo#define RT2860_EEPROM_TSSI5_5GHZ 0x6e 914261868Skevlo#define RT2860_EEPROM_RPWR 0x6f 915261868Skevlo#define RT2860_EEPROM_BBP_BASE 0x78 916261868Skevlo#define RT3071_EEPROM_RF_BASE 0x82 917203134Sthompsa 918261868Skevlo/* EEPROM registers for RT3593. */ 919261868Skevlo#define RT3593_EEPROM_FREQ_LEDS 0x21 920261868Skevlo#define RT3593_EEPROM_FREQ 0x22 921261868Skevlo#define RT3593_EEPROM_LED1 0x22 922261868Skevlo#define RT3593_EEPROM_LED2 0x23 923261868Skevlo#define RT3593_EEPROM_LED3 0x24 924261868Skevlo#define RT3593_EEPROM_LNA 0x26 925261868Skevlo#define RT3593_EEPROM_LNA_5GHZ 0x27 926261868Skevlo#define RT3593_EEPROM_RSSI1_2GHZ 0x28 927261868Skevlo#define RT3593_EEPROM_RSSI2_2GHZ 0x29 928261868Skevlo#define RT3593_EEPROM_RSSI1_5GHZ 0x2a 929261868Skevlo#define RT3593_EEPROM_RSSI2_5GHZ 0x2b 930261868Skevlo#define RT3593_EEPROM_PWR2GHZ_BASE1 0x30 931261868Skevlo#define RT3593_EEPROM_PWR2GHZ_BASE2 0x37 932261868Skevlo#define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e 933261868Skevlo#define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b 934261868Skevlo#define RT3593_EEPROM_PWR5GHZ_BASE2 0x65 935261868Skevlo#define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f 936203134Sthompsa 937203134Sthompsa/* 938261868Skevlo * EEPROM IQ calibration. 939261868Skevlo */ 940261868Skevlo#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130 941261868Skevlo#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131 942261868Skevlo#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133 943261868Skevlo#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134 944261868Skevlo#define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c 945261868Skevlo#define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d 946261868Skevlo#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144 947261868Skevlo#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145 948261868Skevlo#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146 949261868Skevlo#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147 950261868Skevlo#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148 951261868Skevlo#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149 952261868Skevlo#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a 953261868Skevlo#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b 954261868Skevlo#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c 955261868Skevlo#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d 956261868Skevlo#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e 957261868Skevlo#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f 958261868Skevlo 959261868Skevlo#define RT2860_RIDX_CCK1 0 960261868Skevlo#define RT2860_RIDX_CCK11 3 961261868Skevlo#define RT2860_RIDX_OFDM6 4 962261868Skevlo#define RT2860_RIDX_MAX 12 963261868Skevlo 964261868Skevlo/* 965203134Sthompsa * Control and status registers access macros. 966203134Sthompsa */ 967203134Sthompsa#define RAL_READ(sc, reg) \ 968203134Sthompsa bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 969203134Sthompsa 970203134Sthompsa#define RAL_WRITE(sc, reg, val) \ 971203134Sthompsa bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 972203134Sthompsa 973203134Sthompsa#define RAL_BARRIER_WRITE(sc) \ 974203134Sthompsa bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 975203134Sthompsa BUS_SPACE_BARRIER_WRITE) 976203134Sthompsa 977203134Sthompsa#define RAL_BARRIER_READ_WRITE(sc) \ 978203134Sthompsa bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 979203134Sthompsa BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 980203134Sthompsa 981203134Sthompsa#define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 982203134Sthompsa bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 983203134Sthompsa (datap), (count)) 984203134Sthompsa 985203134Sthompsa#define RAL_SET_REGION_4(sc, offset, val, count) \ 986203134Sthompsa bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 987203134Sthompsa (val), (count)) 988203134Sthompsa 989203134Sthompsa/* 990203134Sthompsa * EEPROM access macro. 991203134Sthompsa */ 992203134Sthompsa#define RT2860_EEPROM_CTL(sc, val) do { \ 993203134Sthompsa RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 994203134Sthompsa RAL_BARRIER_READ_WRITE((sc)); \ 995203134Sthompsa DELAY(RT2860_EEPROM_DELAY); \ 996203134Sthompsa} while (/* CONSTCOND */0) 997203134Sthompsa 998203134Sthompsa/* 999203134Sthompsa * Default values for MAC registers; values taken from the reference driver. 1000203134Sthompsa */ 1001261868Skevlo#define RT2870_DEF_MAC \ 1002203134Sthompsa { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1003259461Shselasky { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \ 1004203134Sthompsa { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1005203134Sthompsa { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1006203134Sthompsa { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1007203134Sthompsa { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1008203134Sthompsa { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1009203134Sthompsa { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1010203134Sthompsa { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1011203134Sthompsa { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1012259461Shselasky { RT2860_MAX_LEN_CFG, 0x00001f00 }, \ 1013203134Sthompsa { RT2860_LED_CFG, 0x7f031e46 }, \ 1014203134Sthompsa { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1015203134Sthompsa { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1016203134Sthompsa { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1017203134Sthompsa { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1018203134Sthompsa { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1019203134Sthompsa { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1020203134Sthompsa { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1021203134Sthompsa { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1022203134Sthompsa { RT2860_PBF_CFG, 0x00f40006 }, \ 1023203134Sthompsa { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 1024203134Sthompsa { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1025203134Sthompsa { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1026203134Sthompsa { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1027203134Sthompsa { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 1028203134Sthompsa { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1029203134Sthompsa { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1030203134Sthompsa { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1031203134Sthompsa { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1032203134Sthompsa { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1033203134Sthompsa { RT2860_PWR_PIN_CFG, 0x00000003 } 1034203134Sthompsa 1035203134Sthompsa/* 1036203134Sthompsa * Default values for BBP registers; values taken from the reference driver. 1037203134Sthompsa */ 1038261868Skevlo#define RT2860_DEF_BBP \ 1039203134Sthompsa { 65, 0x2c }, \ 1040203134Sthompsa { 66, 0x38 }, \ 1041259461Shselasky { 68, 0x0b }, \ 1042203134Sthompsa { 69, 0x12 }, \ 1043203134Sthompsa { 70, 0x0a }, \ 1044203134Sthompsa { 73, 0x10 }, \ 1045203134Sthompsa { 81, 0x37 }, \ 1046203134Sthompsa { 82, 0x62 }, \ 1047203134Sthompsa { 83, 0x6a }, \ 1048203134Sthompsa { 84, 0x99 }, \ 1049203134Sthompsa { 86, 0x00 }, \ 1050203134Sthompsa { 91, 0x04 }, \ 1051203134Sthompsa { 92, 0x00 }, \ 1052203134Sthompsa { 103, 0x00 }, \ 1053205042Sthompsa { 105, 0x05 }, \ 1054205042Sthompsa { 106, 0x35 } 1055203134Sthompsa 1056261868Skevlo#define RT5390_DEF_BBP \ 1057259453Shselasky { 31, 0x08 }, \ 1058259453Shselasky { 65, 0x2c }, \ 1059259453Shselasky { 66, 0x38 }, \ 1060259453Shselasky { 68, 0x0b }, \ 1061259453Shselasky { 69, 0x0d }, \ 1062259453Shselasky { 70, 0x06 }, \ 1063259453Shselasky { 73, 0x13 }, \ 1064259453Shselasky { 75, 0x46 }, \ 1065259453Shselasky { 76, 0x28 }, \ 1066259453Shselasky { 77, 0x59 }, \ 1067259453Shselasky { 81, 0x37 }, \ 1068259453Shselasky { 82, 0x62 }, \ 1069259453Shselasky { 83, 0x7a }, \ 1070259453Shselasky { 84, 0x9a }, \ 1071259453Shselasky { 86, 0x38 }, \ 1072259453Shselasky { 91, 0x04 }, \ 1073259453Shselasky { 92, 0x02 }, \ 1074259453Shselasky { 103, 0xc0 }, \ 1075259453Shselasky { 104, 0x92 }, \ 1076259453Shselasky { 105, 0x3c }, \ 1077259453Shselasky { 106, 0x03 }, \ 1078259453Shselasky { 128, 0x12 } 1079259453Shselasky 1080261868Skevlo#define RT5592_DEF_BBP \ 1081259453Shselasky { 20, 0x06 }, \ 1082259453Shselasky { 31, 0x08 }, \ 1083259453Shselasky { 65, 0x2c }, \ 1084259453Shselasky { 66, 0x38 }, \ 1085259453Shselasky { 68, 0xdd }, \ 1086259453Shselasky { 69, 0x1a }, \ 1087259453Shselasky { 70, 0x05 }, \ 1088259453Shselasky { 73, 0x13 }, \ 1089259453Shselasky { 74, 0x0f }, \ 1090259453Shselasky { 75, 0x4f }, \ 1091259453Shselasky { 76, 0x28 }, \ 1092259453Shselasky { 77, 0x59 }, \ 1093259453Shselasky { 81, 0x37 }, \ 1094259453Shselasky { 82, 0x62 }, \ 1095259453Shselasky { 83, 0x6a }, \ 1096259453Shselasky { 84, 0x9a }, \ 1097259453Shselasky { 86, 0x38 }, \ 1098259453Shselasky { 88, 0x90 }, \ 1099259453Shselasky { 91, 0x04 }, \ 1100259453Shselasky { 92, 0x02 }, \ 1101259453Shselasky { 95, 0x9a }, \ 1102259453Shselasky { 98, 0x12 }, \ 1103259453Shselasky { 103, 0xc0 }, \ 1104259453Shselasky { 104, 0x92 }, \ 1105259453Shselasky { 105, 0x3c }, \ 1106259453Shselasky { 106, 0x35 }, \ 1107259453Shselasky { 128, 0x12 }, \ 1108259453Shselasky { 134, 0xd0 }, \ 1109259453Shselasky { 135, 0xf6 }, \ 1110259453Shselasky { 137, 0x0f } 1111259453Shselasky 1112203134Sthompsa/* 1113203134Sthompsa * Default settings for RF registers; values derived from the reference driver. 1114203134Sthompsa */ 1115261868Skevlo#define RT2860_RF2850 \ 1116259453Shselasky { 1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b }, \ 1117259453Shselasky { 2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f }, \ 1118259453Shselasky { 3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b }, \ 1119259453Shselasky { 4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f }, \ 1120259453Shselasky { 5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b }, \ 1121259453Shselasky { 6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f }, \ 1122259453Shselasky { 7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b }, \ 1123259453Shselasky { 8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f }, \ 1124259453Shselasky { 9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b }, \ 1125259453Shselasky { 10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f }, \ 1126259453Shselasky { 11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b }, \ 1127259453Shselasky { 12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f }, \ 1128259453Shselasky { 13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b }, \ 1129259453Shselasky { 14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193 }, \ 1130259453Shselasky { 36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3 }, \ 1131259453Shselasky { 38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193 }, \ 1132259453Shselasky { 40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183 }, \ 1133259453Shselasky { 44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3 }, \ 1134259453Shselasky { 46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b }, \ 1135259453Shselasky { 48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b }, \ 1136259453Shselasky { 52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193 }, \ 1137259453Shselasky { 54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3 }, \ 1138259453Shselasky { 56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b }, \ 1139259453Shselasky { 60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183 }, \ 1140259453Shselasky { 62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193 }, \ 1141259453Shselasky { 64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3 }, \ 1142259453Shselasky { 100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783 }, \ 1143259453Shselasky { 102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793 }, \ 1144259453Shselasky { 104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3 }, \ 1145259453Shselasky { 108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193 }, \ 1146259453Shselasky { 110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183 }, \ 1147259453Shselasky { 112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b }, \ 1148259453Shselasky { 116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3 }, \ 1149259453Shselasky { 118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193 }, \ 1150259453Shselasky { 120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183 }, \ 1151259453Shselasky { 124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193 }, \ 1152259453Shselasky { 126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b }, \ 1153259453Shselasky { 128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3 }, \ 1154259453Shselasky { 132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b }, \ 1155259453Shselasky { 134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193 }, \ 1156259453Shselasky { 136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b }, \ 1157259453Shselasky { 140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183 }, \ 1158259453Shselasky { 149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7 }, \ 1159259453Shselasky { 151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187 }, \ 1160259453Shselasky { 153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f }, \ 1161259453Shselasky { 157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f }, \ 1162259453Shselasky { 159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7 }, \ 1163259453Shselasky { 161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187 }, \ 1164259453Shselasky { 165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197 }, \ 1165259453Shselasky { 167, 0x98402ec4, 0x984c03d2, 0x98179855, 0x9815531f }, \ 1166259453Shselasky { 169, 0x98402ec4, 0x984c03d2, 0x98179855, 0x98155327 }, \ 1167259453Shselasky { 171, 0x98402ec4, 0x984c03d6, 0x98179855, 0x98155307 }, \ 1168259453Shselasky { 173, 0x98402ec4, 0x984c03d6, 0x98179855, 0x9815530f }, \ 1169259453Shselasky { 184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b }, \ 1170259453Shselasky { 188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13 }, \ 1171259453Shselasky { 192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b }, \ 1172259453Shselasky { 196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23 }, \ 1173259453Shselasky { 208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13 }, \ 1174259453Shselasky { 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b }, \ 1175259453Shselasky { 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 } 1176203134Sthompsa 1177261868Skevlo#define RT3070_RF3052 \ 1178205042Sthompsa { 0xf1, 2, 2 }, \ 1179205042Sthompsa { 0xf1, 2, 7 }, \ 1180205042Sthompsa { 0xf2, 2, 2 }, \ 1181205042Sthompsa { 0xf2, 2, 7 }, \ 1182205042Sthompsa { 0xf3, 2, 2 }, \ 1183205042Sthompsa { 0xf3, 2, 7 }, \ 1184205042Sthompsa { 0xf4, 2, 2 }, \ 1185205042Sthompsa { 0xf4, 2, 7 }, \ 1186205042Sthompsa { 0xf5, 2, 2 }, \ 1187205042Sthompsa { 0xf5, 2, 7 }, \ 1188205042Sthompsa { 0xf6, 2, 2 }, \ 1189205042Sthompsa { 0xf6, 2, 7 }, \ 1190205042Sthompsa { 0xf7, 2, 2 }, \ 1191205042Sthompsa { 0xf8, 2, 4 }, \ 1192205042Sthompsa { 0x56, 0, 4 }, \ 1193205042Sthompsa { 0x56, 0, 6 }, \ 1194205042Sthompsa { 0x56, 0, 8 }, \ 1195205042Sthompsa { 0x57, 0, 0 }, \ 1196205042Sthompsa { 0x57, 0, 2 }, \ 1197205042Sthompsa { 0x57, 0, 4 }, \ 1198205042Sthompsa { 0x57, 0, 8 }, \ 1199205042Sthompsa { 0x57, 0, 10 }, \ 1200205042Sthompsa { 0x58, 0, 0 }, \ 1201205042Sthompsa { 0x58, 0, 4 }, \ 1202205042Sthompsa { 0x58, 0, 6 }, \ 1203205042Sthompsa { 0x58, 0, 8 }, \ 1204205042Sthompsa { 0x5b, 0, 8 }, \ 1205205042Sthompsa { 0x5b, 0, 10 }, \ 1206205042Sthompsa { 0x5c, 0, 0 }, \ 1207205042Sthompsa { 0x5c, 0, 4 }, \ 1208205042Sthompsa { 0x5c, 0, 6 }, \ 1209205042Sthompsa { 0x5c, 0, 8 }, \ 1210205042Sthompsa { 0x5d, 0, 0 }, \ 1211205042Sthompsa { 0x5d, 0, 2 }, \ 1212205042Sthompsa { 0x5d, 0, 4 }, \ 1213205042Sthompsa { 0x5d, 0, 8 }, \ 1214205042Sthompsa { 0x5d, 0, 10 }, \ 1215205042Sthompsa { 0x5e, 0, 0 }, \ 1216205042Sthompsa { 0x5e, 0, 4 }, \ 1217205042Sthompsa { 0x5e, 0, 6 }, \ 1218205042Sthompsa { 0x5e, 0, 8 }, \ 1219205042Sthompsa { 0x5f, 0, 0 }, \ 1220205042Sthompsa { 0x5f, 0, 9 }, \ 1221205042Sthompsa { 0x5f, 0, 11 }, \ 1222205042Sthompsa { 0x60, 0, 1 }, \ 1223205042Sthompsa { 0x60, 0, 5 }, \ 1224205042Sthompsa { 0x60, 0, 7 }, \ 1225205042Sthompsa { 0x60, 0, 9 }, \ 1226205042Sthompsa { 0x61, 0, 1 }, \ 1227205042Sthompsa { 0x61, 0, 3 }, \ 1228205042Sthompsa { 0x61, 0, 5 }, \ 1229205042Sthompsa { 0x61, 0, 7 }, \ 1230205042Sthompsa { 0x61, 0, 9 } 1231205042Sthompsa 1232261868Skevlo#define RT5592_RF5592_20MHZ \ 1233259453Shselasky { 0x1e2, 4, 10, 3 }, \ 1234259453Shselasky { 0x1e3, 4, 10, 3 }, \ 1235259453Shselasky { 0x1e4, 4, 10, 3 }, \ 1236259453Shselasky { 0x1e5, 4, 10, 3 }, \ 1237259453Shselasky { 0x1e6, 4, 10, 3 }, \ 1238259453Shselasky { 0x1e7, 4, 10, 3 }, \ 1239259453Shselasky { 0x1e8, 4, 10, 3 }, \ 1240259453Shselasky { 0x1e9, 4, 10, 3 }, \ 1241259453Shselasky { 0x1ea, 4, 10, 3 }, \ 1242259453Shselasky { 0x1eb, 4, 10, 3 }, \ 1243259453Shselasky { 0x1ec, 4, 10, 3 }, \ 1244259453Shselasky { 0x1ed, 4, 10, 3 }, \ 1245259453Shselasky { 0x1ee, 4, 10, 3 }, \ 1246259453Shselasky { 0x1f0, 8, 10, 3 }, \ 1247259453Shselasky { 0xac, 8, 12, 1 }, \ 1248259453Shselasky { 0xad, 0, 12, 1 }, \ 1249259453Shselasky { 0xad, 4, 12, 1 }, \ 1250259453Shselasky { 0xae, 0, 12, 1 }, \ 1251259453Shselasky { 0xae, 4, 12, 1 }, \ 1252259453Shselasky { 0xae, 8, 12, 1 }, \ 1253259453Shselasky { 0xaf, 4, 12, 1 }, \ 1254259453Shselasky { 0xaf, 8, 12, 1 }, \ 1255259453Shselasky { 0xb0, 0, 12, 1 }, \ 1256259453Shselasky { 0xb0, 8, 12, 1 }, \ 1257259453Shselasky { 0xb1, 0, 12, 1 }, \ 1258259453Shselasky { 0xb1, 4, 12, 1 }, \ 1259259453Shselasky { 0xb7, 4, 12, 1 }, \ 1260259453Shselasky { 0xb7, 8, 12, 1 }, \ 1261259453Shselasky { 0xb8, 0, 12, 1 }, \ 1262259453Shselasky { 0xb8, 8, 12, 1 }, \ 1263259453Shselasky { 0xb9, 0, 12, 1 }, \ 1264259453Shselasky { 0xb9, 4, 12, 1 }, \ 1265259453Shselasky { 0xba, 0, 12, 1 }, \ 1266259453Shselasky { 0xba, 4, 12, 1 }, \ 1267259453Shselasky { 0xba, 8, 12, 1 }, \ 1268259453Shselasky { 0xbb, 4, 12, 1 }, \ 1269259453Shselasky { 0xbb, 8, 12, 1 }, \ 1270259453Shselasky { 0xbc, 0, 12, 1 }, \ 1271259453Shselasky { 0xbc, 8, 12, 1 }, \ 1272259453Shselasky { 0xbd, 0, 12, 1 }, \ 1273259453Shselasky { 0xbd, 4, 12, 1 }, \ 1274259453Shselasky { 0xbe, 0, 12, 1 }, \ 1275259453Shselasky { 0xbf, 6, 12, 1 }, \ 1276259453Shselasky { 0xbf, 10, 12, 1 }, \ 1277259453Shselasky { 0xc0, 2, 12, 1 }, \ 1278259453Shselasky { 0xc0, 10, 12, 1 }, \ 1279259453Shselasky { 0xc1, 2, 12, 1 }, \ 1280259453Shselasky { 0xc1, 6, 12, 1 }, \ 1281259453Shselasky { 0xc2, 2, 12, 1 }, \ 1282259453Shselasky { 0xa4, 0, 12, 1 }, \ 1283259453Shselasky { 0xa4, 4, 12, 1 }, \ 1284259453Shselasky { 0xa5, 8, 12, 1 }, \ 1285259453Shselasky { 0xa6, 0, 12, 1 } 1286259453Shselasky 1287261868Skevlo#define RT5592_RF5592_40MHZ \ 1288259453Shselasky { 0xf1, 2, 10, 3 }, \ 1289259453Shselasky { 0xf1, 7, 10, 3 }, \ 1290259453Shselasky { 0xf2, 2, 10, 3 }, \ 1291259453Shselasky { 0xf2, 7, 10, 3 }, \ 1292259453Shselasky { 0xf3, 2, 10, 3 }, \ 1293259453Shselasky { 0xf3, 7, 10, 3 }, \ 1294259453Shselasky { 0xf4, 2, 10, 3 }, \ 1295259453Shselasky { 0xf4, 7, 10, 3 }, \ 1296259453Shselasky { 0xf5, 2, 10, 3 }, \ 1297259453Shselasky { 0xf5, 7, 10, 3 }, \ 1298259453Shselasky { 0xf6, 2, 10, 3 }, \ 1299259453Shselasky { 0xf6, 7, 10, 3 }, \ 1300259453Shselasky { 0xf7, 2, 10, 3 }, \ 1301259453Shselasky { 0xf8, 4, 10, 3 }, \ 1302259453Shselasky { 0x56, 4, 12, 1 }, \ 1303259453Shselasky { 0x56, 6, 12, 1 }, \ 1304259453Shselasky { 0x56, 8, 12, 1 }, \ 1305259453Shselasky { 0x57, 0, 12, 1 }, \ 1306259453Shselasky { 0x57, 2, 12, 1 }, \ 1307259453Shselasky { 0x57, 4, 12, 1 }, \ 1308259453Shselasky { 0x57, 8, 12, 1 }, \ 1309259453Shselasky { 0x57, 10, 12, 1 }, \ 1310259453Shselasky { 0x58, 0, 12, 1 }, \ 1311259453Shselasky { 0x58, 4, 12, 1 }, \ 1312259453Shselasky { 0x58, 6, 12, 1 }, \ 1313259453Shselasky { 0x58, 8, 12, 1 }, \ 1314259453Shselasky { 0x5b, 8, 12, 1 }, \ 1315259453Shselasky { 0x5b, 10, 12, 1 }, \ 1316259453Shselasky { 0x5c, 0, 12, 1 }, \ 1317259453Shselasky { 0x5c, 4, 12, 1 }, \ 1318259453Shselasky { 0x5c, 6, 12, 1 }, \ 1319259453Shselasky { 0x5c, 8, 12, 1 }, \ 1320259453Shselasky { 0x5d, 0, 12, 1 }, \ 1321259453Shselasky { 0x5d, 2, 12, 1 }, \ 1322259453Shselasky { 0x5d, 4, 12, 1 }, \ 1323259453Shselasky { 0x5d, 8, 12, 1 }, \ 1324259453Shselasky { 0x5d, 10, 12, 1 }, \ 1325259453Shselasky { 0x5e, 0, 12, 1 }, \ 1326259453Shselasky { 0x5e, 4, 12, 1 }, \ 1327259453Shselasky { 0x5e, 6, 12, 1 }, \ 1328259453Shselasky { 0x5e, 8, 12, 1 }, \ 1329259453Shselasky { 0x5f, 0, 12, 1 }, \ 1330259453Shselasky { 0x5f, 9, 12, 1 }, \ 1331259453Shselasky { 0x5f, 11, 12, 1 }, \ 1332259453Shselasky { 0x60, 1, 12, 1 }, \ 1333259453Shselasky { 0x60, 5, 12, 1 }, \ 1334259453Shselasky { 0x60, 7, 12, 1 }, \ 1335259453Shselasky { 0x60, 9, 12, 1 }, \ 1336259453Shselasky { 0x61, 1, 12, 1 }, \ 1337259453Shselasky { 0x52, 0, 12, 1 }, \ 1338259453Shselasky { 0x52, 4, 12, 1 }, \ 1339259453Shselasky { 0x52, 8, 12, 1 }, \ 1340259453Shselasky { 0x53, 0, 12, 1 } 1341259453Shselasky 1342261868Skevlo#define RT3070_DEF_RF \ 1343203134Sthompsa { 4, 0x40 }, \ 1344203134Sthompsa { 5, 0x03 }, \ 1345203134Sthompsa { 6, 0x02 }, \ 1346259461Shselasky { 7, 0x60 }, \ 1347203134Sthompsa { 9, 0x0f }, \ 1348203134Sthompsa { 10, 0x41 }, \ 1349203134Sthompsa { 11, 0x21 }, \ 1350203134Sthompsa { 12, 0x7b }, \ 1351203134Sthompsa { 14, 0x90 }, \ 1352203134Sthompsa { 15, 0x58 }, \ 1353203134Sthompsa { 16, 0xb3 }, \ 1354203134Sthompsa { 17, 0x92 }, \ 1355203134Sthompsa { 18, 0x2c }, \ 1356203134Sthompsa { 19, 0x02 }, \ 1357203134Sthompsa { 20, 0xba }, \ 1358203134Sthompsa { 21, 0xdb }, \ 1359203134Sthompsa { 24, 0x16 }, \ 1360259461Shselasky { 25, 0x03 }, \ 1361203134Sthompsa { 29, 0x1f } 1362203134Sthompsa 1363261868Skevlo#define RT3572_DEF_RF \ 1364205042Sthompsa { 0, 0x70 }, \ 1365205042Sthompsa { 1, 0x81 }, \ 1366205042Sthompsa { 2, 0xf1 }, \ 1367205042Sthompsa { 3, 0x02 }, \ 1368205042Sthompsa { 4, 0x4c }, \ 1369205042Sthompsa { 5, 0x05 }, \ 1370205042Sthompsa { 6, 0x4a }, \ 1371205042Sthompsa { 7, 0xd8 }, \ 1372205042Sthompsa { 9, 0xc3 }, \ 1373205042Sthompsa { 10, 0xf1 }, \ 1374205042Sthompsa { 11, 0xb9 }, \ 1375205042Sthompsa { 12, 0x70 }, \ 1376205042Sthompsa { 13, 0x65 }, \ 1377205042Sthompsa { 14, 0xa0 }, \ 1378205042Sthompsa { 15, 0x53 }, \ 1379205042Sthompsa { 16, 0x4c }, \ 1380205042Sthompsa { 17, 0x23 }, \ 1381205042Sthompsa { 18, 0xac }, \ 1382205042Sthompsa { 19, 0x93 }, \ 1383205042Sthompsa { 20, 0xb3 }, \ 1384205042Sthompsa { 21, 0xd0 }, \ 1385205042Sthompsa { 22, 0x00 }, \ 1386205042Sthompsa { 23, 0x3c }, \ 1387205042Sthompsa { 24, 0x16 }, \ 1388205042Sthompsa { 25, 0x15 }, \ 1389205042Sthompsa { 26, 0x85 }, \ 1390205042Sthompsa { 27, 0x00 }, \ 1391205042Sthompsa { 28, 0x00 }, \ 1392205042Sthompsa { 29, 0x9b }, \ 1393205042Sthompsa { 30, 0x09 }, \ 1394205042Sthompsa { 31, 0x10 } 1395205042Sthompsa 1396261868Skevlo#define RT3593_DEF_RF \ 1397261868Skevlo { 1, 0x03 }, \ 1398261868Skevlo { 3, 0x80 }, \ 1399261868Skevlo { 5, 0x00 }, \ 1400261868Skevlo { 6, 0x40 }, \ 1401261868Skevlo { 8, 0xf1 }, \ 1402261868Skevlo { 9, 0x02 }, \ 1403261868Skevlo { 10, 0xd3 }, \ 1404261868Skevlo { 11, 0x40 }, \ 1405261868Skevlo { 12, 0x4e }, \ 1406261868Skevlo { 13, 0x12 }, \ 1407261868Skevlo { 18, 0x40 }, \ 1408261868Skevlo { 22, 0x20 }, \ 1409261868Skevlo { 30, 0x10 }, \ 1410261868Skevlo { 31, 0x80 }, \ 1411261868Skevlo { 32, 0x78 }, \ 1412261868Skevlo { 33, 0x3b }, \ 1413261868Skevlo { 34, 0x3c }, \ 1414261868Skevlo { 35, 0xe0 }, \ 1415261868Skevlo { 38, 0x86 }, \ 1416261868Skevlo { 39, 0x23 }, \ 1417261868Skevlo { 44, 0xd3 }, \ 1418261868Skevlo { 45, 0xbb }, \ 1419261868Skevlo { 46, 0x60 }, \ 1420261868Skevlo { 49, 0x81 }, \ 1421261868Skevlo { 50, 0x86 }, \ 1422261868Skevlo { 51, 0x75 }, \ 1423261868Skevlo { 52, 0x45 }, \ 1424261868Skevlo { 53, 0x18 }, \ 1425261868Skevlo { 54, 0x18 }, \ 1426261868Skevlo { 55, 0x18 }, \ 1427261868Skevlo { 56, 0xdb }, \ 1428261868Skevlo { 57, 0x6e } 1429261868Skevlo 1430261868Skevlo#define RT5390_DEF_RF \ 1431259453Shselasky { 1, 0x0f }, \ 1432259453Shselasky { 2, 0x80 }, \ 1433259453Shselasky { 3, 0x88 }, \ 1434259453Shselasky { 5, 0x10 }, \ 1435259453Shselasky { 6, 0xa0 }, \ 1436259453Shselasky { 7, 0x00 }, \ 1437259453Shselasky { 10, 0x53 }, \ 1438259453Shselasky { 11, 0x4a }, \ 1439259453Shselasky { 12, 0x46 }, \ 1440259453Shselasky { 13, 0x9f }, \ 1441259453Shselasky { 14, 0x00 }, \ 1442259453Shselasky { 15, 0x00 }, \ 1443259453Shselasky { 16, 0x00 }, \ 1444259453Shselasky { 18, 0x03 }, \ 1445259453Shselasky { 19, 0x00 }, \ 1446259453Shselasky { 20, 0x00 }, \ 1447259453Shselasky { 21, 0x00 }, \ 1448259453Shselasky { 22, 0x20 }, \ 1449259453Shselasky { 23, 0x00 }, \ 1450259453Shselasky { 24, 0x00 }, \ 1451259453Shselasky { 25, 0xc0 }, \ 1452259453Shselasky { 26, 0x00 }, \ 1453259453Shselasky { 27, 0x09 }, \ 1454259453Shselasky { 28, 0x00 }, \ 1455259453Shselasky { 29, 0x10 }, \ 1456259453Shselasky { 30, 0x10 }, \ 1457259453Shselasky { 31, 0x80 }, \ 1458259453Shselasky { 32, 0x80 }, \ 1459259453Shselasky { 33, 0x00 }, \ 1460259453Shselasky { 34, 0x07 }, \ 1461259453Shselasky { 35, 0x12 }, \ 1462259453Shselasky { 36, 0x00 }, \ 1463259453Shselasky { 37, 0x08 }, \ 1464259453Shselasky { 38, 0x85 }, \ 1465259453Shselasky { 39, 0x1b }, \ 1466259453Shselasky { 40, 0x0b }, \ 1467259453Shselasky { 41, 0xbb }, \ 1468259453Shselasky { 42, 0xd2 }, \ 1469259453Shselasky { 43, 0x9a }, \ 1470259453Shselasky { 44, 0x0e }, \ 1471259453Shselasky { 45, 0xa2 }, \ 1472259453Shselasky { 46, 0x7b }, \ 1473259453Shselasky { 47, 0x00 }, \ 1474259453Shselasky { 48, 0x10 }, \ 1475259453Shselasky { 49, 0x94 }, \ 1476259453Shselasky { 52, 0x38 }, \ 1477259453Shselasky { 53, 0x84 }, \ 1478259453Shselasky { 54, 0x78 }, \ 1479259453Shselasky { 55, 0x44 }, \ 1480259453Shselasky { 56, 0x22 }, \ 1481259453Shselasky { 57, 0x80 }, \ 1482259453Shselasky { 58, 0x7f }, \ 1483259453Shselasky { 59, 0x8f }, \ 1484259453Shselasky { 60, 0x45 }, \ 1485259453Shselasky { 61, 0xdd }, \ 1486259453Shselasky { 62, 0x00 }, \ 1487259453Shselasky { 63, 0x00 } 1488218676Shselasky 1489261868Skevlo#define RT5392_DEF_RF \ 1490259453Shselasky { 1, 0x17 }, \ 1491259453Shselasky { 3, 0x88 }, \ 1492259453Shselasky { 5, 0x10 }, \ 1493259453Shselasky { 6, 0xe0 }, \ 1494259453Shselasky { 7, 0x00 }, \ 1495259453Shselasky { 10, 0x53 }, \ 1496259453Shselasky { 11, 0x4a }, \ 1497259453Shselasky { 12, 0x46 }, \ 1498259453Shselasky { 13, 0x9f }, \ 1499259453Shselasky { 14, 0x00 }, \ 1500259453Shselasky { 15, 0x00 }, \ 1501259453Shselasky { 16, 0x00 }, \ 1502259453Shselasky { 18, 0x03 }, \ 1503259453Shselasky { 19, 0x4d }, \ 1504259453Shselasky { 20, 0x00 }, \ 1505259453Shselasky { 21, 0x8d }, \ 1506259453Shselasky { 22, 0x20 }, \ 1507259453Shselasky { 23, 0x0b }, \ 1508259453Shselasky { 24, 0x44 }, \ 1509259453Shselasky { 25, 0x80 }, \ 1510259453Shselasky { 26, 0x82 }, \ 1511259453Shselasky { 27, 0x09 }, \ 1512259453Shselasky { 28, 0x00 }, \ 1513259453Shselasky { 29, 0x10 }, \ 1514259453Shselasky { 30, 0x10 }, \ 1515259453Shselasky { 31, 0x80 }, \ 1516259453Shselasky { 32, 0x20 }, \ 1517259453Shselasky { 33, 0xc0 }, \ 1518259453Shselasky { 34, 0x07 }, \ 1519259453Shselasky { 35, 0x12 }, \ 1520259453Shselasky { 36, 0x00 }, \ 1521259453Shselasky { 37, 0x08 }, \ 1522259453Shselasky { 38, 0x89 }, \ 1523259453Shselasky { 39, 0x1b }, \ 1524259453Shselasky { 40, 0x0f }, \ 1525259453Shselasky { 41, 0xbb }, \ 1526259453Shselasky { 42, 0xd5 }, \ 1527259453Shselasky { 43, 0x9b }, \ 1528259453Shselasky { 44, 0x0e }, \ 1529259453Shselasky { 45, 0xa2 }, \ 1530259453Shselasky { 46, 0x73 }, \ 1531259453Shselasky { 47, 0x0c }, \ 1532259453Shselasky { 48, 0x10 }, \ 1533259453Shselasky { 49, 0x94 }, \ 1534259453Shselasky { 50, 0x94 }, \ 1535259453Shselasky { 51, 0x3a }, \ 1536259453Shselasky { 52, 0x48 }, \ 1537259453Shselasky { 53, 0x44 }, \ 1538259453Shselasky { 54, 0x38 }, \ 1539259453Shselasky { 55, 0x43 }, \ 1540259453Shselasky { 56, 0xa1 }, \ 1541259453Shselasky { 57, 0x00 }, \ 1542259453Shselasky { 58, 0x39 }, \ 1543259453Shselasky { 59, 0x07 }, \ 1544259453Shselasky { 60, 0x45 }, \ 1545259453Shselasky { 61, 0x91 }, \ 1546259453Shselasky { 62, 0x39 }, \ 1547259453Shselasky { 63, 0x07 } 1548259453Shselasky 1549261868Skevlo#define RT5592_DEF_RF \ 1550259453Shselasky { 1, 0x3f }, \ 1551259453Shselasky { 3, 0x08 }, \ 1552259453Shselasky { 5, 0x10 }, \ 1553259453Shselasky { 6, 0xe4 }, \ 1554259453Shselasky { 7, 0x00 }, \ 1555259453Shselasky { 14, 0x00 }, \ 1556259453Shselasky { 15, 0x00 }, \ 1557259453Shselasky { 16, 0x00 }, \ 1558259453Shselasky { 18, 0x03 }, \ 1559259453Shselasky { 19, 0x4d }, \ 1560259453Shselasky { 20, 0x10 }, \ 1561259453Shselasky { 21, 0x8d }, \ 1562259453Shselasky { 26, 0x82 }, \ 1563259453Shselasky { 28, 0x00 }, \ 1564259453Shselasky { 29, 0x10 }, \ 1565259453Shselasky { 33, 0xc0 }, \ 1566259453Shselasky { 34, 0x07 }, \ 1567259453Shselasky { 35, 0x12 }, \ 1568259453Shselasky { 47, 0x0c }, \ 1569259453Shselasky { 53, 0x22 }, \ 1570259453Shselasky { 63, 0x07 } 1571259453Shselasky 1572261868Skevlo#define RT5592_2GHZ_DEF_RF \ 1573259453Shselasky { 10, 0x90 }, \ 1574259453Shselasky { 11, 0x4a }, \ 1575259453Shselasky { 12, 0x52 }, \ 1576259453Shselasky { 13, 0x42 }, \ 1577259453Shselasky { 22, 0x40 }, \ 1578259453Shselasky { 24, 0x4a }, \ 1579259453Shselasky { 25, 0x80 }, \ 1580259453Shselasky { 27, 0x42 }, \ 1581259453Shselasky { 36, 0x80 }, \ 1582259453Shselasky { 37, 0x08 }, \ 1583259453Shselasky { 38, 0x89 }, \ 1584259453Shselasky { 39, 0x1b }, \ 1585259453Shselasky { 40, 0x0d }, \ 1586259453Shselasky { 41, 0x9b }, \ 1587259453Shselasky { 42, 0xd5 }, \ 1588259453Shselasky { 43, 0x72 }, \ 1589259453Shselasky { 44, 0x0e }, \ 1590259453Shselasky { 45, 0xa2 }, \ 1591259453Shselasky { 46, 0x6b }, \ 1592259453Shselasky { 48, 0x10 }, \ 1593259453Shselasky { 51, 0x3e }, \ 1594259453Shselasky { 52, 0x48 }, \ 1595259453Shselasky { 54, 0x38 }, \ 1596259453Shselasky { 56, 0xa1 }, \ 1597259453Shselasky { 57, 0x00 }, \ 1598259453Shselasky { 58, 0x39 }, \ 1599259453Shselasky { 60, 0x45 }, \ 1600259453Shselasky { 61, 0x91 }, \ 1601259453Shselasky { 62, 0x39 } 1602259453Shselasky 1603261868Skevlo#define RT5592_5GHZ_DEF_RF \ 1604259453Shselasky { 10, 0x97 }, \ 1605259453Shselasky { 11, 0x40 }, \ 1606259453Shselasky { 25, 0xbf }, \ 1607259453Shselasky { 27, 0x42 }, \ 1608259453Shselasky { 36, 0x00 }, \ 1609259453Shselasky { 37, 0x04 }, \ 1610259453Shselasky { 38, 0x85 }, \ 1611259453Shselasky { 40, 0x42 }, \ 1612259453Shselasky { 41, 0xbb }, \ 1613259453Shselasky { 42, 0xd7 }, \ 1614259453Shselasky { 45, 0x41 }, \ 1615259453Shselasky { 48, 0x00 }, \ 1616259453Shselasky { 57, 0x77 }, \ 1617259453Shselasky { 60, 0x05 }, \ 1618259453Shselasky { 61, 0x01 } 1619259453Shselasky 1620261868Skevlo#define RT5592_CHAN_5GHZ \ 1621259453Shselasky { 36, 64, 12, 0x2e }, \ 1622259453Shselasky { 100, 165, 12, 0x0e }, \ 1623259453Shselasky { 36, 64, 13, 0x22 }, \ 1624259453Shselasky { 100, 165, 13, 0x42 }, \ 1625259453Shselasky { 36, 64, 22, 0x60 }, \ 1626259453Shselasky { 100, 165, 22, 0x40 }, \ 1627259453Shselasky { 36, 64, 23, 0x7f }, \ 1628259453Shselasky { 100, 153, 23, 0x3c }, \ 1629259453Shselasky { 155, 165, 23, 0x38 }, \ 1630259453Shselasky { 36, 50, 24, 0x09 }, \ 1631259453Shselasky { 52, 64, 24, 0x07 }, \ 1632259453Shselasky { 100, 153, 24, 0x06 }, \ 1633259453Shselasky { 155, 165, 24, 0x05 }, \ 1634259453Shselasky { 36, 64, 39, 0x1c }, \ 1635259453Shselasky { 100, 138, 39, 0x1a }, \ 1636259453Shselasky { 140, 165, 39, 0x18 }, \ 1637259453Shselasky { 36, 64, 43, 0x5b }, \ 1638259453Shselasky { 100, 138, 43, 0x3b }, \ 1639259453Shselasky { 140, 165, 43, 0x1b }, \ 1640259453Shselasky { 36, 64, 44, 0x40 }, \ 1641259453Shselasky { 100, 138, 44, 0x20 }, \ 1642259453Shselasky { 140, 165, 44, 0x10 }, \ 1643259453Shselasky { 36, 64, 46, 0x00 }, \ 1644259453Shselasky { 100, 138, 46, 0x18 }, \ 1645259453Shselasky { 140, 165, 46, 0x08 }, \ 1646259453Shselasky { 36, 64, 51, 0xfe }, \ 1647259453Shselasky { 100, 124, 51, 0xfc }, \ 1648259453Shselasky { 126, 165, 51, 0xec }, \ 1649259453Shselasky { 36, 64, 52, 0x0c }, \ 1650259453Shselasky { 100, 138, 52, 0x06 }, \ 1651259453Shselasky { 140, 165, 52, 0x06 }, \ 1652259453Shselasky { 36, 64, 54, 0xf8 }, \ 1653259453Shselasky { 100, 165, 54, 0xeb }, \ 1654259453Shselasky { 36, 50, 55, 0x06 }, \ 1655259453Shselasky { 52, 64, 55, 0x04 }, \ 1656259453Shselasky { 100, 138, 55, 0x01 }, \ 1657259453Shselasky { 140, 165, 55, 0x00 }, \ 1658259453Shselasky { 36, 50, 56, 0xd3 }, \ 1659259453Shselasky { 52, 128, 56, 0xbb }, \ 1660259453Shselasky { 130, 165, 56, 0xab }, \ 1661259453Shselasky { 36, 64, 58, 0x15 }, \ 1662259453Shselasky { 100, 116, 58, 0x1d }, \ 1663259453Shselasky { 118, 165, 58, 0x15 }, \ 1664259453Shselasky { 36, 64, 59, 0x7f }, \ 1665259453Shselasky { 100, 138, 59, 0x3f }, \ 1666259453Shselasky { 140, 165, 59, 0x7c }, \ 1667259453Shselasky { 36, 64, 62, 0x15 }, \ 1668259453Shselasky { 100, 116, 62, 0x1d }, \ 1669259453Shselasky { 118, 165, 62, 0x15 } 1670259453Shselasky 1671218676Shselaskyunion run_stats { 1672218676Shselasky uint32_t raw; 1673218676Shselasky struct { 1674218676Shselasky uint16_t fail; 1675218676Shselasky uint16_t pad; 1676218676Shselasky } error; 1677218676Shselasky struct { 1678218676Shselasky uint16_t success; 1679218676Shselasky uint16_t retry; 1680218676Shselasky } tx; 1681218676Shselasky} __aligned(4); 1682218676Shselasky 1683203134Sthompsa#endif /* _IF_RUNREG_H_ */ 1684