1184610Salfred/*- 2184610Salfred * Copyright (c) 2001-2003, Shunsuke Akiyama <akiyama@FreeBSD.org>. 3184610Salfred * All rights reserved. 4184610Salfred * 5184610Salfred * Redistribution and use in source and binary forms, with or without 6184610Salfred * modification, are permitted provided that the following conditions 7184610Salfred * are met: 8184610Salfred * 1. Redistributions of source code must retain the above copyright 9184610Salfred * notice, this list of conditions and the following disclaimer. 10184610Salfred * 2. Redistributions in binary form must reproduce the above copyright 11184610Salfred * notice, this list of conditions and the following disclaimer in the 12184610Salfred * documentation and/or other materials provided with the distribution. 13184610Salfred * 14184610Salfred * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15184610Salfred * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16184610Salfred * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17184610Salfred * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18184610Salfred * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19184610Salfred * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20184610Salfred * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21184610Salfred * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22184610Salfred * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23184610Salfred * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24184610Salfred * SUCH DAMAGE. 25184610Salfred * 26184610Salfred * $FreeBSD$ 27184610Salfred */ 28184610Salfred 29184610Salfred#define RUE_CONFIG_IDX 0 /* config number 1 */ 30184610Salfred#define RUE_IFACE_IDX 0 31184610Salfred 32184610Salfred#define RUE_INTR_PKTLEN 0x8 33184610Salfred 34184610Salfred#define RUE_TIMEOUT 50 35184610Salfred#define RUE_MIN_FRAMELEN 60 36184610Salfred 37184610Salfred/* Registers. */ 38184610Salfred#define RUE_IDR0 0x0120 39184610Salfred#define RUE_IDR1 0x0121 40184610Salfred#define RUE_IDR2 0x0122 41184610Salfred#define RUE_IDR3 0x0123 42184610Salfred#define RUE_IDR4 0x0124 43184610Salfred#define RUE_IDR5 0x0125 44184610Salfred 45184610Salfred#define RUE_MAR0 0x0126 46184610Salfred#define RUE_MAR1 0x0127 47184610Salfred#define RUE_MAR2 0x0128 48184610Salfred#define RUE_MAR3 0x0129 49184610Salfred#define RUE_MAR4 0x012A 50184610Salfred#define RUE_MAR5 0x012B 51184610Salfred#define RUE_MAR6 0x012C 52184610Salfred#define RUE_MAR7 0x012D 53184610Salfred 54184610Salfred#define RUE_CR 0x012E /* B, R/W */ 55184610Salfred#define RUE_CR_SOFT_RST 0x10 56184610Salfred#define RUE_CR_RE 0x08 57184610Salfred#define RUE_CR_TE 0x04 58184610Salfred#define RUE_CR_EP3CLREN 0x02 59184610Salfred 60184610Salfred#define RUE_TCR 0x012F /* B, R/W */ 61184610Salfred#define RUE_TCR_TXRR1 0x80 62184610Salfred#define RUE_TCR_TXRR0 0x40 63184610Salfred#define RUE_TCR_IFG1 0x10 64184610Salfred#define RUE_TCR_IFG0 0x08 65184610Salfred#define RUE_TCR_NOCRC 0x01 66184610Salfred#define RUE_TCR_CONFIG (RUE_TCR_TXRR1 | RUE_TCR_TXRR0 | \ 67184610Salfred RUE_TCR_IFG1 | RUE_TCR_IFG0) 68184610Salfred 69184610Salfred#define RUE_RCR 0x0130 /* W, R/W */ 70184610Salfred#define RUE_RCR_TAIL 0x80 71184610Salfred#define RUE_RCR_AER 0x40 72184610Salfred#define RUE_RCR_AR 0x20 73184610Salfred#define RUE_RCR_AM 0x10 74184610Salfred#define RUE_RCR_AB 0x08 75184610Salfred#define RUE_RCR_AD 0x04 76184610Salfred#define RUE_RCR_AAM 0x02 77184610Salfred#define RUE_RCR_AAP 0x01 78184610Salfred#define RUE_RCR_CONFIG (RUE_RCR_TAIL | RUE_RCR_AD) 79184610Salfred 80184610Salfred#define RUE_TSR 0x0132 81184610Salfred#define RUE_RSR 0x0133 82184610Salfred#define RUE_CON0 0x0135 83184610Salfred#define RUE_CON1 0x0136 84184610Salfred#define RUE_MSR 0x0137 85184610Salfred#define RUE_PHYADD 0x0138 86184610Salfred#define RUE_PHYDAT 0x0139 87184610Salfred 88184610Salfred#define RUE_PHYCNT 0x013B /* B, R/W */ 89184610Salfred#define RUE_PHYCNT_PHYOWN 0x40 90184610Salfred#define RUE_PHYCNT_RWCR 0x20 91184610Salfred 92184610Salfred#define RUE_GPPC 0x013D 93184610Salfred#define RUE_WAKECNT 0x013E 94184610Salfred 95184610Salfred#define RUE_BMCR 0x0140 96184610Salfred#define RUE_BMCR_SPD_SET 0x2000 97184610Salfred#define RUE_BMCR_DUPLEX 0x0100 98184610Salfred 99184610Salfred#define RUE_BMSR 0x0142 100184610Salfred 101184610Salfred#define RUE_ANAR 0x0144 /* W, R/W */ 102184610Salfred#define RUE_ANAR_PAUSE 0x0400 103184610Salfred 104184610Salfred#define RUE_ANLP 0x0146 /* W, R/O */ 105184610Salfred#define RUE_ANLP_PAUSE 0x0400 106184610Salfred 107184610Salfred#define RUE_AER 0x0148 108184610Salfred 109184610Salfred#define RUE_NWAYT 0x014A 110184610Salfred#define RUE_CSCR 0x014C 111184610Salfred 112184610Salfred#define RUE_CRC0 0x014E 113184610Salfred#define RUE_CRC1 0x0150 114184610Salfred#define RUE_CRC2 0x0152 115184610Salfred#define RUE_CRC3 0x0154 116184610Salfred#define RUE_CRC4 0x0156 117184610Salfred 118184610Salfred#define RUE_BYTEMASK0 0x0158 119184610Salfred#define RUE_BYTEMASK1 0x0160 120184610Salfred#define RUE_BYTEMASK2 0x0168 121184610Salfred#define RUE_BYTEMASK3 0x0170 122184610Salfred#define RUE_BYTEMASK4 0x0178 123184610Salfred 124184610Salfred#define RUE_PHY1 0x0180 125184610Salfred#define RUE_PHY2 0x0184 126184610Salfred 127184610Salfred#define RUE_TW1 0x0186 128184610Salfred 129184610Salfred#define RUE_REG_MIN 0x0120 130184610Salfred#define RUE_REG_MAX 0x0189 131184610Salfred 132184610Salfred/* EEPROM address declarations. */ 133184610Salfred#define RUE_EEPROM_BASE 0x1200 134184610Salfred#define RUE_EEPROM_IDR0 (RUE_EEPROM_BASE + 0x02) 135184610Salfred#define RUE_EEPROM_IDR1 (RUE_EEPROM_BASE + 0x03) 136184610Salfred#define RUE_EEPROM_IDR2 (RUE_EEPROM_BASE + 0x03) 137184610Salfred#define RUE_EEPROM_IDR3 (RUE_EEPROM_BASE + 0x03) 138184610Salfred#define RUE_EEPROM_IDR4 (RUE_EEPROM_BASE + 0x03) 139184610Salfred#define RUE_EEPROM_IDR5 (RUE_EEPROM_BASE + 0x03) 140184610Salfred#define RUE_EEPROM_INTERVAL (RUE_EEPROM_BASE + 0x17) 141184610Salfred 142184610Salfred#define RUE_RXSTAT_VALID (0x01 << 12) 143184610Salfred#define RUE_RXSTAT_RUNT (0x02 << 12) 144184610Salfred#define RUE_RXSTAT_PMATCH (0x04 << 12) 145184610Salfred#define RUE_RXSTAT_MCAST (0x08 << 12) 146184610Salfred 147194228Sthompsa#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 148184610Salfred 149184610Salfredstruct rue_intrpkt { 150184610Salfred uint8_t rue_tsr; 151184610Salfred uint8_t rue_rsr; 152184610Salfred uint8_t rue_gep_msr; 153184610Salfred uint8_t rue_waksr; 154184610Salfred uint8_t rue_txok_cnt; 155184610Salfred uint8_t rue_rxlost_cnt; 156184610Salfred uint8_t rue_crcerr_cnt; 157184610Salfred uint8_t rue_col_cnt; 158184610Salfred} __packed; 159184610Salfred 160187259Sthompsaenum { 161187259Sthompsa RUE_BULK_DT_WR, 162187259Sthompsa RUE_BULK_DT_RD, 163187259Sthompsa RUE_INTR_DT_RD, 164188412Sthompsa RUE_N_TRANSFER, 165187259Sthompsa}; 166187259Sthompsa 167184610Salfredstruct rue_softc { 168192984Sthompsa struct usb_ether sc_ue; 169188412Sthompsa struct mtx sc_mtx; 170192984Sthompsa struct usb_xfer *sc_xfer[RUE_N_TRANSFER]; 171184610Salfred 172188412Sthompsa int sc_flags; 173188412Sthompsa#define RUE_FLAG_LINK 0x0001 174188412Sthompsa}; 175184610Salfred 176188412Sthompsa#define RUE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 177188412Sthompsa#define RUE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 178188412Sthompsa#define RUE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 179