if_axereg.h revision 224020
1184610Salfred/*- 2184610Salfred * Copyright (c) 1997, 1998, 1999, 2000-2003 3184610Salfred * Bill Paul <wpaul@windriver.com>. All rights reserved. 4184610Salfred * 5184610Salfred * Redistribution and use in source and binary forms, with or without 6184610Salfred * modification, are permitted provided that the following conditions 7184610Salfred * are met: 8184610Salfred * 1. Redistributions of source code must retain the above copyright 9184610Salfred * notice, this list of conditions and the following disclaimer. 10184610Salfred * 2. Redistributions in binary form must reproduce the above copyright 11184610Salfred * notice, this list of conditions and the following disclaimer in the 12184610Salfred * documentation and/or other materials provided with the distribution. 13184610Salfred * 3. All advertising materials mentioning features or use of this software 14184610Salfred * must display the following acknowledgement: 15184610Salfred * This product includes software developed by Bill Paul. 16184610Salfred * 4. Neither the name of the author nor the names of any co-contributors 17184610Salfred * may be used to endorse or promote products derived from this software 18184610Salfred * without specific prior written permission. 19184610Salfred * 20184610Salfred * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21184610Salfred * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22184610Salfred * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23184610Salfred * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24184610Salfred * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25184610Salfred * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26184610Salfred * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27184610Salfred * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28184610Salfred * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29184610Salfred * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30184610Salfred * THE POSSIBILITY OF SUCH DAMAGE. 31184610Salfred * 32184610Salfred * $FreeBSD: head/sys/dev/usb/net/if_axereg.h 224020 2011-07-14 17:19:00Z yongari $ 33184610Salfred */ 34184610Salfred 35184610Salfred/* 36184610Salfred * Definitions for the ASIX Electronics AX88172, AX88178 37184610Salfred * and AX88772 to ethernet controllers. 38184610Salfred */ 39184610Salfred 40184610Salfred/* 41184610Salfred * Vendor specific commands. ASIX conveniently doesn't document the 'set 42184610Salfred * NODEID' command in their datasheet (thanks a lot guys). 43184610Salfred * To make handling these commands easier, I added some extra data which is 44184610Salfred * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with 45184610Salfred * the format: LDCC. L and D are both nibbles in the high byte. L represents 46184610Salfred * the data length (0 to 15) and D represents the direction (0 for vendor read, 47184610Salfred * 1 for vendor write). CC is the command byte, as specified in the manual. 48184610Salfred */ 49184610Salfred 50184610Salfred#define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8) 51184610Salfred#define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 52184610Salfred#define AXE_CMD_CMD(x) ((x) & 0x00FF) 53184610Salfred 54184610Salfred#define AXE_172_CMD_READ_RXTX_SRAM 0x2002 55184610Salfred#define AXE_182_CMD_READ_RXTX_SRAM 0x8002 56184610Salfred#define AXE_172_CMD_WRITE_RX_SRAM 0x0103 57184610Salfred#define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 58184610Salfred#define AXE_172_CMD_WRITE_TX_SRAM 0x0104 59184610Salfred#define AXE_CMD_MII_OPMODE_SW 0x0106 60184610Salfred#define AXE_CMD_MII_READ_REG 0x2007 61184610Salfred#define AXE_CMD_MII_WRITE_REG 0x2108 62184610Salfred#define AXE_CMD_MII_READ_OPMODE 0x1009 63184610Salfred#define AXE_CMD_MII_OPMODE_HW 0x010A 64184610Salfred#define AXE_CMD_SROM_READ 0x200B 65184610Salfred#define AXE_CMD_SROM_WRITE 0x010C 66184610Salfred#define AXE_CMD_SROM_WR_ENABLE 0x010D 67184610Salfred#define AXE_CMD_SROM_WR_DISABLE 0x010E 68184610Salfred#define AXE_CMD_RXCTL_READ 0x200F 69184610Salfred#define AXE_CMD_RXCTL_WRITE 0x0110 70184610Salfred#define AXE_CMD_READ_IPG012 0x3011 71184610Salfred#define AXE_172_CMD_WRITE_IPG0 0x0112 72184610Salfred#define AXE_178_CMD_WRITE_IPG012 0x0112 73184610Salfred#define AXE_172_CMD_WRITE_IPG1 0x0113 74184610Salfred#define AXE_178_CMD_READ_NODEID 0x6013 75184610Salfred#define AXE_172_CMD_WRITE_IPG2 0x0114 76184610Salfred#define AXE_178_CMD_WRITE_NODEID 0x6114 77184610Salfred#define AXE_CMD_READ_MCAST 0x8015 78184610Salfred#define AXE_CMD_WRITE_MCAST 0x8116 79184610Salfred#define AXE_172_CMD_READ_NODEID 0x6017 80184610Salfred#define AXE_172_CMD_WRITE_NODEID 0x6118 81184610Salfred 82184610Salfred#define AXE_CMD_READ_PHYID 0x2019 83184610Salfred#define AXE_172_CMD_READ_MEDIA 0x101A 84184610Salfred#define AXE_178_CMD_READ_MEDIA 0x201A 85184610Salfred#define AXE_CMD_WRITE_MEDIA 0x011B 86184610Salfred#define AXE_CMD_READ_MONITOR_MODE 0x101C 87184610Salfred#define AXE_CMD_WRITE_MONITOR_MODE 0x011D 88184610Salfred#define AXE_CMD_READ_GPIO 0x101E 89184610Salfred#define AXE_CMD_WRITE_GPIO 0x011F 90184610Salfred 91184610Salfred#define AXE_CMD_SW_RESET_REG 0x0120 92184610Salfred#define AXE_CMD_SW_PHY_STATUS 0x0021 93184610Salfred#define AXE_CMD_SW_PHY_SELECT 0x0122 94184610Salfred 95215969Syongari/* AX88772A and AX88772B only. */ 96215969Syongari#define AXE_CMD_READ_VLAN_CTRL 0x4027 97215969Syongari#define AXE_CMD_WRITE_VLAN_CTRL 0x4028 98215969Syongari 99224020Syongari#define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A 100224020Syongari 101184610Salfred#define AXE_SW_RESET_CLEAR 0x00 102184610Salfred#define AXE_SW_RESET_RR 0x01 103184610Salfred#define AXE_SW_RESET_RT 0x02 104184610Salfred#define AXE_SW_RESET_PRTE 0x04 105184610Salfred#define AXE_SW_RESET_PRL 0x08 106184610Salfred#define AXE_SW_RESET_BZ 0x10 107184610Salfred#define AXE_SW_RESET_IPRL 0x20 108184610Salfred#define AXE_SW_RESET_IPPD 0x40 109184610Salfred 110184610Salfred/* AX88178 documentation says to always write this bit... */ 111184610Salfred#define AXE_178_RESET_MAGIC 0x40 112184610Salfred 113184610Salfred#define AXE_178_MEDIA_GMII 0x0001 114184610Salfred#define AXE_MEDIA_FULL_DUPLEX 0x0002 115184610Salfred#define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 116184610Salfred 117184610Salfred/* AX88178/88772 documentation says to always write 1 to bit 2 */ 118184610Salfred#define AXE_178_MEDIA_MAGIC 0x0004 119184610Salfred/* AX88772 documentation says to always write 0 to bit 3 */ 120184610Salfred#define AXE_178_MEDIA_ENCK 0x0008 121184610Salfred#define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 122184610Salfred#define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 123184610Salfred#define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 124184610Salfred#define AXE_178_MEDIA_JUMBO_EN 0x0040 125184610Salfred#define AXE_178_MEDIA_LTPF_ONLY 0x0080 126184610Salfred#define AXE_178_MEDIA_RX_EN 0x0100 127184610Salfred#define AXE_178_MEDIA_100TX 0x0200 128184610Salfred#define AXE_178_MEDIA_SBP 0x0800 129184610Salfred#define AXE_178_MEDIA_SUPERMAC 0x1000 130184610Salfred 131184610Salfred#define AXE_RXCMD_PROMISC 0x0001 132184610Salfred#define AXE_RXCMD_ALLMULTI 0x0002 133184610Salfred#define AXE_172_RXCMD_UNICAST 0x0004 134184610Salfred#define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 135184610Salfred#define AXE_RXCMD_BROADCAST 0x0008 136184610Salfred#define AXE_RXCMD_MULTICAST 0x0010 137224020Syongari#define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */ 138184610Salfred#define AXE_RXCMD_ENABLE 0x0080 139184610Salfred#define AXE_178_RXCMD_MFB_MASK 0x0300 140184610Salfred#define AXE_178_RXCMD_MFB_2048 0x0000 141184610Salfred#define AXE_178_RXCMD_MFB_4096 0x0100 142184610Salfred#define AXE_178_RXCMD_MFB_8192 0x0200 143184610Salfred#define AXE_178_RXCMD_MFB_16384 0x0300 144224020Syongari#define AXE_772B_RXCMD_HDR_TYPE_0 0x0000 145224020Syongari#define AXE_772B_RXCMD_HDR_TYPE_1 0x0100 146224020Syongari#define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200 147224020Syongari#define AXE_772B_RXCMD_ADD_CHKSUM 0x0400 148224020Syongari#define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */ 149184610Salfred 150186730Salfred#define AXE_PHY_SEL_PRI 1 151186730Salfred#define AXE_PHY_SEL_SEC 0 152186730Salfred#define AXE_PHY_TYPE_MASK 0xE0 153186730Salfred#define AXE_PHY_TYPE_SHIFT 5 154186730Salfred#define AXE_PHY_TYPE(x) \ 155186730Salfred (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 156184610Salfred 157186730Salfred#define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 158186730Salfred#define PHY_TYPE_GIG 1 /* Gigabit PHY */ 159186730Salfred#define PHY_TYPE_SPECIAL 4 /* Special case */ 160186730Salfred#define PHY_TYPE_RSVD 5 /* Reserved */ 161186730Salfred#define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 162186730Salfred 163186730Salfred#define AXE_PHY_NO_MASK 0x1F 164186730Salfred#define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 165186730Salfred 166186730Salfred#define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 167186730Salfred 168212130Sthompsa#define AXE_GPIO0_EN 0x01 169212130Sthompsa#define AXE_GPIO0 0x02 170212130Sthompsa#define AXE_GPIO1_EN 0x04 171212130Sthompsa#define AXE_GPIO1 0x08 172212130Sthompsa#define AXE_GPIO2_EN 0x10 173212130Sthompsa#define AXE_GPIO2 0x20 174212130Sthompsa#define AXE_GPIO_RELOAD_EEPROM 0x80 175212130Sthompsa 176212130Sthompsa#define AXE_PHY_MODE_MARVELL 0x00 177212130Sthompsa#define AXE_PHY_MODE_CICADA 0x01 178212130Sthompsa#define AXE_PHY_MODE_AGERE 0x02 179212130Sthompsa#define AXE_PHY_MODE_CICADA_V2 0x05 180212130Sthompsa#define AXE_PHY_MODE_AGERE_GMII 0x06 181212130Sthompsa#define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 182212130Sthompsa#define AXE_PHY_MODE_REALTEK_8211CL 0x0C 183212130Sthompsa#define AXE_PHY_MODE_REALTEK_8211BN 0x0D 184212130Sthompsa#define AXE_PHY_MODE_REALTEK_8251CL 0x0E 185212130Sthompsa#define AXE_PHY_MODE_ATTANSIC 0x40 186212130Sthompsa 187224020Syongari/* AX88772A/AX88772B only. */ 188215969Syongari#define AXE_SW_PHY_SELECT_EXT 0x0000 189215969Syongari#define AXE_SW_PHY_SELECT_EMBEDDED 0x0001 190215969Syongari#define AXE_SW_PHY_SELECT_AUTO 0x0002 191215969Syongari#define AXE_SW_PHY_SELECT_SS_MII 0x0004 192215969Syongari#define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008 193215969Syongari#define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C 194215969Syongari#define AXE_SW_PHY_SELECT_SS_ENB 0x0010 195215969Syongari 196215969Syongari/* AX88772A/AX88772B VLAN control. */ 197215969Syongari#define AXE_VLAN_CTRL_ENB 0x00001000 198215969Syongari#define AXE_VLAN_CTRL_STRIP 0x00002000 199215969Syongari#define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF 200215969Syongari#define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000 201215969Syongari 202184610Salfred#define AXE_BULK_BUF_SIZE 16384 /* bytes */ 203184610Salfred 204184610Salfred#define AXE_CTL_READ 0x01 205184610Salfred#define AXE_CTL_WRITE 0x02 206184610Salfred 207184610Salfred#define AXE_CONFIG_IDX 0 /* config number 1 */ 208184610Salfred#define AXE_IFACE_IDX 0 209184610Salfred 210224020Syongari/* EEPROM Map. */ 211224020Syongari#define AXE_EEPROM_772B_NODE_ID 0x04 212224020Syongari#define AXE_EEPROM_772B_PHY_PWRCFG 0x18 213224020Syongari 214224020Syongaristruct ax88772b_mfb { 215224020Syongari int byte_cnt; 216224020Syongari int threshold; 217224020Syongari int size; 218224020Syongari}; 219224020Syongari#define AX88772B_MFB_2K 0 220224020Syongari#define AX88772B_MFB_4K 1 221224020Syongari#define AX88772B_MFB_6K 2 222224020Syongari#define AX88772B_MFB_8K 3 223224020Syongari#define AX88772B_MFB_16K 4 224224020Syongari#define AX88772B_MFB_20K 5 225224020Syongari#define AX88772B_MFB_24K 6 226224020Syongari#define AX88772B_MFB_32K 7 227224020Syongari 228184610Salfredstruct axe_sframe_hdr { 229184610Salfred uint16_t len; 230184610Salfred uint16_t ilen; 231184610Salfred} __packed; 232184610Salfred 233194228Sthompsa#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 234184610Salfred 235187259Sthompsa/* The interrupt endpoint is currently unused by the ASIX part. */ 236187259Sthompsaenum { 237187259Sthompsa AXE_BULK_DT_WR, 238187259Sthompsa AXE_BULK_DT_RD, 239188412Sthompsa AXE_N_TRANSFER, 240187259Sthompsa}; 241187259Sthompsa 242184610Salfredstruct axe_softc { 243192984Sthompsa struct usb_ether sc_ue; 244188412Sthompsa struct mtx sc_mtx; 245192984Sthompsa struct usb_xfer *sc_xfer[AXE_N_TRANSFER]; 246188412Sthompsa int sc_phyno; 247184610Salfred 248188412Sthompsa int sc_flags; 249186730Salfred#define AXE_FLAG_LINK 0x0001 250188412Sthompsa#define AXE_FLAG_772 0x1000 /* AX88772 */ 251215968Syongari#define AXE_FLAG_772A 0x2000 /* AX88772A */ 252215968Syongari#define AXE_FLAG_772B 0x4000 /* AX88772B */ 253215968Syongari#define AXE_FLAG_178 0x8000 /* AX88178 */ 254184610Salfred 255188412Sthompsa uint8_t sc_ipgs[3]; 256188412Sthompsa uint8_t sc_phyaddrs[2]; 257224020Syongari uint16_t sc_pwrcfg; 258215968Syongari int sc_tx_bufsz; 259188412Sthompsa}; 260184610Salfred 261215968Syongari#define AXE_IS_178_FAMILY(sc) \ 262215968Syongari ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \ 263215968Syongari AXE_FLAG_178)) 264215968Syongari 265215968Syongari#define AXE_IS_772(sc) \ 266215968Syongari ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B)) 267215968Syongari 268188412Sthompsa#define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 269188412Sthompsa#define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 270188412Sthompsa#define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 271