if_axe.c revision 212980
1/*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 212980 2010-09-21 22:42:14Z sanpei $"); 35 36/* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51/* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70/* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79#include <sys/stdint.h> 80#include <sys/stddef.h> 81#include <sys/param.h> 82#include <sys/queue.h> 83#include <sys/types.h> 84#include <sys/systm.h> 85#include <sys/kernel.h> 86#include <sys/bus.h> 87#include <sys/linker_set.h> 88#include <sys/module.h> 89#include <sys/lock.h> 90#include <sys/mutex.h> 91#include <sys/condvar.h> 92#include <sys/sysctl.h> 93#include <sys/sx.h> 94#include <sys/unistd.h> 95#include <sys/callout.h> 96#include <sys/malloc.h> 97#include <sys/priv.h> 98 99#include <dev/usb/usb.h> 100#include <dev/usb/usbdi.h> 101#include <dev/usb/usbdi_util.h> 102#include "usbdevs.h" 103 104#define USB_DEBUG_VAR axe_debug 105#include <dev/usb/usb_debug.h> 106#include <dev/usb/usb_process.h> 107 108#include <dev/usb/net/usb_ethernet.h> 109#include <dev/usb/net/if_axereg.h> 110 111/* 112 * AXE_178_MAX_FRAME_BURST 113 * max frame burst size for Ax88178 and Ax88772 114 * 0 2048 bytes 115 * 1 4096 bytes 116 * 2 8192 bytes 117 * 3 16384 bytes 118 * use the largest your system can handle without USB stalling. 119 * 120 * NB: 88772 parts appear to generate lots of input errors with 121 * a 2K rx buffer and 8K is only slightly faster than 4K on an 122 * EHCI port on a T42 so change at your own risk. 123 */ 124#define AXE_178_MAX_FRAME_BURST 1 125 126#ifdef USB_DEBUG 127static int axe_debug = 0; 128 129SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 130SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0, 131 "Debug level"); 132#endif 133 134/* 135 * Various supported device vendors/products. 136 */ 137static const struct usb_device_id axe_devs[] = { 138#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 139 AXE_DEV(ABOCOM, UF200, 0), 140 AXE_DEV(ACERCM, EP1427X2, 0), 141 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 142 AXE_DEV(ASIX, AX88172, 0), 143 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 144 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 145 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772), 146 AXE_DEV(ATEN, UC210T, 0), 147 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 148 AXE_DEV(BILLIONTON, USB2AR, 0), 149 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772), 150 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 151 AXE_DEV(DLINK, DUBE100, 0), 152 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 153 AXE_DEV(GOODWAY, GWUSB2E, 0), 154 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 155 AXE_DEV(JVC, MP_PRX1, 0), 156 AXE_DEV(LINKSYS2, USB200M, 0), 157 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 158 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 159 AXE_DEV(MELCO, LUAU2KTX, 0), 160 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 161 AXE_DEV(NETGEAR, FA120, 0), 162 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 163 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 164 AXE_DEV(SITECOM, LN029, 0), 165 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 166 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 167#undef AXE_DEV 168}; 169 170static device_probe_t axe_probe; 171static device_attach_t axe_attach; 172static device_detach_t axe_detach; 173 174static usb_callback_t axe_intr_callback; 175static usb_callback_t axe_bulk_read_callback; 176static usb_callback_t axe_bulk_write_callback; 177 178static miibus_readreg_t axe_miibus_readreg; 179static miibus_writereg_t axe_miibus_writereg; 180static miibus_statchg_t axe_miibus_statchg; 181 182static uether_fn_t axe_attach_post; 183static uether_fn_t axe_init; 184static uether_fn_t axe_stop; 185static uether_fn_t axe_start; 186static uether_fn_t axe_tick; 187static uether_fn_t axe_setmulti; 188static uether_fn_t axe_setpromisc; 189 190static int axe_ifmedia_upd(struct ifnet *); 191static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 192static int axe_cmd(struct axe_softc *, int, int, int, void *); 193static void axe_ax88178_init(struct axe_softc *); 194static void axe_ax88772_init(struct axe_softc *); 195static int axe_get_phyno(struct axe_softc *, int); 196 197static const struct usb_config axe_config[AXE_N_TRANSFER] = { 198 199 [AXE_BULK_DT_WR] = { 200 .type = UE_BULK, 201 .endpoint = UE_ADDR_ANY, 202 .direction = UE_DIR_OUT, 203 .bufsize = AXE_BULK_BUF_SIZE, 204 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 205 .callback = axe_bulk_write_callback, 206 .timeout = 10000, /* 10 seconds */ 207 }, 208 209 [AXE_BULK_DT_RD] = { 210 .type = UE_BULK, 211 .endpoint = UE_ADDR_ANY, 212 .direction = UE_DIR_IN, 213 .bufsize = 16384, /* bytes */ 214 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 215 .callback = axe_bulk_read_callback, 216 .timeout = 0, /* no timeout */ 217 }, 218 219 [AXE_INTR_DT_RD] = { 220 .type = UE_INTERRUPT, 221 .endpoint = UE_ADDR_ANY, 222 .direction = UE_DIR_IN, 223 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 224 .bufsize = 0, /* use wMaxPacketSize */ 225 .callback = axe_intr_callback, 226 }, 227}; 228 229static device_method_t axe_methods[] = { 230 /* Device interface */ 231 DEVMETHOD(device_probe, axe_probe), 232 DEVMETHOD(device_attach, axe_attach), 233 DEVMETHOD(device_detach, axe_detach), 234 235 /* bus interface */ 236 DEVMETHOD(bus_print_child, bus_generic_print_child), 237 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 238 239 /* MII interface */ 240 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 241 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 242 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 243 244 {0, 0} 245}; 246 247static driver_t axe_driver = { 248 .name = "axe", 249 .methods = axe_methods, 250 .size = sizeof(struct axe_softc), 251}; 252 253static devclass_t axe_devclass; 254 255DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 256DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 257MODULE_DEPEND(axe, uether, 1, 1, 1); 258MODULE_DEPEND(axe, usb, 1, 1, 1); 259MODULE_DEPEND(axe, ether, 1, 1, 1); 260MODULE_DEPEND(axe, miibus, 1, 1, 1); 261MODULE_VERSION(axe, 1); 262 263static const struct usb_ether_methods axe_ue_methods = { 264 .ue_attach_post = axe_attach_post, 265 .ue_start = axe_start, 266 .ue_init = axe_init, 267 .ue_stop = axe_stop, 268 .ue_tick = axe_tick, 269 .ue_setmulti = axe_setmulti, 270 .ue_setpromisc = axe_setpromisc, 271 .ue_mii_upd = axe_ifmedia_upd, 272 .ue_mii_sts = axe_ifmedia_sts, 273}; 274 275static int 276axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 277{ 278 struct usb_device_request req; 279 usb_error_t err; 280 281 AXE_LOCK_ASSERT(sc, MA_OWNED); 282 283 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 284 UT_WRITE_VENDOR_DEVICE : 285 UT_READ_VENDOR_DEVICE); 286 req.bRequest = AXE_CMD_CMD(cmd); 287 USETW(req.wValue, val); 288 USETW(req.wIndex, index); 289 USETW(req.wLength, AXE_CMD_LEN(cmd)); 290 291 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 292 293 return (err); 294} 295 296static int 297axe_miibus_readreg(device_t dev, int phy, int reg) 298{ 299 struct axe_softc *sc = device_get_softc(dev); 300 uint16_t val; 301 int locked; 302 303 if (sc->sc_phyno != phy) 304 return (0); 305 306 locked = mtx_owned(&sc->sc_mtx); 307 if (!locked) 308 AXE_LOCK(sc); 309 310 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 311 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 312 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 313 314 val = le16toh(val); 315 if ((sc->sc_flags & AXE_FLAG_772) != 0 && reg == MII_BMSR) { 316 /* 317 * BMSR of AX88772 indicates that it supports extended 318 * capability but the extended status register is 319 * revered for embedded ethernet PHY. So clear the 320 * extended capability bit of BMSR. 321 */ 322 val &= ~BMSR_EXTCAP; 323 } 324 325 if (!locked) 326 AXE_UNLOCK(sc); 327 return (val); 328} 329 330static int 331axe_miibus_writereg(device_t dev, int phy, int reg, int val) 332{ 333 struct axe_softc *sc = device_get_softc(dev); 334 int locked; 335 336 val = htole32(val); 337 338 if (sc->sc_phyno != phy) 339 return (0); 340 341 locked = mtx_owned(&sc->sc_mtx); 342 if (!locked) 343 AXE_LOCK(sc); 344 345 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 346 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 347 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 348 349 if (!locked) 350 AXE_UNLOCK(sc); 351 return (0); 352} 353 354static void 355axe_miibus_statchg(device_t dev) 356{ 357 struct axe_softc *sc = device_get_softc(dev); 358 struct mii_data *mii = GET_MII(sc); 359 struct ifnet *ifp; 360 uint16_t val; 361 int err, locked; 362 363 locked = mtx_owned(&sc->sc_mtx); 364 if (!locked) 365 AXE_LOCK(sc); 366 367 ifp = uether_getifp(&sc->sc_ue); 368 if (mii == NULL || ifp == NULL || 369 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 370 goto done; 371 372 sc->sc_flags &= ~AXE_FLAG_LINK; 373 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 374 (IFM_ACTIVE | IFM_AVALID)) { 375 switch (IFM_SUBTYPE(mii->mii_media_active)) { 376 case IFM_10_T: 377 case IFM_100_TX: 378 sc->sc_flags |= AXE_FLAG_LINK; 379 break; 380 case IFM_1000_T: 381 if ((sc->sc_flags & AXE_FLAG_178) == 0) 382 break; 383 sc->sc_flags |= AXE_FLAG_LINK; 384 break; 385 default: 386 break; 387 } 388 } 389 390 /* Lost link, do nothing. */ 391 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 392 goto done; 393 394 val = 0; 395 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 396 val |= AXE_MEDIA_FULL_DUPLEX; 397 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772)) { 398 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 399 if ((sc->sc_flags & AXE_FLAG_178) != 0) 400 val |= AXE_178_MEDIA_ENCK; 401 switch (IFM_SUBTYPE(mii->mii_media_active)) { 402 case IFM_1000_T: 403 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 404 break; 405 case IFM_100_TX: 406 val |= AXE_178_MEDIA_100TX; 407 break; 408 case IFM_10_T: 409 /* doesn't need to be handled */ 410 break; 411 } 412 } 413 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 414 if (err) 415 device_printf(dev, "media change failed, error %d\n", err); 416done: 417 if (!locked) 418 AXE_UNLOCK(sc); 419} 420 421/* 422 * Set media options. 423 */ 424static int 425axe_ifmedia_upd(struct ifnet *ifp) 426{ 427 struct axe_softc *sc = ifp->if_softc; 428 struct mii_data *mii = GET_MII(sc); 429 int error; 430 431 AXE_LOCK_ASSERT(sc, MA_OWNED); 432 433 if (mii->mii_instance) { 434 struct mii_softc *miisc; 435 436 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 437 mii_phy_reset(miisc); 438 } 439 error = mii_mediachg(mii); 440 return (error); 441} 442 443/* 444 * Report current media status. 445 */ 446static void 447axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 448{ 449 struct axe_softc *sc = ifp->if_softc; 450 struct mii_data *mii = GET_MII(sc); 451 452 AXE_LOCK(sc); 453 mii_pollstat(mii); 454 AXE_UNLOCK(sc); 455 ifmr->ifm_active = mii->mii_media_active; 456 ifmr->ifm_status = mii->mii_media_status; 457} 458 459static void 460axe_setmulti(struct usb_ether *ue) 461{ 462 struct axe_softc *sc = uether_getsc(ue); 463 struct ifnet *ifp = uether_getifp(ue); 464 struct ifmultiaddr *ifma; 465 uint32_t h = 0; 466 uint16_t rxmode; 467 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 468 469 AXE_LOCK_ASSERT(sc, MA_OWNED); 470 471 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 472 rxmode = le16toh(rxmode); 473 474 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 475 rxmode |= AXE_RXCMD_ALLMULTI; 476 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 477 return; 478 } 479 rxmode &= ~AXE_RXCMD_ALLMULTI; 480 481 if_maddr_rlock(ifp); 482 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 483 { 484 if (ifma->ifma_addr->sa_family != AF_LINK) 485 continue; 486 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 487 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 488 hashtbl[h / 8] |= 1 << (h % 8); 489 } 490 if_maddr_runlock(ifp); 491 492 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 493 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 494} 495 496static int 497axe_get_phyno(struct axe_softc *sc, int sel) 498{ 499 int phyno; 500 501 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 502 case PHY_TYPE_100_HOME: 503 case PHY_TYPE_GIG: 504 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 505 break; 506 case PHY_TYPE_SPECIAL: 507 /* FALLTHROUGH */ 508 case PHY_TYPE_RSVD: 509 /* FALLTHROUGH */ 510 case PHY_TYPE_NON_SUP: 511 /* FALLTHROUGH */ 512 default: 513 phyno = -1; 514 break; 515 } 516 517 return (phyno); 518} 519 520#define AXE_GPIO_WRITE(x, y) do { \ 521 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 522 uether_pause(ue, (y)); \ 523} while (0) 524 525static void 526axe_ax88178_init(struct axe_softc *sc) 527{ 528 struct usb_ether *ue; 529 int gpio0, phymode; 530 uint16_t eeprom, val; 531 532 ue = &sc->sc_ue; 533 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 534 /* XXX magic */ 535 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 536 eeprom = le16toh(eeprom); 537 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 538 539 /* if EEPROM is invalid we have to use to GPIO0 */ 540 if (eeprom == 0xffff) { 541 phymode = AXE_PHY_MODE_MARVELL; 542 gpio0 = 1; 543 } else { 544 phymode = eeprom & 0x7f; 545 gpio0 = (eeprom & 0x80) ? 0 : 1; 546 } 547 548 if (bootverbose) 549 device_printf(sc->sc_ue.ue_dev, "EEPROM data : 0x%04x\n", 550 eeprom); 551 /* Program GPIOs depending on PHY hardware. */ 552 switch (phymode) { 553 case AXE_PHY_MODE_MARVELL: 554 if (gpio0 == 1) { 555 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 556 hz / 32); 557 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 558 hz / 32); 559 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 560 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 561 hz / 32); 562 } else 563 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 564 AXE_GPIO1_EN, hz / 32); 565 break; 566 case AXE_PHY_MODE_CICADA: 567 if (gpio0 == 1) 568 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 569 AXE_GPIO0_EN, hz / 32); 570 else 571 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 572 AXE_GPIO1_EN, hz / 32); 573 break; 574 case AXE_PHY_MODE_AGERE: 575 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 576 AXE_GPIO1_EN, hz / 32); 577 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 578 AXE_GPIO2_EN, hz / 32); 579 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 580 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 581 AXE_GPIO2_EN, hz / 32); 582 break; 583 case AXE_PHY_MODE_REALTEK_8211CL: 584 case AXE_PHY_MODE_REALTEK_8211BN: 585 case AXE_PHY_MODE_REALTEK_8251CL: 586 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 587 AXE_GPIO1 | AXE_GPIO1_EN; 588 AXE_GPIO_WRITE(val, hz / 32); 589 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 590 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 591 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 592 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 593 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 594 0x1F, 0x0005); 595 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 596 0x0C, 0x0000); 597 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 598 0x0001); 599 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 600 0x01, val | 0x0080); 601 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 602 0x1F, 0x0000); 603 } 604 break; 605 default: 606 /* Unknown PHY model or no need to program GPIOs. */ 607 break; 608 } 609 610 /* soft reset */ 611 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 612 uether_pause(ue, hz / 4); 613 614 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 615 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 616 uether_pause(ue, hz / 4); 617 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 618 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 619 uether_pause(ue, hz / 4); 620 621 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 622} 623#undef AXE_GPIO_WRITE 624 625static void 626axe_ax88772_init(struct axe_softc *sc) 627{ 628 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 629 uether_pause(&sc->sc_ue, hz / 16); 630 631 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 632 /* ask for the embedded PHY */ 633 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 634 uether_pause(&sc->sc_ue, hz / 64); 635 636 /* power down and reset state, pin reset state */ 637 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 638 AXE_SW_RESET_CLEAR, NULL); 639 uether_pause(&sc->sc_ue, hz / 16); 640 641 /* power down/reset state, pin operating state */ 642 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 643 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 644 uether_pause(&sc->sc_ue, hz / 4); 645 646 /* power up, reset */ 647 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 648 649 /* power up, operating */ 650 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 651 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 652 } else { 653 /* ask for external PHY */ 654 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 655 uether_pause(&sc->sc_ue, hz / 64); 656 657 /* power down internal PHY */ 658 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 659 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 660 } 661 662 uether_pause(&sc->sc_ue, hz / 4); 663 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 664} 665 666static void 667axe_reset(struct axe_softc *sc) 668{ 669 struct usb_config_descriptor *cd; 670 usb_error_t err; 671 672 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 673 674 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 675 cd->bConfigurationValue); 676 if (err) 677 DPRINTF("reset failed (ignored)\n"); 678 679 /* Wait a little while for the chip to get its brains in order. */ 680 uether_pause(&sc->sc_ue, hz / 100); 681} 682 683static void 684axe_attach_post(struct usb_ether *ue) 685{ 686 struct axe_softc *sc = uether_getsc(ue); 687 688 /* 689 * Load PHY indexes first. Needed by axe_xxx_init(). 690 */ 691 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 692 if (bootverbose) 693 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 694 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 695 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 696 if (sc->sc_phyno == -1) 697 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 698 if (sc->sc_phyno == -1) { 699 device_printf(sc->sc_ue.ue_dev, 700 "no valid PHY address found, assuming PHY address 0\n"); 701 sc->sc_phyno = 0; 702 } 703 704 if (sc->sc_flags & AXE_FLAG_178) 705 axe_ax88178_init(sc); 706 else if (sc->sc_flags & AXE_FLAG_772) 707 axe_ax88772_init(sc); 708 709 /* 710 * Get station address. 711 */ 712 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772)) 713 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 714 else 715 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 716 717 /* 718 * Fetch IPG values. 719 */ 720 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 721} 722 723/* 724 * Probe for a AX88172 chip. 725 */ 726static int 727axe_probe(device_t dev) 728{ 729 struct usb_attach_arg *uaa = device_get_ivars(dev); 730 731 if (uaa->usb_mode != USB_MODE_HOST) 732 return (ENXIO); 733 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 734 return (ENXIO); 735 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 736 return (ENXIO); 737 738 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 739} 740 741/* 742 * Attach the interface. Allocate softc structures, do ifmedia 743 * setup and ethernet/BPF attach. 744 */ 745static int 746axe_attach(device_t dev) 747{ 748 struct usb_attach_arg *uaa = device_get_ivars(dev); 749 struct axe_softc *sc = device_get_softc(dev); 750 struct usb_ether *ue = &sc->sc_ue; 751 uint8_t iface_index; 752 int error; 753 754 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 755 756 device_set_usb_desc(dev); 757 758 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 759 760 iface_index = AXE_IFACE_IDX; 761 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 762 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 763 if (error) { 764 device_printf(dev, "allocating USB transfers failed\n"); 765 goto detach; 766 } 767 768 ue->ue_sc = sc; 769 ue->ue_dev = dev; 770 ue->ue_udev = uaa->device; 771 ue->ue_mtx = &sc->sc_mtx; 772 ue->ue_methods = &axe_ue_methods; 773 774 error = uether_ifattach(ue); 775 if (error) { 776 device_printf(dev, "could not attach interface\n"); 777 goto detach; 778 } 779 return (0); /* success */ 780 781detach: 782 axe_detach(dev); 783 return (ENXIO); /* failure */ 784} 785 786static int 787axe_detach(device_t dev) 788{ 789 struct axe_softc *sc = device_get_softc(dev); 790 struct usb_ether *ue = &sc->sc_ue; 791 792 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 793 uether_ifdetach(ue); 794 mtx_destroy(&sc->sc_mtx); 795 796 return (0); 797} 798 799static void 800axe_intr_callback(struct usb_xfer *xfer, usb_error_t error) 801{ 802 switch (USB_GET_STATE(xfer)) { 803 case USB_ST_TRANSFERRED: 804 case USB_ST_SETUP: 805tr_setup: 806 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 807 usbd_transfer_submit(xfer); 808 return; 809 810 default: /* Error */ 811 if (error != USB_ERR_CANCELLED) { 812 /* try to clear stall first */ 813 usbd_xfer_set_stall(xfer); 814 goto tr_setup; 815 } 816 return; 817 } 818} 819 820#if (AXE_BULK_BUF_SIZE >= 0x10000) 821#error "Please update axe_bulk_read_callback()!" 822#endif 823 824static void 825axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 826{ 827 struct axe_softc *sc = usbd_xfer_softc(xfer); 828 struct usb_ether *ue = &sc->sc_ue; 829 struct ifnet *ifp = uether_getifp(ue); 830 struct axe_sframe_hdr hdr; 831 struct usb_page_cache *pc; 832 int err, pos, len; 833 int actlen; 834 835 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 836 837 switch (USB_GET_STATE(xfer)) { 838 case USB_ST_TRANSFERRED: 839 pos = 0; 840 len = 0; 841 err = 0; 842 843 pc = usbd_xfer_get_frame(xfer, 0); 844 if (sc->sc_flags & (AXE_FLAG_772 | AXE_FLAG_178)) { 845 while (pos < actlen) { 846 if ((pos + sizeof(hdr)) > actlen) { 847 /* too little data */ 848 err = EINVAL; 849 break; 850 } 851 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 852 853 if ((hdr.len ^ hdr.ilen) != 0xFFFF) { 854 /* we lost sync */ 855 err = EINVAL; 856 break; 857 } 858 pos += sizeof(hdr); 859 860 len = le16toh(hdr.len); 861 if ((pos + len) > actlen) { 862 /* invalid length */ 863 err = EINVAL; 864 break; 865 } 866 err = uether_rxbuf(ue, pc, pos, len); 867 868 pos += len + (len % 2); 869 } 870 } else { 871 err = uether_rxbuf(ue, pc, 0, actlen); 872 } 873 874 if (err != 0) 875 ifp->if_ierrors++; 876 877 /* FALLTHROUGH */ 878 case USB_ST_SETUP: 879tr_setup: 880 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 881 usbd_transfer_submit(xfer); 882 uether_rxflush(ue); 883 return; 884 885 default: /* Error */ 886 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 887 888 if (error != USB_ERR_CANCELLED) { 889 /* try to clear stall first */ 890 usbd_xfer_set_stall(xfer); 891 goto tr_setup; 892 } 893 return; 894 895 } 896} 897 898#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 899#error "Please update axe_bulk_write_callback()!" 900#endif 901 902static void 903axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 904{ 905 struct axe_softc *sc = usbd_xfer_softc(xfer); 906 struct axe_sframe_hdr hdr; 907 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 908 struct usb_page_cache *pc; 909 struct mbuf *m; 910 int pos; 911 912 switch (USB_GET_STATE(xfer)) { 913 case USB_ST_TRANSFERRED: 914 DPRINTFN(11, "transfer complete\n"); 915 ifp->if_opackets++; 916 /* FALLTHROUGH */ 917 case USB_ST_SETUP: 918tr_setup: 919 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 920 /* 921 * don't send anything if there is no link ! 922 */ 923 return; 924 } 925 pos = 0; 926 pc = usbd_xfer_get_frame(xfer, 0); 927 928 while (1) { 929 930 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 931 932 if (m == NULL) { 933 if (pos > 0) 934 break; /* send out data */ 935 return; 936 } 937 if (m->m_pkthdr.len > MCLBYTES) { 938 m->m_pkthdr.len = MCLBYTES; 939 } 940 if (sc->sc_flags & (AXE_FLAG_772 | AXE_FLAG_178)) { 941 942 hdr.len = htole16(m->m_pkthdr.len); 943 hdr.ilen = ~hdr.len; 944 945 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 946 947 pos += sizeof(hdr); 948 949 /* 950 * NOTE: Some drivers force a short packet 951 * by appending a dummy header with zero 952 * length at then end of the USB transfer. 953 * This driver uses the 954 * USB_FORCE_SHORT_XFER flag instead. 955 */ 956 } 957 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 958 pos += m->m_pkthdr.len; 959 960 /* 961 * if there's a BPF listener, bounce a copy 962 * of this frame to him: 963 */ 964 BPF_MTAP(ifp, m); 965 966 m_freem(m); 967 968 if (sc->sc_flags & (AXE_FLAG_772 | AXE_FLAG_178)) { 969 if (pos > (AXE_BULK_BUF_SIZE - MCLBYTES - sizeof(hdr))) { 970 /* send out frame(s) */ 971 break; 972 } 973 } else { 974 /* send out frame */ 975 break; 976 } 977 } 978 979 usbd_xfer_set_frame_len(xfer, 0, pos); 980 usbd_transfer_submit(xfer); 981 return; 982 983 default: /* Error */ 984 DPRINTFN(11, "transfer error, %s\n", 985 usbd_errstr(error)); 986 987 ifp->if_oerrors++; 988 989 if (error != USB_ERR_CANCELLED) { 990 /* try to clear stall first */ 991 usbd_xfer_set_stall(xfer); 992 goto tr_setup; 993 } 994 return; 995 996 } 997} 998 999static void 1000axe_tick(struct usb_ether *ue) 1001{ 1002 struct axe_softc *sc = uether_getsc(ue); 1003 struct mii_data *mii = GET_MII(sc); 1004 1005 AXE_LOCK_ASSERT(sc, MA_OWNED); 1006 1007 mii_tick(mii); 1008 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1009 axe_miibus_statchg(ue->ue_dev); 1010 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1011 axe_start(ue); 1012 } 1013} 1014 1015static void 1016axe_start(struct usb_ether *ue) 1017{ 1018 struct axe_softc *sc = uether_getsc(ue); 1019 1020 /* 1021 * start the USB transfers, if not already started: 1022 */ 1023 usbd_transfer_start(sc->sc_xfer[AXE_INTR_DT_RD]); 1024 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1025 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1026} 1027 1028static void 1029axe_init(struct usb_ether *ue) 1030{ 1031 struct axe_softc *sc = uether_getsc(ue); 1032 struct ifnet *ifp = uether_getifp(ue); 1033 uint16_t rxmode; 1034 1035 AXE_LOCK_ASSERT(sc, MA_OWNED); 1036 1037 /* Cancel pending I/O */ 1038 axe_stop(ue); 1039 1040 /* Set MAC address. */ 1041 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772)) 1042 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1043 else 1044 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1045 1046 /* Set transmitter IPG values */ 1047 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772)) { 1048 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1049 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1050 } else { 1051 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1052 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1053 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1054 } 1055 1056 /* Enable receiver, set RX mode */ 1057 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1058 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772)) { 1059#if 0 1060 rxmode |= AXE_178_RXCMD_MFB_2048; /* chip default */ 1061#else 1062 /* 1063 * Default Rx buffer size is too small to get 1064 * maximum performance. 1065 */ 1066 rxmode |= AXE_178_RXCMD_MFB_16384; 1067#endif 1068 } else { 1069 rxmode |= AXE_172_RXCMD_UNICAST; 1070 } 1071 1072 /* If we want promiscuous mode, set the allframes bit. */ 1073 if (ifp->if_flags & IFF_PROMISC) 1074 rxmode |= AXE_RXCMD_PROMISC; 1075 1076 if (ifp->if_flags & IFF_BROADCAST) 1077 rxmode |= AXE_RXCMD_BROADCAST; 1078 1079 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1080 1081 /* Load the multicast filter. */ 1082 axe_setmulti(ue); 1083 1084 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1085 1086 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1087 axe_start(ue); 1088} 1089 1090static void 1091axe_setpromisc(struct usb_ether *ue) 1092{ 1093 struct axe_softc *sc = uether_getsc(ue); 1094 struct ifnet *ifp = uether_getifp(ue); 1095 uint16_t rxmode; 1096 1097 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1098 1099 rxmode = le16toh(rxmode); 1100 1101 if (ifp->if_flags & IFF_PROMISC) { 1102 rxmode |= AXE_RXCMD_PROMISC; 1103 } else { 1104 rxmode &= ~AXE_RXCMD_PROMISC; 1105 } 1106 1107 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1108 1109 axe_setmulti(ue); 1110} 1111 1112static void 1113axe_stop(struct usb_ether *ue) 1114{ 1115 struct axe_softc *sc = uether_getsc(ue); 1116 struct ifnet *ifp = uether_getifp(ue); 1117 1118 AXE_LOCK_ASSERT(sc, MA_OWNED); 1119 1120 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1121 sc->sc_flags &= ~AXE_FLAG_LINK; 1122 1123 /* 1124 * stop all the transfers, if not already stopped: 1125 */ 1126 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1127 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1128 usbd_transfer_stop(sc->sc_xfer[AXE_INTR_DT_RD]); 1129 1130 axe_reset(sc); 1131} 1132