if_axe.c revision 221407
1/*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 221407 2011-05-03 19:51:29Z marius $"); 35 36/* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51/* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70/* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79#include <sys/stdint.h> 80#include <sys/stddef.h> 81#include <sys/param.h> 82#include <sys/queue.h> 83#include <sys/types.h> 84#include <sys/systm.h> 85#include <sys/kernel.h> 86#include <sys/bus.h> 87#include <sys/module.h> 88#include <sys/lock.h> 89#include <sys/mutex.h> 90#include <sys/condvar.h> 91#include <sys/sysctl.h> 92#include <sys/sx.h> 93#include <sys/unistd.h> 94#include <sys/callout.h> 95#include <sys/malloc.h> 96#include <sys/priv.h> 97 98#include <dev/usb/usb.h> 99#include <dev/usb/usbdi.h> 100#include <dev/usb/usbdi_util.h> 101#include "usbdevs.h" 102 103#define USB_DEBUG_VAR axe_debug 104#include <dev/usb/usb_debug.h> 105#include <dev/usb/usb_process.h> 106 107#include <dev/usb/net/usb_ethernet.h> 108#include <dev/usb/net/if_axereg.h> 109 110/* 111 * AXE_178_MAX_FRAME_BURST 112 * max frame burst size for Ax88178 and Ax88772 113 * 0 2048 bytes 114 * 1 4096 bytes 115 * 2 8192 bytes 116 * 3 16384 bytes 117 * use the largest your system can handle without USB stalling. 118 * 119 * NB: 88772 parts appear to generate lots of input errors with 120 * a 2K rx buffer and 8K is only slightly faster than 4K on an 121 * EHCI port on a T42 so change at your own risk. 122 */ 123#define AXE_178_MAX_FRAME_BURST 1 124 125#ifdef USB_DEBUG 126static int axe_debug = 0; 127 128SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 129SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0, 130 "Debug level"); 131#endif 132 133/* 134 * Various supported device vendors/products. 135 */ 136static const struct usb_device_id axe_devs[] = { 137#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 138 AXE_DEV(ABOCOM, UF200, 0), 139 AXE_DEV(ACERCM, EP1427X2, 0), 140 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 141 AXE_DEV(ASIX, AX88172, 0), 142 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 143 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 144 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 145 AXE_DEV(ATEN, UC210T, 0), 146 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 147 AXE_DEV(BILLIONTON, USB2AR, 0), 148 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 149 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 150 AXE_DEV(DLINK, DUBE100, 0), 151 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 152 AXE_DEV(GOODWAY, GWUSB2E, 0), 153 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 154 AXE_DEV(JVC, MP_PRX1, 0), 155 AXE_DEV(LINKSYS2, USB200M, 0), 156 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 157 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 158 AXE_DEV(MELCO, LUAU2KTX, 0), 159 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 160 AXE_DEV(NETGEAR, FA120, 0), 161 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 162 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 163 AXE_DEV(SITECOM, LN029, 0), 164 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 165 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 166#undef AXE_DEV 167}; 168 169static device_probe_t axe_probe; 170static device_attach_t axe_attach; 171static device_detach_t axe_detach; 172 173static usb_callback_t axe_bulk_read_callback; 174static usb_callback_t axe_bulk_write_callback; 175 176static miibus_readreg_t axe_miibus_readreg; 177static miibus_writereg_t axe_miibus_writereg; 178static miibus_statchg_t axe_miibus_statchg; 179 180static uether_fn_t axe_attach_post; 181static uether_fn_t axe_init; 182static uether_fn_t axe_stop; 183static uether_fn_t axe_start; 184static uether_fn_t axe_tick; 185static uether_fn_t axe_setmulti; 186static uether_fn_t axe_setpromisc; 187 188static int axe_ifmedia_upd(struct ifnet *); 189static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 190static int axe_cmd(struct axe_softc *, int, int, int, void *); 191static void axe_ax88178_init(struct axe_softc *); 192static void axe_ax88772_init(struct axe_softc *); 193static void axe_ax88772a_init(struct axe_softc *); 194static int axe_get_phyno(struct axe_softc *, int); 195 196static const struct usb_config axe_config[AXE_N_TRANSFER] = { 197 198 [AXE_BULK_DT_WR] = { 199 .type = UE_BULK, 200 .endpoint = UE_ADDR_ANY, 201 .direction = UE_DIR_OUT, 202 .frames = 16, 203 .bufsize = 16 * MCLBYTES, 204 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 205 .callback = axe_bulk_write_callback, 206 .timeout = 10000, /* 10 seconds */ 207 }, 208 209 [AXE_BULK_DT_RD] = { 210 .type = UE_BULK, 211 .endpoint = UE_ADDR_ANY, 212 .direction = UE_DIR_IN, 213 .bufsize = 16384, /* bytes */ 214 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 215 .callback = axe_bulk_read_callback, 216 .timeout = 0, /* no timeout */ 217 }, 218}; 219 220static device_method_t axe_methods[] = { 221 /* Device interface */ 222 DEVMETHOD(device_probe, axe_probe), 223 DEVMETHOD(device_attach, axe_attach), 224 DEVMETHOD(device_detach, axe_detach), 225 226 /* bus interface */ 227 DEVMETHOD(bus_print_child, bus_generic_print_child), 228 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 232 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 233 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 234 235 {0, 0} 236}; 237 238static driver_t axe_driver = { 239 .name = "axe", 240 .methods = axe_methods, 241 .size = sizeof(struct axe_softc), 242}; 243 244static devclass_t axe_devclass; 245 246DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 247DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 248MODULE_DEPEND(axe, uether, 1, 1, 1); 249MODULE_DEPEND(axe, usb, 1, 1, 1); 250MODULE_DEPEND(axe, ether, 1, 1, 1); 251MODULE_DEPEND(axe, miibus, 1, 1, 1); 252MODULE_VERSION(axe, 1); 253 254static const struct usb_ether_methods axe_ue_methods = { 255 .ue_attach_post = axe_attach_post, 256 .ue_start = axe_start, 257 .ue_init = axe_init, 258 .ue_stop = axe_stop, 259 .ue_tick = axe_tick, 260 .ue_setmulti = axe_setmulti, 261 .ue_setpromisc = axe_setpromisc, 262 .ue_mii_upd = axe_ifmedia_upd, 263 .ue_mii_sts = axe_ifmedia_sts, 264}; 265 266static int 267axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 268{ 269 struct usb_device_request req; 270 usb_error_t err; 271 272 AXE_LOCK_ASSERT(sc, MA_OWNED); 273 274 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 275 UT_WRITE_VENDOR_DEVICE : 276 UT_READ_VENDOR_DEVICE); 277 req.bRequest = AXE_CMD_CMD(cmd); 278 USETW(req.wValue, val); 279 USETW(req.wIndex, index); 280 USETW(req.wLength, AXE_CMD_LEN(cmd)); 281 282 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 283 284 return (err); 285} 286 287static int 288axe_miibus_readreg(device_t dev, int phy, int reg) 289{ 290 struct axe_softc *sc = device_get_softc(dev); 291 uint16_t val; 292 int locked; 293 294 if (sc->sc_phyno != phy) 295 return (0); 296 297 locked = mtx_owned(&sc->sc_mtx); 298 if (!locked) 299 AXE_LOCK(sc); 300 301 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 302 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 303 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 304 305 val = le16toh(val); 306 if (AXE_IS_772(sc) && reg == MII_BMSR) { 307 /* 308 * BMSR of AX88772 indicates that it supports extended 309 * capability but the extended status register is 310 * revered for embedded ethernet PHY. So clear the 311 * extended capability bit of BMSR. 312 */ 313 val &= ~BMSR_EXTCAP; 314 } 315 316 if (!locked) 317 AXE_UNLOCK(sc); 318 return (val); 319} 320 321static int 322axe_miibus_writereg(device_t dev, int phy, int reg, int val) 323{ 324 struct axe_softc *sc = device_get_softc(dev); 325 int locked; 326 327 val = htole32(val); 328 329 if (sc->sc_phyno != phy) 330 return (0); 331 332 locked = mtx_owned(&sc->sc_mtx); 333 if (!locked) 334 AXE_LOCK(sc); 335 336 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 337 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 339 340 if (!locked) 341 AXE_UNLOCK(sc); 342 return (0); 343} 344 345static void 346axe_miibus_statchg(device_t dev) 347{ 348 struct axe_softc *sc = device_get_softc(dev); 349 struct mii_data *mii = GET_MII(sc); 350 struct ifnet *ifp; 351 uint16_t val; 352 int err, locked; 353 354 locked = mtx_owned(&sc->sc_mtx); 355 if (!locked) 356 AXE_LOCK(sc); 357 358 ifp = uether_getifp(&sc->sc_ue); 359 if (mii == NULL || ifp == NULL || 360 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 361 goto done; 362 363 sc->sc_flags &= ~AXE_FLAG_LINK; 364 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 365 (IFM_ACTIVE | IFM_AVALID)) { 366 switch (IFM_SUBTYPE(mii->mii_media_active)) { 367 case IFM_10_T: 368 case IFM_100_TX: 369 sc->sc_flags |= AXE_FLAG_LINK; 370 break; 371 case IFM_1000_T: 372 if ((sc->sc_flags & AXE_FLAG_178) == 0) 373 break; 374 sc->sc_flags |= AXE_FLAG_LINK; 375 break; 376 default: 377 break; 378 } 379 } 380 381 /* Lost link, do nothing. */ 382 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 383 goto done; 384 385 val = 0; 386 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 387 val |= AXE_MEDIA_FULL_DUPLEX; 388 if (AXE_IS_178_FAMILY(sc)) { 389 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 390 if ((sc->sc_flags & AXE_FLAG_178) != 0) 391 val |= AXE_178_MEDIA_ENCK; 392 switch (IFM_SUBTYPE(mii->mii_media_active)) { 393 case IFM_1000_T: 394 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 395 break; 396 case IFM_100_TX: 397 val |= AXE_178_MEDIA_100TX; 398 break; 399 case IFM_10_T: 400 /* doesn't need to be handled */ 401 break; 402 } 403 } 404 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 405 if (err) 406 device_printf(dev, "media change failed, error %d\n", err); 407done: 408 if (!locked) 409 AXE_UNLOCK(sc); 410} 411 412/* 413 * Set media options. 414 */ 415static int 416axe_ifmedia_upd(struct ifnet *ifp) 417{ 418 struct axe_softc *sc = ifp->if_softc; 419 struct mii_data *mii = GET_MII(sc); 420 struct mii_softc *miisc; 421 int error; 422 423 AXE_LOCK_ASSERT(sc, MA_OWNED); 424 425 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 426 PHY_RESET(miisc); 427 error = mii_mediachg(mii); 428 return (error); 429} 430 431/* 432 * Report current media status. 433 */ 434static void 435axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 436{ 437 struct axe_softc *sc = ifp->if_softc; 438 struct mii_data *mii = GET_MII(sc); 439 440 AXE_LOCK(sc); 441 mii_pollstat(mii); 442 AXE_UNLOCK(sc); 443 ifmr->ifm_active = mii->mii_media_active; 444 ifmr->ifm_status = mii->mii_media_status; 445} 446 447static void 448axe_setmulti(struct usb_ether *ue) 449{ 450 struct axe_softc *sc = uether_getsc(ue); 451 struct ifnet *ifp = uether_getifp(ue); 452 struct ifmultiaddr *ifma; 453 uint32_t h = 0; 454 uint16_t rxmode; 455 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 456 457 AXE_LOCK_ASSERT(sc, MA_OWNED); 458 459 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 460 rxmode = le16toh(rxmode); 461 462 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 463 rxmode |= AXE_RXCMD_ALLMULTI; 464 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 465 return; 466 } 467 rxmode &= ~AXE_RXCMD_ALLMULTI; 468 469 if_maddr_rlock(ifp); 470 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 471 { 472 if (ifma->ifma_addr->sa_family != AF_LINK) 473 continue; 474 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 475 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 476 hashtbl[h / 8] |= 1 << (h % 8); 477 } 478 if_maddr_runlock(ifp); 479 480 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 481 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 482} 483 484static int 485axe_get_phyno(struct axe_softc *sc, int sel) 486{ 487 int phyno; 488 489 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 490 case PHY_TYPE_100_HOME: 491 case PHY_TYPE_GIG: 492 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 493 break; 494 case PHY_TYPE_SPECIAL: 495 /* FALLTHROUGH */ 496 case PHY_TYPE_RSVD: 497 /* FALLTHROUGH */ 498 case PHY_TYPE_NON_SUP: 499 /* FALLTHROUGH */ 500 default: 501 phyno = -1; 502 break; 503 } 504 505 return (phyno); 506} 507 508#define AXE_GPIO_WRITE(x, y) do { \ 509 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 510 uether_pause(ue, (y)); \ 511} while (0) 512 513static void 514axe_ax88178_init(struct axe_softc *sc) 515{ 516 struct usb_ether *ue; 517 int gpio0, phymode; 518 uint16_t eeprom, val; 519 520 ue = &sc->sc_ue; 521 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 522 /* XXX magic */ 523 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 524 eeprom = le16toh(eeprom); 525 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 526 527 /* if EEPROM is invalid we have to use to GPIO0 */ 528 if (eeprom == 0xffff) { 529 phymode = AXE_PHY_MODE_MARVELL; 530 gpio0 = 1; 531 } else { 532 phymode = eeprom & 0x7f; 533 gpio0 = (eeprom & 0x80) ? 0 : 1; 534 } 535 536 if (bootverbose) 537 device_printf(sc->sc_ue.ue_dev, 538 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 539 phymode); 540 /* Program GPIOs depending on PHY hardware. */ 541 switch (phymode) { 542 case AXE_PHY_MODE_MARVELL: 543 if (gpio0 == 1) { 544 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 545 hz / 32); 546 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 547 hz / 32); 548 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 549 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 550 hz / 32); 551 } else 552 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 553 AXE_GPIO1_EN, hz / 32); 554 break; 555 case AXE_PHY_MODE_CICADA: 556 case AXE_PHY_MODE_CICADA_V2: 557 case AXE_PHY_MODE_CICADA_V2_ASIX: 558 if (gpio0 == 1) 559 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 560 AXE_GPIO0_EN, hz / 32); 561 else 562 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 563 AXE_GPIO1_EN, hz / 32); 564 break; 565 case AXE_PHY_MODE_AGERE: 566 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 567 AXE_GPIO1_EN, hz / 32); 568 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 569 AXE_GPIO2_EN, hz / 32); 570 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 571 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 572 AXE_GPIO2_EN, hz / 32); 573 break; 574 case AXE_PHY_MODE_REALTEK_8211CL: 575 case AXE_PHY_MODE_REALTEK_8211BN: 576 case AXE_PHY_MODE_REALTEK_8251CL: 577 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 578 AXE_GPIO1 | AXE_GPIO1_EN; 579 AXE_GPIO_WRITE(val, hz / 32); 580 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 581 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 582 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 583 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 584 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 585 0x1F, 0x0005); 586 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 587 0x0C, 0x0000); 588 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 589 0x0001); 590 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 591 0x01, val | 0x0080); 592 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 593 0x1F, 0x0000); 594 } 595 break; 596 default: 597 /* Unknown PHY model or no need to program GPIOs. */ 598 break; 599 } 600 601 /* soft reset */ 602 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 603 uether_pause(ue, hz / 4); 604 605 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 606 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 607 uether_pause(ue, hz / 4); 608 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 609 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 610 uether_pause(ue, hz / 4); 611 612 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 613} 614 615static void 616axe_ax88772_init(struct axe_softc *sc) 617{ 618 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 619 uether_pause(&sc->sc_ue, hz / 16); 620 621 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 622 /* ask for the embedded PHY */ 623 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 624 uether_pause(&sc->sc_ue, hz / 64); 625 626 /* power down and reset state, pin reset state */ 627 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 628 AXE_SW_RESET_CLEAR, NULL); 629 uether_pause(&sc->sc_ue, hz / 16); 630 631 /* power down/reset state, pin operating state */ 632 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 633 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 634 uether_pause(&sc->sc_ue, hz / 4); 635 636 /* power up, reset */ 637 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 638 639 /* power up, operating */ 640 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 641 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 642 } else { 643 /* ask for external PHY */ 644 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 645 uether_pause(&sc->sc_ue, hz / 64); 646 647 /* power down internal PHY */ 648 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 649 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 650 } 651 652 uether_pause(&sc->sc_ue, hz / 4); 653 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 654} 655 656static void 657axe_ax88772a_init(struct axe_softc *sc) 658{ 659 struct usb_ether *ue; 660 uint16_t eeprom; 661 662 ue = &sc->sc_ue; 663 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 664 eeprom = le16toh(eeprom); 665 /* Reload EEPROM. */ 666 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 667 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 668 /* Manually select internal(embedded) PHY - MAC mode. */ 669 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 670 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 671 NULL); 672 uether_pause(&sc->sc_ue, hz / 32); 673 } else { 674 /* 675 * Manually select external PHY - MAC mode. 676 * Reverse MII/RMII is for AX88772A PHY mode. 677 */ 678 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 679 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 680 uether_pause(&sc->sc_ue, hz / 32); 681 } 682 /* Take PHY out of power down. */ 683 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 684 AXE_SW_RESET_IPRL, NULL); 685 uether_pause(&sc->sc_ue, hz / 4); 686 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 687 uether_pause(&sc->sc_ue, hz); 688 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 689 uether_pause(&sc->sc_ue, hz / 32); 690 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 691 uether_pause(&sc->sc_ue, hz / 32); 692 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 693} 694 695#undef AXE_GPIO_WRITE 696 697static void 698axe_reset(struct axe_softc *sc) 699{ 700 struct usb_config_descriptor *cd; 701 usb_error_t err; 702 703 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 704 705 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 706 cd->bConfigurationValue); 707 if (err) 708 DPRINTF("reset failed (ignored)\n"); 709 710 /* Wait a little while for the chip to get its brains in order. */ 711 uether_pause(&sc->sc_ue, hz / 100); 712 713 /* Reinitialize controller to achieve full reset. */ 714 if (sc->sc_flags & AXE_FLAG_178) 715 axe_ax88178_init(sc); 716 else if (sc->sc_flags & AXE_FLAG_772) 717 axe_ax88772_init(sc); 718 else if (sc->sc_flags & AXE_FLAG_772A) 719 axe_ax88772a_init(sc); 720} 721 722static void 723axe_attach_post(struct usb_ether *ue) 724{ 725 struct axe_softc *sc = uether_getsc(ue); 726 727 /* 728 * Load PHY indexes first. Needed by axe_xxx_init(). 729 */ 730 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 731 if (bootverbose) 732 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 733 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 734 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 735 if (sc->sc_phyno == -1) 736 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 737 if (sc->sc_phyno == -1) { 738 device_printf(sc->sc_ue.ue_dev, 739 "no valid PHY address found, assuming PHY address 0\n"); 740 sc->sc_phyno = 0; 741 } 742 743 if (sc->sc_flags & AXE_FLAG_178) { 744 axe_ax88178_init(sc); 745 sc->sc_tx_bufsz = 16 * 1024; 746 } else if (sc->sc_flags & AXE_FLAG_772) { 747 axe_ax88772_init(sc); 748 sc->sc_tx_bufsz = 8 * 1024; 749 } else if (sc->sc_flags & AXE_FLAG_772A) { 750 axe_ax88772a_init(sc); 751 sc->sc_tx_bufsz = 8 * 1024; 752 } 753 754 /* 755 * Get station address. 756 */ 757 if (AXE_IS_178_FAMILY(sc)) 758 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 759 else 760 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 761 762 /* 763 * Fetch IPG values. 764 */ 765 if (sc->sc_flags & AXE_FLAG_772A) { 766 /* Set IPG values. */ 767 sc->sc_ipgs[0] = 0x15; 768 sc->sc_ipgs[1] = 0x16; 769 sc->sc_ipgs[2] = 0x1A; 770 } else 771 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 772} 773 774/* 775 * Probe for a AX88172 chip. 776 */ 777static int 778axe_probe(device_t dev) 779{ 780 struct usb_attach_arg *uaa = device_get_ivars(dev); 781 782 if (uaa->usb_mode != USB_MODE_HOST) 783 return (ENXIO); 784 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 785 return (ENXIO); 786 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 787 return (ENXIO); 788 789 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 790} 791 792/* 793 * Attach the interface. Allocate softc structures, do ifmedia 794 * setup and ethernet/BPF attach. 795 */ 796static int 797axe_attach(device_t dev) 798{ 799 struct usb_attach_arg *uaa = device_get_ivars(dev); 800 struct axe_softc *sc = device_get_softc(dev); 801 struct usb_ether *ue = &sc->sc_ue; 802 uint8_t iface_index; 803 int error; 804 805 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 806 807 device_set_usb_desc(dev); 808 809 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 810 811 iface_index = AXE_IFACE_IDX; 812 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 813 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 814 if (error) { 815 device_printf(dev, "allocating USB transfers failed\n"); 816 goto detach; 817 } 818 819 ue->ue_sc = sc; 820 ue->ue_dev = dev; 821 ue->ue_udev = uaa->device; 822 ue->ue_mtx = &sc->sc_mtx; 823 ue->ue_methods = &axe_ue_methods; 824 825 error = uether_ifattach(ue); 826 if (error) { 827 device_printf(dev, "could not attach interface\n"); 828 goto detach; 829 } 830 return (0); /* success */ 831 832detach: 833 axe_detach(dev); 834 return (ENXIO); /* failure */ 835} 836 837static int 838axe_detach(device_t dev) 839{ 840 struct axe_softc *sc = device_get_softc(dev); 841 struct usb_ether *ue = &sc->sc_ue; 842 843 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 844 uether_ifdetach(ue); 845 mtx_destroy(&sc->sc_mtx); 846 847 return (0); 848} 849 850#if (AXE_BULK_BUF_SIZE >= 0x10000) 851#error "Please update axe_bulk_read_callback()!" 852#endif 853 854static void 855axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 856{ 857 struct axe_softc *sc = usbd_xfer_softc(xfer); 858 struct usb_ether *ue = &sc->sc_ue; 859 struct ifnet *ifp = uether_getifp(ue); 860 struct axe_sframe_hdr hdr; 861 struct usb_page_cache *pc; 862 int err, pos, len; 863 int actlen; 864 865 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 866 867 switch (USB_GET_STATE(xfer)) { 868 case USB_ST_TRANSFERRED: 869 pos = 0; 870 len = 0; 871 err = 0; 872 873 pc = usbd_xfer_get_frame(xfer, 0); 874 if (AXE_IS_178_FAMILY(sc)) { 875 while (pos < actlen) { 876 if ((pos + sizeof(hdr)) > actlen) { 877 /* too little data */ 878 err = EINVAL; 879 break; 880 } 881 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 882 883 if ((hdr.len ^ hdr.ilen) != 0xFFFF) { 884 /* we lost sync */ 885 err = EINVAL; 886 break; 887 } 888 pos += sizeof(hdr); 889 890 len = le16toh(hdr.len); 891 if ((pos + len) > actlen) { 892 /* invalid length */ 893 err = EINVAL; 894 break; 895 } 896 uether_rxbuf(ue, pc, pos, len); 897 898 pos += len + (len % 2); 899 } 900 } else 901 uether_rxbuf(ue, pc, 0, actlen); 902 903 if (err != 0) 904 ifp->if_ierrors++; 905 906 /* FALLTHROUGH */ 907 case USB_ST_SETUP: 908tr_setup: 909 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 910 usbd_transfer_submit(xfer); 911 uether_rxflush(ue); 912 return; 913 914 default: /* Error */ 915 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 916 917 if (error != USB_ERR_CANCELLED) { 918 /* try to clear stall first */ 919 usbd_xfer_set_stall(xfer); 920 goto tr_setup; 921 } 922 return; 923 924 } 925} 926 927#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 928#error "Please update axe_bulk_write_callback()!" 929#endif 930 931static void 932axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 933{ 934 struct axe_softc *sc = usbd_xfer_softc(xfer); 935 struct axe_sframe_hdr hdr; 936 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 937 struct usb_page_cache *pc; 938 struct mbuf *m; 939 int nframes, pos; 940 941 switch (USB_GET_STATE(xfer)) { 942 case USB_ST_TRANSFERRED: 943 DPRINTFN(11, "transfer complete\n"); 944 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 945 /* FALLTHROUGH */ 946 case USB_ST_SETUP: 947tr_setup: 948 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 949 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 950 /* 951 * Don't send anything if there is no link or 952 * controller is busy. 953 */ 954 return; 955 } 956 957 for (nframes = 0; nframes < 16 && 958 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 959 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 960 if (m == NULL) 961 break; 962 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 963 nframes); 964 pos = 0; 965 pc = usbd_xfer_get_frame(xfer, nframes); 966 if (AXE_IS_178_FAMILY(sc)) { 967 hdr.len = htole16(m->m_pkthdr.len); 968 hdr.ilen = ~hdr.len; 969 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 970 pos += sizeof(hdr); 971 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 972 pos += m->m_pkthdr.len; 973 if ((pos % 512) == 0) { 974 hdr.len = 0; 975 hdr.ilen = 0xffff; 976 usbd_copy_in(pc, pos, &hdr, 977 sizeof(hdr)); 978 pos += sizeof(hdr); 979 } 980 } else { 981 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 982 pos += m->m_pkthdr.len; 983 } 984 985 /* 986 * XXX 987 * Update TX packet counter here. This is not 988 * correct way but it seems that there is no way 989 * to know how many packets are sent at the end 990 * of transfer because controller combines 991 * multiple writes into single one if there is 992 * room in TX buffer of controller. 993 */ 994 ifp->if_opackets++; 995 996 /* 997 * if there's a BPF listener, bounce a copy 998 * of this frame to him: 999 */ 1000 BPF_MTAP(ifp, m); 1001 1002 m_freem(m); 1003 1004 /* Set frame length. */ 1005 usbd_xfer_set_frame_len(xfer, nframes, pos); 1006 } 1007 if (nframes != 0) { 1008 usbd_xfer_set_frames(xfer, nframes); 1009 usbd_transfer_submit(xfer); 1010 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1011 } 1012 return; 1013 /* NOTREACHED */ 1014 default: /* Error */ 1015 DPRINTFN(11, "transfer error, %s\n", 1016 usbd_errstr(error)); 1017 1018 ifp->if_oerrors++; 1019 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1020 1021 if (error != USB_ERR_CANCELLED) { 1022 /* try to clear stall first */ 1023 usbd_xfer_set_stall(xfer); 1024 goto tr_setup; 1025 } 1026 return; 1027 1028 } 1029} 1030 1031static void 1032axe_tick(struct usb_ether *ue) 1033{ 1034 struct axe_softc *sc = uether_getsc(ue); 1035 struct mii_data *mii = GET_MII(sc); 1036 1037 AXE_LOCK_ASSERT(sc, MA_OWNED); 1038 1039 mii_tick(mii); 1040 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1041 axe_miibus_statchg(ue->ue_dev); 1042 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1043 axe_start(ue); 1044 } 1045} 1046 1047static void 1048axe_start(struct usb_ether *ue) 1049{ 1050 struct axe_softc *sc = uether_getsc(ue); 1051 1052 /* 1053 * start the USB transfers, if not already started: 1054 */ 1055 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1056 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1057} 1058 1059static void 1060axe_init(struct usb_ether *ue) 1061{ 1062 struct axe_softc *sc = uether_getsc(ue); 1063 struct ifnet *ifp = uether_getifp(ue); 1064 uint16_t rxmode; 1065 1066 AXE_LOCK_ASSERT(sc, MA_OWNED); 1067 1068 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1069 return; 1070 1071 /* Cancel pending I/O */ 1072 axe_stop(ue); 1073 1074 axe_reset(sc); 1075 1076 /* Set MAC address. */ 1077 if (AXE_IS_178_FAMILY(sc)) 1078 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1079 else 1080 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1081 1082 /* Set transmitter IPG values */ 1083 if (AXE_IS_178_FAMILY(sc)) 1084 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1085 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1086 else { 1087 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1088 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1089 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1090 } 1091 1092 /* Enable receiver, set RX mode */ 1093 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1094 if (AXE_IS_178_FAMILY(sc)) { 1095#if 0 1096 rxmode |= AXE_178_RXCMD_MFB_2048; /* chip default */ 1097#else 1098 /* 1099 * Default Rx buffer size is too small to get 1100 * maximum performance. 1101 */ 1102 rxmode |= AXE_178_RXCMD_MFB_16384; 1103#endif 1104 } else { 1105 rxmode |= AXE_172_RXCMD_UNICAST; 1106 } 1107 1108 /* If we want promiscuous mode, set the allframes bit. */ 1109 if (ifp->if_flags & IFF_PROMISC) 1110 rxmode |= AXE_RXCMD_PROMISC; 1111 1112 if (ifp->if_flags & IFF_BROADCAST) 1113 rxmode |= AXE_RXCMD_BROADCAST; 1114 1115 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1116 1117 /* Load the multicast filter. */ 1118 axe_setmulti(ue); 1119 1120 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1121 1122 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1123 /* Switch to selected media. */ 1124 axe_ifmedia_upd(ifp); 1125 axe_start(ue); 1126} 1127 1128static void 1129axe_setpromisc(struct usb_ether *ue) 1130{ 1131 struct axe_softc *sc = uether_getsc(ue); 1132 struct ifnet *ifp = uether_getifp(ue); 1133 uint16_t rxmode; 1134 1135 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1136 1137 rxmode = le16toh(rxmode); 1138 1139 if (ifp->if_flags & IFF_PROMISC) { 1140 rxmode |= AXE_RXCMD_PROMISC; 1141 } else { 1142 rxmode &= ~AXE_RXCMD_PROMISC; 1143 } 1144 1145 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1146 1147 axe_setmulti(ue); 1148} 1149 1150static void 1151axe_stop(struct usb_ether *ue) 1152{ 1153 struct axe_softc *sc = uether_getsc(ue); 1154 struct ifnet *ifp = uether_getifp(ue); 1155 1156 AXE_LOCK_ASSERT(sc, MA_OWNED); 1157 1158 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1159 sc->sc_flags &= ~AXE_FLAG_LINK; 1160 1161 /* 1162 * stop all the transfers, if not already stopped: 1163 */ 1164 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1165 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1166} 1167