if_axe.c revision 215969
1/*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 215969 2010-11-28 01:56:44Z yongari $"); 35 36/* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51/* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70/* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79#include <sys/stdint.h> 80#include <sys/stddef.h> 81#include <sys/param.h> 82#include <sys/queue.h> 83#include <sys/types.h> 84#include <sys/systm.h> 85#include <sys/kernel.h> 86#include <sys/bus.h> 87#include <sys/linker_set.h> 88#include <sys/module.h> 89#include <sys/lock.h> 90#include <sys/mutex.h> 91#include <sys/condvar.h> 92#include <sys/sysctl.h> 93#include <sys/sx.h> 94#include <sys/unistd.h> 95#include <sys/callout.h> 96#include <sys/malloc.h> 97#include <sys/priv.h> 98 99#include <dev/usb/usb.h> 100#include <dev/usb/usbdi.h> 101#include <dev/usb/usbdi_util.h> 102#include "usbdevs.h" 103 104#define USB_DEBUG_VAR axe_debug 105#include <dev/usb/usb_debug.h> 106#include <dev/usb/usb_process.h> 107 108#include <dev/usb/net/usb_ethernet.h> 109#include <dev/usb/net/if_axereg.h> 110 111/* 112 * AXE_178_MAX_FRAME_BURST 113 * max frame burst size for Ax88178 and Ax88772 114 * 0 2048 bytes 115 * 1 4096 bytes 116 * 2 8192 bytes 117 * 3 16384 bytes 118 * use the largest your system can handle without USB stalling. 119 * 120 * NB: 88772 parts appear to generate lots of input errors with 121 * a 2K rx buffer and 8K is only slightly faster than 4K on an 122 * EHCI port on a T42 so change at your own risk. 123 */ 124#define AXE_178_MAX_FRAME_BURST 1 125 126#ifdef USB_DEBUG 127static int axe_debug = 0; 128 129SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 130SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0, 131 "Debug level"); 132#endif 133 134/* 135 * Various supported device vendors/products. 136 */ 137static const struct usb_device_id axe_devs[] = { 138#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 139 AXE_DEV(ABOCOM, UF200, 0), 140 AXE_DEV(ACERCM, EP1427X2, 0), 141 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 142 AXE_DEV(ASIX, AX88172, 0), 143 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 144 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 145 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 146 AXE_DEV(ATEN, UC210T, 0), 147 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 148 AXE_DEV(BILLIONTON, USB2AR, 0), 149 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 150 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 151 AXE_DEV(DLINK, DUBE100, 0), 152 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 153 AXE_DEV(GOODWAY, GWUSB2E, 0), 154 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 155 AXE_DEV(JVC, MP_PRX1, 0), 156 AXE_DEV(LINKSYS2, USB200M, 0), 157 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 158 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 159 AXE_DEV(MELCO, LUAU2KTX, 0), 160 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 161 AXE_DEV(NETGEAR, FA120, 0), 162 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 163 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 164 AXE_DEV(SITECOM, LN029, 0), 165 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 166 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 167#undef AXE_DEV 168}; 169 170static device_probe_t axe_probe; 171static device_attach_t axe_attach; 172static device_detach_t axe_detach; 173 174static usb_callback_t axe_bulk_read_callback; 175static usb_callback_t axe_bulk_write_callback; 176 177static miibus_readreg_t axe_miibus_readreg; 178static miibus_writereg_t axe_miibus_writereg; 179static miibus_statchg_t axe_miibus_statchg; 180 181static uether_fn_t axe_attach_post; 182static uether_fn_t axe_init; 183static uether_fn_t axe_stop; 184static uether_fn_t axe_start; 185static uether_fn_t axe_tick; 186static uether_fn_t axe_setmulti; 187static uether_fn_t axe_setpromisc; 188 189static int axe_ifmedia_upd(struct ifnet *); 190static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191static int axe_cmd(struct axe_softc *, int, int, int, void *); 192static void axe_ax88178_init(struct axe_softc *); 193static void axe_ax88772_init(struct axe_softc *); 194static void axe_ax88772a_init(struct axe_softc *); 195static int axe_get_phyno(struct axe_softc *, int); 196 197static const struct usb_config axe_config[AXE_N_TRANSFER] = { 198 199 [AXE_BULK_DT_WR] = { 200 .type = UE_BULK, 201 .endpoint = UE_ADDR_ANY, 202 .direction = UE_DIR_OUT, 203 .bufsize = AXE_BULK_BUF_SIZE, 204 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 205 .callback = axe_bulk_write_callback, 206 .timeout = 10000, /* 10 seconds */ 207 }, 208 209 [AXE_BULK_DT_RD] = { 210 .type = UE_BULK, 211 .endpoint = UE_ADDR_ANY, 212 .direction = UE_DIR_IN, 213 .bufsize = 16384, /* bytes */ 214 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 215 .callback = axe_bulk_read_callback, 216 .timeout = 0, /* no timeout */ 217 }, 218}; 219 220static device_method_t axe_methods[] = { 221 /* Device interface */ 222 DEVMETHOD(device_probe, axe_probe), 223 DEVMETHOD(device_attach, axe_attach), 224 DEVMETHOD(device_detach, axe_detach), 225 226 /* bus interface */ 227 DEVMETHOD(bus_print_child, bus_generic_print_child), 228 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 232 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 233 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 234 235 {0, 0} 236}; 237 238static driver_t axe_driver = { 239 .name = "axe", 240 .methods = axe_methods, 241 .size = sizeof(struct axe_softc), 242}; 243 244static devclass_t axe_devclass; 245 246DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 247DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 248MODULE_DEPEND(axe, uether, 1, 1, 1); 249MODULE_DEPEND(axe, usb, 1, 1, 1); 250MODULE_DEPEND(axe, ether, 1, 1, 1); 251MODULE_DEPEND(axe, miibus, 1, 1, 1); 252MODULE_VERSION(axe, 1); 253 254static const struct usb_ether_methods axe_ue_methods = { 255 .ue_attach_post = axe_attach_post, 256 .ue_start = axe_start, 257 .ue_init = axe_init, 258 .ue_stop = axe_stop, 259 .ue_tick = axe_tick, 260 .ue_setmulti = axe_setmulti, 261 .ue_setpromisc = axe_setpromisc, 262 .ue_mii_upd = axe_ifmedia_upd, 263 .ue_mii_sts = axe_ifmedia_sts, 264}; 265 266static int 267axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 268{ 269 struct usb_device_request req; 270 usb_error_t err; 271 272 AXE_LOCK_ASSERT(sc, MA_OWNED); 273 274 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 275 UT_WRITE_VENDOR_DEVICE : 276 UT_READ_VENDOR_DEVICE); 277 req.bRequest = AXE_CMD_CMD(cmd); 278 USETW(req.wValue, val); 279 USETW(req.wIndex, index); 280 USETW(req.wLength, AXE_CMD_LEN(cmd)); 281 282 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 283 284 return (err); 285} 286 287static int 288axe_miibus_readreg(device_t dev, int phy, int reg) 289{ 290 struct axe_softc *sc = device_get_softc(dev); 291 uint16_t val; 292 int locked; 293 294 if (sc->sc_phyno != phy) 295 return (0); 296 297 locked = mtx_owned(&sc->sc_mtx); 298 if (!locked) 299 AXE_LOCK(sc); 300 301 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 302 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 303 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 304 305 val = le16toh(val); 306 if (AXE_IS_772(sc) && reg == MII_BMSR) { 307 /* 308 * BMSR of AX88772 indicates that it supports extended 309 * capability but the extended status register is 310 * revered for embedded ethernet PHY. So clear the 311 * extended capability bit of BMSR. 312 */ 313 val &= ~BMSR_EXTCAP; 314 } 315 316 if (!locked) 317 AXE_UNLOCK(sc); 318 return (val); 319} 320 321static int 322axe_miibus_writereg(device_t dev, int phy, int reg, int val) 323{ 324 struct axe_softc *sc = device_get_softc(dev); 325 int locked; 326 327 val = htole32(val); 328 329 if (sc->sc_phyno != phy) 330 return (0); 331 332 locked = mtx_owned(&sc->sc_mtx); 333 if (!locked) 334 AXE_LOCK(sc); 335 336 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 337 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 339 340 if (!locked) 341 AXE_UNLOCK(sc); 342 return (0); 343} 344 345static void 346axe_miibus_statchg(device_t dev) 347{ 348 struct axe_softc *sc = device_get_softc(dev); 349 struct mii_data *mii = GET_MII(sc); 350 struct ifnet *ifp; 351 uint16_t val; 352 int err, locked; 353 354 locked = mtx_owned(&sc->sc_mtx); 355 if (!locked) 356 AXE_LOCK(sc); 357 358 ifp = uether_getifp(&sc->sc_ue); 359 if (mii == NULL || ifp == NULL || 360 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 361 goto done; 362 363 sc->sc_flags &= ~AXE_FLAG_LINK; 364 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 365 (IFM_ACTIVE | IFM_AVALID)) { 366 switch (IFM_SUBTYPE(mii->mii_media_active)) { 367 case IFM_10_T: 368 case IFM_100_TX: 369 sc->sc_flags |= AXE_FLAG_LINK; 370 break; 371 case IFM_1000_T: 372 if ((sc->sc_flags & AXE_FLAG_178) == 0) 373 break; 374 sc->sc_flags |= AXE_FLAG_LINK; 375 break; 376 default: 377 break; 378 } 379 } 380 381 /* Lost link, do nothing. */ 382 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 383 goto done; 384 385 val = 0; 386 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 387 val |= AXE_MEDIA_FULL_DUPLEX; 388 if (AXE_IS_178_FAMILY(sc)) { 389 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 390 if ((sc->sc_flags & AXE_FLAG_178) != 0) 391 val |= AXE_178_MEDIA_ENCK; 392 switch (IFM_SUBTYPE(mii->mii_media_active)) { 393 case IFM_1000_T: 394 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 395 break; 396 case IFM_100_TX: 397 val |= AXE_178_MEDIA_100TX; 398 break; 399 case IFM_10_T: 400 /* doesn't need to be handled */ 401 break; 402 } 403 } 404 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 405 if (err) 406 device_printf(dev, "media change failed, error %d\n", err); 407done: 408 if (!locked) 409 AXE_UNLOCK(sc); 410} 411 412/* 413 * Set media options. 414 */ 415static int 416axe_ifmedia_upd(struct ifnet *ifp) 417{ 418 struct axe_softc *sc = ifp->if_softc; 419 struct mii_data *mii = GET_MII(sc); 420 int error; 421 422 AXE_LOCK_ASSERT(sc, MA_OWNED); 423 424 if (mii->mii_instance) { 425 struct mii_softc *miisc; 426 427 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 428 mii_phy_reset(miisc); 429 } 430 error = mii_mediachg(mii); 431 return (error); 432} 433 434/* 435 * Report current media status. 436 */ 437static void 438axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 439{ 440 struct axe_softc *sc = ifp->if_softc; 441 struct mii_data *mii = GET_MII(sc); 442 443 AXE_LOCK(sc); 444 mii_pollstat(mii); 445 AXE_UNLOCK(sc); 446 ifmr->ifm_active = mii->mii_media_active; 447 ifmr->ifm_status = mii->mii_media_status; 448} 449 450static void 451axe_setmulti(struct usb_ether *ue) 452{ 453 struct axe_softc *sc = uether_getsc(ue); 454 struct ifnet *ifp = uether_getifp(ue); 455 struct ifmultiaddr *ifma; 456 uint32_t h = 0; 457 uint16_t rxmode; 458 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 459 460 AXE_LOCK_ASSERT(sc, MA_OWNED); 461 462 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 463 rxmode = le16toh(rxmode); 464 465 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 466 rxmode |= AXE_RXCMD_ALLMULTI; 467 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 468 return; 469 } 470 rxmode &= ~AXE_RXCMD_ALLMULTI; 471 472 if_maddr_rlock(ifp); 473 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 474 { 475 if (ifma->ifma_addr->sa_family != AF_LINK) 476 continue; 477 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 478 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 479 hashtbl[h / 8] |= 1 << (h % 8); 480 } 481 if_maddr_runlock(ifp); 482 483 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 484 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 485} 486 487static int 488axe_get_phyno(struct axe_softc *sc, int sel) 489{ 490 int phyno; 491 492 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 493 case PHY_TYPE_100_HOME: 494 case PHY_TYPE_GIG: 495 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 496 break; 497 case PHY_TYPE_SPECIAL: 498 /* FALLTHROUGH */ 499 case PHY_TYPE_RSVD: 500 /* FALLTHROUGH */ 501 case PHY_TYPE_NON_SUP: 502 /* FALLTHROUGH */ 503 default: 504 phyno = -1; 505 break; 506 } 507 508 return (phyno); 509} 510 511#define AXE_GPIO_WRITE(x, y) do { \ 512 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 513 uether_pause(ue, (y)); \ 514} while (0) 515 516static void 517axe_ax88178_init(struct axe_softc *sc) 518{ 519 struct usb_ether *ue; 520 int gpio0, phymode; 521 uint16_t eeprom, val; 522 523 ue = &sc->sc_ue; 524 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 525 /* XXX magic */ 526 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 527 eeprom = le16toh(eeprom); 528 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 529 530 /* if EEPROM is invalid we have to use to GPIO0 */ 531 if (eeprom == 0xffff) { 532 phymode = AXE_PHY_MODE_MARVELL; 533 gpio0 = 1; 534 } else { 535 phymode = eeprom & 0x7f; 536 gpio0 = (eeprom & 0x80) ? 0 : 1; 537 } 538 539 if (bootverbose) 540 device_printf(sc->sc_ue.ue_dev, 541 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 542 phymode); 543 /* Program GPIOs depending on PHY hardware. */ 544 switch (phymode) { 545 case AXE_PHY_MODE_MARVELL: 546 if (gpio0 == 1) { 547 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 548 hz / 32); 549 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 550 hz / 32); 551 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 552 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 553 hz / 32); 554 } else 555 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 556 AXE_GPIO1_EN, hz / 32); 557 break; 558 case AXE_PHY_MODE_CICADA: 559 case AXE_PHY_MODE_CICADA_V2: 560 case AXE_PHY_MODE_CICADA_V2_ASIX: 561 if (gpio0 == 1) 562 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 563 AXE_GPIO0_EN, hz / 32); 564 else 565 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 566 AXE_GPIO1_EN, hz / 32); 567 break; 568 case AXE_PHY_MODE_AGERE: 569 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 570 AXE_GPIO1_EN, hz / 32); 571 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 572 AXE_GPIO2_EN, hz / 32); 573 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 574 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 575 AXE_GPIO2_EN, hz / 32); 576 break; 577 case AXE_PHY_MODE_REALTEK_8211CL: 578 case AXE_PHY_MODE_REALTEK_8211BN: 579 case AXE_PHY_MODE_REALTEK_8251CL: 580 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 581 AXE_GPIO1 | AXE_GPIO1_EN; 582 AXE_GPIO_WRITE(val, hz / 32); 583 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 584 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 585 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 586 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 587 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 588 0x1F, 0x0005); 589 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 590 0x0C, 0x0000); 591 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 592 0x0001); 593 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 594 0x01, val | 0x0080); 595 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 596 0x1F, 0x0000); 597 } 598 break; 599 default: 600 /* Unknown PHY model or no need to program GPIOs. */ 601 break; 602 } 603 604 /* soft reset */ 605 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 606 uether_pause(ue, hz / 4); 607 608 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 609 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 610 uether_pause(ue, hz / 4); 611 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 612 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 613 uether_pause(ue, hz / 4); 614 615 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 616} 617 618static void 619axe_ax88772_init(struct axe_softc *sc) 620{ 621 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 622 uether_pause(&sc->sc_ue, hz / 16); 623 624 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 625 /* ask for the embedded PHY */ 626 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 627 uether_pause(&sc->sc_ue, hz / 64); 628 629 /* power down and reset state, pin reset state */ 630 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 631 AXE_SW_RESET_CLEAR, NULL); 632 uether_pause(&sc->sc_ue, hz / 16); 633 634 /* power down/reset state, pin operating state */ 635 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 636 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 637 uether_pause(&sc->sc_ue, hz / 4); 638 639 /* power up, reset */ 640 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 641 642 /* power up, operating */ 643 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 644 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 645 } else { 646 /* ask for external PHY */ 647 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 648 uether_pause(&sc->sc_ue, hz / 64); 649 650 /* power down internal PHY */ 651 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 652 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 653 } 654 655 uether_pause(&sc->sc_ue, hz / 4); 656 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 657} 658 659static void 660axe_ax88772a_init(struct axe_softc *sc) 661{ 662 struct usb_ether *ue; 663 uint16_t eeprom; 664 665 ue = &sc->sc_ue; 666 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 667 eeprom = le16toh(eeprom); 668 /* Reload EEPROM. */ 669 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 670 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 671 /* Manually select internal(embedded) PHY - MAC mode. */ 672 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 673 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 674 NULL); 675 uether_pause(&sc->sc_ue, hz / 32); 676 } else { 677 /* 678 * Manually select external PHY - MAC mode. 679 * Reverse MII/RMII is for AX88772A PHY mode. 680 */ 681 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 682 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 683 uether_pause(&sc->sc_ue, hz / 32); 684 } 685 /* Take PHY out of power down. */ 686 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 687 AXE_SW_RESET_IPRL, NULL); 688 uether_pause(&sc->sc_ue, hz / 4); 689 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 690 uether_pause(&sc->sc_ue, hz); 691 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 692 uether_pause(&sc->sc_ue, hz / 32); 693 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 694 uether_pause(&sc->sc_ue, hz / 32); 695 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 696} 697 698#undef AXE_GPIO_WRITE 699 700static void 701axe_reset(struct axe_softc *sc) 702{ 703 struct usb_config_descriptor *cd; 704 usb_error_t err; 705 706 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 707 708 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 709 cd->bConfigurationValue); 710 if (err) 711 DPRINTF("reset failed (ignored)\n"); 712 713 /* Wait a little while for the chip to get its brains in order. */ 714 uether_pause(&sc->sc_ue, hz / 100); 715 716 /* Reinitialize controller to achieve full reset. */ 717 if (sc->sc_flags & AXE_FLAG_178) 718 axe_ax88178_init(sc); 719 else if (sc->sc_flags & AXE_FLAG_772) 720 axe_ax88772_init(sc); 721 else if (sc->sc_flags & AXE_FLAG_772A) 722 axe_ax88772a_init(sc); 723} 724 725static void 726axe_attach_post(struct usb_ether *ue) 727{ 728 struct axe_softc *sc = uether_getsc(ue); 729 730 /* 731 * Load PHY indexes first. Needed by axe_xxx_init(). 732 */ 733 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 734 if (bootverbose) 735 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 736 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 737 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 738 if (sc->sc_phyno == -1) 739 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 740 if (sc->sc_phyno == -1) { 741 device_printf(sc->sc_ue.ue_dev, 742 "no valid PHY address found, assuming PHY address 0\n"); 743 sc->sc_phyno = 0; 744 } 745 746 if (sc->sc_flags & AXE_FLAG_178) { 747 axe_ax88178_init(sc); 748 sc->sc_tx_bufsz = 16 * 1024; 749 } else if (sc->sc_flags & AXE_FLAG_772) { 750 axe_ax88772_init(sc); 751 sc->sc_tx_bufsz = 8 * 1024; 752 } else if (sc->sc_flags & AXE_FLAG_772A) { 753 axe_ax88772a_init(sc); 754 sc->sc_tx_bufsz = 8 * 1024; 755 } 756 757 /* 758 * Get station address. 759 */ 760 if (AXE_IS_178_FAMILY(sc)) 761 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 762 else 763 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 764 765 /* 766 * Fetch IPG values. 767 */ 768 if (sc->sc_flags & AXE_FLAG_772A) { 769 /* Set IPG values. */ 770 sc->sc_ipgs[0] = 0x15; 771 sc->sc_ipgs[1] = 0x16; 772 sc->sc_ipgs[2] = 0x1A; 773 } else 774 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 775} 776 777/* 778 * Probe for a AX88172 chip. 779 */ 780static int 781axe_probe(device_t dev) 782{ 783 struct usb_attach_arg *uaa = device_get_ivars(dev); 784 785 if (uaa->usb_mode != USB_MODE_HOST) 786 return (ENXIO); 787 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 788 return (ENXIO); 789 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 790 return (ENXIO); 791 792 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 793} 794 795/* 796 * Attach the interface. Allocate softc structures, do ifmedia 797 * setup and ethernet/BPF attach. 798 */ 799static int 800axe_attach(device_t dev) 801{ 802 struct usb_attach_arg *uaa = device_get_ivars(dev); 803 struct axe_softc *sc = device_get_softc(dev); 804 struct usb_ether *ue = &sc->sc_ue; 805 uint8_t iface_index; 806 int error; 807 808 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 809 810 device_set_usb_desc(dev); 811 812 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 813 814 iface_index = AXE_IFACE_IDX; 815 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 816 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 817 if (error) { 818 device_printf(dev, "allocating USB transfers failed\n"); 819 goto detach; 820 } 821 822 ue->ue_sc = sc; 823 ue->ue_dev = dev; 824 ue->ue_udev = uaa->device; 825 ue->ue_mtx = &sc->sc_mtx; 826 ue->ue_methods = &axe_ue_methods; 827 828 error = uether_ifattach(ue); 829 if (error) { 830 device_printf(dev, "could not attach interface\n"); 831 goto detach; 832 } 833 return (0); /* success */ 834 835detach: 836 axe_detach(dev); 837 return (ENXIO); /* failure */ 838} 839 840static int 841axe_detach(device_t dev) 842{ 843 struct axe_softc *sc = device_get_softc(dev); 844 struct usb_ether *ue = &sc->sc_ue; 845 846 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 847 uether_ifdetach(ue); 848 mtx_destroy(&sc->sc_mtx); 849 850 return (0); 851} 852 853#if (AXE_BULK_BUF_SIZE >= 0x10000) 854#error "Please update axe_bulk_read_callback()!" 855#endif 856 857static void 858axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 859{ 860 struct axe_softc *sc = usbd_xfer_softc(xfer); 861 struct usb_ether *ue = &sc->sc_ue; 862 struct ifnet *ifp = uether_getifp(ue); 863 struct axe_sframe_hdr hdr; 864 struct usb_page_cache *pc; 865 int err, pos, len; 866 int actlen; 867 868 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 869 870 switch (USB_GET_STATE(xfer)) { 871 case USB_ST_TRANSFERRED: 872 pos = 0; 873 len = 0; 874 err = 0; 875 876 pc = usbd_xfer_get_frame(xfer, 0); 877 if (AXE_IS_178_FAMILY(sc)) { 878 while (pos < actlen) { 879 if ((pos + sizeof(hdr)) > actlen) { 880 /* too little data */ 881 err = EINVAL; 882 break; 883 } 884 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 885 886 if ((hdr.len ^ hdr.ilen) != 0xFFFF) { 887 /* we lost sync */ 888 err = EINVAL; 889 break; 890 } 891 pos += sizeof(hdr); 892 893 len = le16toh(hdr.len); 894 if ((pos + len) > actlen) { 895 /* invalid length */ 896 err = EINVAL; 897 break; 898 } 899 uether_rxbuf(ue, pc, pos, len); 900 901 pos += len + (len % 2); 902 } 903 } else 904 uether_rxbuf(ue, pc, 0, actlen); 905 906 if (err != 0) 907 ifp->if_ierrors++; 908 909 /* FALLTHROUGH */ 910 case USB_ST_SETUP: 911tr_setup: 912 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 913 usbd_transfer_submit(xfer); 914 uether_rxflush(ue); 915 return; 916 917 default: /* Error */ 918 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 919 920 if (error != USB_ERR_CANCELLED) { 921 /* try to clear stall first */ 922 usbd_xfer_set_stall(xfer); 923 goto tr_setup; 924 } 925 return; 926 927 } 928} 929 930#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 931#error "Please update axe_bulk_write_callback()!" 932#endif 933 934static void 935axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 936{ 937 struct axe_softc *sc = usbd_xfer_softc(xfer); 938 struct axe_sframe_hdr hdr; 939 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 940 struct usb_page_cache *pc; 941 struct mbuf *m; 942 int pos; 943 944 switch (USB_GET_STATE(xfer)) { 945 case USB_ST_TRANSFERRED: 946 DPRINTFN(11, "transfer complete\n"); 947 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 948 /* FALLTHROUGH */ 949 case USB_ST_SETUP: 950tr_setup: 951 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 952 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 953 /* 954 * Don't send anything if there is no link or 955 * controller is busy. 956 */ 957 return; 958 } 959 pos = 0; 960 pc = usbd_xfer_get_frame(xfer, 0); 961 962 while (1) { 963 964 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 965 966 if (m == NULL) { 967 if (pos > 0) 968 break; /* send out data */ 969 return; 970 } 971 if (m->m_pkthdr.len > MCLBYTES) { 972 m->m_pkthdr.len = MCLBYTES; 973 } 974 if (AXE_IS_178_FAMILY(sc)) { 975 976 hdr.len = htole16(m->m_pkthdr.len); 977 hdr.ilen = ~hdr.len; 978 979 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 980 981 pos += sizeof(hdr); 982 983 /* 984 * NOTE: Some drivers force a short packet 985 * by appending a dummy header with zero 986 * length at then end of the USB transfer. 987 * This driver uses the 988 * USB_FORCE_SHORT_XFER flag instead. 989 */ 990 } 991 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 992 pos += m->m_pkthdr.len; 993 994 /* 995 * XXX 996 * Update TX packet counter here. This is not 997 * correct way but it seems that there is no way 998 * to know how many packets are sent at the end 999 * of transfer because controller combines 1000 * multiple writes into single one if there is 1001 * room in TX buffer of controller. 1002 */ 1003 ifp->if_opackets++; 1004 1005 /* 1006 * if there's a BPF listener, bounce a copy 1007 * of this frame to him: 1008 */ 1009 BPF_MTAP(ifp, m); 1010 1011 m_freem(m); 1012 1013 if (AXE_IS_178_FAMILY(sc)) { 1014 if (pos > (AXE_BULK_BUF_SIZE - MCLBYTES - sizeof(hdr))) { 1015 /* send out frame(s) */ 1016 break; 1017 } 1018 } else { 1019 /* send out frame */ 1020 break; 1021 } 1022 } 1023 1024 usbd_xfer_set_frame_len(xfer, 0, pos); 1025 usbd_transfer_submit(xfer); 1026 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1027 return; 1028 1029 default: /* Error */ 1030 DPRINTFN(11, "transfer error, %s\n", 1031 usbd_errstr(error)); 1032 1033 ifp->if_oerrors++; 1034 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1035 1036 if (error != USB_ERR_CANCELLED) { 1037 /* try to clear stall first */ 1038 usbd_xfer_set_stall(xfer); 1039 goto tr_setup; 1040 } 1041 return; 1042 1043 } 1044} 1045 1046static void 1047axe_tick(struct usb_ether *ue) 1048{ 1049 struct axe_softc *sc = uether_getsc(ue); 1050 struct mii_data *mii = GET_MII(sc); 1051 1052 AXE_LOCK_ASSERT(sc, MA_OWNED); 1053 1054 mii_tick(mii); 1055 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1056 axe_miibus_statchg(ue->ue_dev); 1057 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1058 axe_start(ue); 1059 } 1060} 1061 1062static void 1063axe_start(struct usb_ether *ue) 1064{ 1065 struct axe_softc *sc = uether_getsc(ue); 1066 1067 /* 1068 * start the USB transfers, if not already started: 1069 */ 1070 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1071 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1072} 1073 1074static void 1075axe_init(struct usb_ether *ue) 1076{ 1077 struct axe_softc *sc = uether_getsc(ue); 1078 struct ifnet *ifp = uether_getifp(ue); 1079 uint16_t rxmode; 1080 1081 AXE_LOCK_ASSERT(sc, MA_OWNED); 1082 1083 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1084 return; 1085 1086 /* Cancel pending I/O */ 1087 axe_stop(ue); 1088 1089 axe_reset(sc); 1090 1091 /* Set MAC address. */ 1092 if (AXE_IS_178_FAMILY(sc)) 1093 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1094 else 1095 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1096 1097 /* Set transmitter IPG values */ 1098 if (AXE_IS_178_FAMILY(sc)) 1099 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1100 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1101 else { 1102 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1103 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1104 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1105 } 1106 1107 /* Enable receiver, set RX mode */ 1108 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1109 if (AXE_IS_178_FAMILY(sc)) { 1110#if 0 1111 rxmode |= AXE_178_RXCMD_MFB_2048; /* chip default */ 1112#else 1113 /* 1114 * Default Rx buffer size is too small to get 1115 * maximum performance. 1116 */ 1117 rxmode |= AXE_178_RXCMD_MFB_16384; 1118#endif 1119 } else { 1120 rxmode |= AXE_172_RXCMD_UNICAST; 1121 } 1122 1123 /* If we want promiscuous mode, set the allframes bit. */ 1124 if (ifp->if_flags & IFF_PROMISC) 1125 rxmode |= AXE_RXCMD_PROMISC; 1126 1127 if (ifp->if_flags & IFF_BROADCAST) 1128 rxmode |= AXE_RXCMD_BROADCAST; 1129 1130 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1131 1132 /* Load the multicast filter. */ 1133 axe_setmulti(ue); 1134 1135 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1136 1137 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1138 /* Switch to selected media. */ 1139 axe_ifmedia_upd(ifp); 1140 axe_start(ue); 1141} 1142 1143static void 1144axe_setpromisc(struct usb_ether *ue) 1145{ 1146 struct axe_softc *sc = uether_getsc(ue); 1147 struct ifnet *ifp = uether_getifp(ue); 1148 uint16_t rxmode; 1149 1150 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1151 1152 rxmode = le16toh(rxmode); 1153 1154 if (ifp->if_flags & IFF_PROMISC) { 1155 rxmode |= AXE_RXCMD_PROMISC; 1156 } else { 1157 rxmode &= ~AXE_RXCMD_PROMISC; 1158 } 1159 1160 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1161 1162 axe_setmulti(ue); 1163} 1164 1165static void 1166axe_stop(struct usb_ether *ue) 1167{ 1168 struct axe_softc *sc = uether_getsc(ue); 1169 struct ifnet *ifp = uether_getifp(ue); 1170 1171 AXE_LOCK_ASSERT(sc, MA_OWNED); 1172 1173 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1174 sc->sc_flags &= ~AXE_FLAG_LINK; 1175 1176 /* 1177 * stop all the transfers, if not already stopped: 1178 */ 1179 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1180 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1181} 1182