1213379Shselasky/* $FreeBSD$ */ 2213379Shselasky 3213379Shselasky/*- 4213379Shselasky * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5213379Shselasky * 6213379Shselasky * Redistribution and use in source and binary forms, with or without 7213379Shselasky * modification, are permitted provided that the following conditions 8213379Shselasky * are met: 9213379Shselasky * 1. Redistributions of source code must retain the above copyright 10213379Shselasky * notice, this list of conditions and the following disclaimer. 11213379Shselasky * 2. Redistributions in binary form must reproduce the above copyright 12213379Shselasky * notice, this list of conditions and the following disclaimer in the 13213379Shselasky * documentation and/or other materials provided with the distribution. 14213379Shselasky * 15213379Shselasky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16213379Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17213379Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18213379Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19213379Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20213379Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21213379Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22213379Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23213379Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24213379Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25213379Shselasky * SUCH DAMAGE. 26213379Shselasky */ 27213379Shselasky 28213379Shselasky#ifndef _XHCI_H_ 29213379Shselasky#define _XHCI_H_ 30213379Shselasky 31213379Shselasky#define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 32213379Shselasky#define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 33213379Shselasky#define XHCI_MAX_SCRATCHPADS 32 34213379Shselasky#define XHCI_MAX_EVENTS (16 * 13) 35213379Shselasky#define XHCI_MAX_COMMANDS (16 * 1) 36213379Shselasky#define XHCI_MAX_RSEG 1 37213379Shselasky#define XHCI_MAX_TRANSFERS 4 38239214Shselasky#if USB_MAX_EP_STREAMS == 8 39239214Shselasky#define XHCI_MAX_STREAMS 8 40239214Shselasky#define XHCI_MAX_STREAMS_LOG 3 41239214Shselasky#elif USB_MAX_EP_STREAMS == 1 42239214Shselasky#define XHCI_MAX_STREAMS 1 43239214Shselasky#define XHCI_MAX_STREAMS_LOG 0 44239214Shselasky#else 45239214Shselasky#error "The USB_MAX_EP_STREAMS value is not supported." 46239214Shselasky#endif 47213379Shselasky#define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 48213379Shselasky#define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 49213379Shselasky#define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 50213379Shselasky#define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 51213379Shselasky#define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 52213379Shselasky#define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 53213379Shselasky#define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 54213379Shselasky#define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 55213379Shselasky#define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 56213379Shselasky#define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 57213379Shselasky#define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 58213379Shselasky#define XHCI_TRB_ALIGN 16 /* bytes */ 59213379Shselasky#define XHCI_TD_ALIGN 64 /* bytes */ 60213379Shselasky#define XHCI_PAGE_SIZE 4096 /* bytes */ 61213379Shselasky 62213379Shselaskystruct xhci_dev_ctx_addr { 63213379Shselasky volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1]; 64213379Shselasky struct { 65213379Shselasky volatile uint64_t dummy; 66213379Shselasky } __aligned(64) padding; 67213379Shselasky volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]; 68213379Shselasky}; 69213379Shselasky 70213379Shselasky#define XHCI_EPNO2EPID(x) \ 71213379Shselasky ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR))) 72213379Shselasky 73213379Shselaskystruct xhci_slot_ctx { 74213379Shselasky volatile uint32_t dwSctx0; 75213379Shselasky#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 76213379Shselasky#define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 77213379Shselasky#define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 78213379Shselasky#define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 79213379Shselasky#define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 80213379Shselasky#define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 81213379Shselasky#define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 82213379Shselasky#define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 83213379Shselasky#define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 84213379Shselasky#define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 85213379Shselasky volatile uint32_t dwSctx1; 86213379Shselasky#define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 87213379Shselasky#define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 88213379Shselasky#define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 89213379Shselasky#define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 90213379Shselasky#define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 91213379Shselasky#define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 92213379Shselasky volatile uint32_t dwSctx2; 93213379Shselasky#define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 94213379Shselasky#define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 95213379Shselasky#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 96213379Shselasky#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 97213379Shselasky#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 98213379Shselasky#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 99213379Shselasky#define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 100213379Shselasky#define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 101213379Shselasky volatile uint32_t dwSctx3; 102213379Shselasky#define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 103213379Shselasky#define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 104213379Shselasky#define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 105213379Shselasky#define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 106213379Shselasky volatile uint32_t dwSctx4; 107213379Shselasky volatile uint32_t dwSctx5; 108213379Shselasky volatile uint32_t dwSctx6; 109213379Shselasky volatile uint32_t dwSctx7; 110213379Shselasky}; 111213379Shselasky 112213379Shselaskystruct xhci_endp_ctx { 113213379Shselasky volatile uint32_t dwEpCtx0; 114213379Shselasky#define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 115213379Shselasky#define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 116213379Shselasky#define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 117213379Shselasky#define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 118213379Shselasky#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 119213379Shselasky#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 120213379Shselasky#define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 121213379Shselasky#define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 122213379Shselasky#define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 123213379Shselasky#define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 124213379Shselasky volatile uint32_t dwEpCtx1; 125213379Shselasky#define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 126213379Shselasky#define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 127213379Shselasky#define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 128213379Shselasky#define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 129213379Shselasky#define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 130213379Shselasky#define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 131213379Shselasky#define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 132213379Shselasky#define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 133213379Shselasky#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 134213379Shselasky#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 135213379Shselasky volatile uint64_t qwEpCtx2; 136213379Shselasky#define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 137213379Shselasky#define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 138213379Shselasky#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 139213379Shselasky volatile uint32_t dwEpCtx4; 140213379Shselasky#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 141213379Shselasky#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 142213379Shselasky#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 143213379Shselasky#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 144213379Shselasky volatile uint32_t dwEpCtx5; 145213379Shselasky volatile uint32_t dwEpCtx6; 146213379Shselasky volatile uint32_t dwEpCtx7; 147213379Shselasky}; 148213379Shselasky 149213379Shselaskystruct xhci_input_ctx { 150213379Shselasky#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 151213379Shselasky volatile uint32_t dwInCtx0; 152213379Shselasky#define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 153213379Shselasky volatile uint32_t dwInCtx1; 154213379Shselasky#define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 155213379Shselasky volatile uint32_t dwInCtx2; 156213379Shselasky volatile uint32_t dwInCtx3; 157213379Shselasky volatile uint32_t dwInCtx4; 158213379Shselasky volatile uint32_t dwInCtx5; 159213379Shselasky volatile uint32_t dwInCtx6; 160213379Shselasky volatile uint32_t dwInCtx7; 161213379Shselasky}; 162213379Shselasky 163213379Shselaskystruct xhci_input_dev_ctx { 164213379Shselasky struct xhci_input_ctx ctx_input; 165213379Shselasky struct xhci_slot_ctx ctx_slot; 166213379Shselasky struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 167213379Shselasky}; 168213379Shselasky 169213379Shselaskystruct xhci_dev_ctx { 170213379Shselasky struct xhci_slot_ctx ctx_slot; 171213379Shselasky struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 172213379Shselasky} __aligned(XHCI_DEV_CTX_ALIGN); 173213379Shselasky 174213379Shselaskystruct xhci_stream_ctx { 175213379Shselasky volatile uint64_t qwSctx0; 176213379Shselasky#define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 177213379Shselasky#define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 178213379Shselasky#define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 179213379Shselasky#define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 180213379Shselasky#define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 181213379Shselasky#define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 182213379Shselasky#define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 183213379Shselasky#define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 184213379Shselasky#define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 185213379Shselasky#define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 186213379Shselasky#define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 187213379Shselasky#define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 188213379Shselasky#define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 189213379Shselasky volatile uint32_t dwSctx2; 190213379Shselasky volatile uint32_t dwSctx3; 191213379Shselasky}; 192213379Shselasky 193213379Shselaskystruct xhci_trb { 194213379Shselasky volatile uint64_t qwTrb0; 195262370Shselasky#define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) 196213379Shselasky#define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 197213379Shselasky volatile uint32_t dwTrb2; 198213379Shselasky#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 199213379Shselasky#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 200213379Shselasky#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 201213379Shselasky#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 202213379Shselasky#define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 203213379Shselasky#define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 204213379Shselasky#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 205213379Shselasky#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 206213379Shselasky#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 207213379Shselasky#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 208213379Shselasky#define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 209213379Shselasky#define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 210213379Shselasky 211213379Shselasky volatile uint32_t dwTrb3; 212213379Shselasky#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 213213379Shselasky#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 214213379Shselasky#define XHCI_TRB_3_CYCLE_BIT (1U << 0) 215213379Shselasky#define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 216213379Shselasky#define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 217213379Shselasky#define XHCI_TRB_3_ISP_BIT (1U << 2) 218213379Shselasky#define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 219213379Shselasky#define XHCI_TRB_3_CHAIN_BIT (1U << 4) 220213379Shselasky#define XHCI_TRB_3_IOC_BIT (1U << 5) 221213379Shselasky#define XHCI_TRB_3_IDT_BIT (1U << 6) 222213379Shselasky#define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 223213379Shselasky#define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 224213379Shselasky#define XHCI_TRB_3_BEI_BIT (1U << 9) 225213379Shselasky#define XHCI_TRB_3_DCEP_BIT (1U << 9) 226213379Shselasky#define XHCI_TRB_3_PRSV_BIT (1U << 9) 227213379Shselasky#define XHCI_TRB_3_BSR_BIT (1U << 9) 228213379Shselasky#define XHCI_TRB_3_TRT_MASK (3U << 16) 229213379Shselasky#define XHCI_TRB_3_TRT_NONE (0U << 16) 230213379Shselasky#define XHCI_TRB_3_TRT_OUT (2U << 16) 231213379Shselasky#define XHCI_TRB_3_TRT_IN (3U << 16) 232213379Shselasky#define XHCI_TRB_3_DIR_IN (1U << 16) 233213379Shselasky#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 234213379Shselasky#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 235213379Shselasky#define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 236213379Shselasky#define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 237213379Shselasky#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 238213379Shselasky#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 239213379Shselasky#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 240213379Shselasky#define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 241213379Shselasky#define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 242213379Shselasky#define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 243213379Shselasky 244213379Shselasky/* Commands */ 245213379Shselasky#define XHCI_TRB_TYPE_RESERVED 0x00 246213379Shselasky#define XHCI_TRB_TYPE_NORMAL 0x01 247213379Shselasky#define XHCI_TRB_TYPE_SETUP_STAGE 0x02 248213379Shselasky#define XHCI_TRB_TYPE_DATA_STAGE 0x03 249213379Shselasky#define XHCI_TRB_TYPE_STATUS_STAGE 0x04 250213379Shselasky#define XHCI_TRB_TYPE_ISOCH 0x05 251213379Shselasky#define XHCI_TRB_TYPE_LINK 0x06 252213379Shselasky#define XHCI_TRB_TYPE_EVENT_DATA 0x07 253213379Shselasky#define XHCI_TRB_TYPE_NOOP 0x08 254213379Shselasky#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 255213379Shselasky#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 256213379Shselasky#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 257213379Shselasky#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 258213379Shselasky#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 259213379Shselasky#define XHCI_TRB_TYPE_RESET_EP 0x0E 260213379Shselasky#define XHCI_TRB_TYPE_STOP_EP 0x0F 261213379Shselasky#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 262213379Shselasky#define XHCI_TRB_TYPE_RESET_DEVICE 0x11 263213379Shselasky#define XHCI_TRB_TYPE_FORCE_EVENT 0x12 264213379Shselasky#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 265213379Shselasky#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 266213379Shselasky#define XHCI_TRB_TYPE_GET_PORT_BW 0x15 267213379Shselasky#define XHCI_TRB_TYPE_FORCE_HEADER 0x16 268213379Shselasky#define XHCI_TRB_TYPE_NOOP_CMD 0x17 269213379Shselasky 270213379Shselasky/* Events */ 271213379Shselasky#define XHCI_TRB_EVENT_TRANSFER 0x20 272213379Shselasky#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 273213379Shselasky#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 274213379Shselasky#define XHCI_TRB_EVENT_BW_REQUEST 0x23 275213379Shselasky#define XHCI_TRB_EVENT_DOORBELL 0x24 276213379Shselasky#define XHCI_TRB_EVENT_HOST_CTRL 0x25 277213379Shselasky#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 278213379Shselasky#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 279213379Shselasky 280213379Shselasky/* Error codes */ 281213379Shselasky#define XHCI_TRB_ERROR_INVALID 0x00 282213379Shselasky#define XHCI_TRB_ERROR_SUCCESS 0x01 283213379Shselasky#define XHCI_TRB_ERROR_DATA_BUF 0x02 284213379Shselasky#define XHCI_TRB_ERROR_BABBLE 0x03 285213379Shselasky#define XHCI_TRB_ERROR_XACT 0x04 286213379Shselasky#define XHCI_TRB_ERROR_TRB 0x05 287213379Shselasky#define XHCI_TRB_ERROR_STALL 0x06 288213379Shselasky#define XHCI_TRB_ERROR_RESOURCE 0x07 289213379Shselasky#define XHCI_TRB_ERROR_BANDWIDTH 0x08 290213379Shselasky#define XHCI_TRB_ERROR_NO_SLOTS 0x09 291213379Shselasky#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 292213379Shselasky#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 293213379Shselasky#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 294213379Shselasky#define XHCI_TRB_ERROR_SHORT_PKT 0x0D 295213379Shselasky#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 296213379Shselasky#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 297213379Shselasky#define XHCI_TRB_ERROR_VF_RING_FULL 0x10 298213379Shselasky#define XHCI_TRB_ERROR_PARAMETER 0x11 299213379Shselasky#define XHCI_TRB_ERROR_BW_OVERRUN 0x12 300213379Shselasky#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 301213379Shselasky#define XHCI_TRB_ERROR_NO_PING_RESP 0x14 302213379Shselasky#define XHCI_TRB_ERROR_EV_RING_FULL 0x15 303213379Shselasky#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 304213379Shselasky#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 305213379Shselasky#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 306213379Shselasky#define XHCI_TRB_ERROR_CMD_ABORTED 0x19 307213379Shselasky#define XHCI_TRB_ERROR_STOPPED 0x1A 308213379Shselasky#define XHCI_TRB_ERROR_LENGTH 0x1B 309213379Shselasky#define XHCI_TRB_ERROR_BAD_MELAT 0x1D 310213379Shselasky#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 311213379Shselasky#define XHCI_TRB_ERROR_EVENT_LOST 0x20 312213379Shselasky#define XHCI_TRB_ERROR_UNDEFINED 0x21 313213379Shselasky#define XHCI_TRB_ERROR_INVALID_SID 0x22 314213379Shselasky#define XHCI_TRB_ERROR_SEC_BW 0x23 315213379Shselasky#define XHCI_TRB_ERROR_SPLIT_XACT 0x24 316213379Shselasky} __aligned(4); 317213379Shselasky 318213379Shselaskystruct xhci_dev_endpoint_trbs { 319269447Shselasky struct xhci_trb trb[(XHCI_MAX_STREAMS * 320269447Shselasky XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; 321213379Shselasky}; 322213379Shselasky 323213379Shselasky#define XHCI_TD_PAGE_NBUF 17 /* units, room enough for 64Kbytes */ 324213379Shselasky#define XHCI_TD_PAGE_SIZE 4096 /* bytes */ 325213379Shselasky#define XHCI_TD_PAYLOAD_MAX (XHCI_TD_PAGE_SIZE * (XHCI_TD_PAGE_NBUF - 1)) 326213379Shselasky 327213379Shselaskystruct xhci_td { 328213379Shselasky struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; 329213379Shselasky 330213379Shselasky/* 331213379Shselasky * Extra information needed: 332213379Shselasky */ 333213379Shselasky uint64_t td_self; 334213379Shselasky struct xhci_td *next; 335213379Shselasky struct xhci_td *alt_next; 336213379Shselasky struct xhci_td *obj_next; 337213379Shselasky struct usb_page_cache *page_cache; 338213379Shselasky uint32_t len; 339213379Shselasky uint32_t remainder; 340213379Shselasky uint8_t ntrb; 341213379Shselasky uint8_t status; 342213379Shselasky} __aligned(XHCI_TRB_ALIGN); 343213379Shselasky 344213379Shselaskystruct xhci_command { 345213379Shselasky struct xhci_trb trb; 346213379Shselasky TAILQ_ENTRY(xhci_command) entry; 347213379Shselasky}; 348213379Shselasky 349213379Shselaskystruct xhci_event_ring_seg { 350213379Shselasky volatile uint64_t qwEvrsTablePtr; 351213379Shselasky volatile uint32_t dwEvrsTableSize; 352213379Shselasky volatile uint32_t dwEvrsReserved; 353213379Shselasky}; 354213379Shselasky 355213379Shselaskystruct xhci_hw_root { 356213379Shselasky struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]; 357213379Shselasky struct { 358213379Shselasky volatile uint64_t dummy; 359213379Shselasky } __aligned(64) padding; 360213379Shselasky struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; 361213379Shselasky struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; 362213379Shselasky}; 363213379Shselasky 364213379Shselaskystruct xhci_endpoint_ext { 365213379Shselasky struct xhci_trb *trb; 366239214Shselasky struct usb_xfer *xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS]; 367213379Shselasky struct usb_page_cache *page_cache; 368213379Shselasky uint64_t physaddr; 369239214Shselasky uint8_t trb_used[XHCI_MAX_STREAMS]; 370239214Shselasky uint8_t trb_index[XHCI_MAX_STREAMS]; 371213379Shselasky uint8_t trb_halted; 372213379Shselasky uint8_t trb_running; 373251247Shselasky uint8_t trb_ep_mode; 374213379Shselasky}; 375213379Shselasky 376213379Shselaskyenum { 377213379Shselasky XHCI_ST_DISABLED, 378213379Shselasky XHCI_ST_ENABLED, 379213379Shselasky XHCI_ST_DEFAULT, 380213379Shselasky XHCI_ST_ADDRESSED, 381213379Shselasky XHCI_ST_CONFIGURED, 382213379Shselasky XHCI_ST_MAX 383213379Shselasky}; 384213379Shselasky 385213379Shselaskystruct xhci_hw_dev { 386213379Shselasky struct usb_page_cache device_pc; 387213379Shselasky struct usb_page_cache input_pc; 388269447Shselasky struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS]; 389213379Shselasky 390213379Shselasky struct usb_page device_pg; 391213379Shselasky struct usb_page input_pg; 392269447Shselasky struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS]; 393213379Shselasky 394213379Shselasky struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]; 395213379Shselasky 396213379Shselasky uint8_t state; 397213379Shselasky uint8_t nports; 398213379Shselasky uint8_t tt; 399243780Shselasky uint8_t context_num; 400213379Shselasky}; 401213379Shselasky 402213379Shselaskystruct xhci_hw_softc { 403213379Shselasky struct usb_page_cache root_pc; 404213379Shselasky struct usb_page_cache ctx_pc; 405213379Shselasky struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]; 406213379Shselasky 407213379Shselasky struct usb_page root_pg; 408213379Shselasky struct usb_page ctx_pg; 409213379Shselasky struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]; 410213379Shselasky 411213379Shselasky struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1]; 412213379Shselasky}; 413213379Shselasky 414213379Shselaskystruct xhci_config_desc { 415213379Shselasky struct usb_config_descriptor confd; 416213379Shselasky struct usb_interface_descriptor ifcd; 417213379Shselasky struct usb_endpoint_descriptor endpd; 418213379Shselasky struct usb_endpoint_ss_comp_descriptor endpcd; 419213379Shselasky} __packed; 420213379Shselasky 421213379Shselaskystruct xhci_bos_desc { 422213379Shselasky struct usb_bos_descriptor bosd; 423213379Shselasky struct usb_devcap_usb2ext_descriptor usb2extd; 424213379Shselasky struct usb_devcap_ss_descriptor usbdcd; 425213379Shselasky struct usb_devcap_container_id_descriptor cidd; 426213379Shselasky} __packed; 427213379Shselasky 428213379Shselaskyunion xhci_hub_desc { 429213379Shselasky struct usb_status stat; 430213379Shselasky struct usb_port_status ps; 431213379Shselasky struct usb_hub_ss_descriptor hubd; 432213379Shselasky uint8_t temp[128]; 433213379Shselasky}; 434213379Shselasky 435255768Shselaskytypedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t); 436255768Shselasky 437213379Shselaskystruct xhci_softc { 438213379Shselasky struct xhci_hw_softc sc_hw; 439213379Shselasky /* base device */ 440213379Shselasky struct usb_bus sc_bus; 441246363Shselasky /* configure message */ 442213379Shselasky struct usb_bus_msg sc_config_msg[2]; 443213379Shselasky 444251499Shselasky struct usb_callout sc_callout; 445251499Shselasky 446255768Shselasky xhci_port_route_t *sc_port_route; 447255768Shselasky 448213379Shselasky union xhci_hub_desc sc_hub_desc; 449213379Shselasky 450213379Shselasky struct cv sc_cmd_cv; 451213379Shselasky struct sx sc_cmd_sx; 452213379Shselasky 453213379Shselasky struct usb_device *sc_devices[XHCI_MAX_DEVICES]; 454213379Shselasky struct resource *sc_io_res; 455253094Skib int sc_irq_rid; 456213379Shselasky struct resource *sc_irq_res; 457213379Shselasky 458213379Shselasky void *sc_intr_hdl; 459213379Shselasky bus_size_t sc_io_size; 460213379Shselasky bus_space_tag_t sc_io_tag; 461213379Shselasky bus_space_handle_t sc_io_hdl; 462213379Shselasky /* last pending command address */ 463213379Shselasky uint64_t sc_cmd_addr; 464213379Shselasky /* result of command */ 465213379Shselasky uint32_t sc_cmd_result[2]; 466213379Shselasky /* copy of cmd register */ 467213379Shselasky uint32_t sc_cmd; 468213379Shselasky /* worst case exit latency */ 469213379Shselasky uint32_t sc_exit_lat_max; 470213379Shselasky 471213379Shselasky /* offset to operational registers */ 472213379Shselasky uint32_t sc_oper_off; 473213379Shselasky /* offset to capability registers */ 474213379Shselasky uint32_t sc_capa_off; 475213379Shselasky /* offset to runtime registers */ 476213379Shselasky uint32_t sc_runt_off; 477213379Shselasky /* offset to doorbell registers */ 478213379Shselasky uint32_t sc_door_off; 479213379Shselasky 480213379Shselasky /* chip specific */ 481213379Shselasky uint16_t sc_erst_max; 482213379Shselasky uint16_t sc_event_idx; 483213379Shselasky uint16_t sc_command_idx; 484265078Shselasky uint16_t sc_imod_default; 485213379Shselasky 486213379Shselasky uint8_t sc_event_ccs; 487213379Shselasky uint8_t sc_command_ccs; 488213379Shselasky /* number of XHCI device slots */ 489213379Shselasky uint8_t sc_noslot; 490213379Shselasky /* number of ports on root HUB */ 491213379Shselasky uint8_t sc_noport; 492213379Shselasky /* number of scratch pages */ 493213379Shselasky uint8_t sc_noscratch; 494213379Shselasky /* root HUB device configuration */ 495213379Shselasky uint8_t sc_conf; 496272608Shselasky /* root HUB port event bitmap, max 256 ports */ 497272608Shselasky uint8_t sc_hub_idata[32]; 498213379Shselasky 499217374Shselasky /* size of context */ 500217374Shselasky uint8_t sc_ctx_is_64_byte; 501217374Shselasky 502213379Shselasky /* vendor string for root HUB */ 503213379Shselasky char sc_vendor[16]; 504213379Shselasky}; 505213379Shselasky 506213379Shselasky#define XHCI_CMD_LOCK(sc) sx_xlock(&(sc)->sc_cmd_sx) 507213379Shselasky#define XHCI_CMD_UNLOCK(sc) sx_xunlock(&(sc)->sc_cmd_sx) 508213379Shselasky#define XHCI_CMD_ASSERT_LOCKED(sc) sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED) 509213379Shselasky 510213379Shselasky/* prototypes */ 511213379Shselasky 512251499Shselaskyuint8_t xhci_use_polling(void); 513213379Shselaskyusb_error_t xhci_halt_controller(struct xhci_softc *); 514213379Shselaskyusb_error_t xhci_init(struct xhci_softc *, device_t); 515213379Shselaskyusb_error_t xhci_start_controller(struct xhci_softc *); 516213379Shselaskyvoid xhci_interrupt(struct xhci_softc *); 517213379Shselaskyvoid xhci_uninit(struct xhci_softc *); 518213379Shselasky 519213379Shselasky#endif /* _XHCI_H_ */ 520