musb_otg.h revision 190735
1/* $FreeBSD: head/sys/dev/usb/controller/musb_otg.h 190735 2009-04-05 18:20:49Z thompsa $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * This header file defines the registers of the Mentor Graphics 29 * USB OnTheGo Inventra chip. 30 */ 31 32#ifndef _MUSB2_OTG_H_ 33#define _MUSB2_OTG_H_ 34 35#define MUSB2_MAX_DEVICES (USB_MIN_DEVICES + 1) 36 37/* Common registers */ 38 39#define MUSB2_REG_FADDR 0x0000 /* function address register */ 40#define MUSB2_MASK_FADDR 0x7F 41 42#define MUSB2_REG_POWER 0x0001 /* power register */ 43#define MUSB2_MASK_SUSPM_ENA 0x01 44#define MUSB2_MASK_SUSPMODE 0x02 45#define MUSB2_MASK_RESUME 0x04 46#define MUSB2_MASK_RESET 0x08 47#define MUSB2_MASK_HSMODE 0x10 48#define MUSB2_MASK_HSENAB 0x20 49#define MUSB2_MASK_SOFTC 0x40 50#define MUSB2_MASK_ISOUPD 0x80 51 52/* Endpoint interrupt handling */ 53 54#define MUSB2_REG_INTTX 0x0002 /* transmit interrupt register */ 55#define MUSB2_REG_INTRX 0x0004 /* receive interrupt register */ 56#define MUSB2_REG_INTTXE 0x0006 /* transmit interrupt enable register */ 57#define MUSB2_REG_INTRXE 0x0008 /* receive interrupt enable register */ 58#define MUSB2_MASK_EPINT(epn) (1 << (epn)) /* epn = [0..15] */ 59 60/* Common interrupt handling */ 61 62#define MUSB2_REG_INTUSB 0x000A /* USB interrupt register */ 63#define MUSB2_MASK_ISUSP 0x01 64#define MUSB2_MASK_IRESUME 0x02 65#define MUSB2_MASK_IRESET 0x04 66#define MUSB2_MASK_IBABBLE 0x04 67#define MUSB2_MASK_ISOF 0x08 68#define MUSB2_MASK_ICONN 0x10 69#define MUSB2_MASK_IDISC 0x20 70#define MUSB2_MASK_ISESSRQ 0x40 71#define MUSB2_MASK_IVBUSERR 0x80 72 73#define MUSB2_REG_INTUSBE 0x000B /* USB interrupt enable register */ 74#define MUSB2_REG_FRAME 0x000C /* USB frame register */ 75#define MUSB2_MASK_FRAME 0x3FF /* 0..1023 */ 76 77#define MUSB2_REG_EPINDEX 0x000E /* endpoint index register */ 78#define MUSB2_MASK_EPINDEX 0x0F 79 80#define MUSB2_REG_TESTMODE 0x000F /* test mode register */ 81#define MUSB2_MASK_TSE0_NAK 0x01 82#define MUSB2_MASK_TJ 0x02 83#define MUSB2_MASK_TK 0x04 84#define MUSB2_MASK_TPACKET 0x08 85#define MUSB2_MASK_TFORCE_HS 0x10 86#define MUSB2_MASK_TFORCE_LS 0x20 87#define MUSB2_MASK_TFIFO_ACC 0x40 88#define MUSB2_MASK_TFORCE_HC 0x80 89 90#define MUSB2_REG_INDEXED_CSR 0x0010 /* EP control status register offset */ 91 92#define MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR) 93#define MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR) 94#define MUSB2_MASK_PKTSIZE 0x03FF /* in bytes, should be even */ 95#define MUSB2_MASK_PKTMULT 0xFC00 /* HS packet multiplier: 0..2 */ 96 97#define MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR) 98#define MUSB2_MASK_CSRL_TXPKTRDY 0x01 99#define MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02 100#define MUSB2_MASK_CSRL_TXUNDERRUN 0x04 /* Device Mode */ 101#define MUSB2_MASK_CSRL_TXERROR 0x04 /* Host Mode */ 102#define MUSB2_MASK_CSRL_TXFFLUSH 0x08 103#define MUSB2_MASK_CSRL_TXSENDSTALL 0x10/* Device Mode */ 104#define MUSB2_MASK_CSRL_TXSETUPPKT 0x10 /* Host Mode */ 105#define MUSB2_MASK_CSRL_TXSENTSTALL 0x20/* Device Mode */ 106#define MUSB2_MASK_CSRL_TXSTALLED 0x20 /* Host Mode */ 107#define MUSB2_MASK_CSRL_TXDT_CLR 0x40 108#define MUSB2_MASK_CSRL_TXINCOMP 0x80 109 110/* Device Side Mode */ 111#define MUSB2_MASK_CSR0L_RXPKTRDY 0x01 112#define MUSB2_MASK_CSR0L_TXPKTRDY 0x02 113#define MUSB2_MASK_CSR0L_SENTSTALL 0x04 114#define MUSB2_MASK_CSR0L_DATAEND 0x08 115#define MUSB2_MASK_CSR0L_SETUPEND 0x10 116#define MUSB2_MASK_CSR0L_SENDSTALL 0x20 117#define MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40 118#define MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80 119 120/* Host Side Mode */ 121#define MUSB2_MASK_CSR0L_RXSTALL 0x04 122#define MUSB2_MASK_CSR0L_SETUPPKT 0x08 123#define MUSB2_MASK_CSR0L_ERROR 0x10 124#define MUSB2_MASK_CSR0L_REQPKT 0x20 125#define MUSB2_MASK_CSR0L_STATUSPKT 0x40 126#define MUSB2_MASK_CSR0L_NAKTIMO 0x80 127 128#define MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR) 129#define MUSB2_MASK_CSRH_TXDT_VAL 0x01 /* Host Mode */ 130#define MUSB2_MASK_CSRH_TXDT_WR 0x02 /* Host Mode */ 131#define MUSB2_MASK_CSRH_TXDMAREQMODE 0x04 132#define MUSB2_MASK_CSRH_TXDT_SWITCH 0x08 133#define MUSB2_MASK_CSRH_TXDMAREQENA 0x10 134#define MUSB2_MASK_CSRH_RXMODE 0x00 135#define MUSB2_MASK_CSRH_TXMODE 0x20 136#define MUSB2_MASK_CSRH_TXISO 0x40 /* Device Mode */ 137#define MUSB2_MASK_CSRH_TXAUTOSET 0x80 138 139#define MUSB2_MASK_CSR0H_FFLUSH 0x01 /* Device Side flush FIFO */ 140#define MUSB2_MASK_CSR0H_DT 0x02 /* Host Side data toggle */ 141#define MUSB2_MASK_CSR0H_DT_SET 0x04 /* Host Side */ 142#define MUSB2_MASK_CSR0H_PING_DIS 0x08 /* Host Side */ 143 144#define MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR) 145#define MUSB2_MASK_CSRL_RXPKTRDY 0x01 146#define MUSB2_MASK_CSRL_RXFIFOFULL 0x02 147#define MUSB2_MASK_CSRL_RXOVERRUN 0x04 148#define MUSB2_MASK_CSRL_RXDATAERR 0x08 149#define MUSB2_MASK_CSRL_RXFFLUSH 0x10 150#define MUSB2_MASK_CSRL_RXSENDSTALL 0x20/* Device Mode */ 151#define MUSB2_MASK_CSRL_RXREQPKT 0x20 /* Host Mode */ 152#define MUSB2_MASK_CSRL_RXSENTSTALL 0x40/* Device Mode */ 153#define MUSB2_MASK_CSRL_RXSTALL 0x40 /* Host Mode */ 154#define MUSB2_MASK_CSRL_RXDT_CLR 0x80 155 156#define MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR) 157#define MUSB2_MASK_CSRH_RXINCOMP 0x01 158#define MUSB2_MASK_CSRH_RXDT_VAL 0x02 /* Host Mode */ 159#define MUSB2_MASK_CSRH_RXDT_SET 0x04 /* Host Mode */ 160#define MUSB2_MASK_CSRH_RXDMAREQMODE 0x08 161#define MUSB2_MASK_CSRH_RXNYET 0x10 162#define MUSB2_MASK_CSRH_RXDMAREQENA 0x20 163#define MUSB2_MASK_CSRH_RXISO 0x40 /* Device Mode */ 164#define MUSB2_MASK_CSRH_RXAUTOREQ 0x40 /* Host Mode */ 165#define MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80 166 167#define MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR) 168#define MUSB2_MASK_RXCOUNT 0xFFFF 169 170#define MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR) 171#define MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR) 172 173/* Host Mode */ 174#define MUSB2_MASK_TI_SPEED 0xC0 175#define MUSB2_MASK_TI_SPEED_LO 0xC0 176#define MUSB2_MASK_TI_SPEED_FS 0x80 177#define MUSB2_MASK_TI_SPEED_HS 0x40 178#define MUSB2_MASK_TI_PROTO_CTRL 0x00 179#define MUSB2_MASK_TI_PROTO_ISOC 0x10 180#define MUSB2_MASK_TI_PROTO_BULK 0x20 181#define MUSB2_MASK_TI_PROTO_INTR 0x30 182#define MUSB2_MASK_TI_EP_NUM 0x0F 183 184#define MUSB2_REG_TXNAKLIMIT (0x000B /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) 185#define MUSB2_REG_RXNAKLIMIT (0x000D /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) 186#define MUSB2_MASK_NAKLIMIT 0xFF 187 188#define MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR) 189#define MUSB2_MASK_RX_FSIZE 0xF0 /* 3..13, 2**n bytes */ 190#define MUSB2_MASK_TX_FSIZE 0x0F /* 3..13, 2**n bytes */ 191 192#define MUSB2_REG_EPFIFO(n) (0x0020 + (4*(n))) 193 194#define MUSB2_REG_CONFDATA 0x000F /* EPN=0 */ 195#define MUSB2_MASK_CD_UTMI_DW 0x01 196#define MUSB2_MASK_CD_SOFTCONE 0x02 197#define MUSB2_MASK_CD_DYNFIFOSZ 0x04 198#define MUSB2_MASK_CD_HBTXE 0x08 199#define MUSB2_MASK_CD_HBRXE 0x10 200#define MUSB2_MASK_CD_BIGEND 0x20 201#define MUSB2_MASK_CD_MPTXE 0x40 202#define MUSB2_MASK_CD_MPRXE 0x80 203 204/* Various registers */ 205 206#define MUSB2_REG_DEVCTL 0x0060 207#define MUSB2_MASK_SESS 0x01 208#define MUSB2_MASK_HOSTREQ 0x02 209#define MUSB2_MASK_HOSTMD 0x04 210#define MUSB2_MASK_VBUS0 0x08 211#define MUSB2_MASK_VBUS1 0x10 212#define MUSB2_MASK_LSDEV 0x20 213#define MUSB2_MASK_FSDEV 0x40 214#define MUSB2_MASK_BDEV 0x80 215 216#define MUSB2_REG_MISC 0x0061 217#define MUSB2_MASK_RXEDMA 0x01 218#define MUSB2_MASK_TXEDMA 0x02 219 220#define MUSB2_REG_TXFIFOSZ 0x0062 221#define MUSB2_REG_RXFIFOSZ 0x0063 222#define MUSB2_MASK_FIFODB 0x10 /* set if double buffering, r/w */ 223#define MUSB2_MASK_FIFOSZ 0x0F 224#define MUSB2_VAL_FIFOSZ_8 0 225#define MUSB2_VAL_FIFOSZ_16 1 226#define MUSB2_VAL_FIFOSZ_32 2 227#define MUSB2_VAL_FIFOSZ_64 3 228#define MUSB2_VAL_FIFOSZ_128 4 229#define MUSB2_VAL_FIFOSZ_256 5 230#define MUSB2_VAL_FIFOSZ_512 6 231#define MUSB2_VAL_FIFOSZ_1024 7 232#define MUSB2_VAL_FIFOSZ_2048 8 233#define MUSB2_VAL_FIFOSZ_4096 9 234 235#define MUSB2_REG_TXFIFOADD 0x0064 236#define MUSB2_REG_RXFIFOADD 0x0066 237#define MUSB2_MASK_FIFOADD 0xFFF /* unit is 8-bytes */ 238 239#define MUSB2_REG_VSTATUS 0x0068 240#define MUSB2_REG_VCONTROL 0x0068 241#define MUSB2_REG_HWVERS 0x006C 242#define MUSB2_REG_ULPI_BASE 0x0070 243 244#define MUSB2_REG_EPINFO 0x0078 245#define MUSB2_MASK_NRXEP 0xF0 246#define MUSB2_MASK_NTXEP 0x0F 247 248#define MUSB2_REG_RAMINFO 0x0079 249#define MUSB2_REG_LINKINFO 0x007A 250 251#define MUSB2_REG_VPLEN 0x007B 252#define MUSB2_MASK_VPLEN 0xFF 253 254#define MUSB2_REG_HS_EOF1 0x007C 255#define MUSB2_REG_FS_EOF1 0x007D 256#define MUSB2_REG_LS_EOF1 0x007E 257#define MUSB2_REG_SOFT_RST 0x007F 258#define MUSB2_MASK_SRST 0x01 259#define MUSB2_MASK_SRSTX 0x02 260 261#define MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n)) 262#define MUSB2_REG_RXDBDIS 0x0340 263#define MUSB2_REG_TXDBDIS 0x0342 264#define MUSB2_MASK_DB(n) (1 << (n)) /* disable double buffer, n = [0..15] */ 265 266#define MUSB2_REG_CHIRPTO 0x0344 267#define MUSB2_REG_HSRESUM 0x0346 268 269/* Host Mode only registers */ 270 271#define MUSB2_REG_TXFADDR(n) (0x0080 + (8*(n))) 272#define MUSB2_REG_TXHADDR(n) (0x0082 + (8*(n))) 273#define MUSB2_REG_TXHUBPORT(n) (0x0083 + (8*(n))) 274#define MUSB2_REG_RXFADDR(n) (0x0084 + (8*(n))) 275#define MUSB2_REG_RXHADDR(n) (0x0086 + (8*(n))) 276#define MUSB2_REG_RXHPORT(n) (0x0087 + (8*(n))) 277 278#define MUSB2_EP_MAX 16 /* maximum number of endpoints */ 279 280#define MUSB2_READ_2(sc, reg) \ 281 bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 282 283#define MUSB2_WRITE_2(sc, reg, data) \ 284 bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 285 286#define MUSB2_READ_1(sc, reg) \ 287 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 288 289#define MUSB2_WRITE_1(sc, reg, data) \ 290 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 291 292struct musbotg_td; 293struct musbotg_softc; 294 295typedef uint8_t (musbotg_cmd_t)(struct musbotg_td *td); 296 297struct musbotg_dma { 298 struct musbotg_softc *sc; 299 uint32_t dma_chan; 300 uint8_t busy:1; 301 uint8_t complete:1; 302 uint8_t error:1; 303}; 304 305struct musbotg_td { 306 struct musbotg_td *obj_next; 307 musbotg_cmd_t *func; 308 struct usb2_page_cache *pc; 309 uint32_t offset; 310 uint32_t remainder; 311 uint16_t max_frame_size; /* packet_size * mult */ 312 uint8_t ep_no; 313 uint8_t error:1; 314 uint8_t alt_next:1; 315 uint8_t short_pkt:1; 316 uint8_t support_multi_buffer:1; 317 uint8_t did_stall:1; 318 uint8_t dma_enabled:1; 319}; 320 321struct musbotg_std_temp { 322 musbotg_cmd_t *func; 323 struct usb2_page_cache *pc; 324 struct musbotg_td *td; 325 struct musbotg_td *td_next; 326 uint32_t len; 327 uint32_t offset; 328 uint16_t max_frame_size; 329 uint8_t short_pkt; 330 /* 331 * short_pkt = 0: transfer should be short terminated 332 * short_pkt = 1: transfer should not be short terminated 333 */ 334 uint8_t setup_alt_next; 335}; 336 337struct musbotg_config_desc { 338 struct usb2_config_descriptor confd; 339 struct usb2_interface_descriptor ifcd; 340 struct usb2_endpoint_descriptor endpd; 341} __packed; 342 343union musbotg_hub_temp { 344 uWord wValue; 345 struct usb2_port_status ps; 346}; 347 348struct musbotg_flags { 349 uint8_t change_connect:1; 350 uint8_t change_suspend:1; 351 uint8_t status_suspend:1; /* set if suspended */ 352 uint8_t status_vbus:1; /* set if present */ 353 uint8_t status_bus_reset:1; /* set if reset complete */ 354 uint8_t status_high_speed:1; /* set if High Speed is selected */ 355 uint8_t remote_wakeup:1; 356 uint8_t self_powered:1; 357 uint8_t clocks_off:1; 358 uint8_t port_powered:1; 359 uint8_t port_enabled:1; 360 uint8_t d_pulled_up:1; 361}; 362 363struct musbotg_softc { 364 struct usb2_bus sc_bus; 365 union musbotg_hub_temp sc_hub_temp; 366 struct usb2_hw_ep_profile sc_hw_ep_profile[16]; 367 368 struct usb2_device *sc_devices[MUSB2_MAX_DEVICES]; 369 struct resource *sc_io_res; 370 struct resource *sc_irq_res; 371 void *sc_intr_hdl; 372 bus_size_t sc_io_size; 373 bus_space_tag_t sc_io_tag; 374 bus_space_handle_t sc_io_hdl; 375 376 void (*sc_clocks_on) (void *arg); 377 void (*sc_clocks_off) (void *arg); 378 void *sc_clocks_arg; 379 380 uint32_t sc_bounce_buf[(1024 * 3) / 4]; /* bounce buffer */ 381 382 uint8_t sc_ep_max; /* maximum number of RX and TX 383 * endpoints supported */ 384 uint8_t sc_rt_addr; /* root HUB address */ 385 uint8_t sc_dv_addr; /* device address */ 386 uint8_t sc_conf; /* root HUB config */ 387 uint8_t sc_ep0_busy; /* set if ep0 is busy */ 388 uint8_t sc_ep0_cmd; /* pending commands */ 389 uint8_t sc_conf_data; /* copy of hardware register */ 390 391 uint8_t sc_hub_idata[1]; 392 393 struct musbotg_flags sc_flags; 394}; 395 396/* prototypes */ 397 398usb2_error_t musbotg_init(struct musbotg_softc *sc); 399void musbotg_uninit(struct musbotg_softc *sc); 400void musbotg_suspend(struct musbotg_softc *sc); 401void musbotg_resume(struct musbotg_softc *sc); 402void musbotg_interrupt(struct musbotg_softc *sc); 403void musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on); 404 405#endif /* _MUSB2_OTG_H_ */ 406