1230424Shselasky/* $FreeBSD$ */ 2230424Shselasky/*- 3230424Shselasky * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4230424Shselasky * 5230424Shselasky * Redistribution and use in source and binary forms, with or without 6230424Shselasky * modification, are permitted provided that the following conditions 7230424Shselasky * are met: 8230424Shselasky * 1. Redistributions of source code must retain the above copyright 9230424Shselasky * notice, this list of conditions and the following disclaimer. 10230424Shselasky * 2. Redistributions in binary form must reproduce the above copyright 11230424Shselasky * notice, this list of conditions and the following disclaimer in the 12230424Shselasky * documentation and/or other materials provided with the distribution. 13230424Shselasky * 14230424Shselasky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15230424Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16230424Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17230424Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18230424Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19230424Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20230424Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21230424Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22230424Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23230424Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24230424Shselasky * SUCH DAMAGE. 25230424Shselasky */ 26230424Shselasky 27230424Shselasky#ifndef _DWC_OTG_H_ 28230424Shselasky#define _DWC_OTG_H_ 29230424Shselasky 30240279Shselasky#define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32) 31230424Shselasky#define DWC_OTG_FRAME_MASK 0x7FF 32230424Shselasky#define DWC_OTG_MAX_TXP 4 33230424Shselasky#define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP) 34240279Shselasky#define DWC_OTG_MAX_CHANNELS 16 35240279Shselasky#define DWC_OTG_MAX_ENDPOINTS 16 36240857Shselasky#define DWC_OTG_HOST_TIMER_RATE 10 /* ms */ 37266575Shselasky#define DWC_OTG_TT_SLOT_MAX 8 38267242Shselasky#define DWC_OTG_SLOT_IDLE_MAX 3 39266575Shselasky#define DWC_OTG_SLOT_IDLE_MIN 2 40266575Shselasky#define DWC_OTG_NAK_MAX 8 /* 1 ms */ 41230424Shselasky 42230424Shselasky#define DWC_OTG_READ_4(sc, reg) \ 43230424Shselasky bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 44230424Shselasky 45230424Shselasky#define DWC_OTG_WRITE_4(sc, reg, data) \ 46230424Shselasky bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 47230424Shselasky 48230424Shselaskystruct dwc_otg_td; 49230424Shselaskystruct dwc_otg_softc; 50230424Shselasky 51266575Shselaskytypedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_softc *sc, struct dwc_otg_td *td); 52230424Shselasky 53230424Shselaskystruct dwc_otg_td { 54230424Shselasky struct dwc_otg_td *obj_next; 55230424Shselasky dwc_otg_cmd_t *func; 56230424Shselasky struct usb_page_cache *pc; 57230424Shselasky uint32_t tx_bytes; 58230424Shselasky uint32_t offset; 59230424Shselasky uint32_t remainder; 60240279Shselasky uint32_t hcchar; /* HOST CFG */ 61240279Shselasky uint32_t hcsplt; /* HOST CFG */ 62230424Shselasky uint16_t max_packet_size; /* packet_size */ 63230424Shselasky uint16_t npkt; 64266575Shselasky uint8_t max_packet_count; /* packet_count */ 65240857Shselasky uint8_t errcnt; 66240857Shselasky uint8_t tmr_res; 67240857Shselasky uint8_t tmr_val; 68266575Shselasky uint8_t did_nak; /* NAK counter */ 69230424Shselasky uint8_t ep_no; 70266575Shselasky uint8_t ep_type; 71267242Shselasky uint8_t channel; 72267242Shselasky uint8_t tt_index; /* TT data */ 73266575Shselasky uint8_t tt_start_slot; /* TT data */ 74266575Shselasky uint8_t tt_complete_slot; /* TT data */ 75266575Shselasky uint8_t tt_xactpos; /* TT data */ 76240857Shselasky uint8_t state; 77240857Shselasky#define DWC_CHAN_ST_START 0 78240857Shselasky#define DWC_CHAN_ST_WAIT_ANE 1 79240857Shselasky#define DWC_CHAN_ST_WAIT_S_ANE 2 80240857Shselasky#define DWC_CHAN_ST_WAIT_C_ANE 3 81266575Shselasky#define DWC_CHAN_ST_WAIT_C_PKT 4 82266575Shselasky#define DWC_CHAN_ST_TX_PKT_ISOC 5 83266575Shselasky#define DWC_CHAN_ST_TX_WAIT_ISOC 6 84240279Shselasky uint8_t error_any:1; 85240279Shselasky uint8_t error_stall:1; 86230424Shselasky uint8_t alt_next:1; 87230424Shselasky uint8_t short_pkt:1; 88230424Shselasky uint8_t did_stall:1; 89240279Shselasky uint8_t toggle:1; 90240279Shselasky uint8_t set_toggle:1; 91240419Shselasky uint8_t got_short:1; 92266575Shselasky uint8_t tt_scheduled:1; 93230424Shselasky}; 94230424Shselasky 95267242Shselaskystruct dwc_otg_tt_info { 96267242Shselasky uint8_t slot_index; 97267242Shselasky}; 98267242Shselasky 99230424Shselaskystruct dwc_otg_std_temp { 100230424Shselasky dwc_otg_cmd_t *func; 101230424Shselasky struct usb_page_cache *pc; 102230424Shselasky struct dwc_otg_td *td; 103230424Shselasky struct dwc_otg_td *td_next; 104230424Shselasky uint32_t len; 105230424Shselasky uint32_t offset; 106230424Shselasky uint16_t max_frame_size; 107230424Shselasky uint8_t short_pkt; 108240279Shselasky 109230424Shselasky /* 110230424Shselasky * short_pkt = 0: transfer should be short terminated 111230424Shselasky * short_pkt = 1: transfer should not be short terminated 112230424Shselasky */ 113230424Shselasky uint8_t setup_alt_next; 114230424Shselasky uint8_t did_stall; 115230424Shselasky uint8_t bulk_or_control; 116230424Shselasky}; 117230424Shselasky 118230424Shselaskystruct dwc_otg_config_desc { 119230424Shselasky struct usb_config_descriptor confd; 120230424Shselasky struct usb_interface_descriptor ifcd; 121230424Shselasky struct usb_endpoint_descriptor endpd; 122230424Shselasky} __packed; 123230424Shselasky 124230424Shselaskyunion dwc_otg_hub_temp { 125230424Shselasky uWord wValue; 126230424Shselasky struct usb_port_status ps; 127230424Shselasky}; 128230424Shselasky 129230424Shselaskystruct dwc_otg_flags { 130230424Shselasky uint8_t change_connect:1; 131230424Shselasky uint8_t change_suspend:1; 132240279Shselasky uint8_t change_reset:1; 133240279Shselasky uint8_t change_enabled:1; 134240279Shselasky uint8_t change_over_current:1; 135230424Shselasky uint8_t status_suspend:1; /* set if suspended */ 136230424Shselasky uint8_t status_vbus:1; /* set if present */ 137230424Shselasky uint8_t status_bus_reset:1; /* set if reset complete */ 138230424Shselasky uint8_t status_high_speed:1; /* set if High Speed is selected */ 139240279Shselasky uint8_t status_low_speed:1; /* set if Low Speed is selected */ 140240279Shselasky uint8_t status_device_mode:1; /* set if device mode */ 141230424Shselasky uint8_t self_powered:1; 142230424Shselasky uint8_t clocks_off:1; 143230424Shselasky uint8_t port_powered:1; 144230424Shselasky uint8_t port_enabled:1; 145240279Shselasky uint8_t port_over_current:1; 146230424Shselasky uint8_t d_pulled_up:1; 147230424Shselasky}; 148230424Shselasky 149230424Shselaskystruct dwc_otg_profile { 150230424Shselasky struct usb_hw_ep_profile usb; 151230424Shselasky uint16_t max_buffer; 152230424Shselasky}; 153230424Shselasky 154240482Shselaskystruct dwc_otg_chan_state { 155266575Shselasky uint16_t allocated; 156266575Shselasky uint16_t wait_sof; 157240482Shselasky uint32_t hcint; 158266575Shselasky uint16_t tx_p_size; /* periodic */ 159266575Shselasky uint16_t tx_np_size; /* non-periodic */ 160240482Shselasky}; 161240482Shselasky 162230424Shselaskystruct dwc_otg_softc { 163230424Shselasky struct usb_bus sc_bus; 164230424Shselasky union dwc_otg_hub_temp sc_hub_temp; 165240279Shselasky struct dwc_otg_profile sc_hw_ep_profile[DWC_OTG_MAX_ENDPOINTS]; 166267242Shselasky struct dwc_otg_tt_info sc_tt_info[DWC_OTG_MAX_DEVICES]; 167240857Shselasky struct usb_callout sc_timer; 168230424Shselasky 169230424Shselasky struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES]; 170230424Shselasky struct resource *sc_io_res; 171230424Shselasky struct resource *sc_irq_res; 172230424Shselasky void *sc_intr_hdl; 173230424Shselasky bus_size_t sc_io_size; 174230424Shselasky bus_space_tag_t sc_io_tag; 175230424Shselasky bus_space_handle_t sc_io_hdl; 176230424Shselasky 177230424Shselasky uint32_t sc_rx_bounce_buffer[1024 / 4]; 178266575Shselasky uint32_t sc_tx_bounce_buffer[MAX(512 * DWC_OTG_MAX_TXP, 1024) / 4]; 179230424Shselasky 180230424Shselasky uint32_t sc_fifo_size; 181266575Shselasky uint32_t sc_tx_max_size; 182266575Shselasky uint32_t sc_tx_cur_p_level; /* periodic */ 183266575Shselasky uint32_t sc_tx_cur_np_level; /* non-periodic */ 184230424Shselasky uint32_t sc_irq_mask; 185230424Shselasky uint32_t sc_last_rx_status; 186240279Shselasky uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS]; 187240279Shselasky uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS]; 188240482Shselasky struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS]; 189240857Shselasky uint32_t sc_tmr_val; 190240279Shselasky uint32_t sc_hprt_val; 191266575Shselasky uint32_t sc_xfer_complete; 192230424Shselasky 193240279Shselasky uint16_t sc_active_rx_ep; 194266575Shselasky uint16_t sc_last_frame_num; 195230424Shselasky 196240857Shselasky uint8_t sc_timer_active; 197230424Shselasky uint8_t sc_dev_ep_max; 198230424Shselasky uint8_t sc_dev_in_ep_max; 199240279Shselasky uint8_t sc_host_ch_max; 200266575Shselasky uint8_t sc_needsof; 201230424Shselasky uint8_t sc_rt_addr; /* root HUB address */ 202230424Shselasky uint8_t sc_conf; /* root HUB config */ 203240279Shselasky uint8_t sc_mode; /* mode of operation */ 204240279Shselasky#define DWC_MODE_OTG 0 /* both modes */ 205240279Shselasky#define DWC_MODE_DEVICE 1 /* device only */ 206240279Shselasky#define DWC_MODE_HOST 2 /* host only */ 207230424Shselasky 208230424Shselasky uint8_t sc_hub_idata[1]; 209230424Shselasky 210230424Shselasky struct dwc_otg_flags sc_flags; 211230424Shselasky}; 212230424Shselasky 213230424Shselasky/* prototypes */ 214230424Shselasky 215266575Shselaskydriver_filter_t dwc_otg_filter_interrupt; 216266575Shselaskydriver_intr_t dwc_otg_interrupt; 217230424Shselaskyint dwc_otg_init(struct dwc_otg_softc *); 218230424Shselaskyvoid dwc_otg_uninit(struct dwc_otg_softc *); 219230424Shselasky 220230424Shselasky#endif /* _DWC_OTG_H_ */ 221