uart_dev_sab82532.c revision 155973
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_sab82532.c 155973 2006-02-24 05:40:17Z marcel $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> 37#include <dev/uart/uart_cpu.h> 38#include <dev/uart/uart_bus.h> 39 40#include <dev/ic/sab82532.h> 41 42#include "uart_if.h" 43 44#define DEFAULT_RCLK 29491200 45 46/* 47 * NOTE: To allow us to read the baudrate divisor from the chip, we 48 * copy the value written to the write-only BGR register to an unused 49 * read-write register. We use TCR for that. 50 */ 51 52static int 53sab82532_delay(struct uart_bas *bas) 54{ 55 int divisor, m, n; 56 uint8_t bgr, ccr2; 57 58 bgr = uart_getreg(bas, SAB_TCR); 59 ccr2 = uart_getreg(bas, SAB_CCR2); 60 n = (bgr & 0x3f) + 1; 61 m = (bgr >> 6) | ((ccr2 >> 4) & 0xC); 62 divisor = n * (1<<m); 63 64 /* 1/10th the time to transmit 1 character (estimate). */ 65 return (16000000 * divisor / bas->rclk); 66} 67 68static int 69sab82532_divisor(int rclk, int baudrate) 70{ 71 int act_baud, act_div, divisor; 72 int error, m, n; 73 74 if (baudrate == 0) 75 return (0); 76 77 divisor = (rclk / (baudrate << 3) + 1) >> 1; 78 if (divisor < 2 || divisor >= 1048576) 79 return (0); 80 81 /* Find the best (N+1,M) pair. */ 82 for (m = 1; m < 15; m++) { 83 n = divisor / (1<<m); 84 if (n < 1 || n > 63) 85 continue; 86 act_div = n * (1<<m); 87 act_baud = rclk / (act_div << 4); 88 89 /* 10 times error in percent: */ 90 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 91 92 /* 3.0% maximum error tolerance: */ 93 if (error < -30 || error > 30) 94 continue; 95 96 /* Got it. */ 97 return ((n - 1) | (m << 6)); 98 } 99 100 return (0); 101} 102 103static void 104sab82532_flush(struct uart_bas *bas, int what) 105{ 106 107 if (what & UART_FLUSH_TRANSMITTER) { 108 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 109 ; 110 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES); 111 uart_barrier(bas); 112 } 113 if (what & UART_FLUSH_RECEIVER) { 114 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 115 ; 116 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES); 117 uart_barrier(bas); 118 } 119} 120 121static int 122sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 123 int parity) 124{ 125 int divisor; 126 uint8_t ccr2, dafo; 127 128 if (databits >= 8) 129 dafo = SAB_DAFO_CHL_CS8; 130 else if (databits == 7) 131 dafo = SAB_DAFO_CHL_CS7; 132 else if (databits == 6) 133 dafo = SAB_DAFO_CHL_CS6; 134 else 135 dafo = SAB_DAFO_CHL_CS5; 136 if (stopbits > 1) 137 dafo |= SAB_DAFO_STOP; 138 switch (parity) { 139 case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break; 140 case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break; 141 case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break; 142 case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break; 143 case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break; 144 default: return (EINVAL); 145 } 146 147 /* Set baudrate. */ 148 if (baudrate > 0) { 149 divisor = sab82532_divisor(bas->rclk, baudrate); 150 if (divisor == 0) 151 return (EINVAL); 152 uart_setreg(bas, SAB_BGR, divisor & 0xff); 153 uart_barrier(bas); 154 /* Allow reading the (n-1,m) tuple from the chip. */ 155 uart_setreg(bas, SAB_TCR, divisor & 0xff); 156 uart_barrier(bas); 157 ccr2 = uart_getreg(bas, SAB_CCR2); 158 ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8); 159 ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8); 160 uart_setreg(bas, SAB_CCR2, ccr2); 161 uart_barrier(bas); 162 } 163 164 uart_setreg(bas, SAB_DAFO, dafo); 165 uart_barrier(bas); 166 return (0); 167} 168 169/* 170 * Low-level UART interface. 171 */ 172static int sab82532_probe(struct uart_bas *bas); 173static void sab82532_init(struct uart_bas *bas, int, int, int, int); 174static void sab82532_term(struct uart_bas *bas); 175static void sab82532_putc(struct uart_bas *bas, int); 176static int sab82532_poll(struct uart_bas *bas); 177static int sab82532_getc(struct uart_bas *bas); 178 179struct uart_ops uart_sab82532_ops = { 180 .probe = sab82532_probe, 181 .init = sab82532_init, 182 .term = sab82532_term, 183 .putc = sab82532_putc, 184 .poll = sab82532_poll, 185 .getc = sab82532_getc, 186}; 187 188static int 189sab82532_probe(struct uart_bas *bas) 190{ 191 192 return (0); 193} 194 195static void 196sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 197 int parity) 198{ 199 uint8_t ccr0, pvr; 200 201 if (bas->rclk == 0) 202 bas->rclk = DEFAULT_RCLK; 203 204 /* 205 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs. 206 * Pin 4 is magical, meaning that I don't know what it does, but 207 * it too has to be set to output. 208 */ 209 uart_setreg(bas, SAB_PCR, 210 ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC)); 211 uart_barrier(bas); 212 /* Disable port interrupts. */ 213 uart_setreg(bas, SAB_PIM, 0xff); 214 uart_barrier(bas); 215 /* Interrupts are active low. */ 216 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL); 217 uart_barrier(bas); 218 /* Set DTR. */ 219 pvr = uart_getreg(bas, SAB_PVR); 220 switch (bas->chan) { 221 case 1: 222 pvr &= ~SAB_PVR_DTR_A; 223 break; 224 case 2: 225 pvr &= ~SAB_PVR_DTR_B; 226 break; 227 } 228 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC); 229 uart_barrier(bas); 230 231 /* power down */ 232 uart_setreg(bas, SAB_CCR0, 0); 233 uart_barrier(bas); 234 235 /* set basic configuration */ 236 ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC; 237 uart_setreg(bas, SAB_CCR0, ccr0); 238 uart_barrier(bas); 239 uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7); 240 uart_barrier(bas); 241 uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE); 242 uart_barrier(bas); 243 uart_setreg(bas, SAB_CCR3, 0); 244 uart_barrier(bas); 245 uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD); 246 uart_barrier(bas); 247 uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC); 248 uart_barrier(bas); 249 uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF| 250 SAB_RFC_RFTH_32CHAR); 251 uart_barrier(bas); 252 253 sab82532_param(bas, baudrate, databits, stopbits, parity); 254 255 /* Clear interrupts. */ 256 uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD); 257 uart_setreg(bas, SAB_IMR1, 0xff); 258 uart_barrier(bas); 259 uart_getreg(bas, SAB_ISR0); 260 uart_getreg(bas, SAB_ISR1); 261 uart_barrier(bas); 262 263 sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER); 264 265 /* Power up. */ 266 uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU); 267 uart_barrier(bas); 268} 269 270static void 271sab82532_term(struct uart_bas *bas) 272{ 273 uint8_t pvr; 274 275 pvr = uart_getreg(bas, SAB_PVR); 276 switch (bas->chan) { 277 case 1: 278 pvr |= SAB_PVR_DTR_A; 279 break; 280 case 2: 281 pvr |= SAB_PVR_DTR_B; 282 break; 283 } 284 uart_setreg(bas, SAB_PVR, pvr); 285 uart_barrier(bas); 286} 287 288static void 289sab82532_putc(struct uart_bas *bas, int c) 290{ 291 int delay, limit; 292 293 /* 1/10th the time to transmit 1 character (estimate). */ 294 delay = sab82532_delay(bas); 295 296 limit = 20; 297 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) 298 DELAY(delay); 299 uart_setreg(bas, SAB_TIC, c); 300 limit = 20; 301 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) 302 DELAY(delay); 303} 304 305static int 306sab82532_poll(struct uart_bas *bas) 307{ 308 309 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) 310 return (sab82532_getc(bas)); 311 return (-1); 312} 313 314static int 315sab82532_getc(struct uart_bas *bas) 316{ 317 int c, delay; 318 319 /* 1/10th the time to transmit 1 character (estimate). */ 320 delay = sab82532_delay(bas); 321 322 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) 323 DELAY(delay); 324 325 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 326 ; 327 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); 328 uart_barrier(bas); 329 330 while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD)) 331 DELAY(delay); 332 333 c = uart_getreg(bas, SAB_RFIFO); 334 uart_barrier(bas); 335 336 /* Blow away everything left in the FIFO... */ 337 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 338 ; 339 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); 340 uart_barrier(bas); 341 return (c); 342} 343 344/* 345 * High-level UART interface. 346 */ 347struct sab82532_softc { 348 struct uart_softc base; 349}; 350 351static int sab82532_bus_attach(struct uart_softc *); 352static int sab82532_bus_detach(struct uart_softc *); 353static int sab82532_bus_flush(struct uart_softc *, int); 354static int sab82532_bus_getsig(struct uart_softc *); 355static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t); 356static int sab82532_bus_ipend(struct uart_softc *); 357static int sab82532_bus_param(struct uart_softc *, int, int, int, int); 358static int sab82532_bus_probe(struct uart_softc *); 359static int sab82532_bus_receive(struct uart_softc *); 360static int sab82532_bus_setsig(struct uart_softc *, int); 361static int sab82532_bus_transmit(struct uart_softc *); 362 363static kobj_method_t sab82532_methods[] = { 364 KOBJMETHOD(uart_attach, sab82532_bus_attach), 365 KOBJMETHOD(uart_detach, sab82532_bus_detach), 366 KOBJMETHOD(uart_flush, sab82532_bus_flush), 367 KOBJMETHOD(uart_getsig, sab82532_bus_getsig), 368 KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl), 369 KOBJMETHOD(uart_ipend, sab82532_bus_ipend), 370 KOBJMETHOD(uart_param, sab82532_bus_param), 371 KOBJMETHOD(uart_probe, sab82532_bus_probe), 372 KOBJMETHOD(uart_receive, sab82532_bus_receive), 373 KOBJMETHOD(uart_setsig, sab82532_bus_setsig), 374 KOBJMETHOD(uart_transmit, sab82532_bus_transmit), 375 { 0, 0 } 376}; 377 378struct uart_class uart_sab82532_class = { 379 "sab82532 class", 380 sab82532_methods, 381 sizeof(struct sab82532_softc), 382 .uc_range = 64, 383 .uc_rclk = DEFAULT_RCLK 384}; 385 386#define SIGCHG(c, i, s, d) \ 387 if (c) { \ 388 i |= (i & s) ? s : s | d; \ 389 } else { \ 390 i = (i & s) ? (i & ~s) | d : i; \ 391 } 392 393static int 394sab82532_bus_attach(struct uart_softc *sc) 395{ 396 struct uart_bas *bas; 397 uint8_t imr0, imr1; 398 399 bas = &sc->sc_bas; 400 if (sc->sc_sysdev == NULL) 401 sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE); 402 403 sc->sc_rxfifosz = 32; 404 sc->sc_txfifosz = 32; 405 406 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO| 407 SAB_IMR0_RPF; 408 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); 409 imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC; 410 uart_setreg(bas, SAB_IMR1, 0xff & ~imr1); 411 uart_barrier(bas); 412 413 if (sc->sc_sysdev == NULL) 414 sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS); 415 (void)sab82532_bus_getsig(sc); 416 return (0); 417} 418 419static int 420sab82532_bus_detach(struct uart_softc *sc) 421{ 422 struct uart_bas *bas; 423 424 bas = &sc->sc_bas; 425 uart_setreg(bas, SAB_IMR0, 0xff); 426 uart_setreg(bas, SAB_IMR1, 0xff); 427 uart_barrier(bas); 428 uart_getreg(bas, SAB_ISR0); 429 uart_getreg(bas, SAB_ISR1); 430 uart_barrier(bas); 431 uart_setreg(bas, SAB_CCR0, 0); 432 uart_barrier(bas); 433 return (0); 434} 435 436static int 437sab82532_bus_flush(struct uart_softc *sc, int what) 438{ 439 440 mtx_lock_spin(&sc->sc_hwmtx); 441 sab82532_flush(&sc->sc_bas, what); 442 mtx_unlock_spin(&sc->sc_hwmtx); 443 return (0); 444} 445 446static int 447sab82532_bus_getsig(struct uart_softc *sc) 448{ 449 struct uart_bas *bas; 450 uint32_t new, old, sig; 451 uint8_t pvr, star, vstr; 452 453 bas = &sc->sc_bas; 454 do { 455 old = sc->sc_hwsig; 456 sig = old; 457 mtx_lock_spin(&sc->sc_hwmtx); 458 star = uart_getreg(bas, SAB_STAR); 459 SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS); 460 vstr = uart_getreg(bas, SAB_VSTR); 461 SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD); 462 pvr = ~uart_getreg(bas, SAB_PVR); 463 switch (bas->chan) { 464 case 1: 465 pvr &= SAB_PVR_DSR_A; 466 break; 467 case 2: 468 pvr &= SAB_PVR_DSR_B; 469 break; 470 } 471 SIGCHG(pvr, sig, SER_DSR, SER_DDSR); 472 mtx_unlock_spin(&sc->sc_hwmtx); 473 new = sig & ~SER_MASK_DELTA; 474 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 475 return (sig); 476} 477 478static int 479sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 480{ 481 struct uart_bas *bas; 482 uint8_t dafo, mode; 483 int error; 484 485 bas = &sc->sc_bas; 486 error = 0; 487 mtx_lock_spin(&sc->sc_hwmtx); 488 switch (request) { 489 case UART_IOCTL_BREAK: 490 dafo = uart_getreg(bas, SAB_DAFO); 491 if (data) 492 dafo |= SAB_DAFO_XBRK; 493 else 494 dafo &= ~SAB_DAFO_XBRK; 495 uart_setreg(bas, SAB_DAFO, dafo); 496 uart_barrier(bas); 497 break; 498 case UART_IOCTL_IFLOW: 499 mode = uart_getreg(bas, SAB_MODE); 500 if (data) { 501 mode &= ~SAB_MODE_RTS; 502 mode |= SAB_MODE_FRTS; 503 } else { 504 mode |= SAB_MODE_RTS; 505 mode &= ~SAB_MODE_FRTS; 506 } 507 uart_setreg(bas, SAB_MODE, mode); 508 uart_barrier(bas); 509 break; 510 case UART_IOCTL_OFLOW: 511 mode = uart_getreg(bas, SAB_MODE); 512 if (data) 513 mode &= ~SAB_MODE_FCTS; 514 else 515 mode |= SAB_MODE_FCTS; 516 uart_setreg(bas, SAB_MODE, mode); 517 uart_barrier(bas); 518 break; 519 default: 520 error = EINVAL; 521 break; 522 } 523 mtx_unlock_spin(&sc->sc_hwmtx); 524 return (error); 525} 526 527static int 528sab82532_bus_ipend(struct uart_softc *sc) 529{ 530 struct uart_bas *bas; 531 int ipend; 532 uint8_t isr0, isr1; 533 534 bas = &sc->sc_bas; 535 mtx_lock_spin(&sc->sc_hwmtx); 536 isr0 = uart_getreg(bas, SAB_ISR0); 537 isr1 = uart_getreg(bas, SAB_ISR1); 538 uart_barrier(bas); 539 if (isr0 & SAB_ISR0_TIME) { 540 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 541 ; 542 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); 543 uart_barrier(bas); 544 } 545 mtx_unlock_spin(&sc->sc_hwmtx); 546 547 ipend = 0; 548 if (isr1 & SAB_ISR1_BRKT) 549 ipend |= SER_INT_BREAK; 550 if (isr0 & SAB_ISR0_RFO) 551 ipend |= SER_INT_OVERRUN; 552 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF)) 553 ipend |= SER_INT_RXREADY; 554 if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC)) 555 ipend |= SER_INT_SIGCHG; 556 if (isr1 & SAB_ISR1_ALLS) 557 ipend |= SER_INT_TXIDLE; 558 559 return (ipend); 560} 561 562static int 563sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits, 564 int stopbits, int parity) 565{ 566 struct uart_bas *bas; 567 int error; 568 569 bas = &sc->sc_bas; 570 mtx_lock_spin(&sc->sc_hwmtx); 571 error = sab82532_param(bas, baudrate, databits, stopbits, parity); 572 mtx_unlock_spin(&sc->sc_hwmtx); 573 return (error); 574} 575 576static int 577sab82532_bus_probe(struct uart_softc *sc) 578{ 579 char buf[80]; 580 const char *vstr; 581 int error; 582 char ch; 583 584 error = sab82532_probe(&sc->sc_bas); 585 if (error) 586 return (error); 587 588 ch = sc->sc_bas.chan - 1 + 'A'; 589 590 switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) { 591 case SAB_VSTR_V_1: 592 vstr = "v1"; 593 break; 594 case SAB_VSTR_V_2: 595 vstr = "v2"; 596 break; 597 case SAB_VSTR_V_32: 598 vstr = "v3.2"; 599 sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */ 600 sc->sc_hwoflow = 1; 601 break; 602 default: 603 vstr = "v4?"; 604 break; 605 } 606 607 snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch); 608 device_set_desc_copy(sc->sc_dev, buf); 609 return (0); 610} 611 612static int 613sab82532_bus_receive(struct uart_softc *sc) 614{ 615 struct uart_bas *bas; 616 int i, rbcl, xc; 617 uint8_t s; 618 619 bas = &sc->sc_bas; 620 mtx_lock_spin(&sc->sc_hwmtx); 621 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) { 622 rbcl = uart_getreg(bas, SAB_RBCL) & 31; 623 if (rbcl == 0) 624 rbcl = 32; 625 for (i = 0; i < rbcl; i += 2) { 626 if (uart_rx_full(sc)) { 627 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 628 break; 629 } 630 xc = uart_getreg(bas, SAB_RFIFO); 631 s = uart_getreg(bas, SAB_RFIFO + 1); 632 if (s & SAB_RSTAT_FE) 633 xc |= UART_STAT_FRAMERR; 634 if (s & SAB_RSTAT_PE) 635 xc |= UART_STAT_PARERR; 636 uart_rx_put(sc, xc); 637 } 638 } 639 640 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 641 ; 642 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); 643 uart_barrier(bas); 644 mtx_unlock_spin(&sc->sc_hwmtx); 645 return (0); 646} 647 648static int 649sab82532_bus_setsig(struct uart_softc *sc, int sig) 650{ 651 struct uart_bas *bas; 652 uint32_t new, old; 653 uint8_t mode, pvr; 654 655 bas = &sc->sc_bas; 656 do { 657 old = sc->sc_hwsig; 658 new = old; 659 if (sig & SER_DDTR) { 660 SIGCHG(sig & SER_DTR, new, SER_DTR, 661 SER_DDTR); 662 } 663 if (sig & SER_DRTS) { 664 SIGCHG(sig & SER_RTS, new, SER_RTS, 665 SER_DRTS); 666 } 667 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 668 669 mtx_lock_spin(&sc->sc_hwmtx); 670 /* Set DTR pin. */ 671 pvr = uart_getreg(bas, SAB_PVR); 672 switch (bas->chan) { 673 case 1: 674 if (new & SER_DTR) 675 pvr &= ~SAB_PVR_DTR_A; 676 else 677 pvr |= SAB_PVR_DTR_A; 678 break; 679 case 2: 680 if (new & SER_DTR) 681 pvr &= ~SAB_PVR_DTR_B; 682 else 683 pvr |= SAB_PVR_DTR_B; 684 break; 685 } 686 uart_setreg(bas, SAB_PVR, pvr); 687 688 /* Set RTS pin. */ 689 mode = uart_getreg(bas, SAB_MODE); 690 if (new & SER_RTS) 691 mode &= ~SAB_MODE_FRTS; 692 else 693 mode |= SAB_MODE_FRTS; 694 uart_setreg(bas, SAB_MODE, mode); 695 uart_barrier(bas); 696 mtx_unlock_spin(&sc->sc_hwmtx); 697 return (0); 698} 699 700static int 701sab82532_bus_transmit(struct uart_softc *sc) 702{ 703 struct uart_bas *bas; 704 int i; 705 706 bas = &sc->sc_bas; 707 mtx_lock_spin(&sc->sc_hwmtx); 708 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW)) 709 ; 710 for (i = 0; i < sc->sc_txdatasz; i++) 711 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]); 712 uart_barrier(bas); 713 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 714 ; 715 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF); 716 sc->sc_txbusy = 1; 717 mtx_unlock_spin(&sc->sc_hwmtx); 718 return (0); 719} 720