if_txp.c revision 121816
1309577Sglebius/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2309577Sglebius 3309577Sglebius/* 4309577Sglebius * Copyright (c) 2001 5309577Sglebius * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6309577Sglebius * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7309577Sglebius * 8309577Sglebius * Redistribution and use in source and binary forms, with or without 9309577Sglebius * modification, are permitted provided that the following conditions 10309577Sglebius * are met: 11309577Sglebius * 1. Redistributions of source code must retain the above copyright 12309577Sglebius * notice, this list of conditions and the following disclaimer. 13325322Sgordon * 2. Redistributions in binary form must reproduce the above copyright 14330568Sgordon * notice, this list of conditions and the following disclaimer in the 15325322Sgordon * documentation and/or other materials provided with the distribution. 16309577Sglebius * 3. All advertising materials mentioning features or use of this software 17309577Sglebius * must display the following acknowledgement: 18309577Sglebius * This product includes software developed by Jason L. Wright, 19309577Sglebius * Theo de Raadt and Aaron Campbell. 20309577Sglebius * 4. Neither the name of the author nor the names of any co-contributors 21330568Sgordon * may be used to endorse or promote products derived from this software 22309577Sglebius * without specific prior written permission. 23309577Sglebius * 24309577Sglebius * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 25309577Sglebius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26309577Sglebius * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27309577Sglebius * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28309577Sglebius * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29309577Sglebius * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30309577Sglebius * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31309577Sglebius * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32309577Sglebius * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33309577Sglebius * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34309577Sglebius * THE POSSIBILITY OF SUCH DAMAGE. 35309577Sglebius */ 36309577Sglebius 37309577Sglebius#include <sys/cdefs.h> 38309577Sglebius__FBSDID("$FreeBSD: head/sys/dev/txp/if_txp.c 121816 2003-10-31 18:32:15Z brooks $"); 39309577Sglebius 40309577Sglebius/* 41309577Sglebius * Driver for 3c990 (Typhoon) Ethernet ASIC 42309577Sglebius */ 43309577Sglebius 44309577Sglebius#include <sys/cdefs.h> 45309577Sglebius__FBSDID("$FreeBSD: head/sys/dev/txp/if_txp.c 121816 2003-10-31 18:32:15Z brooks $"); 46309577Sglebius 47309577Sglebius#include <sys/param.h> 48309577Sglebius#include <sys/systm.h> 49309577Sglebius#include <sys/sockio.h> 50309577Sglebius#include <sys/mbuf.h> 51309577Sglebius#include <sys/malloc.h> 52309577Sglebius#include <sys/kernel.h> 53#include <sys/socket.h> 54 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_types.h> 60#include <net/if_vlan_var.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/ip.h> 66#include <netinet/if_ether.h> 67#include <machine/in_cksum.h> 68 69#include <net/if_media.h> 70 71#include <net/bpf.h> 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/clock.h> /* for DELAY */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85#include <dev/pci/pcireg.h> 86#include <dev/pci/pcivar.h> 87 88#define TXP_USEIOSPACE 89#define __STRICT_ALIGNMENT 90 91#include <dev/txp/if_txpreg.h> 92#include <dev/txp/3c990img.h> 93 94#ifndef lint 95static const char rcsid[] = 96 "$FreeBSD: head/sys/dev/txp/if_txp.c 121816 2003-10-31 18:32:15Z brooks $"; 97#endif 98 99/* 100 * Various supported device vendors/types and their names. 101 */ 102static struct txp_type txp_devs[] = { 103 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 104 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 105 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 106 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 107 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 108 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 109 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 110 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 111 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 112 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 113 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 114 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 115 { 0, 0, NULL } 116}; 117 118static int txp_probe (device_t); 119static int txp_attach (device_t); 120static int txp_detach (device_t); 121static void txp_intr (void *); 122static void txp_tick (void *); 123static int txp_shutdown (device_t); 124static int txp_ioctl (struct ifnet *, u_long, caddr_t); 125static void txp_start (struct ifnet *); 126static void txp_stop (struct txp_softc *); 127static void txp_init (void *); 128static void txp_watchdog (struct ifnet *); 129 130static void txp_release_resources(struct txp_softc *); 131static int txp_chip_init(struct txp_softc *); 132static int txp_reset_adapter(struct txp_softc *); 133static int txp_download_fw(struct txp_softc *); 134static int txp_download_fw_wait(struct txp_softc *); 135static int txp_download_fw_section (struct txp_softc *, 136 struct txp_fw_section_header *, int); 137static int txp_alloc_rings(struct txp_softc *); 138static int txp_rxring_fill(struct txp_softc *); 139static void txp_rxring_empty(struct txp_softc *); 140static void txp_set_filter(struct txp_softc *); 141 142static int txp_cmd_desc_numfree(struct txp_softc *); 143static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 144 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 145static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 146 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 147 struct txp_rsp_desc **, int); 148static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 149 struct txp_rsp_desc **); 150static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 151 struct txp_rsp_desc *); 152static void txp_capabilities(struct txp_softc *); 153 154static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 155static int txp_ifmedia_upd(struct ifnet *); 156#ifdef TXP_DEBUG 157static void txp_show_descriptor(void *); 158#endif 159static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *); 160static void txp_rxbuf_reclaim(struct txp_softc *); 161static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *); 162 163#ifdef TXP_USEIOSPACE 164#define TXP_RES SYS_RES_IOPORT 165#define TXP_RID TXP_PCI_LOIO 166#else 167#define TXP_RES SYS_RES_MEMORY 168#define TXP_RID TXP_PCI_LOMEM 169#endif 170 171static device_method_t txp_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, txp_probe), 174 DEVMETHOD(device_attach, txp_attach), 175 DEVMETHOD(device_detach, txp_detach), 176 DEVMETHOD(device_shutdown, txp_shutdown), 177 { 0, 0 } 178}; 179 180static driver_t txp_driver = { 181 "txp", 182 txp_methods, 183 sizeof(struct txp_softc) 184}; 185 186static devclass_t txp_devclass; 187 188DRIVER_MODULE(txp, pci, txp_driver, txp_devclass, 0, 0); 189MODULE_DEPEND(txp, pci, 1, 1, 1); 190MODULE_DEPEND(txp, ether, 1, 1, 1); 191 192static int 193txp_probe(dev) 194 device_t dev; 195{ 196 struct txp_type *t; 197 198 t = txp_devs; 199 200 while(t->txp_name != NULL) { 201 if ((pci_get_vendor(dev) == t->txp_vid) && 202 (pci_get_device(dev) == t->txp_did)) { 203 device_set_desc(dev, t->txp_name); 204 return(0); 205 } 206 t++; 207 } 208 209 return(ENXIO); 210} 211 212static int 213txp_attach(dev) 214 device_t dev; 215{ 216 struct txp_softc *sc; 217 struct ifnet *ifp; 218 u_int16_t p1; 219 u_int32_t p2; 220 int unit, error = 0, rid; 221 222 sc = device_get_softc(dev); 223 unit = device_get_unit(dev); 224 sc->sc_dev = dev; 225 sc->sc_cold = 1; 226 227 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 228 MTX_DEF | MTX_RECURSE); 229#ifndef BURN_BRIDGES 230 /* 231 * Handle power management nonsense. 232 */ 233 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 234 u_int32_t iobase, membase, irq; 235 236 /* Save important PCI config data. */ 237 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 238 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 239 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 240 241 /* Reset the power state. */ 242 device_printf(dev, "chip is in D%d power mode " 243 "-- setting to D0\n", pci_get_powerstate(dev)); 244 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 245 246 /* Restore PCI config data. */ 247 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 248 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 249 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 250 } 251#endif 252 /* 253 * Map control/status registers. 254 */ 255 pci_enable_busmaster(dev); 256 257 rid = TXP_RID; 258 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 259 0, ~0, 1, RF_ACTIVE); 260 261 if (sc->sc_res == NULL) { 262 device_printf(dev, "couldn't map ports/memory\n"); 263 error = ENXIO; 264 goto fail; 265 } 266 267 sc->sc_bt = rman_get_bustag(sc->sc_res); 268 sc->sc_bh = rman_get_bushandle(sc->sc_res); 269 270 /* Allocate interrupt */ 271 rid = 0; 272 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 273 RF_SHAREABLE | RF_ACTIVE); 274 275 if (sc->sc_irq == NULL) { 276 device_printf(dev, "couldn't map interrupt\n"); 277 txp_release_resources(sc); 278 error = ENXIO; 279 goto fail; 280 } 281 282 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 283 txp_intr, sc, &sc->sc_intrhand); 284 285 if (error) { 286 txp_release_resources(sc); 287 device_printf(dev, "couldn't set up irq\n"); 288 goto fail; 289 } 290 291 if (txp_chip_init(sc)) { 292 txp_release_resources(sc); 293 goto fail; 294 } 295 296 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 297 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 298 error = txp_download_fw(sc); 299 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 300 sc->sc_fwbuf = NULL; 301 302 if (error) { 303 txp_release_resources(sc); 304 goto fail; 305 } 306 307 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 308 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 309 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 310 311 if (txp_alloc_rings(sc)) { 312 txp_release_resources(sc); 313 goto fail; 314 } 315 316 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 317 NULL, NULL, NULL, 1)) { 318 txp_release_resources(sc); 319 goto fail; 320 } 321 322 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 323 &p1, &p2, NULL, 1)) { 324 txp_release_resources(sc); 325 goto fail; 326 } 327 328 txp_set_filter(sc); 329 330 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 331 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 332 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 333 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 334 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 335 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 336 337 printf("txp%d: Ethernet address %6D\n", unit, 338 sc->sc_arpcom.ac_enaddr, ":"); 339 340 sc->sc_cold = 0; 341 342 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 343 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 344 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 345 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 346 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 347 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 348 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 349 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 350 351 sc->sc_xcvr = TXP_XCVR_AUTO; 352 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 353 NULL, NULL, NULL, 0); 354 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 355 356 ifp = &sc->sc_arpcom.ac_if; 357 ifp->if_softc = sc; 358 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 359 ifp->if_mtu = ETHERMTU; 360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 361 ifp->if_ioctl = txp_ioctl; 362 ifp->if_output = ether_output; 363 ifp->if_start = txp_start; 364 ifp->if_watchdog = txp_watchdog; 365 ifp->if_init = txp_init; 366 ifp->if_baudrate = 100000000; 367 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 368 ifp->if_hwassist = 0; 369 txp_capabilities(sc); 370 371 /* 372 * Attach us everywhere 373 */ 374 ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr); 375 callout_handle_init(&sc->sc_tick); 376 return(0); 377 378fail: 379 txp_release_resources(sc); 380 mtx_destroy(&sc->sc_mtx); 381 return(error); 382} 383 384static int 385txp_detach(dev) 386 device_t dev; 387{ 388 struct txp_softc *sc; 389 struct ifnet *ifp; 390 int i; 391 392 sc = device_get_softc(dev); 393 ifp = &sc->sc_arpcom.ac_if; 394 395 txp_stop(sc); 396 txp_shutdown(dev); 397 398 ifmedia_removeall(&sc->sc_ifmedia); 399 ether_ifdetach(ifp); 400 401 for (i = 0; i < RXBUF_ENTRIES; i++) 402 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 403 404 txp_release_resources(sc); 405 406 mtx_destroy(&sc->sc_mtx); 407 return(0); 408} 409 410static void 411txp_release_resources(sc) 412 struct txp_softc *sc; 413{ 414 device_t dev; 415 416 dev = sc->sc_dev; 417 418 if (sc->sc_intrhand != NULL) 419 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 420 421 if (sc->sc_irq != NULL) 422 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 423 424 if (sc->sc_res != NULL) 425 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 426 427 if (sc->sc_ldata != NULL) 428 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 429 430 return; 431} 432 433static int 434txp_chip_init(sc) 435 struct txp_softc *sc; 436{ 437 /* disable interrupts */ 438 WRITE_REG(sc, TXP_IER, 0); 439 WRITE_REG(sc, TXP_IMR, 440 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 441 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 442 TXP_INT_LATCH); 443 444 /* ack all interrupts */ 445 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 446 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 447 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 448 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 449 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 450 451 if (txp_reset_adapter(sc)) 452 return (-1); 453 454 /* disable interrupts */ 455 WRITE_REG(sc, TXP_IER, 0); 456 WRITE_REG(sc, TXP_IMR, 457 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 458 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 459 TXP_INT_LATCH); 460 461 /* ack all interrupts */ 462 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 463 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 464 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 465 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 466 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 467 468 return (0); 469} 470 471static int 472txp_reset_adapter(sc) 473 struct txp_softc *sc; 474{ 475 u_int32_t r; 476 int i; 477 478 r = 0; 479 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 480 DELAY(1000); 481 WRITE_REG(sc, TXP_SRR, 0); 482 483 /* Should wait max 6 seconds */ 484 for (i = 0; i < 6000; i++) { 485 r = READ_REG(sc, TXP_A2H_0); 486 if (r == STAT_WAITING_FOR_HOST_REQUEST) 487 break; 488 DELAY(1000); 489 } 490 491 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 492 device_printf(sc->sc_dev, "reset hung\n"); 493 return (-1); 494 } 495 496 return (0); 497} 498 499static int 500txp_download_fw(sc) 501 struct txp_softc *sc; 502{ 503 struct txp_fw_file_header *fileheader; 504 struct txp_fw_section_header *secthead; 505 int sect; 506 u_int32_t r, i, ier, imr; 507 508 r = 0; 509 ier = READ_REG(sc, TXP_IER); 510 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 511 512 imr = READ_REG(sc, TXP_IMR); 513 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 514 515 for (i = 0; i < 10000; i++) { 516 r = READ_REG(sc, TXP_A2H_0); 517 if (r == STAT_WAITING_FOR_HOST_REQUEST) 518 break; 519 DELAY(50); 520 } 521 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 522 device_printf(sc->sc_dev, "not waiting for host request\n"); 523 return (-1); 524 } 525 526 /* Ack the status */ 527 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 528 529 fileheader = (struct txp_fw_file_header *)tc990image; 530 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 531 device_printf(sc->sc_dev, "fw invalid magic\n"); 532 return (-1); 533 } 534 535 /* Tell boot firmware to get ready for image */ 536 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 537 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 538 539 if (txp_download_fw_wait(sc)) { 540 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 541 return (-1); 542 } 543 544 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 545 sizeof(struct txp_fw_file_header)); 546 547 for (sect = 0; sect < fileheader->nsections; sect++) { 548 if (txp_download_fw_section(sc, secthead, sect)) 549 return (-1); 550 secthead = (struct txp_fw_section_header *) 551 (((u_int8_t *)secthead) + secthead->nbytes + 552 sizeof(*secthead)); 553 } 554 555 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 556 557 for (i = 0; i < 10000; i++) { 558 r = READ_REG(sc, TXP_A2H_0); 559 if (r == STAT_WAITING_FOR_BOOT) 560 break; 561 DELAY(50); 562 } 563 if (r != STAT_WAITING_FOR_BOOT) { 564 device_printf(sc->sc_dev, "not waiting for boot\n"); 565 return (-1); 566 } 567 568 WRITE_REG(sc, TXP_IER, ier); 569 WRITE_REG(sc, TXP_IMR, imr); 570 571 return (0); 572} 573 574static int 575txp_download_fw_wait(sc) 576 struct txp_softc *sc; 577{ 578 u_int32_t i, r; 579 580 r = 0; 581 for (i = 0; i < 10000; i++) { 582 r = READ_REG(sc, TXP_ISR); 583 if (r & TXP_INT_A2H_0) 584 break; 585 DELAY(50); 586 } 587 588 if (!(r & TXP_INT_A2H_0)) { 589 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 590 return (-1); 591 } 592 593 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 594 595 r = READ_REG(sc, TXP_A2H_0); 596 if (r != STAT_WAITING_FOR_SEGMENT) { 597 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 598 return (-1); 599 } 600 return (0); 601} 602 603static int 604txp_download_fw_section(sc, sect, sectnum) 605 struct txp_softc *sc; 606 struct txp_fw_section_header *sect; 607 int sectnum; 608{ 609 vm_offset_t dma; 610 int rseg, err = 0; 611 struct mbuf m; 612 u_int16_t csum; 613 614 /* Skip zero length sections */ 615 if (sect->nbytes == 0) 616 return (0); 617 618 /* Make sure we aren't past the end of the image */ 619 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 620 if (rseg >= sizeof(tc990image)) { 621 device_printf(sc->sc_dev, "fw invalid section address, " 622 "section %d\n", sectnum); 623 return (-1); 624 } 625 626 /* Make sure this section doesn't go past the end */ 627 rseg += sect->nbytes; 628 if (rseg >= sizeof(tc990image)) { 629 device_printf(sc->sc_dev, "fw truncated section %d\n", 630 sectnum); 631 return (-1); 632 } 633 634 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 635 dma = vtophys(sc->sc_fwbuf); 636 637 /* 638 * dummy up mbuf and verify section checksum 639 */ 640 m.m_type = MT_DATA; 641 m.m_next = m.m_nextpkt = NULL; 642 m.m_len = sect->nbytes; 643 m.m_data = sc->sc_fwbuf; 644 m.m_flags = 0; 645 csum = in_cksum(&m, sect->nbytes); 646 if (csum != sect->cksum) { 647 device_printf(sc->sc_dev, "fw section %d, bad " 648 "cksum (expected 0x%x got 0x%x)\n", 649 sectnum, sect->cksum, csum); 650 err = -1; 651 goto bail; 652 } 653 654 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 655 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 656 WRITE_REG(sc, TXP_H2A_3, sect->addr); 657 WRITE_REG(sc, TXP_H2A_4, 0); 658 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 659 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 660 661 if (txp_download_fw_wait(sc)) { 662 device_printf(sc->sc_dev, "fw wait failed, " 663 "section %d\n", sectnum); 664 err = -1; 665 } 666 667bail: 668 return (err); 669} 670 671static void 672txp_intr(vsc) 673 void *vsc; 674{ 675 struct txp_softc *sc = vsc; 676 struct txp_hostvar *hv = sc->sc_hostvar; 677 u_int32_t isr; 678 679 /* mask all interrupts */ 680 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 681 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 682 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 683 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 684 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 685 686 isr = READ_REG(sc, TXP_ISR); 687 while (isr) { 688 WRITE_REG(sc, TXP_ISR, isr); 689 690 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 691 txp_rx_reclaim(sc, &sc->sc_rxhir); 692 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 693 txp_rx_reclaim(sc, &sc->sc_rxlor); 694 695 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 696 txp_rxbuf_reclaim(sc); 697 698 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 699 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 700 txp_tx_reclaim(sc, &sc->sc_txhir); 701 702 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 703 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 704 txp_tx_reclaim(sc, &sc->sc_txlor); 705 706 isr = READ_REG(sc, TXP_ISR); 707 } 708 709 /* unmask all interrupts */ 710 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 711 712 txp_start(&sc->sc_arpcom.ac_if); 713 714 return; 715} 716 717static void 718txp_rx_reclaim(sc, r) 719 struct txp_softc *sc; 720 struct txp_rx_ring *r; 721{ 722 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 723 struct txp_rx_desc *rxd; 724 struct mbuf *m; 725 struct txp_swdesc *sd = NULL; 726 u_int32_t roff, woff; 727 728 roff = *r->r_roff; 729 woff = *r->r_woff; 730 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 731 732 while (roff != woff) { 733 734 if (rxd->rx_flags & RX_FLAGS_ERROR) { 735 device_printf(sc->sc_dev, "error 0x%x\n", 736 rxd->rx_stat); 737 ifp->if_ierrors++; 738 goto next; 739 } 740 741 /* retrieve stashed pointer */ 742 sd = rxd->rx_sd; 743 744 m = sd->sd_mbuf; 745 sd->sd_mbuf = NULL; 746 747 m->m_pkthdr.len = m->m_len = rxd->rx_len; 748 749#ifdef __STRICT_ALIGNMENT 750 { 751 /* 752 * XXX Nice chip, except it won't accept "off by 2" 753 * buffers, so we're force to copy. Supposedly 754 * this will be fixed in a newer firmware rev 755 * and this will be temporary. 756 */ 757 struct mbuf *mnew; 758 759 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 760 if (mnew == NULL) { 761 m_freem(m); 762 goto next; 763 } 764 if (m->m_len > (MHLEN - 2)) { 765 MCLGET(mnew, M_DONTWAIT); 766 if (!(mnew->m_flags & M_EXT)) { 767 m_freem(mnew); 768 m_freem(m); 769 goto next; 770 } 771 } 772 mnew->m_pkthdr.rcvif = ifp; 773 m_adj(mnew, 2); 774 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 775 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 776 m_freem(m); 777 m = mnew; 778 } 779#endif 780 781 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 782 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 783 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 784 m->m_pkthdr.csum_flags |= 785 CSUM_IP_CHECKED|CSUM_IP_VALID; 786 787 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 788 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 789 m->m_pkthdr.csum_flags |= 790 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 791 m->m_pkthdr.csum_data = 0xffff; 792 } 793 794 if (rxd->rx_stat & RX_STAT_VLAN) { 795 VLAN_INPUT_TAG(ifp, 796 m, htons(rxd->rx_vlan >> 16), goto next); 797 } 798 799 (*ifp->if_input)(ifp, m); 800 801next: 802 803 roff += sizeof(struct txp_rx_desc); 804 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 805 roff = 0; 806 rxd = r->r_desc; 807 } else 808 rxd++; 809 woff = *r->r_woff; 810 } 811 812 *r->r_roff = woff; 813 814 return; 815} 816 817static void 818txp_rxbuf_reclaim(sc) 819 struct txp_softc *sc; 820{ 821 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 822 struct txp_hostvar *hv = sc->sc_hostvar; 823 struct txp_rxbuf_desc *rbd; 824 struct txp_swdesc *sd; 825 u_int32_t i; 826 827 if (!(ifp->if_flags & IFF_RUNNING)) 828 return; 829 830 i = sc->sc_rxbufprod; 831 rbd = sc->sc_rxbufs + i; 832 833 while (1) { 834 sd = rbd->rb_sd; 835 if (sd->sd_mbuf != NULL) 836 break; 837 838 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 839 if (sd->sd_mbuf == NULL) 840 goto err_sd; 841 842 MCLGET(sd->sd_mbuf, M_DONTWAIT); 843 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 844 goto err_mbuf; 845 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 846 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 847 848 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 849 & 0xffffffff; 850 rbd->rb_paddrhi = 0; 851 852 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 853 854 if (++i == RXBUF_ENTRIES) { 855 i = 0; 856 rbd = sc->sc_rxbufs; 857 } else 858 rbd++; 859 } 860 861 sc->sc_rxbufprod = i; 862 863 return; 864 865err_mbuf: 866 m_freem(sd->sd_mbuf); 867err_sd: 868 free(sd, M_DEVBUF); 869} 870 871/* 872 * Reclaim mbufs and entries from a transmit ring. 873 */ 874static void 875txp_tx_reclaim(sc, r) 876 struct txp_softc *sc; 877 struct txp_tx_ring *r; 878{ 879 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 880 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 881 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 882 struct txp_tx_desc *txd = r->r_desc + cons; 883 struct txp_swdesc *sd = sc->sc_txd + cons; 884 struct mbuf *m; 885 886 while (cons != idx) { 887 if (cnt == 0) 888 break; 889 890 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 891 TX_FLAGS_TYPE_DATA) { 892 m = sd->sd_mbuf; 893 if (m != NULL) { 894 m_freem(m); 895 txd->tx_addrlo = 0; 896 txd->tx_addrhi = 0; 897 ifp->if_opackets++; 898 } 899 } 900 ifp->if_flags &= ~IFF_OACTIVE; 901 902 if (++cons == TX_ENTRIES) { 903 txd = r->r_desc; 904 cons = 0; 905 sd = sc->sc_txd; 906 } else { 907 txd++; 908 sd++; 909 } 910 911 cnt--; 912 } 913 914 r->r_cons = cons; 915 r->r_cnt = cnt; 916 if (cnt == 0) 917 ifp->if_timer = 0; 918} 919 920static int 921txp_shutdown(dev) 922 device_t dev; 923{ 924 struct txp_softc *sc; 925 926 sc = device_get_softc(dev); 927 928 /* mask all interrupts */ 929 WRITE_REG(sc, TXP_IMR, 930 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 931 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 932 TXP_INT_LATCH); 933 934 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 935 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 936 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 937 938 return(0); 939} 940 941static int 942txp_alloc_rings(sc) 943 struct txp_softc *sc; 944{ 945 struct txp_boot_record *boot; 946 struct txp_ldata *ld; 947 u_int32_t r; 948 int i; 949 950 r = 0; 951 ld = sc->sc_ldata; 952 boot = &ld->txp_boot; 953 954 /* boot record */ 955 sc->sc_boot = boot; 956 957 /* host variables */ 958 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 959 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 960 boot->br_hostvar_hi = 0; 961 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 962 963 /* hi priority tx ring */ 964 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 965 boot->br_txhipri_hi = 0; 966 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 967 sc->sc_txhir.r_reg = TXP_H2A_1; 968 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 969 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 970 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 971 972 /* lo priority tx ring */ 973 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 974 boot->br_txlopri_hi = 0; 975 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 976 sc->sc_txlor.r_reg = TXP_H2A_3; 977 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 978 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 979 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 980 981 /* high priority rx ring */ 982 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 983 boot->br_rxhipri_hi = 0; 984 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 985 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 986 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 987 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 988 989 /* low priority rx ring */ 990 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 991 boot->br_rxlopri_hi = 0; 992 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 993 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 994 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 995 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 996 997 /* command ring */ 998 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 999 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 1000 boot->br_cmd_hi = 0; 1001 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1002 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1003 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1004 sc->sc_cmdring.lastwrite = 0; 1005 1006 /* response ring */ 1007 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1008 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1009 boot->br_resp_hi = 0; 1010 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1011 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1012 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1013 sc->sc_rspring.lastwrite = 0; 1014 1015 /* receive buffer ring */ 1016 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1017 boot->br_rxbuf_hi = 0; 1018 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1019 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1020 1021 for (i = 0; i < RXBUF_ENTRIES; i++) { 1022 struct txp_swdesc *sd; 1023 if (sc->sc_rxbufs[i].rb_sd != NULL) 1024 continue; 1025 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1026 M_DEVBUF, M_NOWAIT); 1027 if (sc->sc_rxbufs[i].rb_sd == NULL) 1028 return(ENOBUFS); 1029 sd = sc->sc_rxbufs[i].rb_sd; 1030 sd->sd_mbuf = NULL; 1031 } 1032 sc->sc_rxbufprod = 0; 1033 1034 /* zero dma */ 1035 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1036 boot->br_zero_lo = vtophys(&ld->txp_zero); 1037 boot->br_zero_hi = 0; 1038 1039 /* See if it's waiting for boot, and try to boot it */ 1040 for (i = 0; i < 10000; i++) { 1041 r = READ_REG(sc, TXP_A2H_0); 1042 if (r == STAT_WAITING_FOR_BOOT) 1043 break; 1044 DELAY(50); 1045 } 1046 1047 if (r != STAT_WAITING_FOR_BOOT) { 1048 device_printf(sc->sc_dev, "not waiting for boot\n"); 1049 return(ENXIO); 1050 } 1051 1052 WRITE_REG(sc, TXP_H2A_2, 0); 1053 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1054 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1055 1056 /* See if it booted */ 1057 for (i = 0; i < 10000; i++) { 1058 r = READ_REG(sc, TXP_A2H_0); 1059 if (r == STAT_RUNNING) 1060 break; 1061 DELAY(50); 1062 } 1063 if (r != STAT_RUNNING) { 1064 device_printf(sc->sc_dev, "fw not running\n"); 1065 return(ENXIO); 1066 } 1067 1068 /* Clear TX and CMD ring write registers */ 1069 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1070 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1071 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1072 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1073 1074 return (0); 1075} 1076 1077static int 1078txp_ioctl(ifp, command, data) 1079 struct ifnet *ifp; 1080 u_long command; 1081 caddr_t data; 1082{ 1083 struct txp_softc *sc = ifp->if_softc; 1084 struct ifreq *ifr = (struct ifreq *)data; 1085 int s, error = 0; 1086 1087 s = splnet(); 1088 1089 switch(command) { 1090 case SIOCSIFFLAGS: 1091 if (ifp->if_flags & IFF_UP) { 1092 txp_init(sc); 1093 } else { 1094 if (ifp->if_flags & IFF_RUNNING) 1095 txp_stop(sc); 1096 } 1097 break; 1098 case SIOCADDMULTI: 1099 case SIOCDELMULTI: 1100 /* 1101 * Multicast list has changed; set the hardware 1102 * filter accordingly. 1103 */ 1104 txp_set_filter(sc); 1105 error = 0; 1106 break; 1107 case SIOCGIFMEDIA: 1108 case SIOCSIFMEDIA: 1109 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1110 break; 1111 default: 1112 error = ether_ioctl(ifp, command, data); 1113 break; 1114 } 1115 1116 (void)splx(s); 1117 1118 return(error); 1119} 1120 1121static int 1122txp_rxring_fill(sc) 1123 struct txp_softc *sc; 1124{ 1125 int i; 1126 struct ifnet *ifp; 1127 struct txp_swdesc *sd; 1128 1129 ifp = &sc->sc_arpcom.ac_if; 1130 1131 for (i = 0; i < RXBUF_ENTRIES; i++) { 1132 sd = sc->sc_rxbufs[i].rb_sd; 1133 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1134 if (sd->sd_mbuf == NULL) 1135 return(ENOBUFS); 1136 1137 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1138 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1139 m_freem(sd->sd_mbuf); 1140 return(ENOBUFS); 1141 } 1142 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1143 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1144 1145 sc->sc_rxbufs[i].rb_paddrlo = 1146 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1147 sc->sc_rxbufs[i].rb_paddrhi = 0; 1148 } 1149 1150 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1151 sizeof(struct txp_rxbuf_desc); 1152 1153 return(0); 1154} 1155 1156static void 1157txp_rxring_empty(sc) 1158 struct txp_softc *sc; 1159{ 1160 int i; 1161 struct txp_swdesc *sd; 1162 1163 if (sc->sc_rxbufs == NULL) 1164 return; 1165 1166 for (i = 0; i < RXBUF_ENTRIES; i++) { 1167 if (&sc->sc_rxbufs[i] == NULL) 1168 continue; 1169 sd = sc->sc_rxbufs[i].rb_sd; 1170 if (sd == NULL) 1171 continue; 1172 if (sd->sd_mbuf != NULL) { 1173 m_freem(sd->sd_mbuf); 1174 sd->sd_mbuf = NULL; 1175 } 1176 } 1177 1178 return; 1179} 1180 1181static void 1182txp_init(xsc) 1183 void *xsc; 1184{ 1185 struct txp_softc *sc; 1186 struct ifnet *ifp; 1187 u_int16_t p1; 1188 u_int32_t p2; 1189 int s; 1190 1191 sc = xsc; 1192 ifp = &sc->sc_arpcom.ac_if; 1193 1194 if (ifp->if_flags & IFF_RUNNING) 1195 return; 1196 1197 txp_stop(sc); 1198 1199 s = splnet(); 1200 1201 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1202 NULL, NULL, NULL, 1); 1203 1204 /* Set station address. */ 1205 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1206 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1207 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1208 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1209 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1210 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1211 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1212 NULL, NULL, NULL, 1); 1213 1214 txp_set_filter(sc); 1215 1216 txp_rxring_fill(sc); 1217 1218 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1219 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1220 1221 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1222 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1223 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1224 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1225 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1226 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1227 1228 ifp->if_flags |= IFF_RUNNING; 1229 ifp->if_flags &= ~IFF_OACTIVE; 1230 ifp->if_timer = 0; 1231 1232 sc->sc_tick = timeout(txp_tick, sc, hz); 1233 1234 splx(s); 1235} 1236 1237static void 1238txp_tick(vsc) 1239 void *vsc; 1240{ 1241 struct txp_softc *sc = vsc; 1242 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1243 struct txp_rsp_desc *rsp = NULL; 1244 struct txp_ext_desc *ext; 1245 int s; 1246 1247 s = splnet(); 1248 txp_rxbuf_reclaim(sc); 1249 1250 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1251 &rsp, 1)) 1252 goto out; 1253 if (rsp->rsp_numdesc != 6) 1254 goto out; 1255 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1256 NULL, NULL, NULL, 1)) 1257 goto out; 1258 ext = (struct txp_ext_desc *)(rsp + 1); 1259 1260 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1261 ext[4].ext_1 + ext[4].ext_4; 1262 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1263 ext[2].ext_1; 1264 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1265 ext[1].ext_3; 1266 ifp->if_opackets += rsp->rsp_par2; 1267 ifp->if_ipackets += ext[2].ext_3; 1268 1269out: 1270 if (rsp != NULL) 1271 free(rsp, M_DEVBUF); 1272 1273 splx(s); 1274 sc->sc_tick = timeout(txp_tick, sc, hz); 1275 1276 return; 1277} 1278 1279static void 1280txp_start(ifp) 1281 struct ifnet *ifp; 1282{ 1283 struct txp_softc *sc = ifp->if_softc; 1284 struct txp_tx_ring *r = &sc->sc_txhir; 1285 struct txp_tx_desc *txd; 1286 struct txp_frag_desc *fxd; 1287 struct mbuf *m, *m0; 1288 struct txp_swdesc *sd; 1289 u_int32_t firstprod, firstcnt, prod, cnt; 1290 struct m_tag *mtag; 1291 1292 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1293 return; 1294 1295 prod = r->r_prod; 1296 cnt = r->r_cnt; 1297 1298 while (1) { 1299 IF_DEQUEUE(&ifp->if_snd, m); 1300 if (m == NULL) 1301 break; 1302 1303 firstprod = prod; 1304 firstcnt = cnt; 1305 1306 sd = sc->sc_txd + prod; 1307 sd->sd_mbuf = m; 1308 1309 if ((TX_ENTRIES - cnt) < 4) 1310 goto oactive; 1311 1312 txd = r->r_desc + prod; 1313 1314 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1315 txd->tx_numdesc = 0; 1316 txd->tx_addrlo = 0; 1317 txd->tx_addrhi = 0; 1318 txd->tx_totlen = 0; 1319 txd->tx_pflags = 0; 1320 1321 if (++prod == TX_ENTRIES) 1322 prod = 0; 1323 1324 if (++cnt >= (TX_ENTRIES - 4)) 1325 goto oactive; 1326 1327 mtag = VLAN_OUTPUT_TAG(ifp, m); 1328 if (mtag != NULL) { 1329 txd->tx_pflags = TX_PFLAGS_VLAN | 1330 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1331 } 1332 1333 if (m->m_pkthdr.csum_flags & CSUM_IP) 1334 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1335 1336#if 0 1337 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1338 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1339 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1340 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1341#endif 1342 1343 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1344 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1345 if (m0->m_len == 0) 1346 continue; 1347 if (++cnt >= (TX_ENTRIES - 4)) 1348 goto oactive; 1349 1350 txd->tx_numdesc++; 1351 1352 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1353 fxd->frag_rsvd1 = 0; 1354 fxd->frag_len = m0->m_len; 1355 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1356 fxd->frag_addrhi = 0; 1357 fxd->frag_rsvd2 = 0; 1358 1359 if (++prod == TX_ENTRIES) { 1360 fxd = (struct txp_frag_desc *)r->r_desc; 1361 prod = 0; 1362 } else 1363 fxd++; 1364 1365 } 1366 1367 ifp->if_timer = 5; 1368 1369 BPF_MTAP(ifp, m); 1370 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1371 } 1372 1373 r->r_prod = prod; 1374 r->r_cnt = cnt; 1375 return; 1376 1377oactive: 1378 ifp->if_flags |= IFF_OACTIVE; 1379 r->r_prod = firstprod; 1380 r->r_cnt = firstcnt; 1381 IF_PREPEND(&ifp->if_snd, m); 1382 return; 1383} 1384 1385/* 1386 * Handle simple commands sent to the typhoon 1387 */ 1388static int 1389txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1390 struct txp_softc *sc; 1391 u_int16_t id, in1, *out1; 1392 u_int32_t in2, in3, *out2, *out3; 1393 int wait; 1394{ 1395 struct txp_rsp_desc *rsp = NULL; 1396 1397 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1398 return (-1); 1399 1400 if (!wait) 1401 return (0); 1402 1403 if (out1 != NULL) 1404 *out1 = rsp->rsp_par1; 1405 if (out2 != NULL) 1406 *out2 = rsp->rsp_par2; 1407 if (out3 != NULL) 1408 *out3 = rsp->rsp_par3; 1409 free(rsp, M_DEVBUF); 1410 return (0); 1411} 1412 1413static int 1414txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1415 struct txp_softc *sc; 1416 u_int16_t id, in1; 1417 u_int32_t in2, in3; 1418 struct txp_ext_desc *in_extp; 1419 u_int8_t in_extn; 1420 struct txp_rsp_desc **rspp; 1421 int wait; 1422{ 1423 struct txp_hostvar *hv = sc->sc_hostvar; 1424 struct txp_cmd_desc *cmd; 1425 struct txp_ext_desc *ext; 1426 u_int32_t idx, i; 1427 u_int16_t seq; 1428 1429 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1430 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1431 return (-1); 1432 } 1433 1434 idx = sc->sc_cmdring.lastwrite; 1435 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1436 bzero(cmd, sizeof(*cmd)); 1437 1438 cmd->cmd_numdesc = in_extn; 1439 cmd->cmd_seq = seq = sc->sc_seq++; 1440 cmd->cmd_id = id; 1441 cmd->cmd_par1 = in1; 1442 cmd->cmd_par2 = in2; 1443 cmd->cmd_par3 = in3; 1444 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1445 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1446 1447 idx += sizeof(struct txp_cmd_desc); 1448 if (idx == sc->sc_cmdring.size) 1449 idx = 0; 1450 1451 for (i = 0; i < in_extn; i++) { 1452 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1453 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1454 in_extp++; 1455 idx += sizeof(struct txp_cmd_desc); 1456 if (idx == sc->sc_cmdring.size) 1457 idx = 0; 1458 } 1459 1460 sc->sc_cmdring.lastwrite = idx; 1461 1462 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1463 1464 if (!wait) 1465 return (0); 1466 1467 for (i = 0; i < 10000; i++) { 1468 idx = hv->hv_resp_read_idx; 1469 if (idx != hv->hv_resp_write_idx) { 1470 *rspp = NULL; 1471 if (txp_response(sc, idx, id, seq, rspp)) 1472 return (-1); 1473 if (*rspp != NULL) 1474 break; 1475 } 1476 DELAY(50); 1477 } 1478 if (i == 1000 || (*rspp) == NULL) { 1479 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1480 return (-1); 1481 } 1482 1483 return (0); 1484} 1485 1486static int 1487txp_response(sc, ridx, id, seq, rspp) 1488 struct txp_softc *sc; 1489 u_int32_t ridx; 1490 u_int16_t id; 1491 u_int16_t seq; 1492 struct txp_rsp_desc **rspp; 1493{ 1494 struct txp_hostvar *hv = sc->sc_hostvar; 1495 struct txp_rsp_desc *rsp; 1496 1497 while (ridx != hv->hv_resp_write_idx) { 1498 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1499 1500 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1501 *rspp = (struct txp_rsp_desc *)malloc( 1502 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1503 M_DEVBUF, M_NOWAIT); 1504 if ((*rspp) == NULL) 1505 return (-1); 1506 txp_rsp_fixup(sc, rsp, *rspp); 1507 return (0); 1508 } 1509 1510 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1511 device_printf(sc->sc_dev, "response error!\n"); 1512 txp_rsp_fixup(sc, rsp, NULL); 1513 ridx = hv->hv_resp_read_idx; 1514 continue; 1515 } 1516 1517 switch (rsp->rsp_id) { 1518 case TXP_CMD_CYCLE_STATISTICS: 1519 case TXP_CMD_MEDIA_STATUS_READ: 1520 break; 1521 case TXP_CMD_HELLO_RESPONSE: 1522 device_printf(sc->sc_dev, "hello\n"); 1523 break; 1524 default: 1525 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1526 rsp->rsp_id); 1527 } 1528 1529 txp_rsp_fixup(sc, rsp, NULL); 1530 ridx = hv->hv_resp_read_idx; 1531 hv->hv_resp_read_idx = ridx; 1532 } 1533 1534 return (0); 1535} 1536 1537static void 1538txp_rsp_fixup(sc, rsp, dst) 1539 struct txp_softc *sc; 1540 struct txp_rsp_desc *rsp, *dst; 1541{ 1542 struct txp_rsp_desc *src = rsp; 1543 struct txp_hostvar *hv = sc->sc_hostvar; 1544 u_int32_t i, ridx; 1545 1546 ridx = hv->hv_resp_read_idx; 1547 1548 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1549 if (dst != NULL) 1550 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1551 ridx += sizeof(struct txp_rsp_desc); 1552 if (ridx == sc->sc_rspring.size) { 1553 src = sc->sc_rspring.base; 1554 ridx = 0; 1555 } else 1556 src++; 1557 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1558 } 1559 1560 hv->hv_resp_read_idx = ridx; 1561} 1562 1563static int 1564txp_cmd_desc_numfree(sc) 1565 struct txp_softc *sc; 1566{ 1567 struct txp_hostvar *hv = sc->sc_hostvar; 1568 struct txp_boot_record *br = sc->sc_boot; 1569 u_int32_t widx, ridx, nfree; 1570 1571 widx = sc->sc_cmdring.lastwrite; 1572 ridx = hv->hv_cmd_read_idx; 1573 1574 if (widx == ridx) { 1575 /* Ring is completely free */ 1576 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1577 } else { 1578 if (widx > ridx) 1579 nfree = br->br_cmd_siz - 1580 (widx - ridx + sizeof(struct txp_cmd_desc)); 1581 else 1582 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1583 } 1584 1585 return (nfree / sizeof(struct txp_cmd_desc)); 1586} 1587 1588static void 1589txp_stop(sc) 1590 struct txp_softc *sc; 1591{ 1592 struct ifnet *ifp; 1593 1594 ifp = &sc->sc_arpcom.ac_if; 1595 1596 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1597 1598 untimeout(txp_tick, sc, sc->sc_tick); 1599 1600 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1601 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1602 1603 txp_rxring_empty(sc); 1604 1605 return; 1606} 1607 1608static void 1609txp_watchdog(ifp) 1610 struct ifnet *ifp; 1611{ 1612 return; 1613} 1614 1615static int 1616txp_ifmedia_upd(ifp) 1617 struct ifnet *ifp; 1618{ 1619 struct txp_softc *sc = ifp->if_softc; 1620 struct ifmedia *ifm = &sc->sc_ifmedia; 1621 u_int16_t new_xcvr; 1622 1623 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1624 return (EINVAL); 1625 1626 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1627 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1628 new_xcvr = TXP_XCVR_10_FDX; 1629 else 1630 new_xcvr = TXP_XCVR_10_HDX; 1631 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1632 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1633 new_xcvr = TXP_XCVR_100_FDX; 1634 else 1635 new_xcvr = TXP_XCVR_100_HDX; 1636 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1637 new_xcvr = TXP_XCVR_AUTO; 1638 } else 1639 return (EINVAL); 1640 1641 /* nothing to do */ 1642 if (sc->sc_xcvr == new_xcvr) 1643 return (0); 1644 1645 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1646 NULL, NULL, NULL, 0); 1647 sc->sc_xcvr = new_xcvr; 1648 1649 return (0); 1650} 1651 1652static void 1653txp_ifmedia_sts(ifp, ifmr) 1654 struct ifnet *ifp; 1655 struct ifmediareq *ifmr; 1656{ 1657 struct txp_softc *sc = ifp->if_softc; 1658 struct ifmedia *ifm = &sc->sc_ifmedia; 1659 u_int16_t bmsr, bmcr, anlpar; 1660 1661 ifmr->ifm_status = IFM_AVALID; 1662 ifmr->ifm_active = IFM_ETHER; 1663 1664 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1665 &bmsr, NULL, NULL, 1)) 1666 goto bail; 1667 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1668 &bmsr, NULL, NULL, 1)) 1669 goto bail; 1670 1671 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1672 &bmcr, NULL, NULL, 1)) 1673 goto bail; 1674 1675 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1676 &anlpar, NULL, NULL, 1)) 1677 goto bail; 1678 1679 if (bmsr & BMSR_LINK) 1680 ifmr->ifm_status |= IFM_ACTIVE; 1681 1682 if (bmcr & BMCR_ISO) { 1683 ifmr->ifm_active |= IFM_NONE; 1684 ifmr->ifm_status = 0; 1685 return; 1686 } 1687 1688 if (bmcr & BMCR_LOOP) 1689 ifmr->ifm_active |= IFM_LOOP; 1690 1691 if (bmcr & BMCR_AUTOEN) { 1692 if ((bmsr & BMSR_ACOMP) == 0) { 1693 ifmr->ifm_active |= IFM_NONE; 1694 return; 1695 } 1696 1697 if (anlpar & ANLPAR_T4) 1698 ifmr->ifm_active |= IFM_100_T4; 1699 else if (anlpar & ANLPAR_TX_FD) 1700 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1701 else if (anlpar & ANLPAR_TX) 1702 ifmr->ifm_active |= IFM_100_TX; 1703 else if (anlpar & ANLPAR_10_FD) 1704 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1705 else if (anlpar & ANLPAR_10) 1706 ifmr->ifm_active |= IFM_10_T; 1707 else 1708 ifmr->ifm_active |= IFM_NONE; 1709 } else 1710 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1711 return; 1712 1713bail: 1714 ifmr->ifm_active |= IFM_NONE; 1715 ifmr->ifm_status &= ~IFM_AVALID; 1716} 1717 1718#ifdef TXP_DEBUG 1719static void 1720txp_show_descriptor(d) 1721 void *d; 1722{ 1723 struct txp_cmd_desc *cmd = d; 1724 struct txp_rsp_desc *rsp = d; 1725 struct txp_tx_desc *txd = d; 1726 struct txp_frag_desc *frgd = d; 1727 1728 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1729 case CMD_FLAGS_TYPE_CMD: 1730 /* command descriptor */ 1731 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1732 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1733 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1734 break; 1735 case CMD_FLAGS_TYPE_RESP: 1736 /* response descriptor */ 1737 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1738 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1739 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1740 break; 1741 case CMD_FLAGS_TYPE_DATA: 1742 /* data header (assuming tx for now) */ 1743 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1744 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1745 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1746 break; 1747 case CMD_FLAGS_TYPE_FRAG: 1748 /* fragment descriptor */ 1749 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1750 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1751 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1752 break; 1753 default: 1754 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1755 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1756 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1757 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1758 break; 1759 } 1760} 1761#endif 1762 1763static void 1764txp_set_filter(sc) 1765 struct txp_softc *sc; 1766{ 1767 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1768 u_int32_t crc, carry, hashbit, hash[2]; 1769 u_int16_t filter; 1770 u_int8_t octet; 1771 int i, j, mcnt = 0; 1772 struct ifmultiaddr *ifma; 1773 char *enm; 1774 1775 if (ifp->if_flags & IFF_PROMISC) { 1776 filter = TXP_RXFILT_PROMISC; 1777 goto setit; 1778 } 1779 1780 filter = TXP_RXFILT_DIRECT; 1781 1782 if (ifp->if_flags & IFF_BROADCAST) 1783 filter |= TXP_RXFILT_BROADCAST; 1784 1785 if (ifp->if_flags & IFF_ALLMULTI) 1786 filter |= TXP_RXFILT_ALLMULTI; 1787 else { 1788 hash[0] = hash[1] = 0; 1789 1790 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1791 if (ifma->ifma_addr->sa_family != AF_LINK) 1792 continue; 1793 1794 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1795 mcnt++; 1796 crc = 0xffffffff; 1797 1798 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1799 octet = enm[i]; 1800 for (j = 0; j < 8; j++) { 1801 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1802 (octet & 1); 1803 crc <<= 1; 1804 octet >>= 1; 1805 if (carry) 1806 crc = (crc ^ TXP_POLYNOMIAL) | 1807 carry; 1808 } 1809 } 1810 hashbit = (u_int16_t)(crc & (64 - 1)); 1811 hash[hashbit / 32] |= (1 << hashbit % 32); 1812 } 1813 1814 if (mcnt > 0) { 1815 filter |= TXP_RXFILT_HASHMULTI; 1816 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1817 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1818 } 1819 } 1820 1821setit: 1822 1823 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1824 NULL, NULL, NULL, 1); 1825 1826 return; 1827} 1828 1829static void 1830txp_capabilities(sc) 1831 struct txp_softc *sc; 1832{ 1833 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1834 struct txp_rsp_desc *rsp = NULL; 1835 struct txp_ext_desc *ext; 1836 1837 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1838 goto out; 1839 1840 if (rsp->rsp_numdesc != 1) 1841 goto out; 1842 ext = (struct txp_ext_desc *)(rsp + 1); 1843 1844 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1845 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1846 ifp->if_capabilities = 0; 1847 1848 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1849 sc->sc_tx_capability |= OFFLOAD_VLAN; 1850 sc->sc_rx_capability |= OFFLOAD_VLAN; 1851 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1852 } 1853 1854#if 0 1855 /* not ready yet */ 1856 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1857 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1858 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1859 ifp->if_capabilities |= IFCAP_IPSEC; 1860 } 1861#endif 1862 1863 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1864 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1865 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1866 ifp->if_capabilities |= IFCAP_HWCSUM; 1867 ifp->if_hwassist |= CSUM_IP; 1868 } 1869 1870 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1871#if 0 1872 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1873#endif 1874 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1875 ifp->if_capabilities |= IFCAP_HWCSUM; 1876 } 1877 1878 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1879#if 0 1880 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1881#endif 1882 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1883 ifp->if_capabilities |= IFCAP_HWCSUM; 1884 } 1885 ifp->if_capenable = ifp->if_capabilities; 1886 1887 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1888 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1889 goto out; 1890 1891out: 1892 if (rsp != NULL) 1893 free(rsp, M_DEVBUF); 1894 1895 return; 1896} 1897