ich.c revision 152420
1/*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <dev/sound/pcm/sound.h> 29#include <dev/sound/pcm/ac97.h> 30#include <dev/sound/pci/ich.h> 31 32#include <dev/pci/pcireg.h> 33#include <dev/pci/pcivar.h> 34 35SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 152420 2005-11-14 18:18:12Z ariff $"); 36 37/* -------------------------------------------------------------------- */ 38 39#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40#define ICH_DTBL_LENGTH 32 41#define ICH_DEFAULT_BUFSZ 16384 42#define ICH_MAX_BUFSZ 65536 43 44#define INTEL_VENDORID 0x8086 45#define SIS_VENDORID 0x1039 46#define NVIDIA_VENDORID 0x10de 47#define AMD_VENDORID 0x1022 48 49#define INTEL_82440MX 0x7195 50#define INTEL_82801AA 0x2415 51#define INTEL_82801AB 0x2425 52#define INTEL_82801BA 0x2445 53#define INTEL_82801CA 0x2485 54#define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 55#define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 56#define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 57#define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 58#define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 59#define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 60#define NVIDIA_NFORCE 0x01b1 61#define NVIDIA_NFORCE2 0x006a 62#define NVIDIA_NFORCE2_400 0x008a 63#define NVIDIA_NFORCE3 0x00da 64#define NVIDIA_NFORCE3_250 0x00ea 65#define NVIDIA_NFORCE4 0x0059 66#define AMD_768 0x7445 67#define AMD_8111 0x746d 68 69#define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 70#define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 71#define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 72 73static const struct ich_type { 74 uint16_t vendor; 75 uint16_t devid; 76 uint32_t options; 77#define PROBE_LOW 0x01 78 char *name; 79} ich_devs[] = { 80 { INTEL_VENDORID, INTEL_82440MX, 0, 81 "Intel 440MX" }, 82 { INTEL_VENDORID, INTEL_82801AA, 0, 83 "Intel ICH (82801AA)" }, 84 { INTEL_VENDORID, INTEL_82801AB, 0, 85 "Intel ICH (82801AB)" }, 86 { INTEL_VENDORID, INTEL_82801BA, 0, 87 "Intel ICH2 (82801BA)" }, 88 { INTEL_VENDORID, INTEL_82801CA, 0, 89 "Intel ICH3 (82801CA)" }, 90 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 91 "Intel ICH4 (82801DB)" }, 92 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 93 "Intel ICH5 (82801EB)" }, 94 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 95 "Intel 6300ESB" }, 96 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 97 "Intel ICH6 (82801FB)" }, 98 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 99 "Intel ICH7 (82801GB)" }, 100 { SIS_VENDORID, SIS_7012, 0, 101 "SiS 7012" }, 102 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 103 "nVidia nForce" }, 104 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 105 "nVidia nForce2" }, 106 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 107 "nVidia nForce2 400" }, 108 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 109 "nVidia nForce3" }, 110 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 111 "nVidia nForce3 250" }, 112 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 113 "nVidia nForce4" }, 114 { AMD_VENDORID, AMD_768, 0, 115 "AMD-768" }, 116 { AMD_VENDORID, AMD_8111, 0, 117 "AMD-8111" } 118}; 119 120/* buffer descriptor */ 121struct ich_desc { 122 volatile u_int32_t buffer; 123 volatile u_int32_t length; 124}; 125 126struct sc_info; 127 128/* channel registers */ 129struct sc_chinfo { 130 u_int32_t num:8, run:1, run_save:1; 131 u_int32_t blksz, blkcnt, spd; 132 u_int32_t regbase, spdreg; 133 u_int32_t imask; 134 u_int32_t civ; 135 136 struct snd_dbuf *buffer; 137 struct pcm_channel *channel; 138 struct sc_info *parent; 139 140 struct ich_desc *dtbl; 141 bus_addr_t desc_addr; 142}; 143 144/* device private data */ 145struct sc_info { 146 device_t dev; 147 int hasvra, hasvrm, hasmic; 148 unsigned int chnum, bufsz; 149 int sample_size, swap_reg; 150 151 struct resource *nambar, *nabmbar, *irq; 152 int regtype, nambarid, nabmbarid, irqid; 153 bus_space_tag_t nambart, nabmbart; 154 bus_space_handle_t nambarh, nabmbarh; 155 bus_dma_tag_t dmat; 156 bus_dmamap_t dtmap; 157 void *ih; 158 159 struct ac97_info *codec; 160 struct sc_chinfo ch[3]; 161 int ac97rate; 162 struct ich_desc *dtbl; 163 bus_addr_t desc_addr; 164 struct intr_config_hook intrhook; 165 int use_intrhook; 166 uint16_t vendor; 167 uint16_t devid; 168 struct mtx *ich_lock; 169}; 170 171/* -------------------------------------------------------------------- */ 172 173static u_int32_t ich_fmt[] = { 174 AFMT_STEREO | AFMT_S16_LE, 175 0 176}; 177static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 178static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 179 180/* -------------------------------------------------------------------- */ 181/* Hardware */ 182static __inline u_int32_t 183ich_rd(struct sc_info *sc, int regno, int size) 184{ 185 switch (size) { 186 case 1: 187 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 188 case 2: 189 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 190 case 4: 191 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 192 default: 193 return 0xffffffff; 194 } 195} 196 197static __inline void 198ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 199{ 200 switch (size) { 201 case 1: 202 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 203 break; 204 case 2: 205 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 206 break; 207 case 4: 208 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 209 break; 210 } 211} 212 213/* ac97 codec */ 214static int 215ich_waitcd(void *devinfo) 216{ 217 int i; 218 u_int32_t data; 219 struct sc_info *sc = (struct sc_info *)devinfo; 220 221 for (i = 0; i < ICH_TIMEOUT; i++) { 222 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 223 if ((data & 0x01) == 0) 224 return 0; 225 } 226 device_printf(sc->dev, "CODEC semaphore timeout\n"); 227 return ETIMEDOUT; 228} 229 230static int 231ich_rdcd(kobj_t obj, void *devinfo, int regno) 232{ 233 struct sc_info *sc = (struct sc_info *)devinfo; 234 235 regno &= 0xff; 236 ich_waitcd(sc); 237 238 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 239} 240 241static int 242ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 243{ 244 struct sc_info *sc = (struct sc_info *)devinfo; 245 246 regno &= 0xff; 247 ich_waitcd(sc); 248 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 249 250 return 0; 251} 252 253static kobj_method_t ich_ac97_methods[] = { 254 KOBJMETHOD(ac97_read, ich_rdcd), 255 KOBJMETHOD(ac97_write, ich_wrcd), 256 { 0, 0 } 257}; 258AC97_DECLARE(ich_ac97); 259 260/* -------------------------------------------------------------------- */ 261/* common routines */ 262 263static void 264ich_filldtbl(struct sc_chinfo *ch) 265{ 266 struct sc_info *sc = ch->parent; 267 u_int32_t base; 268 int i; 269 270 base = sndbuf_getbufaddr(ch->buffer); 271 if (ch->blksz > sc->bufsz / ch->blkcnt) 272 ch->blksz = sc->bufsz / ch->blkcnt; 273 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz); 274 ch->blksz = sndbuf_getblksz(ch->buffer); 275 276 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 277 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 278 ch->dtbl[i].length = ICH_BDC_IOC 279 | (ch->blksz / ch->parent->sample_size); 280 } 281} 282 283static int 284ich_resetchan(struct sc_info *sc, int num) 285{ 286 int i, cr, regbase; 287 288 if (num == 0) 289 regbase = ICH_REG_PO_BASE; 290 else if (num == 1) 291 regbase = ICH_REG_PI_BASE; 292 else if (num == 2) 293 regbase = ICH_REG_MC_BASE; 294 else 295 return ENXIO; 296 297 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 298#if 1 299 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 300 DELAY(100); 301#else 302 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 303#endif 304 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 305 for (i = 0; i < ICH_TIMEOUT; i++) { 306 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 307 if (cr == 0) 308 return 0; 309 } 310 311 device_printf(sc->dev, "cannot reset channel %d\n", num); 312 return ENXIO; 313} 314 315/* -------------------------------------------------------------------- */ 316/* channel interface */ 317 318static void * 319ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 320{ 321 struct sc_info *sc = devinfo; 322 struct sc_chinfo *ch; 323 unsigned int num; 324 325 ICH_LOCK(sc); 326 num = sc->chnum++; 327 ch = &sc->ch[num]; 328 ch->num = num; 329 ch->buffer = b; 330 ch->channel = c; 331 ch->parent = sc; 332 ch->run = 0; 333 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 334 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 335 sizeof(struct ich_desc); 336 ch->blkcnt = 2; 337 ch->blksz = sc->bufsz / ch->blkcnt; 338 339 switch(ch->num) { 340 case 0: /* play */ 341 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 342 ch->regbase = ICH_REG_PO_BASE; 343 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 344 ch->imask = ICH_GLOB_STA_POINT; 345 break; 346 347 case 1: /* record */ 348 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 349 ch->regbase = ICH_REG_PI_BASE; 350 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 351 ch->imask = ICH_GLOB_STA_PIINT; 352 break; 353 354 case 2: /* mic */ 355 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 356 ch->regbase = ICH_REG_MC_BASE; 357 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 358 ch->imask = ICH_GLOB_STA_MINT; 359 break; 360 361 default: 362 return NULL; 363 } 364 365 ICH_UNLOCK(sc); 366 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 367 return NULL; 368 369 ICH_LOCK(sc); 370 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 371 ICH_UNLOCK(sc); 372 373 return ch; 374} 375 376static int 377ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 378{ 379 return 0; 380} 381 382static int 383ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 384{ 385 struct sc_chinfo *ch = data; 386 struct sc_info *sc = ch->parent; 387 388 if (ch->spdreg) { 389 int r, ac97rate; 390 391 ICH_LOCK(sc); 392 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 393 sc->ac97rate = 48000; 394 ac97rate = sc->ac97rate; 395 ICH_UNLOCK(sc); 396 r = (speed * 48000) / ac97rate; 397 /* 398 * Cast the return value of ac97_setrate() to u_int so that 399 * the math don't overflow into the negative range. 400 */ 401 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 402 ac97rate) / 48000; 403 } else { 404 ch->spd = 48000; 405 } 406 return ch->spd; 407} 408 409static int 410ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 411{ 412 struct sc_chinfo *ch = data; 413 struct sc_info *sc = ch->parent; 414 415 ch->blksz = blocksize; 416 ich_filldtbl(ch); 417 ICH_LOCK(sc); 418 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 419 ICH_UNLOCK(sc); 420 421 return ch->blksz; 422} 423 424static int 425ichchan_trigger(kobj_t obj, void *data, int go) 426{ 427 struct sc_chinfo *ch = data; 428 struct sc_info *sc = ch->parent; 429 430 switch (go) { 431 case PCMTRIG_START: 432 ch->run = 1; 433 ICH_LOCK(sc); 434 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 435 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 436 ICH_UNLOCK(sc); 437 break; 438 439 case PCMTRIG_ABORT: 440 ICH_LOCK(sc); 441 ich_resetchan(sc, ch->num); 442 ICH_UNLOCK(sc); 443 ch->run = 0; 444 break; 445 } 446 return 0; 447} 448 449static int 450ichchan_getptr(kobj_t obj, void *data) 451{ 452 struct sc_chinfo *ch = data; 453 struct sc_info *sc = ch->parent; 454 u_int32_t pos; 455 456 ICH_LOCK(sc); 457 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 458 ICH_UNLOCK(sc); 459 460 pos = ch->civ * ch->blksz; 461 462 return pos; 463} 464 465static struct pcmchan_caps * 466ichchan_getcaps(kobj_t obj, void *data) 467{ 468 struct sc_chinfo *ch = data; 469 470 return ch->spdreg? &ich_vrcaps : &ich_caps; 471} 472 473static kobj_method_t ichchan_methods[] = { 474 KOBJMETHOD(channel_init, ichchan_init), 475 KOBJMETHOD(channel_setformat, ichchan_setformat), 476 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 477 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 478 KOBJMETHOD(channel_trigger, ichchan_trigger), 479 KOBJMETHOD(channel_getptr, ichchan_getptr), 480 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 481 { 0, 0 } 482}; 483CHANNEL_DECLARE(ichchan); 484 485/* -------------------------------------------------------------------- */ 486/* The interrupt handler */ 487 488static void 489ich_intr(void *p) 490{ 491 struct sc_info *sc = (struct sc_info *)p; 492 struct sc_chinfo *ch; 493 u_int32_t cbi, lbi, lvi, st, gs; 494 int i; 495 496 ICH_LOCK(sc); 497 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 498 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 499 /* Clear resume interrupt(s) - nothing doing with them */ 500 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 501 } 502 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 503 504 for (i = 0; i < 3; i++) { 505 ch = &sc->ch[i]; 506 if ((ch->imask & gs) == 0) 507 continue; 508 gs &= ~ch->imask; 509 st = ich_rd(sc, ch->regbase + 510 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 511 2); 512 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 513 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 514 /* block complete - update buffer */ 515 if (ch->run) { 516 ICH_UNLOCK(sc); 517 chn_intr(ch->channel); 518 ICH_LOCK(sc); 519 } 520 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 521 cbi = ch->civ % ch->blkcnt; 522 if (cbi == 0) 523 cbi = ch->blkcnt - 1; 524 else 525 cbi--; 526 lbi = lvi % ch->blkcnt; 527 if (cbi >= lbi) 528 lvi += cbi - lbi; 529 else 530 lvi += cbi + ch->blkcnt - lbi; 531 lvi %= ICH_DTBL_LENGTH; 532 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 533 534 } 535 /* clear status bit */ 536 ich_wr(sc, ch->regbase + 537 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 538 st, 2); 539 } 540 ICH_UNLOCK(sc); 541 if (gs != 0) { 542 device_printf(sc->dev, 543 "Unhandled interrupt, gs_intr = %x\n", gs); 544 } 545} 546 547/* ------------------------------------------------------------------------- */ 548/* Sysctl to control ac97 speed (some boards appear to end up using 549 * XTAL_IN rather than BIT_CLK for link timing). 550 */ 551 552static int 553ich_initsys(struct sc_info* sc) 554{ 555#ifdef SND_DYNSYSCTL 556 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 557 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 558 OID_AUTO, "ac97rate", CTLFLAG_RW, 559 &sc->ac97rate, 48000, 560 "AC97 link rate (default = 48000)"); 561#endif /* SND_DYNSYSCTL */ 562 return 0; 563} 564 565/* -------------------------------------------------------------------- */ 566/* Calibrate card to determine the clock source. The source maybe a 567 * function of the ac97 codec initialization code (to be investigated). 568 */ 569 570static 571void ich_calibrate(void *arg) 572{ 573 struct sc_info *sc; 574 struct sc_chinfo *ch; 575 struct timeval t1, t2; 576 u_int8_t ociv, nciv; 577 u_int32_t wait_us, actual_48k_rate, bytes; 578 579 sc = (struct sc_info *)arg; 580 ch = &sc->ch[1]; 581 582 if (sc->use_intrhook) 583 config_intrhook_disestablish(&sc->intrhook); 584 585 /* 586 * Grab audio from input for fixed interval and compare how 587 * much we actually get with what we expect. Interval needs 588 * to be sufficiently short that no interrupts are 589 * generated. 590 */ 591 592 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 593 594 bytes = sndbuf_getsize(ch->buffer) / 2; 595 ichchan_setblocksize(0, ch, bytes); 596 597 /* 598 * our data format is stereo, 16 bit so each sample is 4 bytes. 599 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 600 * we're going to start recording with interrupts disabled and measure 601 * the time taken for one block to complete. we know the block size, 602 * we know the time in microseconds, we calculate the sample rate: 603 * 604 * actual_rate [bps] = bytes / (time [s] * 4) 605 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 606 * actual_rate [Hz] = (bytes * 250000) / time [us] 607 */ 608 609 /* prepare */ 610 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 611 nciv = ociv; 612 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 613 614 /* start */ 615 microtime(&t1); 616 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 617 618 /* wait */ 619 while (nciv == ociv) { 620 microtime(&t2); 621 if (t2.tv_sec - t1.tv_sec > 1) 622 break; 623 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 624 } 625 microtime(&t2); 626 627 /* stop */ 628 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 629 630 /* reset */ 631 DELAY(100); 632 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 633 634 /* turn time delta into us */ 635 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 636 637 if (nciv == ociv) { 638 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 639 return; 640 } 641 642 actual_48k_rate = (bytes * 250000) / wait_us; 643 644 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 645 sc->ac97rate = actual_48k_rate; 646 } else { 647 sc->ac97rate = 48000; 648 } 649 650 if (bootverbose || sc->ac97rate != 48000) { 651 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 652 if (sc->ac97rate != actual_48k_rate) 653 printf(", will use %d Hz", sc->ac97rate); 654 printf("\n"); 655 } 656 657 return; 658} 659 660/* -------------------------------------------------------------------- */ 661/* Probe and attach the card */ 662 663static void 664ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 665{ 666 struct sc_info *sc = (struct sc_info *)arg; 667 sc->desc_addr = segs->ds_addr; 668 return; 669} 670 671static int 672ich_init(struct sc_info *sc) 673{ 674 u_int32_t stat; 675 int sz; 676 677 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 678 DELAY(600000); 679 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 680 681 if ((stat & ICH_GLOB_STA_PCR) == 0) { 682 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 683 if (sc->vendor == INTEL_VENDORID && ( 684 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 685 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 686 sc->devid == INTEL_82801GB)) { 687 return ENXIO; 688 } 689 } 690 691 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 692 693 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 694 return ENXIO; 695 if (sc->hasmic && ich_resetchan(sc, 2)) 696 return ENXIO; 697 698 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 699 return ENOSPC; 700 701 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 702 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) { 703 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 704 return ENOSPC; 705 } 706 707 return 0; 708} 709 710static int 711ich_pci_probe(device_t dev) 712{ 713 int i; 714 uint16_t devid, vendor; 715 716 vendor = pci_get_vendor(dev); 717 devid = pci_get_device(dev); 718 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 719 if (vendor == ich_devs[i].vendor && 720 devid == ich_devs[i].devid) { 721 device_set_desc(dev, ich_devs[i].name); 722 /* allow a better driver to override us */ 723 if ((ich_devs[i].options & PROBE_LOW) != 0) 724 return (BUS_PROBE_LOW_PRIORITY); 725 return (BUS_PROBE_DEFAULT); 726 } 727 } 728 return (ENXIO); 729} 730 731static int 732ich_pci_attach(device_t dev) 733{ 734 u_int16_t extcaps; 735 uint16_t devid, vendor; 736 struct sc_info *sc; 737 char status[SND_STATUSLEN]; 738 739 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 740 device_printf(dev, "cannot allocate softc\n"); 741 return ENXIO; 742 } 743 744 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 745 sc->dev = dev; 746 747 vendor = sc->vendor = pci_get_vendor(dev); 748 devid = sc->devid = pci_get_device(dev); 749 /* 750 * The SiS 7012 register set isn't quite like the standard ich. 751 * There really should be a general "quirks" mechanism. 752 */ 753 if (vendor == SIS_VENDORID && devid == SIS_7012) { 754 sc->swap_reg = 1; 755 sc->sample_size = 1; 756 } else { 757 sc->swap_reg = 0; 758 sc->sample_size = 2; 759 } 760 761 /* 762 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 763 * read-only. Need to enable "legacy support", by poking into 764 * pci config space. The driver should use MMBAR and MBBAR, 765 * but doing so will mess things up here. ich4 has enough new 766 * features it warrants it's own driver. 767 */ 768 if (vendor == INTEL_VENDORID && devid == INTEL_82801DB) { 769 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 770 } 771 772 /* 773 * Enable bus master. On ich4/5 this may prevent the detection of 774 * the primary codec becoming ready in ich_init(). 775 */ 776 pci_enable_busmaster(dev); 777 778 if (vendor == INTEL_VENDORID && (devid == INTEL_82801EB || 779 devid == INTEL_6300ESB || devid == INTEL_82801FB || 780 devid == INTEL_82801GB)) { 781 sc->nambarid = PCIR_MMBAR; 782 sc->nabmbarid = PCIR_MBBAR; 783 sc->regtype = SYS_RES_MEMORY; 784 } else { 785 sc->nambarid = PCIR_NAMBAR; 786 sc->nabmbarid = PCIR_NABMBAR; 787 sc->regtype = SYS_RES_IOPORT; 788 } 789 790 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 791 &sc->nambarid, RF_ACTIVE); 792 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 793 &sc->nabmbarid, RF_ACTIVE); 794 795 if (!sc->nambar || !sc->nabmbar) { 796 device_printf(dev, "unable to map IO port space\n"); 797 goto bad; 798 } 799 800 sc->nambart = rman_get_bustag(sc->nambar); 801 sc->nambarh = rman_get_bushandle(sc->nambar); 802 sc->nabmbart = rman_get_bustag(sc->nabmbar); 803 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 804 805 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 806 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 807 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 808 NULL, NULL, &sc->dmat) != 0) { 809 device_printf(dev, "unable to create dma tag\n"); 810 goto bad; 811 } 812 813 sc->irqid = 0; 814 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 815 RF_ACTIVE | RF_SHAREABLE); 816 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 817 device_printf(dev, "unable to map interrupt\n"); 818 goto bad; 819 } 820 821 if (ich_init(sc)) { 822 device_printf(dev, "unable to initialize the card\n"); 823 goto bad; 824 } 825 826 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 827 if (sc->codec == NULL) 828 goto bad; 829 mixer_init(dev, ac97_getmixerclass(), sc->codec); 830 831 /* check and set VRA function */ 832 extcaps = ac97_getextcaps(sc->codec); 833 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 834 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 835 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 836 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 837 838 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 839 goto bad; 840 841 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 842 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 843 if (sc->hasmic) 844 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 845 846 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 847 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 848 849 pcm_setstatus(dev, status); 850 851 ich_initsys(sc); 852 853 sc->intrhook.ich_func = ich_calibrate; 854 sc->intrhook.ich_arg = sc; 855 sc->use_intrhook = 1; 856 if (config_intrhook_establish(&sc->intrhook) != 0) { 857 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 858 sc->use_intrhook = 0; 859 ich_calibrate(sc); 860 } 861 862 return 0; 863 864bad: 865 if (sc->codec) 866 ac97_destroy(sc->codec); 867 if (sc->ih) 868 bus_teardown_intr(dev, sc->irq, sc->ih); 869 if (sc->irq) 870 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 871 if (sc->nambar) 872 bus_release_resource(dev, sc->regtype, 873 sc->nambarid, sc->nambar); 874 if (sc->nabmbar) 875 bus_release_resource(dev, sc->regtype, 876 sc->nabmbarid, sc->nabmbar); 877 if (sc->ich_lock) 878 snd_mtxfree(sc->ich_lock); 879 free(sc, M_DEVBUF); 880 return ENXIO; 881} 882 883static int 884ich_pci_detach(device_t dev) 885{ 886 struct sc_info *sc; 887 int r; 888 889 r = pcm_unregister(dev); 890 if (r) 891 return r; 892 sc = pcm_getdevinfo(dev); 893 894 bus_teardown_intr(dev, sc->irq, sc->ih); 895 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 896 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 897 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 898 bus_dma_tag_destroy(sc->dmat); 899 snd_mtxfree(sc->ich_lock); 900 free(sc, M_DEVBUF); 901 return 0; 902} 903 904static void 905ich_pci_codec_reset(struct sc_info *sc) 906{ 907 int i; 908 uint32_t control; 909 910 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 911 control &= ~(ICH_GLOB_CTL_SHUT); 912 control |= (control & ICH_GLOB_CTL_COLD) ? 913 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 914 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 915 916 for (i = 500000; i; i--) { 917 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 918 break; /* or ICH_SCR? */ 919 DELAY(1); 920 } 921 922 if (i <= 0) 923 printf("%s: time out\n", __func__); 924} 925 926static int 927ich_pci_suspend(device_t dev) 928{ 929 struct sc_info *sc; 930 int i; 931 932 sc = pcm_getdevinfo(dev); 933 ICH_LOCK(sc); 934 for (i = 0 ; i < 3; i++) { 935 sc->ch[i].run_save = sc->ch[i].run; 936 if (sc->ch[i].run) { 937 ICH_UNLOCK(sc); 938 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 939 ICH_LOCK(sc); 940 } 941 } 942 ICH_UNLOCK(sc); 943 return 0; 944} 945 946static int 947ich_pci_resume(device_t dev) 948{ 949 struct sc_info *sc; 950 int i; 951 952 sc = pcm_getdevinfo(dev); 953 954 if (sc->regtype == SYS_RES_IOPORT) 955 pci_enable_io(dev, SYS_RES_IOPORT); 956 else 957 pci_enable_io(dev, SYS_RES_MEMORY); 958 pci_enable_busmaster(dev); 959 960 ICH_LOCK(sc); 961 /* Reinit audio device */ 962 if (ich_init(sc) == -1) { 963 device_printf(dev, "unable to reinitialize the card\n"); 964 ICH_UNLOCK(sc); 965 return ENXIO; 966 } 967 /* Reinit mixer */ 968 ich_pci_codec_reset(sc); 969 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 970 if (mixer_reinit(dev) == -1) { 971 device_printf(dev, "unable to reinitialize the mixer\n"); 972 ICH_UNLOCK(sc); 973 return ENXIO; 974 } 975 /* Re-start DMA engines */ 976 for (i = 0 ; i < 3; i++) { 977 struct sc_chinfo *ch = &sc->ch[i]; 978 if (sc->ch[i].run_save) { 979 ICH_UNLOCK(sc); 980 ichchan_setblocksize(0, ch, ch->blksz); 981 ichchan_setspeed(0, ch, ch->spd); 982 ichchan_trigger(0, ch, PCMTRIG_START); 983 ICH_LOCK(sc); 984 } 985 } 986 ICH_UNLOCK(sc); 987 return 0; 988} 989 990static device_method_t ich_methods[] = { 991 /* Device interface */ 992 DEVMETHOD(device_probe, ich_pci_probe), 993 DEVMETHOD(device_attach, ich_pci_attach), 994 DEVMETHOD(device_detach, ich_pci_detach), 995 DEVMETHOD(device_suspend, ich_pci_suspend), 996 DEVMETHOD(device_resume, ich_pci_resume), 997 { 0, 0 } 998}; 999 1000static driver_t ich_driver = { 1001 "pcm", 1002 ich_methods, 1003 PCM_SOFTC_SIZE, 1004}; 1005 1006DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 1007MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1008MODULE_VERSION(snd_ich, 1); 1009