ich.c revision 101738
1239310Sdim/* 2239310Sdim * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3239310Sdim * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4239310Sdim * All rights reserved. 5239310Sdim * 6239310Sdim * Redistribution and use in source and binary forms, with or without 7239310Sdim * modification, are permitted provided that the following conditions 8239310Sdim * are met: 9239310Sdim * 1. Redistributions of source code must retain the above copyright 10239310Sdim * notice, this list of conditions and the following disclaimer. 11239310Sdim * 2. Redistributions in binary form must reproduce the above copyright 12239310Sdim * notice, this list of conditions and the following disclaimer in the 13239310Sdim * documentation and/or other materials provided with the distribution. 14239310Sdim * 15239310Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16239310Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17239310Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18239310Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19249423Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20239310Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21243830Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22249423Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23239310Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24239310Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25239310Sdim * SUCH DAMAGE. 26243830Sdim */ 27243830Sdim 28243830Sdim#include <dev/sound/pcm/sound.h> 29243830Sdim#include <dev/sound/pcm/ac97.h> 30243830Sdim#include <dev/sound/pci/ich.h> 31243830Sdim 32243830Sdim#include <pci/pcireg.h> 33243830Sdim#include <pci/pcivar.h> 34243830Sdim 35243830SdimSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 101738 2002-08-12 15:45:12Z mp $"); 36243830Sdim 37243830Sdim/* -------------------------------------------------------------------- */ 38243830Sdim 39263508Sdim#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40243830Sdim#define ICH_DTBL_LENGTH 32 41243830Sdim#define ICH_DEFAULT_BUFSZ 16384 42263508Sdim#define ICH_MAX_BUFSZ 65536 43263508Sdim 44243830Sdim#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45243830Sdim 46243830Sdim/* buffer descriptor */ 47243830Sdimstruct ich_desc { 48243830Sdim volatile u_int32_t buffer; 49243830Sdim volatile u_int32_t length; 50243830Sdim}; 51243830Sdim 52243830Sdimstruct sc_info; 53243830Sdim 54243830Sdim/* channel registers */ 55243830Sdimstruct sc_chinfo { 56243830Sdim u_int32_t num:8, run:1, run_save:1; 57243830Sdim u_int32_t blksz, blkcnt, spd; 58243830Sdim u_int32_t regbase, spdreg; 59243830Sdim u_int32_t imask; 60243830Sdim u_int32_t civ; 61243830Sdim 62243830Sdim struct snd_dbuf *buffer; 63243830Sdim struct pcm_channel *channel; 64243830Sdim struct sc_info *parent; 65243830Sdim 66243830Sdim struct ich_desc *dtbl; 67243830Sdim}; 68243830Sdim 69243830Sdim/* device private data */ 70243830Sdimstruct sc_info { 71243830Sdim device_t dev; 72243830Sdim int hasvra, hasvrm, hasmic; 73243830Sdim unsigned int chnum, bufsz; 74243830Sdim int sample_size, swap_reg; 75243830Sdim 76243830Sdim struct resource *nambar, *nabmbar, *irq; 77243830Sdim int nambarid, nabmbarid, irqid; 78243830Sdim bus_space_tag_t nambart, nabmbart; 79243830Sdim bus_space_handle_t nambarh, nabmbarh; 80243830Sdim bus_dma_tag_t dmat; 81243830Sdim bus_dmamap_t dtmap; 82243830Sdim void *ih; 83243830Sdim 84243830Sdim struct ac97_info *codec; 85243830Sdim struct sc_chinfo ch[3]; 86243830Sdim int ac97rate; 87243830Sdim struct ich_desc *dtbl; 88263508Sdim struct intr_config_hook intrhook; 89243830Sdim int use_intrhook; 90243830Sdim}; 91239310Sdim 92239310Sdim/* -------------------------------------------------------------------- */ 93249423Sdim 94239310Sdimstatic u_int32_t ich_fmt[] = { 95243830Sdim AFMT_STEREO | AFMT_S16_LE, 96239310Sdim 0 97243830Sdim}; 98243830Sdimstatic struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 99243830Sdimstatic struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 100243830Sdim 101243830Sdim/* -------------------------------------------------------------------- */ 102243830Sdim/* Hardware */ 103243830Sdimstatic u_int32_t 104243830Sdimich_rd(struct sc_info *sc, int regno, int size) 105243830Sdim{ 106243830Sdim switch (size) { 107243830Sdim case 1: 108243830Sdim return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 109243830Sdim case 2: 110243830Sdim return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 111243830Sdim case 4: 112243830Sdim return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 113243830Sdim default: 114243830Sdim return 0xffffffff; 115243830Sdim } 116243830Sdim} 117243830Sdim 118243830Sdimstatic void 119243830Sdimich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 120243830Sdim{ 121243830Sdim switch (size) { 122243830Sdim case 1: 123243830Sdim bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 124243830Sdim break; 125243830Sdim case 2: 126243830Sdim bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 127243830Sdim break; 128243830Sdim case 4: 129243830Sdim bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 130243830Sdim break; 131243830Sdim } 132243830Sdim} 133243830Sdim 134243830Sdim/* ac97 codec */ 135243830Sdimstatic int 136243830Sdimich_waitcd(void *devinfo) 137243830Sdim{ 138239310Sdim int i; 139239310Sdim u_int32_t data; 140243830Sdim struct sc_info *sc = (struct sc_info *)devinfo; 141243830Sdim 142243830Sdim for (i = 0; i < ICH_TIMEOUT; i++) { 143243830Sdim data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 144239310Sdim if ((data & 0x01) == 0) 145243830Sdim return 0; 146243830Sdim } 147243830Sdim device_printf(sc->dev, "CODEC semaphore timeout\n"); 148243830Sdim return ETIMEDOUT; 149243830Sdim} 150243830Sdim 151243830Sdimstatic int 152243830Sdimich_rdcd(kobj_t obj, void *devinfo, int regno) 153243830Sdim{ 154243830Sdim struct sc_info *sc = (struct sc_info *)devinfo; 155243830Sdim 156243830Sdim regno &= 0xff; 157243830Sdim ich_waitcd(sc); 158243830Sdim 159243830Sdim return bus_space_read_2(sc->nambart, sc->nambarh, regno); 160243830Sdim} 161243830Sdim 162243830Sdimstatic int 163243830Sdimich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 164243830Sdim{ 165243830Sdim struct sc_info *sc = (struct sc_info *)devinfo; 166243830Sdim 167243830Sdim regno &= 0xff; 168243830Sdim ich_waitcd(sc); 169243830Sdim bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 170243830Sdim 171243830Sdim return 0; 172243830Sdim} 173243830Sdim 174243830Sdimstatic kobj_method_t ich_ac97_methods[] = { 175243830Sdim KOBJMETHOD(ac97_read, ich_rdcd), 176243830Sdim KOBJMETHOD(ac97_write, ich_wrcd), 177243830Sdim { 0, 0 } 178243830Sdim}; 179243830SdimAC97_DECLARE(ich_ac97); 180243830Sdim 181243830Sdim/* -------------------------------------------------------------------- */ 182243830Sdim/* common routines */ 183243830Sdim 184243830Sdimstatic void 185243830Sdimich_filldtbl(struct sc_chinfo *ch) 186243830Sdim{ 187243830Sdim u_int32_t base; 188243830Sdim int i; 189243830Sdim 190243830Sdim base = vtophys(sndbuf_getbuf(ch->buffer)); 191243830Sdim ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 192243830Sdim if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 193243830Sdim ch->blkcnt = 2; 194243830Sdim ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 195243830Sdim } 196243830Sdim 197243830Sdim for (i = 0; i < ICH_DTBL_LENGTH; i++) { 198243830Sdim ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 199243830Sdim ch->dtbl[i].length = ICH_BDC_IOC 200243830Sdim | (ch->blksz / ch->parent->sample_size); 201243830Sdim } 202243830Sdim} 203243830Sdim 204243830Sdimstatic int 205243830Sdimich_resetchan(struct sc_info *sc, int num) 206243830Sdim{ 207243830Sdim int i, cr, regbase; 208243830Sdim 209243830Sdim if (num == 0) 210243830Sdim regbase = ICH_REG_PO_BASE; 211243830Sdim else if (num == 1) 212243830Sdim regbase = ICH_REG_PI_BASE; 213243830Sdim else if (num == 2) 214243830Sdim regbase = ICH_REG_MC_BASE; 215243830Sdim else 216243830Sdim return ENXIO; 217243830Sdim 218243830Sdim ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 219243830Sdim DELAY(100); 220243830Sdim ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 221243830Sdim for (i = 0; i < ICH_TIMEOUT; i++) { 222249423Sdim cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 223243830Sdim if (cr == 0) 224243830Sdim return 0; 225243830Sdim } 226243830Sdim 227243830Sdim device_printf(sc->dev, "cannot reset channel %d\n", num); 228243830Sdim return ENXIO; 229243830Sdim} 230243830Sdim 231243830Sdim/* -------------------------------------------------------------------- */ 232243830Sdim/* channel interface */ 233243830Sdim 234243830Sdimstatic void * 235243830Sdimichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 236243830Sdim{ 237243830Sdim struct sc_info *sc = devinfo; 238243830Sdim struct sc_chinfo *ch; 239243830Sdim unsigned int num; 240243830Sdim 241243830Sdim num = sc->chnum++; 242243830Sdim ch = &sc->ch[num]; 243243830Sdim ch->num = num; 244243830Sdim ch->buffer = b; 245243830Sdim ch->channel = c; 246243830Sdim ch->parent = sc; 247243830Sdim ch->run = 0; 248243830Sdim ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 249243830Sdim ch->blkcnt = 2; 250243830Sdim ch->blksz = sc->bufsz / ch->blkcnt; 251243830Sdim 252243830Sdim switch(ch->num) { 253243830Sdim case 0: /* play */ 254243830Sdim KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 255243830Sdim ch->regbase = ICH_REG_PO_BASE; 256243830Sdim ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 257243830Sdim ch->imask = ICH_GLOB_STA_POINT; 258243830Sdim break; 259243830Sdim 260243830Sdim case 1: /* record */ 261243830Sdim KASSERT(dir == PCMDIR_REC, ("wrong direction")); 262243830Sdim ch->regbase = ICH_REG_PI_BASE; 263243830Sdim ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 264243830Sdim ch->imask = ICH_GLOB_STA_PIINT; 265243830Sdim break; 266243830Sdim 267243830Sdim case 2: /* mic */ 268243830Sdim KASSERT(dir == PCMDIR_REC, ("wrong direction")); 269243830Sdim ch->regbase = ICH_REG_MC_BASE; 270243830Sdim ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 271243830Sdim ch->imask = ICH_GLOB_STA_MINT; 272243830Sdim break; 273243830Sdim 274243830Sdim default: 275243830Sdim return NULL; 276243830Sdim } 277243830Sdim 278243830Sdim if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 279243830Sdim return NULL; 280243830Sdim 281243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 282243830Sdim 283243830Sdim return ch; 284243830Sdim} 285243830Sdim 286243830Sdimstatic int 287243830Sdimichchan_setformat(kobj_t obj, void *data, u_int32_t format) 288243830Sdim{ 289243830Sdim return 0; 290243830Sdim} 291243830Sdim 292243830Sdimstatic int 293243830Sdimichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 294243830Sdim{ 295243830Sdim struct sc_chinfo *ch = data; 296243830Sdim struct sc_info *sc = ch->parent; 297243830Sdim 298243830Sdim if (ch->spdreg) { 299243830Sdim int r; 300243830Sdim if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 301243830Sdim sc->ac97rate = 48000; 302243830Sdim r = (speed * 48000) / sc->ac97rate; 303243830Sdim /* 304243830Sdim * Cast the return value of ac97_setrate() to u_int so that 305243830Sdim * the math don't overflow into the negative range. 306243830Sdim */ 307243830Sdim ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 308243830Sdim sc->ac97rate) / 48000; 309243830Sdim } else { 310243830Sdim ch->spd = 48000; 311243830Sdim } 312243830Sdim return ch->spd; 313243830Sdim} 314243830Sdim 315243830Sdimstatic int 316243830Sdimichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 317243830Sdim{ 318243830Sdim struct sc_chinfo *ch = data; 319243830Sdim struct sc_info *sc = ch->parent; 320243830Sdim 321243830Sdim ch->blksz = blocksize; 322243830Sdim ich_filldtbl(ch); 323243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 324243830Sdim 325243830Sdim return ch->blksz; 326243830Sdim} 327243830Sdim 328243830Sdimstatic int 329243830Sdimichchan_trigger(kobj_t obj, void *data, int go) 330243830Sdim{ 331243830Sdim struct sc_chinfo *ch = data; 332243830Sdim struct sc_info *sc = ch->parent; 333243830Sdim 334243830Sdim switch (go) { 335243830Sdim case PCMTRIG_START: 336243830Sdim ch->run = 1; 337243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 338243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 339243830Sdim break; 340243830Sdim 341243830Sdim case PCMTRIG_ABORT: 342243830Sdim ich_resetchan(sc, ch->num); 343243830Sdim ch->run = 0; 344243830Sdim break; 345243830Sdim } 346243830Sdim return 0; 347243830Sdim} 348243830Sdim 349243830Sdimstatic int 350243830Sdimichchan_getptr(kobj_t obj, void *data) 351243830Sdim{ 352243830Sdim struct sc_chinfo *ch = data; 353243830Sdim struct sc_info *sc = ch->parent; 354243830Sdim u_int32_t pos; 355243830Sdim 356243830Sdim ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 357243830Sdim 358243830Sdim pos = ch->civ * ch->blksz; 359243830Sdim 360243830Sdim return pos; 361243830Sdim} 362243830Sdim 363243830Sdimstatic struct pcmchan_caps * 364243830Sdimichchan_getcaps(kobj_t obj, void *data) 365243830Sdim{ 366243830Sdim struct sc_chinfo *ch = data; 367243830Sdim 368243830Sdim return ch->spdreg? &ich_vrcaps : &ich_caps; 369243830Sdim} 370243830Sdim 371243830Sdimstatic kobj_method_t ichchan_methods[] = { 372243830Sdim KOBJMETHOD(channel_init, ichchan_init), 373243830Sdim KOBJMETHOD(channel_setformat, ichchan_setformat), 374243830Sdim KOBJMETHOD(channel_setspeed, ichchan_setspeed), 375243830Sdim KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 376243830Sdim KOBJMETHOD(channel_trigger, ichchan_trigger), 377243830Sdim KOBJMETHOD(channel_getptr, ichchan_getptr), 378243830Sdim KOBJMETHOD(channel_getcaps, ichchan_getcaps), 379243830Sdim { 0, 0 } 380243830Sdim}; 381243830SdimCHANNEL_DECLARE(ichchan); 382243830Sdim 383243830Sdim/* -------------------------------------------------------------------- */ 384243830Sdim/* The interrupt handler */ 385243830Sdim 386243830Sdimstatic void 387243830Sdimich_intr(void *p) 388243830Sdim{ 389243830Sdim struct sc_info *sc = (struct sc_info *)p; 390243830Sdim struct sc_chinfo *ch; 391243830Sdim u_int32_t cbi, lbi, lvi, st, gs; 392243830Sdim int i; 393243830Sdim 394243830Sdim gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 395243830Sdim if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 396243830Sdim /* Clear resume interrupt(s) - nothing doing with them */ 397243830Sdim ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 398243830Sdim } 399243830Sdim gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 400243830Sdim 401243830Sdim for (i = 0; i < 3; i++) { 402243830Sdim ch = &sc->ch[i]; 403243830Sdim if ((ch->imask & gs) == 0) 404243830Sdim continue; 405243830Sdim gs &= ~ch->imask; 406243830Sdim st = ich_rd(sc, ch->regbase + 407243830Sdim (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 408243830Sdim 2); 409243830Sdim st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 410243830Sdim if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 411243830Sdim /* block complete - update buffer */ 412243830Sdim if (ch->run) 413243830Sdim chn_intr(ch->channel); 414243830Sdim lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 415243830Sdim cbi = ch->civ % ch->blkcnt; 416243830Sdim if (cbi == 0) 417243830Sdim cbi = ch->blkcnt - 1; 418243830Sdim else 419243830Sdim cbi--; 420243830Sdim lbi = lvi % ch->blkcnt; 421243830Sdim if (cbi >= lbi) 422243830Sdim lvi += cbi - lbi; 423243830Sdim else 424243830Sdim lvi += cbi + ch->blkcnt - lbi; 425243830Sdim lvi %= ICH_DTBL_LENGTH; 426243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 427243830Sdim 428243830Sdim } 429243830Sdim /* clear status bit */ 430243830Sdim ich_wr(sc, ch->regbase + 431243830Sdim (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 432243830Sdim st, 2); 433243830Sdim } 434243830Sdim if (gs != 0) { 435243830Sdim device_printf(sc->dev, 436243830Sdim "Unhandled interrupt, gs_intr = %x\n", gs); 437243830Sdim } 438243830Sdim} 439243830Sdim 440243830Sdim/* ------------------------------------------------------------------------- */ 441243830Sdim/* Sysctl to control ac97 speed (some boards overclocked ac97). */ 442243830Sdim 443243830Sdimstatic int 444243830Sdimich_initsys(struct sc_info* sc) 445243830Sdim{ 446243830Sdim#ifdef SND_DYNSYSCTL 447243830Sdim SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 448243830Sdim SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 449243830Sdim OID_AUTO, "ac97rate", CTLFLAG_RW, 450243830Sdim &sc->ac97rate, 48000, 451243830Sdim "AC97 link rate (default = 48000)"); 452243830Sdim#endif /* SND_DYNSYSCTL */ 453243830Sdim return 0; 454243830Sdim} 455243830Sdim 456243830Sdim/* -------------------------------------------------------------------- */ 457243830Sdim/* Calibrate card (some boards are overclocked and need scaling) */ 458243830Sdim 459243830Sdimstatic 460243830Sdimvoid ich_calibrate(void *arg) 461243830Sdim{ 462243830Sdim struct sc_info *sc; 463243830Sdim struct sc_chinfo *ch; 464243830Sdim struct timeval t1, t2; 465243830Sdim u_int8_t ociv, nciv; 466243830Sdim u_int32_t wait_us, actual_48k_rate, bytes; 467243830Sdim 468243830Sdim sc = (struct sc_info *)arg; 469243830Sdim ch = &sc->ch[1]; 470243830Sdim 471243830Sdim if (sc->use_intrhook) 472243830Sdim config_intrhook_disestablish(&sc->intrhook); 473243830Sdim 474243830Sdim /* 475243830Sdim * Grab audio from input for fixed interval and compare how 476243830Sdim * much we actually get with what we expect. Interval needs 477243830Sdim * to be sufficiently short that no interrupts are 478243830Sdim * generated. 479243830Sdim */ 480243830Sdim 481243830Sdim KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 482243830Sdim 483243830Sdim bytes = sndbuf_getsize(ch->buffer) / 2; 484243830Sdim ichchan_setblocksize(0, ch, bytes); 485243830Sdim 486243830Sdim /* 487243830Sdim * our data format is stereo, 16 bit so each sample is 4 bytes. 488243830Sdim * assuming we get 48000 samples per second, we get 192000 bytes/sec. 489243830Sdim * we're going to start recording with interrupts disabled and measure 490243830Sdim * the time taken for one block to complete. we know the block size, 491243830Sdim * we know the time in microseconds, we calculate the sample rate: 492243830Sdim * 493243830Sdim * actual_rate [bps] = bytes / (time [s] * 4) 494243830Sdim * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 495243830Sdim * actual_rate [Hz] = (bytes * 250000) / time [us] 496243830Sdim */ 497243830Sdim 498243830Sdim /* prepare */ 499243830Sdim ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 500243830Sdim nciv = ociv; 501243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 502243830Sdim 503243830Sdim /* start */ 504243830Sdim microtime(&t1); 505243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 506239310Sdim 507249423Sdim /* wait */ 508249423Sdim while (nciv == ociv) { 509249423Sdim microtime(&t2); 510243830Sdim if (t2.tv_sec - t1.tv_sec > 1) 511239310Sdim break; 512249423Sdim nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 513249423Sdim } 514239310Sdim microtime(&t2); 515239310Sdim 516243830Sdim /* stop */ 517243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 518249423Sdim 519249423Sdim /* reset */ 520249423Sdim DELAY(100); 521243830Sdim ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 522243830Sdim 523249423Sdim /* turn time delta into us */ 524249423Sdim wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 525249423Sdim 526243830Sdim if (nciv == ociv) { 527243830Sdim device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 528243830Sdim return; 529243830Sdim } 530243830Sdim 531243830Sdim actual_48k_rate = (bytes * 250000) / wait_us; 532239310Sdim 533243830Sdim if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 534243830Sdim sc->ac97rate = actual_48k_rate; 535243830Sdim } else { 536243830Sdim sc->ac97rate = 48000; 537243830Sdim } 538243830Sdim 539249423Sdim if (bootverbose || sc->ac97rate != 48000) { 540243830Sdim device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 541243830Sdim if (sc->ac97rate != actual_48k_rate) 542249423Sdim printf(", will use %d Hz", sc->ac97rate); 543243830Sdim printf("\n"); 544249423Sdim } 545249423Sdim 546249423Sdim return; 547249423Sdim} 548249423Sdim 549249423Sdim/* -------------------------------------------------------------------- */ 550249423Sdim/* Probe and attach the card */ 551249423Sdim 552249423Sdimstatic void 553249423Sdimich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 554249423Sdim{ 555249423Sdim return; 556249423Sdim} 557249423Sdim 558249423Sdimstatic int 559249423Sdimich_init(struct sc_info *sc) 560249423Sdim{ 561249423Sdim u_int32_t stat; 562249423Sdim int sz; 563249423Sdim 564249423Sdim ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 565249423Sdim DELAY(600000); 566249423Sdim stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 567249423Sdim 568249423Sdim if ((stat & ICH_GLOB_STA_PCR) == 0) 569249423Sdim return ENXIO; 570249423Sdim 571249423Sdim ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 572249423Sdim 573249423Sdim if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 574249423Sdim return ENXIO; 575249423Sdim if (sc->hasmic && ich_resetchan(sc, 2)) 576243830Sdim return ENXIO; 577243830Sdim 578249423Sdim if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 579249423Sdim return ENOSPC; 580243830Sdim 581243830Sdim sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 582243830Sdim if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 583243830Sdim bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 584243830Sdim return ENOSPC; 585243830Sdim } 586249423Sdim 587249423Sdim return 0; 588249423Sdim} 589249423Sdim 590249423Sdimstatic int 591243830Sdimich_pci_probe(device_t dev) 592243830Sdim{ 593239310Sdim switch(pci_get_devid(dev)) { 594239310Sdim case 0x71958086: 595243830Sdim device_set_desc(dev, "Intel 443MX"); 596243830Sdim return 0; 597249423Sdim 598249423Sdim case 0x24158086: 599243830Sdim device_set_desc(dev, "Intel 82801AA (ICH)"); 600243830Sdim return 0; 601249423Sdim 602249423Sdim case 0x24258086: 603243830Sdim device_set_desc(dev, "Intel 82801AB (ICH)"); 604243830Sdim return 0; 605243830Sdim 606243830Sdim case 0x24458086: 607239310Sdim device_set_desc(dev, "Intel 82801BA (ICH2)"); 608239310Sdim return 0; 609243830Sdim 610243830Sdim case 0x24858086: 611243830Sdim device_set_desc(dev, "Intel 82801CA (ICH3)"); 612239310Sdim return 0; 613249423Sdim 614243830Sdim case 0x24c58086: 615239310Sdim device_set_desc(dev, "Intel 82801DC (ICH4)"); 616243830Sdim return 0; 617249423Sdim 618243830Sdim case SIS7012ID: 619243830Sdim device_set_desc(dev, "SiS 7012"); 620249423Sdim return 0; 621249423Sdim 622243830Sdim case 0x01b110de: 623249423Sdim device_set_desc(dev, "Nvidia nForce AC97 controller"); 624243830Sdim return 0; 625243830Sdim 626243830Sdim default: 627243830Sdim return ENXIO; 628243830Sdim } 629243830Sdim} 630243830Sdim 631243830Sdimstatic int 632243830Sdimich_pci_attach(device_t dev) 633243830Sdim{ 634243830Sdim u_int32_t data; 635243830Sdim u_int16_t extcaps; 636243830Sdim struct sc_info *sc; 637243830Sdim char status[SND_STATUSLEN]; 638243830Sdim 639243830Sdim if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 640243830Sdim device_printf(dev, "cannot allocate softc\n"); 641243830Sdim return ENXIO; 642243830Sdim } 643243830Sdim 644243830Sdim bzero(sc, sizeof(*sc)); 645249423Sdim sc->dev = dev; 646249423Sdim 647249423Sdim /* 648249423Sdim * The SiS 7012 register set isn't quite like the standard ich. 649249423Sdim * There really should be a general "quirks" mechanism. 650243830Sdim */ 651243830Sdim if (pci_get_devid(dev) == SIS7012ID) { 652243830Sdim sc->swap_reg = 1; 653243830Sdim sc->sample_size = 1; 654243830Sdim } else { 655249423Sdim sc->swap_reg = 0; 656249423Sdim sc->sample_size = 2; 657243830Sdim } 658243830Sdim 659243830Sdim data = pci_read_config(dev, PCIR_COMMAND, 2); 660243830Sdim data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 661243830Sdim pci_write_config(dev, PCIR_COMMAND, data, 2); 662243830Sdim data = pci_read_config(dev, PCIR_COMMAND, 2); 663243830Sdim 664243830Sdim sc->nambarid = PCIR_NAMBAR; 665243830Sdim sc->nabmbarid = PCIR_NABMBAR; 666243830Sdim sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 667243830Sdim sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 668249423Sdim 669249423Sdim if (!sc->nambar || !sc->nabmbar) { 670249423Sdim device_printf(dev, "unable to map IO port space\n"); 671243830Sdim goto bad; 672243830Sdim } 673243830Sdim 674243830Sdim sc->nambart = rman_get_bustag(sc->nambar); 675243830Sdim sc->nambarh = rman_get_bushandle(sc->nambar); 676243830Sdim sc->nabmbart = rman_get_bustag(sc->nabmbar); 677243830Sdim sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 678243830Sdim 679243830Sdim sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 680243830Sdim if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 681243830Sdim NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 682243830Sdim device_printf(dev, "unable to create dma tag\n"); 683243830Sdim goto bad; 684243830Sdim } 685243830Sdim 686243830Sdim sc->irqid = 0; 687243830Sdim sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 688243830Sdim if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 689243830Sdim device_printf(dev, "unable to map interrupt\n"); 690243830Sdim goto bad; 691243830Sdim } 692243830Sdim 693249423Sdim if (ich_init(sc)) { 694249423Sdim device_printf(dev, "unable to initialize the card\n"); 695249423Sdim goto bad; 696243830Sdim } 697243830Sdim 698243830Sdim sc->codec = AC97_CREATE(dev, sc, ich_ac97); 699243830Sdim if (sc->codec == NULL) 700243830Sdim goto bad; 701243830Sdim mixer_init(dev, ac97_getmixerclass(), sc->codec); 702243830Sdim 703243830Sdim /* check and set VRA function */ 704243830Sdim extcaps = ac97_getextcaps(sc->codec); 705243830Sdim sc->hasvra = extcaps & AC97_EXTCAP_VRA; 706239310Sdim sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 707243830Sdim sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 708243830Sdim ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 709243830Sdim 710243830Sdim if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 711243830Sdim goto bad; 712243830Sdim 713243830Sdim pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 714243830Sdim pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 715263508Sdim if (sc->hasmic) 716263508Sdim pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 717263508Sdim 718263508Sdim snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 719263508Sdim rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 720263508Sdim 721263508Sdim pcm_setstatus(dev, status); 722263508Sdim 723263508Sdim ich_initsys(sc); 724263508Sdim 725263508Sdim sc->intrhook.ich_func = ich_calibrate; 726263508Sdim sc->intrhook.ich_arg = sc; 727263508Sdim sc->use_intrhook = 1; 728263508Sdim if (config_intrhook_establish(&sc->intrhook) != 0) { 729263508Sdim device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 730263508Sdim sc->use_intrhook = 0; 731263508Sdim ich_calibrate(sc); 732263508Sdim } 733263508Sdim 734263508Sdim return 0; 735243830Sdim 736243830Sdimbad: 737243830Sdim if (sc->codec) 738243830Sdim ac97_destroy(sc->codec); 739249423Sdim if (sc->ih) 740243830Sdim bus_teardown_intr(dev, sc->irq, sc->ih); 741263508Sdim if (sc->irq) 742263508Sdim bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 743263508Sdim if (sc->nambar) 744243830Sdim bus_release_resource(dev, SYS_RES_IOPORT, 745243830Sdim sc->nambarid, sc->nambar); 746243830Sdim if (sc->nabmbar) 747243830Sdim bus_release_resource(dev, SYS_RES_IOPORT, 748243830Sdim sc->nabmbarid, sc->nabmbar); 749243830Sdim free(sc, M_DEVBUF); 750243830Sdim return ENXIO; 751243830Sdim} 752243830Sdim 753243830Sdimstatic int 754243830Sdimich_pci_detach(device_t dev) 755243830Sdim{ 756243830Sdim struct sc_info *sc; 757243830Sdim int r; 758243830Sdim 759243830Sdim r = pcm_unregister(dev); 760243830Sdim if (r) 761243830Sdim return r; 762243830Sdim sc = pcm_getdevinfo(dev); 763243830Sdim 764243830Sdim bus_teardown_intr(dev, sc->irq, sc->ih); 765243830Sdim bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 766243830Sdim bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 767243830Sdim bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 768243830Sdim bus_dma_tag_destroy(sc->dmat); 769243830Sdim free(sc, M_DEVBUF); 770243830Sdim return 0; 771243830Sdim} 772243830Sdim 773243830Sdimstatic int 774249423Sdimich_pci_suspend(device_t dev) 775249423Sdim{ 776249423Sdim struct sc_info *sc; 777249423Sdim int i; 778249423Sdim 779249423Sdim sc = pcm_getdevinfo(dev); 780249423Sdim for (i = 0 ; i < 3; i++) { 781249423Sdim sc->ch[i].run_save = sc->ch[i].run; 782249423Sdim if (sc->ch[i].run) { 783249423Sdim ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 784243830Sdim } 785243830Sdim } 786243830Sdim return 0; 787243830Sdim} 788243830Sdim 789249423Sdimstatic int 790243830Sdimich_pci_resume(device_t dev) 791243830Sdim{ 792249423Sdim struct sc_info *sc; 793249423Sdim int i; 794243830Sdim 795249423Sdim sc = pcm_getdevinfo(dev); 796249423Sdim 797249423Sdim /* Reinit audio device */ 798243830Sdim if (ich_init(sc) == -1) { 799243830Sdim device_printf(dev, "unable to reinitialize the card\n"); 800243830Sdim return ENXIO; 801243830Sdim } 802243830Sdim /* Reinit mixer */ 803249423Sdim if (mixer_reinit(dev) == -1) { 804249423Sdim device_printf(dev, "unable to reinitialize the mixer\n"); 805249423Sdim return ENXIO; 806249423Sdim } 807249423Sdim /* Re-start DMA engines */ 808249423Sdim for (i = 0 ; i < 3; i++) { 809249423Sdim struct sc_chinfo *ch = &sc->ch[i]; 810249423Sdim if (sc->ch[i].run_save) { 811249423Sdim ichchan_setblocksize(0, ch, ch->blksz); 812249423Sdim ichchan_setspeed(0, ch, ch->spd); 813243830Sdim ichchan_trigger(0, ch, PCMTRIG_START); 814249423Sdim } 815243830Sdim } 816243830Sdim return 0; 817243830Sdim} 818243830Sdim 819243830Sdimstatic device_method_t ich_methods[] = { 820243830Sdim /* Device interface */ 821243830Sdim DEVMETHOD(device_probe, ich_pci_probe), 822243830Sdim DEVMETHOD(device_attach, ich_pci_attach), 823243830Sdim DEVMETHOD(device_detach, ich_pci_detach), 824243830Sdim DEVMETHOD(device_suspend, ich_pci_suspend), 825243830Sdim DEVMETHOD(device_resume, ich_pci_resume), 826243830Sdim { 0, 0 } 827243830Sdim}; 828243830Sdim 829243830Sdimstatic driver_t ich_driver = { 830243830Sdim "pcm", 831243830Sdim ich_methods, 832243830Sdim PCM_SOFTC_SIZE, 833243830Sdim}; 834243830Sdim 835243830SdimDRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 836243830SdimMODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 837243830SdimMODULE_VERSION(snd_ich, 1); 838243830Sdim