smbus_if.m revision 41012
121308Sache# 221308Sache# Copyright (c) 1998 Nicolas Souchu 321308Sache# All rights reserved. 421308Sache# 521308Sache# Redistribution and use in source and binary forms, with or without 621308Sache# modification, are permitted provided that the following conditions 721308Sache# are met: 821308Sache# 1. Redistributions of source code must retain the above copyright 921308Sache# notice, this list of conditions and the following disclaimer. 1021308Sache# 2. Redistributions in binary form must reproduce the above copyright 1121308Sache# notice, this list of conditions and the following disclaimer in the 1221308Sache# documentation and/or other materials provided with the distribution. 1321308Sache# 1421308Sache# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1521308Sache# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1621308Sache# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1721308Sache# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1821308Sache# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1921308Sache# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2021308Sache# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2121308Sache# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2221308Sache# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2321308Sache# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2421308Sache# SUCH DAMAGE. 2521308Sache# 2621308Sache# $Id: smbus_if.m,v 1.3 1998/11/07 14:56:04 nsouch Exp $ 2721308Sache# 2821308Sache 2921308SacheINTERFACE smbus; 3021308Sache 3121308Sache# 3221308Sache# Interpret interrupt 3321308Sache# 3421308SacheMETHOD void intr { 3521308Sache device_t dev; 3621308Sache u_char devaddr; 3721308Sache char low; 3821308Sache char high; 3921308Sache int error; 4021308Sache}; 4121308Sache 4221308Sache# 4321308Sache# smbus callback 4421308Sache# 4521308SacheMETHOD int callback { 4621308Sache device_t dev; 4721308Sache int index; 4821308Sache caddr_t data; 4921308Sache}; 5021308Sache 5121308Sache# 5221308Sache# Quick command 5321308Sache# 5421308SacheMETHOD int quick { 5521308Sache device_t dev; 5621308Sache u_char slave; 5721308Sache int how; 5821308Sache}; 5921308Sache 6021308Sache# 6121308Sache# Send Byte command 6221308Sache# 6321308SacheMETHOD int sendb { 6421308Sache device_t dev; 6521308Sache u_char slave; 6621308Sache char byte; 6721308Sache}; 6821308Sache 6921308Sache# 7021308Sache# Receive Byte command 7121308Sache# 7221308SacheMETHOD int recvb { 7321308Sache device_t dev; 7421308Sache u_char slave; 7521308Sache char *byte; 7621308Sache}; 7721308Sache 7821308Sache# 7921308Sache# Write Byte command 8021308Sache# 8121308SacheMETHOD int writeb { 8221308Sache device_t dev; 8321308Sache u_char slave; 8421308Sache char cmd; 8521308Sache char byte; 8621308Sache}; 8721308Sache 8821308Sache# 8921308Sache# Write Word command 9021308Sache# 9121308SacheMETHOD int writew { 9221308Sache device_t dev; 9321308Sache u_char slave; 9421308Sache char cmd; 9521308Sache short word; 9621308Sache}; 9721308Sache 9821308Sache# 9921308Sache# Read Byte command 10021308Sache# 10121308SacheMETHOD int readb { 10221308Sache device_t dev; 10321308Sache u_char slave; 10421308Sache char cmd; 10521308Sache char *byte; 10621308Sache}; 10721308Sache 10821308Sache# 10921308Sache# Read Word command 11021308Sache# 11121308SacheMETHOD int readw { 11221308Sache device_t dev; 11321308Sache u_char slave; 11421308Sache char cmd; 11521308Sache short *word; 11621308Sache}; 11721308Sache 11821308Sache# 11921308Sache# Process Call command 12021308Sache# 12121308SacheMETHOD int pcall { 12221308Sache device_t dev; 12321308Sache u_char slave; 12421308Sache char cmd; 12521308Sache short sdata; 12621308Sache short *rdata; 12721308Sache}; 12821308Sache 12921308Sache# 13021308Sache# Block Write command 13121308Sache# 13221308SacheMETHOD int bwrite { 13321308Sache device_t dev; 13421308Sache u_char slave; 13521308Sache char cmd; 13621308Sache u_char count; 13721308Sache char *buf; 13821308Sache}; 13921308Sache 14021308Sache# 14121308Sache# Block Read command 14221308Sache# 14321308SacheMETHOD int bread { 14421308Sache device_t dev; 14521308Sache u_char slave; 14621308Sache char cmd; 14721308Sache u_char count; 14821308Sache char *buf; 14921308Sache}; 15021308Sache