if_skreg.h revision 50477
160484Sobrien/* 238889Sjdp * Copyright (c) 1997, 1998, 1999 360484Sobrien * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 438889Sjdp * 538889Sjdp * Redistribution and use in source and binary forms, with or without 638889Sjdp * modification, are permitted provided that the following conditions 738889Sjdp * are met: 833965Sjdp * 1. Redistributions of source code must retain the above copyright 938889Sjdp * notice, this list of conditions and the following disclaimer. 1038889Sjdp * 2. Redistributions in binary form must reproduce the above copyright 1138889Sjdp * notice, this list of conditions and the following disclaimer in the 1233965Sjdp * documentation and/or other materials provided with the distribution. 1338889Sjdp * 3. All advertising materials mentioning features or use of this software 1438889Sjdp * must display the following acknowledgement: 1538889Sjdp * This product includes software developed by Bill Paul. 1638889Sjdp * 4. Neither the name of the author nor the names of any co-contributors 1738889Sjdp * may be used to endorse or promote products derived from this software 1833965Sjdp * without specific prior written permission. 1933965Sjdp * 2038889Sjdp * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2133965Sjdp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2233965Sjdp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338889Sjdp * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2438889Sjdp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2538889Sjdp * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2638889Sjdp * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2738889Sjdp * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2838889Sjdp * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2933965Sjdp * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3038889Sjdp * THE POSSIBILITY OF SUCH DAMAGE. 3133965Sjdp * 3233965Sjdp * $FreeBSD: head/sys/dev/sk/if_skreg.h 50477 1999-08-28 01:08:13Z peter $ 3338889Sjdp */ 3433965Sjdp 3560484Sobrien/* 3660484Sobrien * SysKonnect PCI vendor ID 3738889Sjdp */ 3838889Sjdp#define SK_VENDORID 0x1148 3938889Sjdp 4033965Sjdp/* 4138889Sjdp * SK-NET gigabit ethernet device ID 4238889Sjdp */ 4338889Sjdp#define SK_DEVICEID_GE 0x4300 4438889Sjdp 4538889Sjdp/* 4638889Sjdp * GEnesis registers. The GEnesis chip has a 256-byte I/O window 4738889Sjdp * but internally it has a 16K register space. This 16K space is 4833965Sjdp * divided into 128-byte blocks. The first 128 bytes of the I/O 4960484Sobrien * window represent the first block, which is permanently mapped 5033965Sjdp * at the start of the window. The other 127 blocks can be mapped 5138889Sjdp * to the second 128 bytes of the I/O window by setting the desired 5238889Sjdp * block value in the RAP register in block 0. Not all of the 127 5333965Sjdp * blocks are actually used. Most registers are 32 bits wide, but 5438889Sjdp * there are a few 16-bit and 8-bit ones as well. 5538889Sjdp */ 5638889Sjdp 5738889Sjdp 5838889Sjdp/* Start of remappable register window. */ 5938889Sjdp#define SK_WIN_BASE 0x0080 6038889Sjdp 6138889Sjdp/* Size of a window */ 6238889Sjdp#define SK_WIN_LEN 0x80 6338889Sjdp 6438889Sjdp#define SK_WIN_MASK 0x3F80 6538889Sjdp#define SK_REG_MASK 0x7F 6633965Sjdp 6760484Sobrien/* Compute the window of a given register (for the RAP register) */ 6838889Sjdp#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 6960484Sobrien 7060484Sobrien/* Compute the relative offset of a register within the window */ 7133965Sjdp#define SK_REG(reg) ((reg) & SK_REG_MASK) 7260484Sobrien 7360484Sobrien#define SK_PORT_A 0 7460484Sobrien#define SK_PORT_B 1 7538889Sjdp 7660484Sobrien/* 7760484Sobrien * Compute offset of port-specific register. Since there are two 7860484Sobrien * ports, there are two of some GEnesis modules (e.g. two sets of 7960484Sobrien * DMA queues, two sets of FIFO control registers, etc...). Normally, 8060484Sobrien * the block for port 0 is at offset 0x0 and the block for port 1 is 8138889Sjdp * at offset 0x80 (i.e. the next page over). However for the transmit 8260484Sobrien * BMUs and RAMbuffers, there are two blocks for each port: one for 8360484Sobrien * the sync transmit queue and one for the async queue (which we don't 8460484Sobrien * use). However instead of ordering them like this: 8560484Sobrien * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 8660484Sobrien * SysKonnect has instead ordered them like this: 8738889Sjdp * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 8838889Sjdp * This means that when referencing the TX BMU and RAMbuffer registers, 8938889Sjdp * we have to double the block offset (0x80 * 2) in order to reach the 9038889Sjdp * second queue. This prevents us from using the same formula 9160484Sobrien * (sk_port * 0x80) to compute the offsets for all of the port-specific 9260484Sobrien * blocks: we need an extra offset for the BMU and RAMbuffer registers. 9360484Sobrien * The simplest thing is to provide an extra argument to these macros: 9438889Sjdp * the 'skip' parameter. The 'skip' value is the number of extra pages 9560484Sobrien * for skip when computing the port0/port1 offsets. For most registers, 9660484Sobrien * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 9733965Sjdp */ 9860484Sobrien#define SK_IF_READ_4(sc_if, skip, reg) \ 9960484Sobrien sk_win_read_4(sc_if->sk_softc, reg + \ 10038889Sjdp ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 10160484Sobrien#define SK_IF_READ_2(sc_if, skip, reg) \ 10260484Sobrien sk_win_read_2(sc_if->sk_softc, reg + \ 10338889Sjdp ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 10460484Sobrien#define SK_IF_READ_1(sc_if, skip, reg) \ 10533965Sjdp sk_win_read_1(sc_if->sk_softc, reg + \ 10638889Sjdp ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 10733965Sjdp 10860484Sobrien#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 10960484Sobrien sk_win_write_4(sc_if->sk_softc, \ 11033965Sjdp reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 11133965Sjdp#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 11260484Sobrien sk_win_write_2(sc_if->sk_softc, \ 11333965Sjdp reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 11438889Sjdp#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 11533965Sjdp sk_win_write_1(sc_if->sk_softc, \ 11633965Sjdp reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 11733965Sjdp 11833965Sjdp/* Block 0 registers, permanently mapped at iobase. */ 11933965Sjdp#define SK_RAP 0x0000 12033965Sjdp#define SK_CSR 0x0004 12133965Sjdp#define SK_LED 0x0006 12260484Sobrien#define SK_ISR 0x0008 /* interrupt source */ 12333965Sjdp#define SK_IMR 0x000C /* interrupt mask */ 12460484Sobrien#define SK_IESR 0x0010 /* interrupt hardware error source */ 12560484Sobrien#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 12633965Sjdp#define SK_ISSR 0x0018 /* special interrupt source */ 12733965Sjdp#define SK_XM_IMR0 0x0020 12833965Sjdp#define SK_XM_ISR0 0x0028 12933965Sjdp#define SK_XM_PHYADDR0 0x0030 13033965Sjdp#define SK_XM_PHYDATA0 0x0034 13160484Sobrien#define SK_XM_IMR1 0x0040 13233965Sjdp#define SK_XM_ISR1 0x0048 13333965Sjdp#define SK_XM_PHYADDR1 0x0050 13433965Sjdp#define SK_XM_PHYDATA1 0x0054 13533965Sjdp#define SK_BMU_RX_CSR0 0x0060 13633965Sjdp#define SK_BMU_RX_CSR1 0x0064 13760484Sobrien#define SK_BMU_TXS_CSR0 0x0068 13860484Sobrien#define SK_BMU_TXA_CSR0 0x006C 13933965Sjdp#define SK_BMU_TXS_CSR1 0x0070 14060484Sobrien#define SK_BMU_TXA_CSR1 0x0074 14133965Sjdp 14233965Sjdp/* SK_CSR register */ 14333965Sjdp#define SK_CSR_SW_RESET 0x0001 14433965Sjdp#define SK_CSR_SW_UNRESET 0x0002 14533965Sjdp#define SK_CSR_MASTER_RESET 0x0004 14660484Sobrien#define SK_CSR_MASTER_UNRESET 0x0008 14760484Sobrien#define SK_CSR_MASTER_STOP 0x0010 14833965Sjdp#define SK_CSR_MASTER_DONE 0x0020 14933965Sjdp#define SK_CSR_SW_IRQ_CLEAR 0x0040 15060484Sobrien#define SK_CSR_SW_IRQ_SET 0x0080 15160484Sobrien#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 15260484Sobrien#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 15360484Sobrien 15460484Sobrien/* SK_LED register */ 15533965Sjdp#define SK_LED_GREEN_OFF 0x01 15633965Sjdp#define SK_LED_GREEN_ON 0x02 15733965Sjdp 15860484Sobrien/* SK_ISR register */ 15960484Sobrien#define SK_ISR_TX2_AS_CHECK 0x00000001 16033965Sjdp#define SK_ISR_TX2_AS_EOF 0x00000002 16133965Sjdp#define SK_ISR_TX2_AS_EOB 0x00000004 16233965Sjdp#define SK_ISR_TX2_S_CHECK 0x00000008 16360484Sobrien#define SK_ISR_TX2_S_EOF 0x00000010 16433965Sjdp#define SK_ISR_TX2_S_EOB 0x00000020 16560484Sobrien#define SK_ISR_TX1_AS_CHECK 0x00000040 16633965Sjdp#define SK_ISR_TX1_AS_EOF 0x00000080 16760484Sobrien#define SK_ISR_TX1_AS_EOB 0x00000100 16833965Sjdp#define SK_ISR_TX1_S_CHECK 0x00000200 16933965Sjdp#define SK_ISR_TX1_S_EOF 0x00000400 17033965Sjdp#define SK_ISR_TX1_S_EOB 0x00000800 17160484Sobrien#define SK_ISR_RX2_CHECK 0x00001000 17233965Sjdp#define SK_ISR_RX2_EOF 0x00002000 17333965Sjdp#define SK_ISR_RX2_EOB 0x00004000 17433965Sjdp#define SK_ISR_RX1_CHECK 0x00008000 17533965Sjdp#define SK_ISR_RX1_EOF 0x00010000 17633965Sjdp#define SK_ISR_RX1_EOB 0x00020000 17733965Sjdp#define SK_ISR_LINK2_OFLOW 0x00040000 17833965Sjdp#define SK_ISR_MAC2 0x00080000 17933965Sjdp#define SK_ISR_LINK1_OFLOW 0x00100000 18060484Sobrien#define SK_ISR_MAC1 0x00200000 18160484Sobrien#define SK_ISR_TIMER 0x00400000 18233965Sjdp#define SK_ISR_EXTERNAL_REG 0x00800000 18333965Sjdp#define SK_ISR_SW 0x01000000 18433965Sjdp#define SK_ISR_I2C_RDY 0x02000000 18533965Sjdp#define SK_ISR_TX2_TIMEO 0x04000000 18633965Sjdp#define SK_ISR_TX1_TIMEO 0x08000000 18738889Sjdp#define SK_ISR_RX2_TIMEO 0x10000000 18860484Sobrien#define SK_ISR_RX1_TIMEO 0x20000000 18960484Sobrien#define SK_ISR_RSVD 0x40000000 19060484Sobrien#define SK_ISR_HWERR 0x80000000 19160484Sobrien 19260484Sobrien/* SK_IMR register */ 19333965Sjdp#define SK_IMR_TX2_AS_CHECK 0x00000001 19433965Sjdp#define SK_IMR_TX2_AS_EOF 0x00000002 19533965Sjdp#define SK_IMR_TX2_AS_EOB 0x00000004 19633965Sjdp#define SK_IMR_TX2_S_CHECK 0x00000008 19760484Sobrien#define SK_IMR_TX2_S_EOF 0x00000010 19833965Sjdp#define SK_IMR_TX2_S_EOB 0x00000020 19938889Sjdp#define SK_IMR_TX1_AS_CHECK 0x00000040 20038889Sjdp#define SK_IMR_TX1_AS_EOF 0x00000080 20138889Sjdp#define SK_IMR_TX1_AS_EOB 0x00000100 20238889Sjdp#define SK_IMR_TX1_S_CHECK 0x00000200 20338889Sjdp#define SK_IMR_TX1_S_EOF 0x00000400 20438889Sjdp#define SK_IMR_TX1_S_EOB 0x00000800 20560484Sobrien#define SK_IMR_RX2_CHECK 0x00001000 20638889Sjdp#define SK_IMR_RX2_EOF 0x00002000 20738889Sjdp#define SK_IMR_RX2_EOB 0x00004000 20838889Sjdp#define SK_IMR_RX1_CHECK 0x00008000 20938889Sjdp#define SK_IMR_RX1_EOF 0x00010000 21038889Sjdp#define SK_IMR_RX1_EOB 0x00020000 21160484Sobrien#define SK_IMR_LINK2_OFLOW 0x00040000 21260484Sobrien#define SK_IMR_MAC2 0x00080000 21360484Sobrien#define SK_IMR_LINK1_OFLOW 0x00100000 21460484Sobrien#define SK_IMR_MAC1 0x00200000 21560484Sobrien#define SK_IMR_TIMER 0x00400000 21660484Sobrien#define SK_IMR_EXTERNAL_REG 0x00800000 21760484Sobrien#define SK_IMR_SW 0x01000000 21838889Sjdp#define SK_IMR_I2C_RDY 0x02000000 21938889Sjdp#define SK_IMR_TX2_TIMEO 0x04000000 22038889Sjdp#define SK_IMR_TX1_TIMEO 0x08000000 22138889Sjdp#define SK_IMR_RX2_TIMEO 0x10000000 22260484Sobrien#define SK_IMR_RX1_TIMEO 0x20000000 22360484Sobrien#define SK_IMR_RSVD 0x40000000 22438889Sjdp#define SK_IMR_HWERR 0x80000000 22538889Sjdp 22660484Sobrien#define SK_INTRS1 \ 22738889Sjdp (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 22860484Sobrien 22938889Sjdp#define SK_INTRS2 \ 23060484Sobrien (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 23138889Sjdp 23238889Sjdp/* SK_IESR register */ 23338889Sjdp#define SK_IESR_PAR_RX2 0x00000001 23438889Sjdp#define SK_IESR_PAR_RX1 0x00000002 23538889Sjdp#define SK_IESR_PAR_MAC2 0x00000004 23638889Sjdp#define SK_IESR_PAR_MAC1 0x00000008 23738889Sjdp#define SK_IESR_PAR_WR_RAM 0x00000010 23860484Sobrien#define SK_IESR_PAR_RD_RAM 0x00000020 23938889Sjdp#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 24038889Sjdp#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 24138889Sjdp#define SK_IESR_NO_STS_MAC2 0x00000100 24260484Sobrien#define SK_IESR_NO_STS_MAC1 0x00000200 24360484Sobrien#define SK_IESR_IRQ_STS 0x00000400 24438889Sjdp#define SK_IESR_MASTERERR 0x00000800 24538889Sjdp 24638889Sjdp/* SK_IEMR register */ 24738889Sjdp#define SK_IEMR_PAR_RX2 0x00000001 24838889Sjdp#define SK_IEMR_PAR_RX1 0x00000002 24938889Sjdp#define SK_IEMR_PAR_MAC2 0x00000004 25038889Sjdp#define SK_IEMR_PAR_MAC1 0x00000008 25160484Sobrien#define SK_IEMR_PAR_WR_RAM 0x00000010 25260484Sobrien#define SK_IEMR_PAR_RD_RAM 0x00000020 25338889Sjdp#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 25438889Sjdp#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 25560484Sobrien#define SK_IEMR_NO_STS_MAC2 0x00000100 25638889Sjdp#define SK_IEMR_NO_STS_MAC1 0x00000200 25738889Sjdp#define SK_IEMR_IRQ_STS 0x00000400 25833965Sjdp#define SK_IEMR_MASTERERR 0x00000800 25960484Sobrien 26038889Sjdp/* Block 2 */ 26133965Sjdp#define SK_MAC0_0 0x0100 26260484Sobrien#define SK_MAC0_1 0x0104 26333965Sjdp#define SK_MAC1_0 0x0108 26460484Sobrien#define SK_MAC1_1 0x010C 26538889Sjdp#define SK_MAC2_0 0x0110 26660484Sobrien#define SK_MAC2_1 0x0114 26760484Sobrien#define SK_CONNTYPE 0x0118 26833965Sjdp#define SK_PMDTYPE 0x0119 26938889Sjdp#define SK_CONFIG 0x011A 27038889Sjdp#define SK_CHIPVER 0x011B 27138889Sjdp#define SK_EPROM0 0x011C 27238889Sjdp#define SK_EPROM1 0x011D 27338889Sjdp#define SK_EPROM2 0x011E 27438889Sjdp#define SK_EPROM3 0x011F 27538889Sjdp#define SK_EP_ADDR 0x0120 27660484Sobrien#define SK_EP_DATA 0x0124 27760484Sobrien#define SK_EP_LOADCTL 0x0128 27860484Sobrien#define SK_EP_LOADTST 0x0129 27960484Sobrien#define SK_TIMERINIT 0x0130 28060484Sobrien#define SK_TIMER 0x0134 28138889Sjdp#define SK_TIMERCTL 0x0138 28238889Sjdp#define SK_TIMERTST 0x0139 28338889Sjdp#define SK_IMTIMERINIT 0x0140 28438889Sjdp#define SK_IMTIMER 0x0144 28538889Sjdp#define SK_IMTIMERCTL 0x0148 28638889Sjdp#define SK_IMTIMERTST 0x0149 28738889Sjdp#define SK_IMMR 0x014C 28838889Sjdp#define SK_IHWEMR 0x0150 28938889Sjdp#define SK_TESTCTL1 0x0158 29038889Sjdp#define SK_TESTCTL2 0x0159 29138889Sjdp#define SK_GPIO 0x015C 29238889Sjdp#define SK_I2CHWCTL 0x0160 29338889Sjdp#define SK_I2CHWDATA 0x0164 29438889Sjdp#define SK_I2CHWIRQ 0x0168 29538889Sjdp#define SK_I2CSW 0x016C 29638889Sjdp#define SK_BLNKINIT 0x0170 29738889Sjdp#define SK_BLNKCOUNT 0x0174 29838889Sjdp#define SK_BLNKCTL 0x0178 29960484Sobrien#define SK_BLNKSTS 0x0179 30060484Sobrien#define SK_BLNKTST 0x017A 30160484Sobrien 30260484Sobrien#define SK_IMCTL_STOP 0x02 30360484Sobrien#define SK_IMCTL_START 0x04 30460484Sobrien 30538889Sjdp#define SK_IMTIMER_TICKS 54 30638889Sjdp#define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 30738889Sjdp 30838889Sjdp/* 30938889Sjdp * The SK_EPROM0 register contains a byte that describes the 31060484Sobrien * amount of SRAM mounted on the NIC. The value also tells if 31138889Sjdp * the chips are 64K or 128K. This affects the RAMbuffer address 31238889Sjdp * offset that we need to use. 31338889Sjdp */ 31460484Sobrien#define SK_RAMSIZE_512K_64 0x1 31538889Sjdp#define SK_RAMSIZE_1024K_128 0x2 31638889Sjdp#define SK_RAMSIZE_1024K_64 0x3 31760484Sobrien#define SK_RAMSIZE_2048K_128 0x4 31838889Sjdp 31938889Sjdp#define SK_RBOFF_0 0x0 32060484Sobrien#define SK_RBOFF_80000 0x80000 32138889Sjdp 32238889Sjdp#define SK_CONFIG_SINGLEMAC 0x01 32338889Sjdp#define SK_CONFIG_DIS_DSL_CLK 0x02 32460484Sobrien 32538889Sjdp#define SK_PMD_1000BASELX 0x4C 32660484Sobrien#define SK_PMD_1000BASESX 0x53 32738889Sjdp#define SK_PMD_1000BASECX 0x43 32838889Sjdp#define SK_PMD_1000BASETX 0x54 32938889Sjdp 33060484Sobrien/* Block 3 Ram interface and MAC arbiter registers */ 33160484Sobrien#define SK_RAMADDR 0x0180 33260484Sobrien#define SK_RAMDATA0 0x0184 33360484Sobrien#define SK_RAMDATA1 0x0188 33438889Sjdp#define SK_TO0 0x0190 33538889Sjdp#define SK_TO1 0x0191 33638889Sjdp#define SK_TO2 0x0192 33738889Sjdp#define SK_TO3 0x0193 33860484Sobrien#define SK_TO4 0x0194 33960484Sobrien#define SK_TO5 0x0195 34060484Sobrien#define SK_TO6 0x0196 34160484Sobrien#define SK_TO7 0x0197 34260484Sobrien#define SK_TO8 0x0198 34360484Sobrien#define SK_TO9 0x0199 34460484Sobrien#define SK_TO10 0x019A 34538889Sjdp#define SK_TO11 0x019B 34660484Sobrien#define SK_RITIMEO_TMR 0x019C 34738889Sjdp#define SK_RAMCTL 0x01A0 34838889Sjdp#define SK_RITIMER_TST 0x01A2 34938889Sjdp 35038889Sjdp#define SK_RAMCTL_RESET 0x0001 35138889Sjdp#define SK_RAMCTL_UNRESET 0x0002 35238889Sjdp#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 35338889Sjdp#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 35438889Sjdp 35538889Sjdp/* Mac arbiter registers */ 35638889Sjdp#define SK_MINIT_RX1 0x01B0 35738889Sjdp#define SK_MINIT_RX2 0x01B1 35838889Sjdp#define SK_MINIT_TX1 0x01B2 35938889Sjdp#define SK_MINIT_TX2 0x01B3 36038889Sjdp#define SK_MTIMEO_RX1 0x01B4 36138889Sjdp#define SK_MTIMEO_RX2 0x01B5 36238889Sjdp#define SK_MTIMEO_TX1 0x01B6 36338889Sjdp#define SK_MTIEMO_TX2 0x01B7 36438889Sjdp#define SK_MACARB_CTL 0x01B8 36538889Sjdp#define SK_MTIMER_TST 0x01BA 36633965Sjdp#define SK_RCINIT_RX1 0x01C0 36738889Sjdp#define SK_RCINIT_RX2 0x01C1 36833965Sjdp#define SK_RCINIT_TX1 0x01C2 36938889Sjdp#define SK_RCINIT_TX2 0x01C3 37038889Sjdp#define SK_RCTIMEO_RX1 0x01C4 37133965Sjdp#define SK_RCTIMEO_RX2 0x01C5 37238889Sjdp#define SK_RCTIMEO_TX1 0x01C6 37338889Sjdp#define SK_RCTIMEO_TX2 0x01C7 37433965Sjdp#define SK_RECOVERY_CTL 0x01C8 37538889Sjdp#define SK_RCTIMER_TST 0x01CA 37638889Sjdp 37733965Sjdp/* Packet arbiter registers */ 37838889Sjdp#define SK_RXPA1_TINIT 0x01D0 37933965Sjdp#define SK_RXPA2_TINIT 0x01D4 38038889Sjdp#define SK_TXPA1_TINIT 0x01D8 38138889Sjdp#define SK_TXPA2_TINIT 0x01DC 38233965Sjdp#define SK_RXPA1_TIMEO 0x01E0 38338889Sjdp#define SK_RXPA2_TIMEO 0x01E4 38433965Sjdp#define SK_TXPA1_TIMEO 0x01E8 38538889Sjdp#define SK_TXPA2_TIMEO 0x01EC 38638889Sjdp#define SK_PKTARB_CTL 0x01F0 38733965Sjdp#define SK_PKTATB_TST 0x01F2 38838889Sjdp 38938889Sjdp#define SK_PKTARB_TIMEOUT 0x2000 39033965Sjdp 39138889Sjdp#define SK_PKTARBCTL_RESET 0x0001 39238889Sjdp#define SK_PKTARBCTL_UNRESET 0x0002 39333965Sjdp#define SK_PKTARBCTL_RXTO1_OFF 0x0004 39438889Sjdp#define SK_PKTARBCTL_RXTO1_ON 0x0008 39538889Sjdp#define SK_PKTARBCTL_RXTO2_OFF 0x0010 39633965Sjdp#define SK_PKTARBCTL_RXTO2_ON 0x0020 39738889Sjdp#define SK_PKTARBCTL_TXTO1_OFF 0x0040 39838889Sjdp#define SK_PKTARBCTL_TXTO1_ON 0x0080 39933965Sjdp#define SK_PKTARBCTL_TXTO2_OFF 0x0100 40038889Sjdp#define SK_PKTARBCTL_TXTO2_ON 0x0200 40133965Sjdp#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 40238889Sjdp#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 40333965Sjdp#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 40438889Sjdp#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 40533965Sjdp 40638889Sjdp#define SK_MINIT_XMAC_B2 54 40738889Sjdp#define SK_MINIT_XMAC_C1 63 40833965Sjdp 40938889Sjdp#define SK_MACARBCTL_RESET 0x0001 41033965Sjdp#define SK_MACARBCTL_UNRESET 0x0002 41138889Sjdp#define SK_MACARBCTL_FASTOE_OFF 0x0004 41233965Sjdp#define SK_MACARBCRL_FASTOE_ON 0x0008 41338889Sjdp 41438889Sjdp#define SK_RCINIT_XMAC_B2 54 41560484Sobrien#define SK_RCINIT_XMAC_C1 0 41638889Sjdp 41738889Sjdp#define SK_RECOVERYCTL_RX1_OFF 0x0001 41860484Sobrien#define SK_RECOVERYCTL_RX1_ON 0x0002 41960484Sobrien#define SK_RECOVERYCTL_RX2_OFF 0x0004 42038889Sjdp#define SK_RECOVERYCTL_RX2_ON 0x0008 42138889Sjdp#define SK_RECOVERYCTL_TX1_OFF 0x0010 42233965Sjdp#define SK_RECOVERYCTL_TX1_ON 0x0020 42338889Sjdp#define SK_RECOVERYCTL_TX2_OFF 0x0040 42460484Sobrien#define SK_RECOVERYCTL_TX2_ON 0x0080 42538889Sjdp 42660484Sobrien#define SK_RECOVERY_XMAC_B2 \ 42738889Sjdp (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 42833965Sjdp SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 42938889Sjdp 43038889Sjdp#define SK_RECOVERY_XMAC_C1 \ 43133965Sjdp (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 43260484Sobrien SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 43360484Sobrien 43460484Sobrien/* Block 4 -- TX Arbiter MAC 1 */ 43560484Sobrien#define SK_TXAR1_TIMERINIT 0x0200 43660484Sobrien#define SK_TXAR1_TIMERVAL 0x0204 43760484Sobrien#define SK_TXAR1_LIMITINIT 0x0208 43860484Sobrien#define SK_TXAR1_LIMITCNT 0x020C 43960484Sobrien#define SK_TXAR1_COUNTERCTL 0x0210 44060484Sobrien#define SK_TXAR1_COUNTERTST 0x0212 44160484Sobrien#define SK_TXAR1_COUNTERSTS 0x0212 44260484Sobrien 44360484Sobrien/* Block 5 -- TX Arbiter MAC 2 */ 44460484Sobrien#define SK_TXAR2_TIMERINIT 0x0280 44560484Sobrien#define SK_TXAR2_TIMERVAL 0x0284 44660484Sobrien#define SK_TXAR2_LIMITINIT 0x0288 44760484Sobrien#define SK_TXAR2_LIMITCNT 0x028C 44860484Sobrien#define SK_TXAR2_COUNTERCTL 0x0290 44960484Sobrien#define SK_TXAR2_COUNTERTST 0x0291 45060484Sobrien#define SK_TXAR2_COUNTERSTS 0x0292 45160484Sobrien 45260484Sobrien#define SK_TXARCTL_OFF 0x01 45360484Sobrien#define SK_TXARCTL_ON 0x02 45460484Sobrien#define SK_TXARCTL_RATECTL_OFF 0x04 45560484Sobrien#define SK_TXARCTL_RATECTL_ON 0x08 45660484Sobrien#define SK_TXARCTL_ALLOC_OFF 0x10 45760484Sobrien#define SK_TXARCTL_ALLOC_ON 0x20 45860484Sobrien#define SK_TXARCTL_FSYNC_OFF 0x40 45960484Sobrien#define SK_TXARCTL_FSYNC_ON 0x80 46060484Sobrien 46160484Sobrien/* Block 6 -- External registers */ 46260484Sobrien#define SK_EXTREG_BASE 0x300 46360484Sobrien#define SK_EXTREG_END 0x37C 46460484Sobrien 46560484Sobrien/* Block 7 -- PCI config registers */ 46660484Sobrien#define SK_PCI_BASE 0x0380 46760484Sobrien#define SK_PCI_END 0x03FC 46860484Sobrien 46960484Sobrien/* Compute offset of mirrored PCI register */ 47060484Sobrien#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 47160484Sobrien 47260484Sobrien/* Block 8 -- RX queue 1 */ 47360484Sobrien#define SK_RXQ1_BUFCNT 0x0400 47460484Sobrien#define SK_RXQ1_BUFCTL 0x0402 47560484Sobrien#define SK_RXQ1_NEXTDESC 0x0404 47660484Sobrien#define SK_RXQ1_RXBUF_LO 0x0408 47760484Sobrien#define SK_RXQ1_RXBUF_HI 0x040C 47860484Sobrien#define SK_RXQ1_RXSTAT 0x0410 47960484Sobrien#define SK_RXQ1_TIMESTAMP 0x0414 48060484Sobrien#define SK_RXQ1_CSUM1 0x0418 48160484Sobrien#define SK_RXQ1_CSUM2 0x041A 48260484Sobrien#define SK_RXQ1_CSUM1_START 0x041C 48360484Sobrien#define SK_RXQ1_CSUM2_START 0x041E 48460484Sobrien#define SK_RXQ1_CURADDR_LO 0x0420 48560484Sobrien#define SK_RXQ1_CURADDR_HI 0x0424 48660484Sobrien#define SK_RXQ1_CURCNT_LO 0x0428 48738889Sjdp#define SK_RXQ1_CURCNT_HI 0x042C 48833965Sjdp#define SK_RXQ1_CURBYTES 0x0430 48938889Sjdp#define SK_RXQ1_BMU_CSR 0x0434 49060484Sobrien#define SK_RXQ1_WATERMARK 0x0438 49160484Sobrien#define SK_RXQ1_FLAG 0x043A 49260484Sobrien#define SK_RXQ1_TEST1 0x043C 49360484Sobrien#define SK_RXQ1_TEST2 0x0440 49438889Sjdp#define SK_RXQ1_TEST3 0x0444 49560484Sobrien 49638889Sjdp/* Block 9 -- RX queue 2 */ 49760484Sobrien#define SK_RXQ2_BUFCNT 0x0480 49838889Sjdp#define SK_RXQ2_BUFCTL 0x0482 49938889Sjdp#define SK_RXQ2_NEXTDESC 0x0484 50060484Sobrien#define SK_RXQ2_RXBUF_LO 0x0488 50160484Sobrien#define SK_RXQ2_RXBUF_HI 0x048C 50260484Sobrien#define SK_RXQ2_RXSTAT 0x0490 50360484Sobrien#define SK_RXQ2_TIMESTAMP 0x0494 50460484Sobrien#define SK_RXQ2_CSUM1 0x0498 50538889Sjdp#define SK_RXQ2_CSUM2 0x049A 50638889Sjdp#define SK_RXQ2_CSUM1_START 0x049C 50738889Sjdp#define SK_RXQ2_CSUM2_START 0x049E 50838889Sjdp#define SK_RXQ2_CURADDR_LO 0x04A0 50938889Sjdp#define SK_RXQ2_CURADDR_HI 0x04A4 51038889Sjdp#define SK_RXQ2_CURCNT_LO 0x04A8 51138889Sjdp#define SK_RXQ2_CURCNT_HI 0x04AC 51238889Sjdp#define SK_RXQ2_CURBYTES 0x04B0 51338889Sjdp#define SK_RXQ2_BMU_CSR 0x04B4 51438889Sjdp#define SK_RXQ2_WATERMARK 0x04B8 51538889Sjdp#define SK_RXQ2_FLAG 0x04BA 51638889Sjdp#define SK_RXQ2_TEST1 0x04BC 51738889Sjdp#define SK_RXQ2_TEST2 0x04C0 51838889Sjdp#define SK_RXQ2_TEST3 0x04C4 51938889Sjdp 52038889Sjdp#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 52138889Sjdp#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 52238889Sjdp#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 52338889Sjdp#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 52438889Sjdp#define SK_RXBMU_RX_START 0x00000010 52538889Sjdp#define SK_RXBMU_RX_STOP 0x00000020 52638889Sjdp#define SK_RXBMU_POLL_OFF 0x00000040 52738889Sjdp#define SK_RXBMU_POLL_ON 0x00000080 52838889Sjdp#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 52960484Sobrien#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 53038889Sjdp#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 53138889Sjdp#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 53238889Sjdp#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 53338889Sjdp#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 53438889Sjdp#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 53560484Sobrien#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 53660484Sobrien#define SK_RXBMU_PFI_SM_RESET 0x00010000 53760484Sobrien#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 53860484Sobrien#define SK_RXBMU_FIFO_RESET 0x00040000 53960484Sobrien#define SK_RXBMU_FIFO_UNRESET 0x00080000 54060484Sobrien#define SK_RXBMU_DESC_RESET 0x00100000 54138889Sjdp#define SK_RXBMU_DESC_UNRESET 0x00200000 54260484Sobrien#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 54360484Sobrien 54460484Sobrien#define SK_RXBMU_ONLINE \ 54560484Sobrien (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 54660484Sobrien SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 54738889Sjdp SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 54838889Sjdp SK_RXBMU_DESC_UNRESET) 54960484Sobrien 55038889Sjdp#define SK_RXBMU_OFFLINE \ 55138889Sjdp (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 55238889Sjdp SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 55360484Sobrien SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 55438889Sjdp SK_RXBMU_DESC_RESET) 55538889Sjdp 55638889Sjdp/* Block 12 -- TX sync queue 1 */ 55738889Sjdp#define SK_TXQS1_BUFCNT 0x0600 55838889Sjdp#define SK_TXQS1_BUFCTL 0x0602 55938889Sjdp#define SK_TXQS1_NEXTDESC 0x0604 56038889Sjdp#define SK_TXQS1_RXBUF_LO 0x0608 56160484Sobrien#define SK_TXQS1_RXBUF_HI 0x060C 56260484Sobrien#define SK_TXQS1_RXSTAT 0x0610 56360484Sobrien#define SK_TXQS1_CSUM_STARTVAL 0x0614 56460484Sobrien#define SK_TXQS1_CSUM_STARTPOS 0x0618 56560484Sobrien#define SK_TXQS1_CSUM_WRITEPOS 0x061A 56660484Sobrien#define SK_TXQS1_CURADDR_LO 0x0620 56760484Sobrien#define SK_TXQS1_CURADDR_HI 0x0624 56833965Sjdp#define SK_TXQS1_CURCNT_LO 0x0628 56960484Sobrien#define SK_TXQS1_CURCNT_HI 0x062C 57060484Sobrien#define SK_TXQS1_CURBYTES 0x0630 57160484Sobrien#define SK_TXQS1_BMU_CSR 0x0634 57260484Sobrien#define SK_TXQS1_WATERMARK 0x0638 57360484Sobrien#define SK_TXQS1_FLAG 0x063A 57460484Sobrien#define SK_TXQS1_TEST1 0x063C 57560484Sobrien#define SK_TXQS1_TEST2 0x0640 57660484Sobrien#define SK_TXQS1_TEST3 0x0644 57760484Sobrien 57860484Sobrien/* Block 13 -- TX async queue 1 */ 57960484Sobrien#define SK_TXQA1_BUFCNT 0x0680 58060484Sobrien#define SK_TXQA1_BUFCTL 0x0682 58160484Sobrien#define SK_TXQA1_NEXTDESC 0x0684 58260484Sobrien#define SK_TXQA1_RXBUF_LO 0x0688 58360484Sobrien#define SK_TXQA1_RXBUF_HI 0x068C 58460484Sobrien#define SK_TXQA1_RXSTAT 0x0690 58560484Sobrien#define SK_TXQA1_CSUM_STARTVAL 0x0694 58660484Sobrien#define SK_TXQA1_CSUM_STARTPOS 0x0698 58760484Sobrien#define SK_TXQA1_CSUM_WRITEPOS 0x069A 58860484Sobrien#define SK_TXQA1_CURADDR_LO 0x06A0 58960484Sobrien#define SK_TXQA1_CURADDR_HI 0x06A4 59060484Sobrien#define SK_TXQA1_CURCNT_LO 0x06A8 59133965Sjdp#define SK_TXQA1_CURCNT_HI 0x06AC 59260484Sobrien#define SK_TXQA1_CURBYTES 0x06B0 59360484Sobrien#define SK_TXQA1_BMU_CSR 0x06B4 59433965Sjdp#define SK_TXQA1_WATERMARK 0x06B8 59560484Sobrien#define SK_TXQA1_FLAG 0x06BA 59660484Sobrien#define SK_TXQA1_TEST1 0x06BC 59733965Sjdp#define SK_TXQA1_TEST2 0x06C0 59860484Sobrien#define SK_TXQA1_TEST3 0x06C4 59960484Sobrien 60060484Sobrien/* Block 14 -- TX sync queue 2 */ 60160484Sobrien#define SK_TXQS2_BUFCNT 0x0700 60260484Sobrien#define SK_TXQS2_BUFCTL 0x0702 60360484Sobrien#define SK_TXQS2_NEXTDESC 0x0704 60460484Sobrien#define SK_TXQS2_RXBUF_LO 0x0708 60538889Sjdp#define SK_TXQS2_RXBUF_HI 0x070C 60660484Sobrien#define SK_TXQS2_RXSTAT 0x0710 60760484Sobrien#define SK_TXQS2_CSUM_STARTVAL 0x0714 60860484Sobrien#define SK_TXQS2_CSUM_STARTPOS 0x0718 60960484Sobrien#define SK_TXQS2_CSUM_WRITEPOS 0x071A 61038889Sjdp#define SK_TXQS2_CURADDR_LO 0x0720 61138889Sjdp#define SK_TXQS2_CURADDR_HI 0x0724 61238889Sjdp#define SK_TXQS2_CURCNT_LO 0x0728 61338889Sjdp#define SK_TXQS2_CURCNT_HI 0x072C 61438889Sjdp#define SK_TXQS2_CURBYTES 0x0730 61538889Sjdp#define SK_TXQS2_BMU_CSR 0x0734 61638889Sjdp#define SK_TXQS2_WATERMARK 0x0738 61738889Sjdp#define SK_TXQS2_FLAG 0x073A 61860484Sobrien#define SK_TXQS2_TEST1 0x073C 61938889Sjdp#define SK_TXQS2_TEST2 0x0740 62038889Sjdp#define SK_TXQS2_TEST3 0x0744 62138889Sjdp 62260484Sobrien/* Block 15 -- TX async queue 2 */ 62338889Sjdp#define SK_TXQA2_BUFCNT 0x0780 62438889Sjdp#define SK_TXQA2_BUFCTL 0x0782 62538889Sjdp#define SK_TXQA2_NEXTDESC 0x0784 62638889Sjdp#define SK_TXQA2_RXBUF_LO 0x0788 62760484Sobrien#define SK_TXQA2_RXBUF_HI 0x078C 62860484Sobrien#define SK_TXQA2_RXSTAT 0x0790 62960484Sobrien#define SK_TXQA2_CSUM_STARTVAL 0x0794 63038889Sjdp#define SK_TXQA2_CSUM_STARTPOS 0x0798 63160484Sobrien#define SK_TXQA2_CSUM_WRITEPOS 0x079A 63238889Sjdp#define SK_TXQA2_CURADDR_LO 0x07A0 63360484Sobrien#define SK_TXQA2_CURADDR_HI 0x07A4 63460484Sobrien#define SK_TXQA2_CURCNT_LO 0x07A8 63560484Sobrien#define SK_TXQA2_CURCNT_HI 0x07AC 63638889Sjdp#define SK_TXQA2_CURBYTES 0x07B0 63760484Sobrien#define SK_TXQA2_BMU_CSR 0x07B4 63838889Sjdp#define SK_TXQA2_WATERMARK 0x07B8 63938889Sjdp#define SK_TXQA2_FLAG 0x07BA 64060484Sobrien#define SK_TXQA2_TEST1 0x07BC 64160484Sobrien#define SK_TXQA2_TEST2 0x07C0 64260484Sobrien#define SK_TXQA2_TEST3 0x07C4 64360484Sobrien 64460484Sobrien#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 64538889Sjdp#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 64638889Sjdp#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 64760484Sobrien#define SK_TXBMU_TX_START 0x00000010 64838889Sjdp#define SK_TXBMU_TX_STOP 0x00000020 64938889Sjdp#define SK_TXBMU_POLL_OFF 0x00000040 65060484Sobrien#define SK_TXBMU_POLL_ON 0x00000080 65160484Sobrien#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 65238889Sjdp#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 65338889Sjdp#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 65460484Sobrien#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 65560484Sobrien#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 65660484Sobrien#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 65760484Sobrien#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 65860484Sobrien#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 65960484Sobrien#define SK_TXBMU_PFI_SM_RESET 0x00010000 66060484Sobrien#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 66160484Sobrien#define SK_TXBMU_FIFO_RESET 0x00040000 66260484Sobrien#define SK_TXBMU_FIFO_UNRESET 0x00080000 66360484Sobrien#define SK_TXBMU_DESC_RESET 0x00100000 66460484Sobrien#define SK_TXBMU_DESC_UNRESET 0x00200000 66560484Sobrien#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 66660484Sobrien 66760484Sobrien#define SK_TXBMU_ONLINE \ 66860484Sobrien (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 66960484Sobrien SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 67060484Sobrien SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 67160484Sobrien SK_TXBMU_DESC_UNRESET) 67260484Sobrien 67360484Sobrien#define SK_TXBMU_OFFLINE \ 67460484Sobrien (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 67538889Sjdp SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 67638889Sjdp SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 67738889Sjdp SK_TXBMU_DESC_RESET) 67838889Sjdp 67938889Sjdp/* Block 16 -- Receive RAMbuffer 1 */ 68038889Sjdp#define SK_RXRB1_START 0x0800 68160484Sobrien#define SK_RXRB1_END 0x0804 68260484Sobrien#define SK_RXRB1_WR_PTR 0x0808 68360484Sobrien#define SK_RXRB1_RD_PTR 0x080C 68438889Sjdp#define SK_RXRB1_UTHR_PAUSE 0x0810 68533965Sjdp#define SK_RXRB1_LTHR_PAUSE 0x0814 68638889Sjdp#define SK_RXRB1_UTHR_HIPRIO 0x0818 68733965Sjdp#define SK_RXRB1_UTHR_LOPRIO 0x081C 68838889Sjdp#define SK_RXRB1_PKTCNT 0x0820 68960484Sobrien#define SK_RXRB1_LVL 0x0824 69060484Sobrien#define SK_RXRB1_CTLTST 0x0828 69160484Sobrien 69238889Sjdp/* Block 17 -- Receive RAMbuffer 2 */ 69360484Sobrien#define SK_RXRB2_START 0x0880 69460484Sobrien#define SK_RXRB2_END 0x0884 69560484Sobrien#define SK_RXRB2_WR_PTR 0x0888 69660484Sobrien#define SK_RXRB2_RD_PTR 0x088C 69760484Sobrien#define SK_RXRB2_UTHR_PAUSE 0x0890 69860484Sobrien#define SK_RXRB2_LTHR_PAUSE 0x0894 69960484Sobrien#define SK_RXRB2_UTHR_HIPRIO 0x0898 70033965Sjdp#define SK_RXRB2_UTHR_LOPRIO 0x089C 70133965Sjdp#define SK_RXRB2_PKTCNT 0x08A0 70260484Sobrien#define SK_RXRB2_LVL 0x08A4 70360484Sobrien#define SK_RXRB2_CTLTST 0x08A8 70460484Sobrien 70560484Sobrien/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 70660484Sobrien#define SK_TXRBS1_START 0x0A00 70733965Sjdp#define SK_TXRBS1_END 0x0A04 70860484Sobrien#define SK_TXRBS1_WR_PTR 0x0A08 70960484Sobrien#define SK_TXRBS1_RD_PTR 0x0A0C 71060484Sobrien#define SK_TXRBS1_PKTCNT 0x0A20 71160484Sobrien#define SK_TXRBS1_LVL 0x0A24 71260484Sobrien#define SK_TXRBS1_CTLTST 0x0A28 71333965Sjdp 71433965Sjdp/* Block 21 -- Async. Transmit RAMbuffer 1 */ 71533965Sjdp#define SK_TXRBA1_START 0x0A80 71633965Sjdp#define SK_TXRBA1_END 0x0A84 71733965Sjdp#define SK_TXRBA1_WR_PTR 0x0A88 71833965Sjdp#define SK_TXRBA1_RD_PTR 0x0A8C 71933965Sjdp#define SK_TXRBA1_PKTCNT 0x0AA0 72033965Sjdp#define SK_TXRBA1_LVL 0x0AA4 72160484Sobrien#define SK_TXRBA1_CTLTST 0x0AA8 72233965Sjdp 72360484Sobrien/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 72433965Sjdp#define SK_TXRBS2_START 0x0B00 72533965Sjdp#define SK_TXRBS2_END 0x0B04 72660484Sobrien#define SK_TXRBS2_WR_PTR 0x0B08 72733965Sjdp#define SK_TXRBS2_RD_PTR 0x0B0C 72860484Sobrien#define SK_TXRBS2_PKTCNT 0x0B20 72933965Sjdp#define SK_TXRBS2_LVL 0x0B24 73033965Sjdp#define SK_TXRBS2_CTLTST 0x0B28 73160484Sobrien 73238889Sjdp/* Block 23 -- Async. Transmit RAMbuffer 2 */ 73360484Sobrien#define SK_TXRBA2_START 0x0B80 73438889Sjdp#define SK_TXRBA2_END 0x0B84 73533965Sjdp#define SK_TXRBA2_WR_PTR 0x0B88 73638889Sjdp#define SK_TXRBA2_RD_PTR 0x0B8C 73738889Sjdp#define SK_TXRBA2_PKTCNT 0x0BA0 73833965Sjdp#define SK_TXRBA2_LVL 0x0BA4 73933965Sjdp#define SK_TXRBA2_CTLTST 0x0BA8 74033965Sjdp 74133965Sjdp#define SK_RBCTL_RESET 0x00000001 74238889Sjdp#define SK_RBCTL_UNRESET 0x00000002 74333965Sjdp#define SK_RBCTL_OFF 0x00000004 74438889Sjdp#define SK_RBCTL_ON 0x00000008 74533965Sjdp#define SK_RBCTL_STORENFWD_OFF 0x00000010 74638889Sjdp#define SK_RBCTL_STORENFWD_ON 0x00000020 74760484Sobrien 74860484Sobrien/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 74960484Sobrien#define SK_RXF1_END 0x0C00 75060484Sobrien#define SK_RXF1_WPTR 0x0C04 75160484Sobrien#define SK_RXF1_RPTR 0x0C0C 75260484Sobrien#define SK_RXF1_PKTCNT 0x0C10 75360484Sobrien#define SK_RXF1_LVL 0x0C14 75460484Sobrien#define SK_RXF1_MACCTL 0x0C18 75560484Sobrien#define SK_RXF1_CTL 0x0C1C 75660484Sobrien#define SK_RXLED1_CNTINIT 0x0C20 75760484Sobrien#define SK_RXLED1_COUNTER 0x0C24 75860484Sobrien#define SK_RXLED1_CTL 0x0C28 75960484Sobrien#define SK_RXLED1_TST 0x0C29 76060484Sobrien#define SK_LINK_SYNC1_CINIT 0x0C30 76160484Sobrien#define SK_LINK_SYNC1_COUNTER 0x0C34 76238889Sjdp#define SK_LINK_SYNC1_CTL 0x0C38 76360484Sobrien#define SK_LINK_SYNC1_TST 0x0C39 76460484Sobrien#define SK_LINKLED1_CTL 0x0C3C 76538889Sjdp 76638889Sjdp#define SK_FIFO_END 0x3F 76738889Sjdp 76838889Sjdp/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 76938889Sjdp#define SK_RXF2_END 0x0C80 77033965Sjdp#define SK_RXF2_WPTR 0x0C84 77138889Sjdp#define SK_RXF2_RPTR 0x0C8C 77260484Sobrien#define SK_RXF2_PKTCNT 0x0C90 77360484Sobrien#define SK_RXF2_LVL 0x0C94 77460484Sobrien#define SK_RXF2_MACCTL 0x0C98 77538889Sjdp#define SK_RXF2_CTL 0x0C9C 77660484Sobrien#define SK_RXLED2_CNTINIT 0x0CA0 77738889Sjdp#define SK_RXLED2_COUNTER 0x0CA4 77838889Sjdp#define SK_RXLED2_CTL 0x0CA8 77960484Sobrien#define SK_RXLED2_TST 0x0CA9 78060484Sobrien#define SK_LINK_SYNC2_CINIT 0x0CB0 78160484Sobrien#define SK_LINK_SYNC2_COUNTER 0x0CB4 78260484Sobrien#define SK_LINK_SYNC2_CTL 0x0CB8 78360484Sobrien#define SK_LINK_SYNC2_TST 0x0CB9 78460484Sobrien#define SK_LINKLED2_CTL 0x0CBC 78560484Sobrien 78660484Sobrien#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 78760484Sobrien#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 78860484Sobrien#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 78960484Sobrien#define SK_RXMACCTL_RSTAMP_ON 0x00000008 79060484Sobrien#define SK_RXMACCTL_FLUSH_OFF 0x00000010 79160484Sobrien#define SK_RXMACCTL_FLUSH_ON 0x00000020 79260484Sobrien#define SK_RXMACCTL_PAUSE_OFF 0x00000040 79360484Sobrien#define SK_RXMACCTL_PAUSE_ON 0x00000080 79438889Sjdp#define SK_RXMACCTL_AFULL_OFF 0x00000100 79560484Sobrien#define SK_RXMACCTL_AFULL_ON 0x00000200 79638889Sjdp#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 79760484Sobrien#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 79838889Sjdp#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 79933965Sjdp#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 80060484Sobrien#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 80160484Sobrien#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 80260484Sobrien 80338889Sjdp#define SK_RXLEDCTL_ENABLE 0x0001 80460484Sobrien#define SK_RXLEDCTL_COUNTER_STOP 0x0002 80538889Sjdp#define SK_RXLEDCTL_COUNTER_START 0x0004 80633965Sjdp 80738889Sjdp#define SK_LINKLED_OFF 0x0001 80860484Sobrien#define SK_LINKLED_ON 0x0002 80960484Sobrien#define SK_LINKLED_LINKSYNC_OFF 0x0004 81060484Sobrien#define SK_LINKLED_LINKSYNC_ON 0x0008 81160484Sobrien#define SK_LINKLED_BLINK_OFF 0x0010 81260484Sobrien#define SK_LINKLED_BLINK_ON 0x0020 81338889Sjdp 81460484Sobrien/* Block 26 -- TX MAC FIFO 1 regisrers */ 81560484Sobrien#define SK_TXF1_END 0x0D00 81660484Sobrien#define SK_TXF1_WPTR 0x0D04 81760484Sobrien#define SK_TXF1_RPTR 0x0D0C 81860484Sobrien#define SK_TXF1_PKTCNT 0x0D10 81960484Sobrien#define SK_TXF1_LVL 0x0D14 82060484Sobrien#define SK_TXF1_MACCTL 0x0D18 82160484Sobrien#define SK_TXF1_CTL 0x0D1C 82260484Sobrien#define SK_TXLED1_CNTINIT 0x0D20 82360484Sobrien#define SK_TXLED1_COUNTER 0x0D24 82460484Sobrien#define SK_TXLED1_CTL 0x0D28 82538889Sjdp#define SK_TXLED1_TST 0x0D29 82660484Sobrien 82760484Sobrien/* Block 27 -- TX MAC FIFO 2 regisrers */ 82838889Sjdp#define SK_TXF2_END 0x0D80 82938889Sjdp#define SK_TXF2_WPTR 0x0D84 83060484Sobrien#define SK_TXF2_RPTR 0x0D8C 83160484Sobrien#define SK_TXF2_PKTCNT 0x0D90 83260484Sobrien#define SK_TXF2_LVL 0x0D94 83338889Sjdp#define SK_TXF2_MACCTL 0x0D98 83460484Sobrien#define SK_TXF2_CTL 0x0D9C 83533965Sjdp#define SK_TXLED2_CNTINIT 0x0DA0 83660484Sobrien#define SK_TXLED2_COUNTER 0x0DA4 83738889Sjdp#define SK_TXLED2_CTL 0x0DA8 83838889Sjdp#define SK_TXLED2_TST 0x0DA9 83938889Sjdp 84060484Sobrien#define SK_TXMACCTL_XMAC_RESET 0x00000001 84138889Sjdp#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 84238889Sjdp#define SK_TXMACCTL_LOOP_OFF 0x00000004 84360484Sobrien#define SK_TXMACCTL_LOOP_ON 0x00000008 84438889Sjdp#define SK_TXMACCTL_FLUSH_OFF 0x00000010 84538889Sjdp#define SK_TXMACCTL_FLUSH_ON 0x00000020 84660484Sobrien#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 84760484Sobrien#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 84860484Sobrien#define SK_TXMACCTL_AFULL_OFF 0x00000100 84960484Sobrien#define SK_TXMACCTL_AFULL_ON 0x00000200 85060484Sobrien#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 85138889Sjdp#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 85233965Sjdp#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 85360484Sobrien#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 85460484Sobrien#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 85538889Sjdp#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 85633965Sjdp 85738889Sjdp#define SK_TXLEDCTL_ENABLE 0x0001 85833965Sjdp#define SK_TXLEDCTL_COUNTER_STOP 0x0002 85960484Sobrien#define SK_TXLEDCTL_COUNTER_START 0x0004 86038889Sjdp 86160484Sobrien#define SK_FIFO_RESET 0x00000001 86260484Sobrien#define SK_FIFO_UNRESET 0x00000002 86360484Sobrien#define SK_FIFO_OFF 0x00000004 86460484Sobrien#define SK_FIFO_ON 0x00000008 86560484Sobrien 86660484Sobrien/* Block 0x40 to 0x4F -- XMAC 1 registers */ 86760484Sobrien#define SK_XMAC1_BASE 0x2000 86860484Sobrien#define SK_XMAC1_END 0x23FF 86960484Sobrien 87060484Sobrien/* Block 0x60 to 0x6F -- XMAC 2 registers */ 87160484Sobrien#define SK_XMAC2_BASE 0x3000 87238889Sjdp#define SK_XMAC2_END 0x33FF 87333965Sjdp 87438889Sjdp/* Compute relative offset of an XMAC register in the XMAC window(s). */ 87533965Sjdp#define SK_XMAC_REG(reg, mac) (((reg) * 2) + SK_XMAC1_BASE + \ 87638889Sjdp (mac * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 87733965Sjdp 87838889Sjdp#define SK_XM_READ_4(sc, reg) \ 87938889Sjdp (sk_win_read_2(sc->sk_softc, \ 88038889Sjdp SK_XMAC_REG(reg, sc->sk_port)) & 0xFFFF) | \ 88138889Sjdp ((sk_win_read_2(sc->sk_softc, \ 882 SK_XMAC_REG(reg + 2, sc->sk_port)) << 16) & 0xFFFF0000) 883 884#define SK_XM_WRITE_4(sc, reg, val) \ 885 sk_win_write_2(sc->sk_softc, \ 886 SK_XMAC_REG(reg, sc->sk_port), ((val) & 0xFFFF)); \ 887 sk_win_write_2(sc->sk_softc, \ 888 SK_XMAC_REG(reg + 2, sc->sk_port), ((val) >> 16) & 0xFFFF); 889 890#define SK_XM_READ_2(sc, reg) \ 891 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(reg, sc->sk_port)) 892 893#define SK_XM_WRITE_2(sc, reg, val) \ 894 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(reg, sc->sk_port), val) 895 896#define SK_XM_SETBIT_4(sc, reg, x) \ 897 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 898 899#define SK_XM_CLRBIT_4(sc, reg, x) \ 900 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 901 902#define SK_XM_SETBIT_2(sc, reg, x) \ 903 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 904 905#define SK_XM_CLRBIT_2(sc, reg, x) \ 906 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 907 908 909/* 910 * The default FIFO threshold on the XMAC II is 4 bytes. On 911 * dual port NICs, this often leads to transmit underruns, so we 912 * bump the threshold a little. 913 */ 914#define SK_XM_TX_FIFOTHRESH 512 915 916#define SK_PCI_VENDOR_ID 0x0000 917#define SK_PCI_DEVICE_ID 0x0002 918#define SK_PCI_COMMAND 0x0004 919#define SK_PCI_STATUS 0x0006 920#define SK_PCI_REVID 0x0008 921#define SK_PCI_CLASSCODE 0x0009 922#define SK_PCI_CACHELEN 0x000C 923#define SK_PCI_LATENCY_TIMER 0x000D 924#define SK_PCI_HEADER_TYPE 0x000E 925#define SK_PCI_LOMEM 0x0010 926#define SK_PCI_LOIO 0x0014 927#define SK_PCI_SUBVEN_ID 0x002C 928#define SK_PCI_SYBSYS_ID 0x002E 929#define SK_PCI_BIOSROM 0x0030 930#define SK_PCI_INTLINE 0x003C 931#define SK_PCI_INTPIN 0x003D 932#define SK_PCI_MINGNT 0x003E 933#define SK_PCI_MINLAT 0x003F 934 935/* device specific PCI registers */ 936#define SK_PCI_OURREG1 0x0040 937#define SK_PCI_OURREG2 0x0044 938#define SK_PCI_CAPID 0x0048 /* 8 bits */ 939#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 940#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 941#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 942#define SK_PCI_PME_EVENT 0x004F 943#define SK_PCI_VPD_CAPID 0x0050 944#define SK_PCI_VPD_NEXTPTR 0x0051 945#define SK_PCI_VPD_ADDR 0x0052 946#define SK_PCI_VPD_DATA 0x0054 947 948#define SK_PSTATE_MASK 0x0003 949#define SK_PSTATE_D0 0x0000 950#define SK_PSTATE_D1 0x0001 951#define SK_PSTATE_D2 0x0002 952#define SK_PSTATE_D3 0x0003 953#define SK_PME_EN 0x0010 954#define SK_PME_STATUS 0x8000 955 956/* 957 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 958 * read is complete. Set to 1 to initiate a write, will become 0 959 * when write is finished. 960 */ 961#define SK_VPD_FLAG 0x8000 962 963/* VPD structures */ 964struct vpd_res { 965 u_int8_t vr_id; 966 u_int8_t vr_len; 967 u_int8_t vr_pad; 968}; 969 970struct vpd_key { 971 char vk_key[2]; 972 u_int8_t vk_len; 973}; 974 975#define VPD_RES_ID 0x82 /* ID string */ 976#define VPD_RES_READ 0x90 /* start of read only area */ 977#define VPD_RES_WRITE 0x81 /* start of read/write area */ 978#define VPD_RES_END 0x78 /* end tag */ 979 980#define CSR_WRITE_4(sc, reg, val) \ 981 bus_space_write_4(sc->sk_btag, sc->sk_bhandle, reg, val) 982#define CSR_WRITE_2(sc, reg, val) \ 983 bus_space_write_2(sc->sk_btag, sc->sk_bhandle, reg, val) 984#define CSR_WRITE_1(sc, reg, val) \ 985 bus_space_write_1(sc->sk_btag, sc->sk_bhandle, reg, val) 986 987#define CSR_READ_4(sc, reg) \ 988 bus_space_read_4(sc->sk_btag, sc->sk_bhandle, reg) 989#define CSR_READ_2(sc, reg) \ 990 bus_space_read_2(sc->sk_btag, sc->sk_bhandle, reg) 991#define CSR_READ_1(sc, reg) \ 992 bus_space_read_1(sc->sk_btag, sc->sk_bhandle, reg) 993 994struct sk_type { 995 u_int16_t sk_vid; 996 u_int16_t sk_did; 997 char *sk_name; 998}; 999 1000/* RX queue descriptor data structure */ 1001struct sk_rx_desc { 1002 u_int32_t sk_ctl; 1003 u_int32_t sk_next; 1004 u_int32_t sk_data_lo; 1005 u_int32_t sk_data_hi; 1006 u_int32_t sk_xmac_rxstat; 1007 u_int32_t sk_timestamp; 1008 u_int16_t sk_csum2; 1009 u_int16_t sk_csum1; 1010 u_int16_t sk_csum2_start; 1011 u_int16_t sk_csum1_start; 1012}; 1013 1014#define SK_OPCODE_DEFAULT 0x00550000 1015#define SK_OPCODE_CSUM 0x00560000 1016 1017#define SK_RXCTL_LEN 0x0000FFFF 1018#define SK_RXCTL_OPCODE 0x00FF0000 1019#define SK_RXCTL_TSTAMP_VALID 0x01000000 1020#define SK_RXCTL_STATUS_VALID 0x02000000 1021#define SK_RXCTL_DEV0 0x04000000 1022#define SK_RXCTL_EOF_INTR 0x08000000 1023#define SK_RXCTL_EOB_INTR 0x10000000 1024#define SK_RXCTL_LASTFRAG 0x20000000 1025#define SK_RXCTL_FIRSTFRAG 0x40000000 1026#define SK_RXCTL_OWN 0x80000000 1027 1028#define SK_RXSTAT \ 1029 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1030 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1031 1032struct sk_tx_desc { 1033 u_int32_t sk_ctl; 1034 u_int32_t sk_next; 1035 u_int32_t sk_data_lo; 1036 u_int32_t sk_data_hi; 1037 u_int32_t sk_xmac_txstat; 1038 u_int16_t sk_rsvd0; 1039 u_int16_t sk_csum_startval; 1040 u_int16_t sk_csum_startpos; 1041 u_int16_t sk_csum_writepos; 1042 u_int32_t sk_rsvd1; 1043}; 1044 1045#define SK_TXCTL_LEN 0x0000FFFF 1046#define SK_TXCTL_OPCODE 0x00FF0000 1047#define SK_TXCTL_SW 0x01000000 1048#define SK_TXCTL_NOCRC 0x02000000 1049#define SK_TXCTL_STORENFWD 0x04000000 1050#define SK_TXCTL_EOF_INTR 0x08000000 1051#define SK_TXCTL_EOB_INTR 0x10000000 1052#define SK_TXCTL_LASTFRAG 0x20000000 1053#define SK_TXCTL_FIRSTFRAG 0x40000000 1054#define SK_TXCTL_OWN 0x80000000 1055 1056#define SK_TXSTAT \ 1057 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1058 1059#define SK_RXBYTES(x) (x) & 0x0000FFFF; 1060#define SK_TXBYTES SK_RXBYTES 1061 1062#define SK_TX_RING_CNT 512 1063#define SK_RX_RING_CNT 256 1064 1065/* 1066 * Jumbo buffer stuff. Note that we must allocate more jumbo 1067 * buffers than there are descriptors in the receive ring. This 1068 * is because we don't know how long it will take for a packet 1069 * to be released after we hand it off to the upper protocol 1070 * layers. To be safe, we allocate 1.5 times the number of 1071 * receive descriptors. 1072 */ 1073#define SK_JUMBO_FRAMELEN 9018 1074#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1075#define SK_JSLOTS 384 1076 1077#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 1078#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1079 (SK_JRAWLEN % sizeof(u_int64_t)))) 1080#define SK_MCLBYTES (SK_JLEN - sizeof(u_int64_t)) 1081#define SK_JPAGESZ PAGE_SIZE 1082#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1083#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1084 1085struct sk_jslot { 1086 caddr_t sk_buf; 1087 int sk_inuse; 1088}; 1089 1090struct sk_jpool_entry { 1091 int slot; 1092 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1093}; 1094 1095struct sk_chain { 1096 void *sk_desc; 1097 struct mbuf *sk_mbuf; 1098 struct sk_chain *sk_next; 1099}; 1100 1101struct sk_chain_data { 1102 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1103 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1104 int sk_tx_prod; 1105 int sk_tx_cons; 1106 int sk_tx_cnt; 1107 int sk_rx_prod; 1108 int sk_rx_cons; 1109 int sk_rx_cnt; 1110 /* Stick the jumbo mem management stuff here too. */ 1111 struct sk_jslot sk_jslots[SK_JSLOTS]; 1112 void *sk_jumbo_buf; 1113 1114}; 1115 1116struct sk_ring_data { 1117 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1118 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1119}; 1120 1121#define SK_INC(x, y) (x) = (x + 1) % y 1122 1123/* Forward decl. */ 1124struct sk_if_softc; 1125 1126/* Softc for the GEnesis controller. */ 1127struct sk_softc { 1128 bus_space_handle_t sk_bhandle; /* bus space handle */ 1129 bus_space_tag_t sk_btag; /* bus space tag */ 1130 void *sk_intrhand; /* irq handler handle */ 1131 struct resource *sk_irq; /* IRQ resource handle */ 1132 struct resource *sk_res; /* I/O or shared mem handle */ 1133 u_int8_t sk_unit; /* controller number */ 1134 u_int8_t sk_type; 1135 char *sk_vpd_prodname; 1136 char *sk_vpd_readonly; 1137 u_int32_t sk_rboff; /* RAMbuffer offset */ 1138 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1139 u_int32_t sk_pmd; /* physical media type */ 1140 u_int32_t sk_intrmask; 1141 struct sk_if_softc *sk_if[2]; 1142}; 1143 1144/* Softc for each logical interface */ 1145struct sk_if_softc { 1146 struct arpcom arpcom; /* interface info */ 1147 struct ifmedia ifmedia; /* media info */ 1148 u_int8_t sk_unit; /* interface number */ 1149 u_int8_t sk_port; /* port # on controller */ 1150 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1151 u_int8_t sk_link; 1152 u_int32_t sk_rx_ramstart; 1153 u_int32_t sk_rx_ramend; 1154 u_int32_t sk_tx_ramstart; 1155 u_int32_t sk_tx_ramend; 1156 struct sk_chain_data sk_cdata; 1157 struct sk_ring_data *sk_rdata; 1158 struct sk_softc *sk_softc; /* parent controller */ 1159 int sk_tx_bmu; /* TX BMU register */ 1160 int sk_if_flags; 1161 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1162 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1163}; 1164 1165#define SK_TIMEOUT 1000 1166#define ETHER_ALIGN 2 1167 1168#ifdef __alpha__ 1169#undef vtophys 1170#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1171#endif 1172