1139825Simp/*- 250974Swpaul * Copyright (c) 1997, 1998, 1999 350974Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 450974Swpaul * 550974Swpaul * Redistribution and use in source and binary forms, with or without 650974Swpaul * modification, are permitted provided that the following conditions 750974Swpaul * are met: 850974Swpaul * 1. Redistributions of source code must retain the above copyright 950974Swpaul * notice, this list of conditions and the following disclaimer. 1050974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150974Swpaul * notice, this list of conditions and the following disclaimer in the 1250974Swpaul * documentation and/or other materials provided with the distribution. 1350974Swpaul * 3. All advertising materials mentioning features or use of this software 1450974Swpaul * must display the following acknowledgement: 1550974Swpaul * This product includes software developed by Bill Paul. 1650974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750974Swpaul * may be used to endorse or promote products derived from this software 1850974Swpaul * without specific prior written permission. 1950974Swpaul * 2050974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150974Swpaul * 3250974Swpaul * $FreeBSD$ 3350974Swpaul */ 3450974Swpaul 3550974Swpaul/* 3650974Swpaul * Register definitions for the SiS 900 and SiS 7016 chipsets. The 3750974Swpaul * 7016 is actually an older chip and some of its registers differ 3850974Swpaul * from the 900, however the core operational registers are the same: 3950974Swpaul * the differences lie in the OnNow/Wake on LAN stuff which we don't 4050974Swpaul * use anyway. The 7016 needs an external MII compliant PHY while the 4150974Swpaul * SiS 900 has one built in. All registers are 32-bits wide. 4250974Swpaul */ 4350974Swpaul 4450974Swpaul/* Registers common to SiS 900 and SiS 7016 */ 4550974Swpaul#define SIS_CSR 0x00 4650974Swpaul#define SIS_CFG 0x04 4750974Swpaul#define SIS_EECTL 0x08 4850974Swpaul#define SIS_PCICTL 0x0C 4950974Swpaul#define SIS_ISR 0x10 5050974Swpaul#define SIS_IMR 0x14 5150974Swpaul#define SIS_IER 0x18 5250974Swpaul#define SIS_PHYCTL 0x1C 5350974Swpaul#define SIS_TX_LISTPTR 0x20 5450974Swpaul#define SIS_TX_CFG 0x24 5550974Swpaul#define SIS_RX_LISTPTR 0x30 5650974Swpaul#define SIS_RX_CFG 0x34 5750974Swpaul#define SIS_FLOWCTL 0x38 5850974Swpaul#define SIS_RXFILT_CTL 0x48 5950974Swpaul#define SIS_RXFILT_DATA 0x4C 6050974Swpaul#define SIS_PWRMAN_CTL 0xB0 6150974Swpaul#define SIS_PWERMAN_WKUP_EVENT 0xB4 6250974Swpaul#define SIS_WKUP_FRAME_CRC 0xBC 6350974Swpaul#define SIS_WKUP_FRAME_MASK0 0xC0 6450974Swpaul#define SIS_WKUP_FRAME_MASKXX 0xEC 6550974Swpaul 6650974Swpaul/* SiS 7016 specific registers */ 6750974Swpaul#define SIS_SILICON_REV 0x5C 6850974Swpaul#define SIS_MIB_CTL0 0x60 6950974Swpaul#define SIS_MIB_CTL1 0x64 7050974Swpaul#define SIS_MIB_CTL2 0x68 7150974Swpaul#define SIS_MIB_CTL3 0x6C 7250974Swpaul#define SIS_MIB 0x80 7350974Swpaul#define SIS_LINKSTS 0xA0 7450974Swpaul#define SIS_TIMEUNIT 0xA4 7550974Swpaul#define SIS_GPIO 0xB8 7650974Swpaul 77119712Sphk/* NS DP83815/6 registers */ 78119712Sphk#define NS_IHR 0x1C 7972813Swpaul#define NS_CLKRUN 0x3C 80212167Syongari#define NS_WCSR 0x40 81119712Sphk#define NS_SRR 0x58 8262672Swpaul#define NS_BMCR 0x80 8362672Swpaul#define NS_BMSR 0x84 8462672Swpaul#define NS_PHYIDR1 0x88 8562672Swpaul#define NS_PHYIDR2 0x8C 8662672Swpaul#define NS_ANAR 0x90 8762672Swpaul#define NS_ANLPAR 0x94 8862672Swpaul#define NS_ANER 0x98 8962672Swpaul#define NS_ANNPTR 0x9C 9062672Swpaul 9164963Swpaul#define NS_PHY_CR 0xE4 9264963Swpaul#define NS_PHY_10BTSCR 0xE8 9364963Swpaul#define NS_PHY_PAGE 0xCC 9464963Swpaul#define NS_PHY_EXTCFG 0xF0 9564963Swpaul#define NS_PHY_DSPCFG 0xF4 9664963Swpaul#define NS_PHY_SDCFG 0xF8 9764963Swpaul#define NS_PHY_TDATA 0xFC 9864963Swpaul 9972813Swpaul#define NS_CLKRUN_PMESTS 0x00008000 10072813Swpaul#define NS_CLKRUN_PMEENB 0x00000100 10172813Swpaul#define NS_CLNRUN_CLKRUN_ENB 0x00000001 10272813Swpaul 103212167Syongari#define NS_WCSR_WAKE_PHYINTR 0x00000001 104212167Syongari#define NS_WCSR_WAKE_UCAST 0x00000002 105212167Syongari#define NS_WCSR_WAKE_MCAST 0x00000004 106212167Syongari#define NS_WCSR_WAKE_BCAST 0x00000008 107212167Syongari#define NS_WCSR_WAKE_ARP 0x00000010 108212167Syongari#define NS_WCSR_WAKE_PATTERN0 0x00000020 109212167Syongari#define NS_WCSR_WAKE_PATTERN1 0x00000040 110212167Syongari#define NS_WCSR_WAKE_PATTERN2 0x00000080 111212167Syongari#define NS_WCSR_WAKE_PATTERN3 0x00000100 112212167Syongari#define NS_WCSR_WAKE_MAGIC 0x00000200 113212167Syongari#define NS_WCSR_WAKE_MAGIC_SEC 0x00000400 114212167Syongari#define NS_WCSR_DET_MAGIC_SECH 0x00100000 115212167Syongari#define NS_WCSR_DET_PHYINTR 0x00400000 116212167Syongari#define NS_WCSR_DET_UCAST 0x00800000 117212167Syongari#define NS_WCSR_DET_MCAST 0x01000000 118212167Syongari#define NS_WCSR_DET_BCAST 0x02000000 119212167Syongari#define NS_WCSR_DET_ARP 0x04000000 120212167Syongari#define NS_WCSR_DET_PATTERN0 0x08000000 121212167Syongari#define NS_WCSR_DET_PATTERN1 0x10000000 122212167Syongari#define NS_WCSR_DET_PATTERN2 0x20000000 123212167Syongari#define NS_WCSR_DET_PATTERN3 0x40000000 124212167Syongari#define NS_WCSR_DET_MAGIC 0x80000000 125212167Syongari 126119712Sphk/* NS silicon revisions */ 127119712Sphk#define NS_SRR_15C 0x302 128119712Sphk#define NS_SRR_15D 0x403 129119712Sphk#define NS_SRR_16A 0x505 130119712Sphk 13150974Swpaul#define SIS_CSR_TX_ENABLE 0x00000001 13250974Swpaul#define SIS_CSR_TX_DISABLE 0x00000002 13350974Swpaul#define SIS_CSR_RX_ENABLE 0x00000004 13450974Swpaul#define SIS_CSR_RX_DISABLE 0x00000008 13550974Swpaul#define SIS_CSR_TX_RESET 0x00000010 13650974Swpaul#define SIS_CSR_RX_RESET 0x00000020 13750974Swpaul#define SIS_CSR_SOFTINTR 0x00000080 13850974Swpaul#define SIS_CSR_RESET 0x00000100 13989296Swpaul#define SIS_CSR_ACCESS_MODE 0x00000200 14089296Swpaul#define SIS_CSR_RELOAD 0x00000400 14150974Swpaul 14250974Swpaul#define SIS_CFG_BIGENDIAN 0x00000001 14350974Swpaul#define SIS_CFG_PERR_DETECT 0x00000008 14450974Swpaul#define SIS_CFG_DEFER_DISABLE 0x00000010 14550974Swpaul#define SIS_CFG_OUTOFWIN_TIMER 0x00000020 14650974Swpaul#define SIS_CFG_SINGLE_BACKOFF 0x00000040 14750974Swpaul#define SIS_CFG_PCIREQ_ALG 0x00000080 148109976Smbr#define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */ 149109976Smbr#define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */ 150109059Smbr#define SIS_CFG_EDB_MASTER_EN 0x00002000 15150974Swpaul 15250974Swpaul#define SIS_EECTL_DIN 0x00000001 15350974Swpaul#define SIS_EECTL_DOUT 0x00000002 15450974Swpaul#define SIS_EECTL_CLK 0x00000004 15550974Swpaul#define SIS_EECTL_CSEL 0x00000008 15650974Swpaul 157109060Smbr#define SIS_MII_CLK 0x00000040 158109060Smbr#define SIS_MII_DIR 0x00000020 159109060Smbr#define SIS_MII_DATA 0x00000010 160109060Smbr 16150974Swpaul#define SIS_EECMD_WRITE 0x140 16250974Swpaul#define SIS_EECMD_READ 0x180 16350974Swpaul#define SIS_EECMD_ERASE 0x1c0 16450974Swpaul 165109061Smbr/* 166109061Smbr * EEPROM Commands for SiS96x 167109061Smbr * chipsets. 168109061Smbr */ 169109061Smbr#define SIS_EECMD_REQ 0x00000400 170109061Smbr#define SIS_EECMD_DONE 0x00000200 171109061Smbr#define SIS_EECMD_GNT 0x00000100 172109061Smbr 17350974Swpaul#define SIS_EE_NODEADDR 0x8 17462672Swpaul#define NS_EE_NODEADDR 0x6 17550974Swpaul 17650974Swpaul#define SIS_PCICTL_SRAMADDR 0x0000001F 17750974Swpaul#define SIS_PCICTL_RAMTSTENB 0x00000020 17850974Swpaul#define SIS_PCICTL_TXTSTENB 0x00000040 17950974Swpaul#define SIS_PCICTL_RXTSTENB 0x00000080 18050974Swpaul#define SIS_PCICTL_BMTSTENB 0x00000200 18150974Swpaul#define SIS_PCICTL_RAMADDR 0x001F0000 18250974Swpaul#define SIS_PCICTL_ROMTIME 0x0F000000 18350974Swpaul#define SIS_PCICTL_DISCTEST 0x40000000 18450974Swpaul 18550974Swpaul#define SIS_ISR_RX_OK 0x00000001 18650974Swpaul#define SIS_ISR_RX_DESC_OK 0x00000002 18750974Swpaul#define SIS_ISR_RX_ERR 0x00000004 18850974Swpaul#define SIS_ISR_RX_EARLY 0x00000008 18950974Swpaul#define SIS_ISR_RX_IDLE 0x00000010 19050974Swpaul#define SIS_ISR_RX_OFLOW 0x00000020 19150974Swpaul#define SIS_ISR_TX_OK 0x00000040 19250974Swpaul#define SIS_ISR_TX_DESC_OK 0x00000080 19350974Swpaul#define SIS_ISR_TX_ERR 0x00000100 19450974Swpaul#define SIS_ISR_TX_IDLE 0x00000200 19550974Swpaul#define SIS_ISR_TX_UFLOW 0x00000400 19650974Swpaul#define SIS_ISR_SOFTINTR 0x00000800 19750974Swpaul#define SIS_ISR_HIBITS 0x00008000 19850974Swpaul#define SIS_ISR_RX_FIFO_OFLOW 0x00010000 19950974Swpaul#define SIS_ISR_TGT_ABRT 0x00100000 20050974Swpaul#define SIS_ISR_BM_ABRT 0x00200000 20150974Swpaul#define SIS_ISR_SYSERR 0x00400000 20250974Swpaul#define SIS_ISR_PARITY_ERR 0x00800000 20350974Swpaul#define SIS_ISR_RX_RESET_DONE 0x01000000 20450974Swpaul#define SIS_ISR_TX_RESET_DONE 0x02000000 20550974Swpaul#define SIS_ISR_TX_PAUSE_START 0x04000000 20650974Swpaul#define SIS_ISR_TX_PAUSE_DONE 0x08000000 20750974Swpaul#define SIS_ISR_WAKE_EVENT 0x10000000 20850974Swpaul 20950974Swpaul#define SIS_IMR_RX_OK 0x00000001 21050974Swpaul#define SIS_IMR_RX_DESC_OK 0x00000002 21150974Swpaul#define SIS_IMR_RX_ERR 0x00000004 21250974Swpaul#define SIS_IMR_RX_EARLY 0x00000008 21350974Swpaul#define SIS_IMR_RX_IDLE 0x00000010 21450974Swpaul#define SIS_IMR_RX_OFLOW 0x00000020 21550974Swpaul#define SIS_IMR_TX_OK 0x00000040 21650974Swpaul#define SIS_IMR_TX_DESC_OK 0x00000080 21750974Swpaul#define SIS_IMR_TX_ERR 0x00000100 21850974Swpaul#define SIS_IMR_TX_IDLE 0x00000200 21950974Swpaul#define SIS_IMR_TX_UFLOW 0x00000400 22050974Swpaul#define SIS_IMR_SOFTINTR 0x00000800 22150974Swpaul#define SIS_IMR_HIBITS 0x00008000 22250974Swpaul#define SIS_IMR_RX_FIFO_OFLOW 0x00010000 22350974Swpaul#define SIS_IMR_TGT_ABRT 0x00100000 22450974Swpaul#define SIS_IMR_BM_ABRT 0x00200000 22550974Swpaul#define SIS_IMR_SYSERR 0x00400000 22650974Swpaul#define SIS_IMR_PARITY_ERR 0x00800000 22750974Swpaul#define SIS_IMR_RX_RESET_DONE 0x01000000 22850974Swpaul#define SIS_IMR_TX_RESET_DONE 0x02000000 22950974Swpaul#define SIS_IMR_TX_PAUSE_START 0x04000000 23050974Swpaul#define SIS_IMR_TX_PAUSE_DONE 0x08000000 23150974Swpaul#define SIS_IMR_WAKE_EVENT 0x10000000 23250974Swpaul 23350974Swpaul#define SIS_INTRS \ 23450974Swpaul (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ 23550974Swpaul SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ 23686984Sluigi SIS_IMR_RX_IDLE|\ 23750974Swpaul SIS_IMR_SYSERR) 23850974Swpaul 23950974Swpaul#define SIS_IER_INTRENB 0x00000001 24050974Swpaul 24150974Swpaul#define SIS_PHYCTL_ACCESS 0x00000010 24250974Swpaul#define SIS_PHYCTL_OP 0x00000020 24350974Swpaul#define SIS_PHYCTL_REGADDR 0x000007C0 24450974Swpaul#define SIS_PHYCTL_PHYADDR 0x0000F800 24550974Swpaul#define SIS_PHYCTL_PHYDATA 0xFFFF0000 24650974Swpaul 24750974Swpaul#define SIS_PHYOP_READ 0x00000020 24850974Swpaul#define SIS_PHYOP_WRITE 0x00000000 24950974Swpaul 25050974Swpaul#define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ 25150974Swpaul#define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ 25250974Swpaul#define SIS_TXCFG_DMABURST 0x00700000 25350974Swpaul#define SIS_TXCFG_AUTOPAD 0x10000000 25450974Swpaul#define SIS_TXCFG_LOOPBK 0x20000000 25550974Swpaul#define SIS_TXCFG_IGN_HBEAT 0x40000000 25650974Swpaul#define SIS_TXCFG_IGN_CARR 0x80000000 25750974Swpaul 25850974Swpaul#define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) 25950974Swpaul#define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) 26050974Swpaul 26150974Swpaul#define SIS_TXDMA_512BYTES 0x00000000 26250974Swpaul#define SIS_TXDMA_4BYTES 0x00100000 26350974Swpaul#define SIS_TXDMA_8BYTES 0x00200000 26450974Swpaul#define SIS_TXDMA_16BYTES 0x00300000 26550974Swpaul#define SIS_TXDMA_32BYTES 0x00400000 26650974Swpaul#define SIS_TXDMA_64BYTES 0x00500000 26750974Swpaul#define SIS_TXDMA_128BYTES 0x00600000 26850974Swpaul#define SIS_TXDMA_256BYTES 0x00700000 26950974Swpaul 27064963Swpaul#define SIS_TXCFG_100 \ 27150974Swpaul (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ 27264963Swpaul SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 27350974Swpaul 27464963Swpaul#define SIS_TXCFG_10 \ 27564963Swpaul (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\ 27664963Swpaul SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 27764963Swpaul 27850974Swpaul#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 279212103Syongari#define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */ 28050974Swpaul#define SIS_RXCFG_DMABURST 0x00700000 28150974Swpaul#define SIS_RXCFG_RX_JABBER 0x08000000 28250974Swpaul#define SIS_RXCFG_RX_TXPKTS 0x10000000 28350974Swpaul#define SIS_RXCFG_RX_RUNTS 0x40000000 28450974Swpaul#define SIS_RXCFG_RX_GIANTS 0x80000000 28550974Swpaul 28650974Swpaul#define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) 28750974Swpaul 28850974Swpaul#define SIS_RXDMA_512BYTES 0x00000000 28950974Swpaul#define SIS_RXDMA_4BYTES 0x00100000 29050974Swpaul#define SIS_RXDMA_8BYTES 0x00200000 29150974Swpaul#define SIS_RXDMA_16BYTES 0x00300000 29250974Swpaul#define SIS_RXDMA_32BYTES 0x00400000 29350974Swpaul#define SIS_RXDMA_64BYTES 0x00500000 29450974Swpaul#define SIS_RXDMA_128BYTES 0x00600000 29550974Swpaul#define SIS_RXDMA_256BYTES 0x00700000 29650974Swpaul 297109059Smbr#define SIS_RXCFG256 \ 29850974Swpaul (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES) 299109059Smbr#define SIS_RXCFG64 \ 300109059Smbr (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES) 30150974Swpaul 30250974Swpaul#define SIS_RXFILTCTL_ADDR 0x000F0000 30362672Swpaul#define NS_RXFILTCTL_MCHASH 0x00200000 30462672Swpaul#define NS_RXFILTCTL_ARP 0x00400000 30562672Swpaul#define NS_RXFILTCTL_PERFECT 0x08000000 30650974Swpaul#define SIS_RXFILTCTL_ALLPHYS 0x10000000 30750974Swpaul#define SIS_RXFILTCTL_ALLMULTI 0x20000000 30850974Swpaul#define SIS_RXFILTCTL_BROAD 0x40000000 30950974Swpaul#define SIS_RXFILTCTL_ENABLE 0x80000000 31050974Swpaul 31150974Swpaul#define SIS_FILTADDR_PAR0 0x00000000 31250974Swpaul#define SIS_FILTADDR_PAR1 0x00010000 31350974Swpaul#define SIS_FILTADDR_PAR2 0x00020000 31450974Swpaul#define SIS_FILTADDR_MAR0 0x00040000 31550974Swpaul#define SIS_FILTADDR_MAR1 0x00050000 31650974Swpaul#define SIS_FILTADDR_MAR2 0x00060000 31750974Swpaul#define SIS_FILTADDR_MAR3 0x00070000 31850974Swpaul#define SIS_FILTADDR_MAR4 0x00080000 31950974Swpaul#define SIS_FILTADDR_MAR5 0x00090000 32050974Swpaul#define SIS_FILTADDR_MAR6 0x000A0000 32150974Swpaul#define SIS_FILTADDR_MAR7 0x000B0000 32250974Swpaul 32362672Swpaul#define NS_FILTADDR_PAR0 0x00000000 32462672Swpaul#define NS_FILTADDR_PAR1 0x00000002 32562672Swpaul#define NS_FILTADDR_PAR2 0x00000004 32662672Swpaul 32762672Swpaul#define NS_FILTADDR_FMEM_LO 0x00000200 32862672Swpaul#define NS_FILTADDR_FMEM_HI 0x000003FE 32962672Swpaul 330212167Syongari#define SIS_PWRMAN_WOL_LINK_OFF 0x00000001 331212167Syongari#define SIS_PWRMAN_WOL_LINK_ON 0x00000002 332212167Syongari#define SIS_PWRMAN_WOL_MAGIC 0x00000400 333212167Syongari 33450974Swpaul/* 335212109Syongari * TX/RX DMA descriptor structures. 33650974Swpaul */ 33750974Swpaulstruct sis_desc { 33850974Swpaul /* SiS hardware descriptor section */ 339212113Syongari uint32_t sis_next; 340219102Syongari volatile uint32_t sis_cmdsts; 341219102Syongari volatile uint32_t sis_ptr; 34250974Swpaul}; 34350974Swpaul 34450974Swpaul#define SIS_CMDSTS_BUFLEN 0x00000FFF 34550974Swpaul#define SIS_CMDSTS_PKT_OK 0x08000000 34650974Swpaul#define SIS_CMDSTS_CRC 0x10000000 34750974Swpaul#define SIS_CMDSTS_INTR 0x20000000 34850974Swpaul#define SIS_CMDSTS_MORE 0x40000000 34950974Swpaul#define SIS_CMDSTS_OWN 0x80000000 35050974Swpaul 35150974Swpaul#define SIS_RXSTAT_COLL 0x00010000 35250974Swpaul#define SIS_RXSTAT_LOOPBK 0x00020000 35350974Swpaul#define SIS_RXSTAT_ALIGNERR 0x00040000 35450974Swpaul#define SIS_RXSTAT_CRCERR 0x00080000 35550974Swpaul#define SIS_RXSTAT_SYMBOLERR 0x00100000 35650974Swpaul#define SIS_RXSTAT_RUNT 0x00200000 35750974Swpaul#define SIS_RXSTAT_GIANT 0x00400000 35850974Swpaul#define SIS_RXSTAT_DSTCLASS 0x01800000 35950974Swpaul#define SIS_RXSTAT_OVERRUN 0x02000000 36050974Swpaul#define SIS_RXSTAT_RX_ABORT 0x04000000 36150974Swpaul 362185784Syongari#define SIS_RXSTAT_ERROR(x) \ 363185784Syongari ((x) & (SIS_RXSTAT_RX_ABORT | SIS_RXSTAT_OVERRUN | \ 364185784Syongari SIS_RXSTAT_GIANT | SIS_RXSTAT_SYMBOLERR | SIS_RXSTAT_RUNT | \ 365185784Syongari SIS_RXSTAT_CRCERR | SIS_RXSTAT_ALIGNERR)) 366185784Syongari 36750974Swpaul#define SIS_DSTCLASS_REJECT 0x00000000 36850974Swpaul#define SIS_DSTCLASS_UNICAST 0x00800000 36950974Swpaul#define SIS_DSTCLASS_MULTICAST 0x01000000 37050974Swpaul#define SIS_DSTCLASS_BROADCAST 0x02000000 37150974Swpaul 37250974Swpaul#define SIS_TXSTAT_COLLCNT 0x000F0000 37350974Swpaul#define SIS_TXSTAT_EXCESSCOLLS 0x00100000 37450974Swpaul#define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 37550974Swpaul#define SIS_TXSTAT_EXCESS_DEFER 0x00400000 37650974Swpaul#define SIS_TXSTAT_DEFERED 0x00800000 37750974Swpaul#define SIS_TXSTAT_CARR_LOST 0x01000000 37850974Swpaul#define SIS_TXSTAT_UNDERRUN 0x02000000 37950974Swpaul#define SIS_TXSTAT_TX_ABORT 0x04000000 38050974Swpaul 381212109Syongari#define SIS_DESC_ALIGN 16 382212109Syongari#define SIS_RX_BUF_ALIGN 4 383212109Syongari#define SIS_MAXTXSEGS 16 384139888Sphk#define SIS_RX_LIST_CNT 64 38550974Swpaul#define SIS_TX_LIST_CNT 128 38650974Swpaul 38781713Swpaul#define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc) 38881713Swpaul#define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc) 38981713Swpaul 390212109Syongari#define SIS_ADDR_LO(x) ((uint64_t) (x) & 0xffffffff) 391212109Syongari#define SIS_ADDR_HI(x) ((uint64_t) (x) >> 32) 392212109Syongari 393212109Syongari#define SIS_RX_RING_ADDR(sc, i) \ 394212109Syongari ((sc)->sis_rx_paddr + sizeof(struct sis_desc) * (i)) 395212109Syongari#define SIS_TX_RING_ADDR(sc, i) \ 396212109Syongari ((sc)->sis_tx_paddr + sizeof(struct sis_desc) * (i)) 397212109Syongari 398212109Syongari#define SIS_INC(x, y) (x) = (x + 1) % (y) 399212109Syongari 40050974Swpaul/* 40150974Swpaul * SiS PCI vendor ID. 40250974Swpaul */ 40350974Swpaul#define SIS_VENDORID 0x1039 40450974Swpaul 40550974Swpaul/* 40650974Swpaul * SiS PCI device IDs 40750974Swpaul */ 40850974Swpaul#define SIS_DEVICEID_900 0x0900 40950974Swpaul#define SIS_DEVICEID_7016 0x7016 41050974Swpaul 41162672Swpaul/* 41272197Swpaul * SiS 900 PCI revision codes. 41372197Swpaul */ 414109976Smbr#define SIS_REV_900B 0x0003 415109976Smbr#define SIS_REV_630A 0x0080 41672197Swpaul#define SIS_REV_630E 0x0081 41772197Swpaul#define SIS_REV_630S 0x0082 41872197Swpaul#define SIS_REV_630EA1 0x0083 41990328Sambrisko#define SIS_REV_630ET 0x0084 42089296Swpaul#define SIS_REV_635 0x0090 421109061Smbr#define SIS_REV_96x 0x0091 42272197Swpaul 42372197Swpaul/* 42462672Swpaul * NatSemi vendor ID 42562672Swpaul */ 42662672Swpaul#define NS_VENDORID 0x100B 42762672Swpaul 42862672Swpaul/* 42962672Swpaul * DP83815 device ID 43062672Swpaul */ 43162672Swpaul#define NS_DEVICEID_DP83815 0x0020 43262672Swpaul 43350974Swpaulstruct sis_type { 434212113Syongari uint16_t sis_vid; 435212113Syongari uint16_t sis_did; 436226995Smarius const char *sis_name; 43750974Swpaul}; 43850974Swpaul 43950974Swpaul#define SIS_TYPE_900 1 44050974Swpaul#define SIS_TYPE_7016 2 44162672Swpaul#define SIS_TYPE_83815 3 44250974Swpaul 443212109Syongaristruct sis_txdesc { 444212109Syongari struct mbuf *tx_m; 445212109Syongari bus_dmamap_t tx_dmamap; 446212109Syongari}; 447212109Syongari 448212109Syongaristruct sis_rxdesc { 449212109Syongari struct mbuf *rx_m; 450212109Syongari bus_dmamap_t rx_dmamap; 451212109Syongari struct sis_desc *rx_desc; 452212109Syongari}; 453212109Syongari 45450974Swpaulstruct sis_softc { 455147256Sbrooks struct ifnet *sis_ifp; /* interface info */ 456150526Sphk struct resource *sis_res[2]; 45750974Swpaul void *sis_intrhand; 458162315Sglebius device_t sis_dev; 45950974Swpaul device_t sis_miibus; 460212113Syongari uint8_t sis_type; 461212113Syongari uint8_t sis_rev; 462212157Syongari uint32_t sis_flags; 463212157Syongari#define SIS_FLAG_MANUAL_PAD 0x0800 464212157Syongari#define SIS_FLAG_LINK 0x8000 465212157Syongari int sis_manual_pad; 466212113Syongari uint32_t sis_srr; 467139690Sphk struct sis_desc *sis_rx_list; 468139690Sphk struct sis_desc *sis_tx_list; 469212109Syongari bus_dma_tag_t sis_rx_list_tag; 470212109Syongari bus_dmamap_t sis_rx_list_map; 471212109Syongari bus_dma_tag_t sis_tx_list_tag; 472212109Syongari bus_dmamap_t sis_tx_list_map; 473212109Syongari bus_dma_tag_t sis_parent_tag; 474139690Sphk bus_dma_tag_t sis_rx_tag; 475212109Syongari bus_dmamap_t sis_rx_sparemap; 476139690Sphk bus_dma_tag_t sis_tx_tag; 477212109Syongari struct sis_rxdesc sis_rxdesc[SIS_RX_LIST_CNT]; 478212109Syongari struct sis_txdesc sis_txdesc[SIS_TX_LIST_CNT]; 479139690Sphk int sis_tx_prod; 480139690Sphk int sis_tx_cons; 481139690Sphk int sis_tx_cnt; 482216227Skevlo int sis_rx_cons; 483212109Syongari bus_addr_t sis_rx_paddr; 484212109Syongari bus_addr_t sis_tx_paddr; 485119785Ssam struct callout sis_stat_ch; 486166940Sdelphij int sis_watchdog_timer; 487212119Syongari int sis_if_flags; 48887902Sluigi#ifdef DEVICE_POLLING 48987902Sluigi int rxcycles; 49087902Sluigi#endif 49167087Swpaul struct mtx sis_mtx; 49250974Swpaul}; 49350974Swpaul 49450974Swpaul#define SIS_TIMEOUT 1000 49550974Swpaul#define ETHER_ALIGN 2 49650974Swpaul#define SIS_RXLEN 1536 49750974Swpaul#define SIS_MIN_FRAMELEN 60 49850974Swpaul 49950974Swpaul/* 50050974Swpaul * PCI low memory base and low I/O base register, and 50150974Swpaul * other PCI registers. 50250974Swpaul */ 50350974Swpaul 50450974Swpaul#define SIS_PCI_VENDOR_ID 0x00 50550974Swpaul#define SIS_PCI_DEVICE_ID 0x02 50650974Swpaul#define SIS_PCI_COMMAND 0x04 50750974Swpaul#define SIS_PCI_STATUS 0x06 50850974Swpaul#define SIS_PCI_REVID 0x08 50950974Swpaul#define SIS_PCI_CLASSCODE 0x09 51050974Swpaul#define SIS_PCI_CACHELEN 0x0C 51150974Swpaul#define SIS_PCI_LATENCY_TIMER 0x0D 51250974Swpaul#define SIS_PCI_HEADER_TYPE 0x0E 51350974Swpaul#define SIS_PCI_LOIO 0x10 51450974Swpaul#define SIS_PCI_LOMEM 0x14 51550974Swpaul#define SIS_PCI_BIOSROM 0x30 51650974Swpaul#define SIS_PCI_INTLINE 0x3C 51750974Swpaul#define SIS_PCI_INTPIN 0x3D 51850974Swpaul#define SIS_PCI_MINGNT 0x3E 51950974Swpaul#define SIS_PCI_MINLAT 0x0F 52050974Swpaul#define SIS_PCI_RESETOPT 0x48 52150974Swpaul#define SIS_PCI_EEPROM_DATA 0x4C 52250974Swpaul 52350974Swpaul/* power management registers */ 52450974Swpaul#define SIS_PCI_CAPID 0x50 /* 8 bits */ 52550974Swpaul#define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ 52650974Swpaul#define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 52750974Swpaul#define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 52850974Swpaul 52950974Swpaul#define SIS_PSTATE_MASK 0x0003 53050974Swpaul#define SIS_PSTATE_D0 0x0000 53150974Swpaul#define SIS_PSTATE_D1 0x0001 53250974Swpaul#define SIS_PSTATE_D2 0x0002 53350974Swpaul#define SIS_PSTATE_D3 0x0003 53450974Swpaul#define SIS_PME_EN 0x0010 53550974Swpaul#define SIS_PME_STATUS 0x8000 536