if_sis.c revision 51533
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 51533 1999-09-22 06:08:11Z wpaul $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * Written by Bill Paul <wpaul@ee.columbia.edu> 40 * Electrical Engineering Department 41 * Columbia University, New York City 42 */ 43 44/* 45 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 46 * simple TX and RX descriptors of 3 longwords in size. The receiver 47 * has a single perfect filter entry for the station address and a 48 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 49 * transceiver while the 7016 requires an external transceiver chip. 50 * Both chips offer the standard bit-bang MII interface as well as 51 * an enchanced PHY interface which simplifies accessing MII registers. 52 * 53 * The only downside to this chipset is that RX descriptors must be 54 * longword aligned. 55 */ 56 57#include "bpf.h" 58 59#include <sys/param.h> 60#include <sys/systm.h> 61#include <sys/sockio.h> 62#include <sys/mbuf.h> 63#include <sys/malloc.h> 64#include <sys/kernel.h> 65#include <sys/socket.h> 66 67#include <net/if.h> 68#include <net/if_arp.h> 69#include <net/ethernet.h> 70#include <net/if_dl.h> 71#include <net/if_media.h> 72 73#if NBPF > 0 74#include <net/bpf.h> 75#endif 76 77#include <vm/vm.h> /* for vtophys */ 78#include <vm/pmap.h> /* for vtophys */ 79#include <machine/clock.h> /* for DELAY */ 80#include <machine/bus_pio.h> 81#include <machine/bus_memio.h> 82#include <machine/bus.h> 83#include <machine/resource.h> 84#include <sys/bus.h> 85#include <sys/rman.h> 86 87#include <dev/mii/mii.h> 88#include <dev/mii/miivar.h> 89 90#include <pci/pcireg.h> 91#include <pci/pcivar.h> 92 93#define SIS_USEIOSPACE 94 95#include <pci/if_sisreg.h> 96 97/* "controller miibus0" required. See GENERIC if you get errors here. */ 98#include "miibus_if.h" 99 100#ifndef lint 101static const char rcsid[] = 102 "$FreeBSD: head/sys/pci/if_sis.c 51533 1999-09-22 06:08:11Z wpaul $"; 103#endif 104 105/* 106 * Various supported device vendors/types and their names. 107 */ 108static struct sis_type sis_devs[] = { 109 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 110 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 111 { 0, 0, NULL } 112}; 113 114static int sis_probe __P((device_t)); 115static int sis_attach __P((device_t)); 116static int sis_detach __P((device_t)); 117 118static int sis_newbuf __P((struct sis_softc *, 119 struct sis_desc *, 120 struct mbuf *)); 121static int sis_encap __P((struct sis_softc *, 122 struct mbuf *, u_int32_t *)); 123static void sis_rxeof __P((struct sis_softc *)); 124static void sis_rxeoc __P((struct sis_softc *)); 125static void sis_txeof __P((struct sis_softc *)); 126static void sis_intr __P((void *)); 127static void sis_tick __P((void *)); 128static void sis_start __P((struct ifnet *)); 129static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 130static void sis_init __P((void *)); 131static void sis_stop __P((struct sis_softc *)); 132static void sis_watchdog __P((struct ifnet *)); 133static void sis_shutdown __P((device_t)); 134static int sis_ifmedia_upd __P((struct ifnet *)); 135static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 136 137static void sis_delay __P((struct sis_softc *)); 138static void sis_eeprom_idle __P((struct sis_softc *)); 139static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 140static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 141static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 142 int, int)); 143static int sis_miibus_readreg __P((device_t, int, int)); 144static int sis_miibus_writereg __P((device_t, int, int, int)); 145static void sis_miibus_statchg __P((device_t)); 146 147static void sis_setmulti __P((struct sis_softc *)); 148static u_int32_t sis_calchash __P((caddr_t)); 149static void sis_reset __P((struct sis_softc *)); 150static int sis_list_rx_init __P((struct sis_softc *)); 151static int sis_list_tx_init __P((struct sis_softc *)); 152 153#ifdef SIS_USEIOSPACE 154#define SIS_RES SYS_RES_IOPORT 155#define SIS_RID SIS_PCI_LOIO 156#else 157#define SIS_RES SYS_RES_MEMORY 158#define SIS_RID SIS_PCI_LOMEM 159#endif 160 161static device_method_t sis_methods[] = { 162 /* Device interface */ 163 DEVMETHOD(device_probe, sis_probe), 164 DEVMETHOD(device_attach, sis_attach), 165 DEVMETHOD(device_detach, sis_detach), 166 DEVMETHOD(device_shutdown, sis_shutdown), 167 168 /* bus interface */ 169 DEVMETHOD(bus_print_child, bus_generic_print_child), 170 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 171 172 /* MII interface */ 173 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 174 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 175 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 176 177 { 0, 0 } 178}; 179 180static driver_t sis_driver = { 181 "sis", 182 sis_methods, 183 sizeof(struct sis_softc) 184}; 185 186static devclass_t sis_devclass; 187 188DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 189DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 190 191#define SIS_SETBIT(sc, reg, x) \ 192 CSR_WRITE_4(sc, reg, \ 193 CSR_READ_4(sc, reg) | (x)) 194 195#define SIS_CLRBIT(sc, reg, x) \ 196 CSR_WRITE_4(sc, reg, \ 197 CSR_READ_4(sc, reg) & ~(x)) 198 199#define SIO_SET(x) \ 200 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 201 202#define SIO_CLR(x) \ 203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 204 205static void sis_delay(sc) 206 struct sis_softc *sc; 207{ 208 int idx; 209 210 for (idx = (300 / 33) + 1; idx > 0; idx--) 211 CSR_READ_4(sc, SIS_CSR); 212 213 return; 214} 215 216static void sis_eeprom_idle(sc) 217 struct sis_softc *sc; 218{ 219 register int i; 220 221 SIO_SET(SIS_EECTL_CSEL); 222 sis_delay(sc); 223 SIO_SET(SIS_EECTL_CLK); 224 sis_delay(sc); 225 226 for (i = 0; i < 25; i++) { 227 SIO_CLR(SIS_EECTL_CLK); 228 sis_delay(sc); 229 SIO_SET(SIS_EECTL_CLK); 230 sis_delay(sc); 231 } 232 233 SIO_CLR(SIS_EECTL_CLK); 234 sis_delay(sc); 235 SIO_CLR(SIS_EECTL_CSEL); 236 sis_delay(sc); 237 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 238 239 return; 240} 241 242/* 243 * Send a read command and address to the EEPROM, check for ACK. 244 */ 245static void sis_eeprom_putbyte(sc, addr) 246 struct sis_softc *sc; 247 int addr; 248{ 249 register int d, i; 250 251 d = addr | SIS_EECMD_READ; 252 253 /* 254 * Feed in each bit and stobe the clock. 255 */ 256 for (i = 0x400; i; i >>= 1) { 257 if (d & i) { 258 SIO_SET(SIS_EECTL_DIN); 259 } else { 260 SIO_CLR(SIS_EECTL_DIN); 261 } 262 sis_delay(sc); 263 SIO_SET(SIS_EECTL_CLK); 264 sis_delay(sc); 265 SIO_CLR(SIS_EECTL_CLK); 266 sis_delay(sc); 267 } 268 269 return; 270} 271 272/* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275static void sis_eeprom_getword(sc, addr, dest) 276 struct sis_softc *sc; 277 int addr; 278 u_int16_t *dest; 279{ 280 register int i; 281 u_int16_t word = 0; 282 283 /* Force EEPROM to idle state. */ 284 sis_eeprom_idle(sc); 285 286 /* Enter EEPROM access mode. */ 287 sis_delay(sc); 288 SIO_SET(SIS_EECTL_CSEL); 289 sis_delay(sc); 290 SIO_SET(SIS_EECTL_CLK); 291 sis_delay(sc); 292 293 /* 294 * Send address of word we want to read. 295 */ 296 sis_eeprom_putbyte(sc, addr); 297 298 /* 299 * Start reading bits from EEPROM. 300 */ 301 for (i = 0x8000; i; i >>= 1) { 302 SIO_SET(SIS_EECTL_CLK); 303 sis_delay(sc); 304 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 305 word |= i; 306 sis_delay(sc); 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 } 310 311 /* Turn off EEPROM access mode. */ 312 sis_eeprom_idle(sc); 313 314 *dest = word; 315 316 return; 317} 318 319/* 320 * Read a sequence of words from the EEPROM. 321 */ 322static void sis_read_eeprom(sc, dest, off, cnt, swap) 323 struct sis_softc *sc; 324 caddr_t dest; 325 int off; 326 int cnt; 327 int swap; 328{ 329 int i; 330 u_int16_t word = 0, *ptr; 331 332 for (i = 0; i < cnt; i++) { 333 sis_eeprom_getword(sc, off + i, &word); 334 ptr = (u_int16_t *)(dest + (i * 2)); 335 if (swap) 336 *ptr = ntohs(word); 337 else 338 *ptr = word; 339 } 340 341 return; 342} 343 344static int sis_miibus_readreg(dev, phy, reg) 345 device_t dev; 346 int phy, reg; 347{ 348 struct sis_softc *sc; 349 int i, val; 350 351 sc = device_get_softc(dev); 352 353 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 354 return(0); 355 356 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 357 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 358 359 for (i = 0; i < SIS_TIMEOUT; i++) { 360 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 361 break; 362 } 363 364 if (i == SIS_TIMEOUT) { 365 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 366 return(0); 367 } 368 369 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 370 371 if (val == 0xFFFF) 372 return(0); 373 374 return(val); 375} 376 377static int sis_miibus_writereg(dev, phy, reg, data) 378 device_t dev; 379 int phy, reg, data; 380{ 381 struct sis_softc *sc; 382 int i; 383 384 sc = device_get_softc(dev); 385 386 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 387 return(0); 388 389 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 390 (reg << 6) | SIS_PHYOP_WRITE); 391 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 392 393 for (i = 0; i < SIS_TIMEOUT; i++) { 394 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 395 break; 396 } 397 398 if (i == SIS_TIMEOUT) 399 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 400 401 return(0); 402} 403 404static void sis_miibus_statchg(dev) 405 device_t dev; 406{ 407 struct sis_softc *sc; 408 struct mii_data *mii; 409 410 sc = device_get_softc(dev); 411 mii = device_get_softc(sc->sis_miibus); 412 413 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 414 SIS_SETBIT(sc, SIS_TX_CFG, 415 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 416 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 417 } else { 418 SIS_CLRBIT(sc, SIS_TX_CFG, 419 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 420 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 421 } 422 423 return; 424} 425 426static u_int32_t sis_calchash(addr) 427 caddr_t addr; 428{ 429 u_int32_t crc, carry; 430 int i, j; 431 u_int8_t c; 432 433 /* Compute CRC for the address value. */ 434 crc = 0xFFFFFFFF; /* initial value */ 435 436 for (i = 0; i < 6; i++) { 437 c = *(addr + i); 438 for (j = 0; j < 8; j++) { 439 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 440 crc <<= 1; 441 c >>= 1; 442 if (carry) 443 crc = (crc ^ 0x04c11db6) | carry; 444 } 445 } 446 447 /* return the filter bit position */ 448 return((crc >> 25) & 0x0000007F); 449} 450 451static void sis_setmulti(sc) 452 struct sis_softc *sc; 453{ 454 struct ifnet *ifp; 455 struct ifmultiaddr *ifma; 456 u_int32_t h = 0, i, filtsave; 457 458 ifp = &sc->arpcom.ac_if; 459 460 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 461 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 462 return; 463 } 464 465 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 466 467 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 468 469 /* first, zot all the existing hash bits */ 470 for (i = 0; i < 8; i++) { 471 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 472 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 473 } 474 475 /* now program new ones */ 476 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 477 ifma = ifma->ifma_link.le_next) { 478 if (ifma->ifma_addr->sa_family != AF_LINK) 479 continue; 480 h = sis_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 481 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 482 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 483 } 484 485 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 486 487 return; 488} 489 490static void sis_reset(sc) 491 struct sis_softc *sc; 492{ 493 register int i; 494 495 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 496 497 for (i = 0; i < SIS_TIMEOUT; i++) { 498 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 499 break; 500 } 501 502 if (i == SIS_TIMEOUT) 503 printf("sis%d: reset never completed\n", sc->sis_unit); 504 505 /* Wait a little while for the chip to get its brains in order. */ 506 DELAY(1000); 507 return; 508} 509 510/* 511 * Probe for an SiS chip. Check the PCI vendor and device 512 * IDs against our list and return a device name if we find a match. 513 */ 514static int sis_probe(dev) 515 device_t dev; 516{ 517 struct sis_type *t; 518 519 t = sis_devs; 520 521 while(t->sis_name != NULL) { 522 if ((pci_get_vendor(dev) == t->sis_vid) && 523 (pci_get_device(dev) == t->sis_did)) { 524 device_set_desc(dev, t->sis_name); 525 return(0); 526 } 527 t++; 528 } 529 530 return(ENXIO); 531} 532 533/* 534 * Attach the interface. Allocate softc structures, do ifmedia 535 * setup and ethernet/BPF attach. 536 */ 537static int sis_attach(dev) 538 device_t dev; 539{ 540 int s; 541 u_char eaddr[ETHER_ADDR_LEN]; 542 u_int32_t command; 543 struct sis_softc *sc; 544 struct ifnet *ifp; 545 int unit, error = 0, rid; 546 547 s = splimp(); 548 549 sc = device_get_softc(dev); 550 unit = device_get_unit(dev); 551 bzero(sc, sizeof(struct sis_softc)); 552 553 if (pci_get_device(dev) == SIS_DEVICEID_900) 554 sc->sis_type = SIS_TYPE_900; 555 if (pci_get_device(dev) == SIS_DEVICEID_7016) 556 sc->sis_type = SIS_TYPE_7016; 557 558 /* 559 * Handle power management nonsense. 560 */ 561 562 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 563 if (command == 0x01) { 564 565 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 566 if (command & SIS_PSTATE_MASK) { 567 u_int32_t iobase, membase, irq; 568 569 /* Save important PCI config data. */ 570 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 571 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 572 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 573 574 /* Reset the power state. */ 575 printf("sis%d: chip is in D%d power mode " 576 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK); 577 command &= 0xFFFFFFFC; 578 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 579 580 /* Restore PCI config data. */ 581 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 582 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 583 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 584 } 585 } 586 587 /* 588 * Map control/status registers. 589 */ 590 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 591 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 592 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 593 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 594 595#ifdef SIS_USEIOSPACE 596 if (!(command & PCIM_CMD_PORTEN)) { 597 printf("sis%d: failed to enable I/O ports!\n", unit); 598 error = ENXIO;; 599 goto fail; 600 } 601#else 602 if (!(command & PCIM_CMD_MEMEN)) { 603 printf("sis%d: failed to enable memory mapping!\n", unit); 604 error = ENXIO;; 605 goto fail; 606 } 607#endif 608 609 rid = SIS_RID; 610 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 611 0, ~0, 1, RF_ACTIVE); 612 613 if (sc->sis_res == NULL) { 614 printf("sis%d: couldn't map ports/memory\n", unit); 615 error = ENXIO; 616 goto fail; 617 } 618 619 sc->sis_btag = rman_get_bustag(sc->sis_res); 620 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 621 622 /* Allocate interrupt */ 623 rid = 0; 624 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 625 RF_SHAREABLE | RF_ACTIVE); 626 627 if (sc->sis_irq == NULL) { 628 printf("sis%d: couldn't map interrupt\n", unit); 629 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 630 error = ENXIO; 631 goto fail; 632 } 633 634 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 635 sis_intr, sc, &sc->sis_intrhand); 636 637 if (error) { 638 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_res); 639 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 640 printf("sis%d: couldn't set up irq\n", unit); 641 goto fail; 642 } 643 644 /* Reset the adapter. */ 645 sis_reset(sc); 646 647 /* 648 * Get station address from the EEPROM. 649 */ 650 sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); 651 652 /* 653 * A SiS chip was detected. Inform the world. 654 */ 655 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 656 657 sc->sis_unit = unit; 658 callout_handle_init(&sc->sis_stat_ch); 659 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 660 661 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF, 662 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 663 664 if (sc->sis_ldata == NULL) { 665 printf("sis%d: no memory for list buffers!\n", unit); 666 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 667 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 668 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 669 error = ENXIO; 670 goto fail; 671 } 672 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 673 674 ifp = &sc->arpcom.ac_if; 675 ifp->if_softc = sc; 676 ifp->if_unit = unit; 677 ifp->if_name = "sis"; 678 ifp->if_mtu = ETHERMTU; 679 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 680 ifp->if_ioctl = sis_ioctl; 681 ifp->if_output = ether_output; 682 ifp->if_start = sis_start; 683 ifp->if_watchdog = sis_watchdog; 684 ifp->if_init = sis_init; 685 ifp->if_baudrate = 10000000; 686 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 687 688 /* 689 * Do MII setup. 690 */ 691 if (mii_phy_probe(dev, &sc->sis_miibus, 692 sis_ifmedia_upd, sis_ifmedia_sts)) { 693 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 694 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 695 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 696 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 697 error = ENXIO; 698 goto fail; 699 } 700 701 /* 702 * Call MI attach routines. 703 */ 704 if_attach(ifp); 705 ether_ifattach(ifp); 706 callout_handle_init(&sc->sis_stat_ch); 707 708#if NBPF > 0 709 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 710#endif 711 712fail: 713 splx(s); 714 return(error); 715} 716 717static int sis_detach(dev) 718 device_t dev; 719{ 720 struct sis_softc *sc; 721 struct ifnet *ifp; 722 int s; 723 724 s = splimp(); 725 726 sc = device_get_softc(dev); 727 ifp = &sc->arpcom.ac_if; 728 729 sis_reset(sc); 730 sis_stop(sc); 731 if_detach(ifp); 732 733 bus_generic_detach(dev); 734 device_delete_child(dev, sc->sis_miibus); 735 736 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 737 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 738 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 739 740 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF); 741 742 splx(s); 743 744 return(0); 745} 746 747/* 748 * Initialize the transmit descriptors. 749 */ 750static int sis_list_tx_init(sc) 751 struct sis_softc *sc; 752{ 753 struct sis_list_data *ld; 754 struct sis_ring_data *cd; 755 int i; 756 757 cd = &sc->sis_cdata; 758 ld = sc->sis_ldata; 759 760 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 761 if (i == (SIS_TX_LIST_CNT - 1)) { 762 ld->sis_tx_list[i].sis_nextdesc = 763 &ld->sis_tx_list[0]; 764 ld->sis_tx_list[i].sis_next = 765 vtophys(&ld->sis_tx_list[0]); 766 } else { 767 ld->sis_tx_list[i].sis_nextdesc = 768 &ld->sis_tx_list[i + 1]; 769 ld->sis_tx_list[i].sis_next = 770 vtophys(&ld->sis_tx_list[i + 1]); 771 } 772 ld->sis_tx_list[i].sis_mbuf = NULL; 773 ld->sis_tx_list[i].sis_ptr = 0; 774 ld->sis_tx_list[i].sis_ctl = 0; 775 } 776 777 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 778 779 return(0); 780} 781 782 783/* 784 * Initialize the RX descriptors and allocate mbufs for them. Note that 785 * we arrange the descriptors in a closed ring, so that the last descriptor 786 * points back to the first. 787 */ 788static int sis_list_rx_init(sc) 789 struct sis_softc *sc; 790{ 791 struct sis_list_data *ld; 792 struct sis_ring_data *cd; 793 int i; 794 795 ld = sc->sis_ldata; 796 cd = &sc->sis_cdata; 797 798 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 799 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 800 return(ENOBUFS); 801 if (i == (SIS_RX_LIST_CNT - 1)) { 802 ld->sis_rx_list[i].sis_nextdesc = 803 &ld->sis_rx_list[0]; 804 ld->sis_rx_list[i].sis_next = 805 vtophys(&ld->sis_rx_list[0]); 806 } else { 807 ld->sis_rx_list[i].sis_nextdesc = 808 &ld->sis_rx_list[i + 1]; 809 ld->sis_rx_list[i].sis_next = 810 vtophys(&ld->sis_rx_list[i + 1]); 811 } 812 } 813 814 cd->sis_rx_prod = 0; 815 816 return(0); 817} 818 819/* 820 * Initialize an RX descriptor and attach an MBUF cluster. 821 */ 822static int sis_newbuf(sc, c, m) 823 struct sis_softc *sc; 824 struct sis_desc *c; 825 struct mbuf *m; 826{ 827 struct mbuf *m_new = NULL; 828 829 if (m == NULL) { 830 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 831 if (m_new == NULL) { 832 printf("sis%d: no memory for rx list " 833 "-- packet dropped!\n", sc->sis_unit); 834 return(ENOBUFS); 835 } 836 837 MCLGET(m_new, M_DONTWAIT); 838 if (!(m_new->m_flags & M_EXT)) { 839 printf("sis%d: no memory for rx list " 840 "-- packet dropped!\n", sc->sis_unit); 841 m_freem(m_new); 842 return(ENOBUFS); 843 } 844 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 845 } else { 846 m_new = m; 847 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 848 m_new->m_data = m_new->m_ext.ext_buf; 849 } 850 851 m_adj(m_new, sizeof(u_int64_t)); 852 853 c->sis_mbuf = m_new; 854 c->sis_ptr = vtophys(mtod(m_new, caddr_t)); 855 c->sis_ctl = SIS_RXLEN; 856 857 return(0); 858} 859 860/* 861 * A frame has been uploaded: pass the resulting mbuf chain up to 862 * the higher level protocols. 863 */ 864static void sis_rxeof(sc) 865 struct sis_softc *sc; 866{ 867 struct ether_header *eh; 868 struct mbuf *m; 869 struct ifnet *ifp; 870 struct sis_desc *cur_rx; 871 int i, total_len = 0; 872 u_int32_t rxstat; 873 874 ifp = &sc->arpcom.ac_if; 875 i = sc->sis_cdata.sis_rx_prod; 876 877 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 878 struct mbuf *m0 = NULL; 879 880 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 881 rxstat = cur_rx->sis_rxstat; 882 m = cur_rx->sis_mbuf; 883 cur_rx->sis_mbuf = NULL; 884 total_len = SIS_RXBYTES(cur_rx); 885 SIS_INC(i, SIS_RX_LIST_CNT); 886 887 /* 888 * If an error occurs, update stats, clear the 889 * status word and leave the mbuf cluster in place: 890 * it should simply get re-used next time this descriptor 891 * comes up in the ring. 892 */ 893 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 894 ifp->if_ierrors++; 895 if (rxstat & SIS_RXSTAT_COLL) 896 ifp->if_collisions++; 897 sis_newbuf(sc, cur_rx, m); 898 continue; 899 } 900 901 /* No errors; receive the packet. */ 902 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 903 total_len + ETHER_ALIGN, 0, ifp, NULL); 904 sis_newbuf(sc, cur_rx, m); 905 if (m0 == NULL) { 906 ifp->if_ierrors++; 907 continue; 908 } 909 m_adj(m0, ETHER_ALIGN); 910 m = m0; 911 912 ifp->if_ipackets++; 913 eh = mtod(m, struct ether_header *); 914#if NBPF > 0 915 /* 916 * Handle BPF listeners. Let the BPF user see the packet, but 917 * don't pass it up to the ether_input() layer unless it's 918 * a broadcast packet, multicast packet, matches our ethernet 919 * address or the interface is in promiscuous mode. 920 */ 921 if (ifp->if_bpf) { 922 bpf_mtap(ifp, m); 923 if (ifp->if_flags & IFF_PROMISC && 924 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 925 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 926 m_freem(m); 927 continue; 928 } 929 } 930#endif 931 /* Remove header from mbuf and pass it on. */ 932 m_adj(m, sizeof(struct ether_header)); 933 ether_input(ifp, eh, m); 934 } 935 936 sc->sis_cdata.sis_rx_prod = i; 937 938 return; 939} 940 941void sis_rxeoc(sc) 942 struct sis_softc *sc; 943{ 944 sis_rxeof(sc); 945 sis_init(sc); 946 return; 947} 948 949/* 950 * A frame was downloaded to the chip. It's safe for us to clean up 951 * the list buffers. 952 */ 953 954static void sis_txeof(sc) 955 struct sis_softc *sc; 956{ 957 struct sis_desc *cur_tx = NULL; 958 struct ifnet *ifp; 959 u_int32_t idx; 960 961 ifp = &sc->arpcom.ac_if; 962 963 /* Clear the timeout timer. */ 964 ifp->if_timer = 0; 965 966 /* 967 * Go through our tx list and free mbufs for those 968 * frames that have been transmitted. 969 */ 970 idx = sc->sis_cdata.sis_tx_cons; 971 while (idx != sc->sis_cdata.sis_tx_prod) { 972 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 973 974 if (SIS_OWNDESC(cur_tx)) 975 break; 976 977 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 978 sc->sis_cdata.sis_tx_cnt--; 979 SIS_INC(idx, SIS_TX_LIST_CNT); 980 continue; 981 } 982 983 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 984 ifp->if_oerrors++; 985 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 986 ifp->if_collisions++; 987 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 988 ifp->if_collisions++; 989 } 990 991 ifp->if_collisions += 992 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 993 994 ifp->if_opackets++; 995 if (cur_tx->sis_mbuf != NULL) { 996 m_freem(cur_tx->sis_mbuf); 997 cur_tx->sis_mbuf = NULL; 998 } 999 1000 sc->sis_cdata.sis_tx_cnt--; 1001 SIS_INC(idx, SIS_TX_LIST_CNT); 1002 ifp->if_timer = 0; 1003 } 1004 1005 sc->sis_cdata.sis_tx_cons = idx; 1006 1007 if (cur_tx != NULL) 1008 ifp->if_flags &= ~IFF_OACTIVE; 1009 1010 return; 1011} 1012 1013static void sis_tick(xsc) 1014 void *xsc; 1015{ 1016 struct sis_softc *sc; 1017 struct mii_data *mii; 1018 int s; 1019 1020 s = splimp(); 1021 1022 sc = xsc; 1023 mii = device_get_softc(sc->sis_miibus); 1024 mii_tick(mii); 1025 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1026 1027 splx(s); 1028 1029 return; 1030} 1031 1032static void sis_intr(arg) 1033 void *arg; 1034{ 1035 struct sis_softc *sc; 1036 struct ifnet *ifp; 1037 u_int32_t status; 1038 1039 sc = arg; 1040 ifp = &sc->arpcom.ac_if; 1041 1042 /* Supress unwanted interrupts */ 1043 if (!(ifp->if_flags & IFF_UP)) { 1044 sis_stop(sc); 1045 return; 1046 } 1047 1048 /* Disable interrupts. */ 1049 CSR_WRITE_4(sc, SIS_IER, 0); 1050 1051 for (;;) { 1052 /* Reading the ISR register clears all interrupts. */ 1053 status = CSR_READ_4(sc, SIS_ISR); 1054 1055 if ((status & SIS_INTRS) == 0) 1056 break; 1057 1058 if ((status & SIS_ISR_TX_OK) || 1059 (status & SIS_ISR_TX_ERR) || 1060 (status & SIS_ISR_TX_IDLE)) 1061 sis_txeof(sc); 1062 1063 if (status & SIS_ISR_RX_OK) 1064 sis_rxeof(sc); 1065 1066 if ((status & SIS_ISR_RX_ERR) || 1067 (status & SIS_ISR_RX_OFLOW)) { 1068 sis_rxeoc(sc); 1069 } 1070 1071 if (status & SIS_ISR_SYSERR) { 1072 sis_reset(sc); 1073 sis_init(sc); 1074 } 1075 } 1076 1077 /* Re-enable interrupts. */ 1078 CSR_WRITE_4(sc, SIS_IER, 1); 1079 1080 if (ifp->if_snd.ifq_head != NULL) 1081 sis_start(ifp); 1082 1083 return; 1084} 1085 1086/* 1087 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1088 * pointers to the fragment pointers. 1089 */ 1090static int sis_encap(sc, m_head, txidx) 1091 struct sis_softc *sc; 1092 struct mbuf *m_head; 1093 u_int32_t *txidx; 1094{ 1095 struct sis_desc *f = NULL; 1096 struct mbuf *m; 1097 int frag, cur, cnt = 0; 1098 1099 /* 1100 * Start packing the mbufs in this chain into 1101 * the fragment pointers. Stop when we run out 1102 * of fragments or hit the end of the mbuf chain. 1103 */ 1104 m = m_head; 1105 cur = frag = *txidx; 1106 1107 for (m = m_head; m != NULL; m = m->m_next) { 1108 if (m->m_len != 0) { 1109 if ((SIS_TX_LIST_CNT - 1110 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1111 return(ENOBUFS); 1112 f = &sc->sis_ldata->sis_tx_list[frag]; 1113 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1114 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1115 if (cnt != 0) 1116 f->sis_ctl |= SIS_CMDSTS_OWN; 1117 cur = frag; 1118 SIS_INC(frag, SIS_TX_LIST_CNT); 1119 cnt++; 1120 } 1121 } 1122 1123 if (m != NULL) 1124 return(ENOBUFS); 1125 1126 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1127 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1128 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1129 sc->sis_cdata.sis_tx_cnt += cnt; 1130 *txidx = frag; 1131 1132 return(0); 1133} 1134 1135/* 1136 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1137 * to the mbuf data regions directly in the transmit lists. We also save a 1138 * copy of the pointers since the transmit list fragment pointers are 1139 * physical addresses. 1140 */ 1141 1142static void sis_start(ifp) 1143 struct ifnet *ifp; 1144{ 1145 struct sis_softc *sc; 1146 struct mbuf *m_head = NULL; 1147 u_int32_t idx; 1148 1149 sc = ifp->if_softc; 1150 1151 idx = sc->sis_cdata.sis_tx_prod; 1152 1153 if (ifp->if_flags & IFF_OACTIVE) 1154 return; 1155 1156 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1157 IF_DEQUEUE(&ifp->if_snd, m_head); 1158 if (m_head == NULL) 1159 break; 1160 1161 if (sis_encap(sc, m_head, &idx)) { 1162 IF_PREPEND(&ifp->if_snd, m_head); 1163 ifp->if_flags |= IFF_OACTIVE; 1164 break; 1165 } 1166 1167#if NBPF > 0 1168 /* 1169 * If there's a BPF listener, bounce a copy of this frame 1170 * to him. 1171 */ 1172 if (ifp->if_bpf) 1173 bpf_mtap(ifp, m_head); 1174#endif 1175 } 1176 1177 /* Transmit */ 1178 sc->sis_cdata.sis_tx_prod = idx; 1179 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1180 1181 /* 1182 * Set a timeout in case the chip goes out to lunch. 1183 */ 1184 ifp->if_timer = 5; 1185 1186 return; 1187} 1188 1189static void sis_init(xsc) 1190 void *xsc; 1191{ 1192 struct sis_softc *sc = xsc; 1193 struct ifnet *ifp = &sc->arpcom.ac_if; 1194 struct mii_data *mii; 1195 int s; 1196 1197 s = splimp(); 1198 1199 /* 1200 * Cancel pending I/O and free all RX/TX buffers. 1201 */ 1202 sis_stop(sc); 1203 1204 mii = device_get_softc(sc->sis_miibus); 1205 1206 /* Set MAC address */ 1207 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1208 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1209 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1210 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1211 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1212 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1213 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1214 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1215 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1216 1217 /* Init circular RX list. */ 1218 if (sis_list_rx_init(sc) == ENOBUFS) { 1219 printf("sis%d: initialization failed: no " 1220 "memory for rx buffers\n", sc->sis_unit); 1221 sis_stop(sc); 1222 (void)splx(s); 1223 return; 1224 } 1225 1226 /* 1227 * Init tx descriptors. 1228 */ 1229 sis_list_tx_init(sc); 1230 1231 /* If we want promiscuous mode, set the allframes bit. */ 1232 if (ifp->if_flags & IFF_PROMISC) { 1233 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1234 } else { 1235 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1236 } 1237 1238 /* 1239 * Set the capture broadcast bit to capture broadcast frames. 1240 */ 1241 if (ifp->if_flags & IFF_BROADCAST) { 1242 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1243 } else { 1244 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1245 } 1246 1247 /* 1248 * Load the multicast filter. 1249 */ 1250 sis_setmulti(sc); 1251 1252 /* Turn the receive filter on */ 1253 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1254 1255 /* 1256 * Load the address of the RX and TX lists. 1257 */ 1258 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1259 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1260 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1261 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1262 1263 /* Set RX configuration */ 1264 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1265 /* Set TX configuration */ 1266 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG); 1267 1268 /* 1269 * Enable interrupts. 1270 */ 1271 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1272 CSR_WRITE_4(sc, SIS_IER, 1); 1273 1274 /* Enable receiver and transmitter. */ 1275 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1276 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1277 1278 mii_mediachg(mii); 1279 1280 ifp->if_flags |= IFF_RUNNING; 1281 ifp->if_flags &= ~IFF_OACTIVE; 1282 1283 (void)splx(s); 1284 1285 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1286 1287 return; 1288} 1289 1290/* 1291 * Set media options. 1292 */ 1293static int sis_ifmedia_upd(ifp) 1294 struct ifnet *ifp; 1295{ 1296 struct sis_softc *sc; 1297 1298 sc = ifp->if_softc; 1299 1300 if (ifp->if_flags & IFF_UP) 1301 sis_init(sc); 1302 1303 return(0); 1304} 1305 1306/* 1307 * Report current media status. 1308 */ 1309static void sis_ifmedia_sts(ifp, ifmr) 1310 struct ifnet *ifp; 1311 struct ifmediareq *ifmr; 1312{ 1313 struct sis_softc *sc; 1314 struct mii_data *mii; 1315 1316 sc = ifp->if_softc; 1317 1318 mii = device_get_softc(sc->sis_miibus); 1319 mii_pollstat(mii); 1320 ifmr->ifm_active = mii->mii_media_active; 1321 ifmr->ifm_status = mii->mii_media_status; 1322 1323 return; 1324} 1325 1326static int sis_ioctl(ifp, command, data) 1327 struct ifnet *ifp; 1328 u_long command; 1329 caddr_t data; 1330{ 1331 struct sis_softc *sc = ifp->if_softc; 1332 struct ifreq *ifr = (struct ifreq *) data; 1333 struct mii_data *mii; 1334 int s, error = 0; 1335 1336 s = splimp(); 1337 1338 switch(command) { 1339 case SIOCSIFADDR: 1340 case SIOCGIFADDR: 1341 case SIOCSIFMTU: 1342 error = ether_ioctl(ifp, command, data); 1343 break; 1344 case SIOCSIFFLAGS: 1345 if (ifp->if_flags & IFF_UP) { 1346 sis_init(sc); 1347 } else { 1348 if (ifp->if_flags & IFF_RUNNING) 1349 sis_stop(sc); 1350 } 1351 error = 0; 1352 break; 1353 case SIOCADDMULTI: 1354 case SIOCDELMULTI: 1355 sis_setmulti(sc); 1356 error = 0; 1357 break; 1358 case SIOCGIFMEDIA: 1359 case SIOCSIFMEDIA: 1360 mii = device_get_softc(sc->sis_miibus); 1361 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1362 break; 1363 default: 1364 error = EINVAL; 1365 break; 1366 } 1367 1368 (void)splx(s); 1369 1370 return(error); 1371} 1372 1373static void sis_watchdog(ifp) 1374 struct ifnet *ifp; 1375{ 1376 struct sis_softc *sc; 1377 1378 sc = ifp->if_softc; 1379 1380 ifp->if_oerrors++; 1381 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1382 1383 sis_stop(sc); 1384 sis_reset(sc); 1385 sis_init(sc); 1386 1387 if (ifp->if_snd.ifq_head != NULL) 1388 sis_start(ifp); 1389 1390 return; 1391} 1392 1393/* 1394 * Stop the adapter and free any mbufs allocated to the 1395 * RX and TX lists. 1396 */ 1397static void sis_stop(sc) 1398 struct sis_softc *sc; 1399{ 1400 register int i; 1401 struct ifnet *ifp; 1402 1403 ifp = &sc->arpcom.ac_if; 1404 ifp->if_timer = 0; 1405 1406 untimeout(sis_tick, sc, sc->sis_stat_ch); 1407 CSR_WRITE_4(sc, SIS_IER, 0); 1408 CSR_WRITE_4(sc, SIS_IMR, 0); 1409 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1410 DELAY(1000); 1411 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 1412 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 1413 1414 /* 1415 * Free data in the RX lists. 1416 */ 1417 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1418 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 1419 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 1420 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 1421 } 1422 } 1423 bzero((char *)&sc->sis_ldata->sis_rx_list, 1424 sizeof(sc->sis_ldata->sis_rx_list)); 1425 1426 /* 1427 * Free the TX list buffers. 1428 */ 1429 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1430 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 1431 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 1432 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 1433 } 1434 } 1435 1436 bzero((char *)&sc->sis_ldata->sis_tx_list, 1437 sizeof(sc->sis_ldata->sis_tx_list)); 1438 1439 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1440 1441 return; 1442} 1443 1444/* 1445 * Stop all chip I/O so that the kernel's probe routines don't 1446 * get confused by errant DMAs when rebooting. 1447 */ 1448static void sis_shutdown(dev) 1449 device_t dev; 1450{ 1451 struct sis_softc *sc; 1452 1453 sc = device_get_softc(dev); 1454 1455 sis_reset(sc); 1456 sis_stop(sc); 1457 1458 return; 1459} 1460