if_sis.c revision 163892
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 163892 2006-11-02 00:05:15Z marius $"); 36 37/* 38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39 * available from http://www.sis.com.tw. 40 * 41 * This driver also supports the NatSemi DP83815. Datasheets are 42 * available from http://www.national.com. 43 * 44 * Written by Bill Paul <wpaul@ee.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48/* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61#ifdef HAVE_KERNEL_OPTION_HEADERS 62#include "opt_device_polling.h" 63#endif 64 65#include <sys/param.h> 66#include <sys/systm.h> 67#include <sys/sockio.h> 68#include <sys/mbuf.h> 69#include <sys/malloc.h> 70#include <sys/kernel.h> 71#include <sys/module.h> 72#include <sys/socket.h> 73 74#include <net/if.h> 75#include <net/if_arp.h> 76#include <net/ethernet.h> 77#include <net/if_dl.h> 78#include <net/if_media.h> 79#include <net/if_types.h> 80#include <net/if_vlan_var.h> 81 82#include <net/bpf.h> 83 84#include <machine/bus.h> 85#include <machine/resource.h> 86#include <sys/bus.h> 87#include <sys/rman.h> 88 89#include <dev/mii/mii.h> 90#include <dev/mii/miivar.h> 91 92#include <dev/pci/pcireg.h> 93#include <dev/pci/pcivar.h> 94 95#define SIS_USEIOSPACE 96 97#include <pci/if_sisreg.h> 98 99MODULE_DEPEND(sis, pci, 1, 1, 1); 100MODULE_DEPEND(sis, ether, 1, 1, 1); 101MODULE_DEPEND(sis, miibus, 1, 1, 1); 102 103/* "device miibus" required. See GENERIC if you get errors here. */ 104#include "miibus_if.h" 105 106#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 107#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 108#define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 109 110/* 111 * register space access macros 112 */ 113#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 114 115#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 116 117#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 118 119/* 120 * Various supported device vendors/types and their names. 121 */ 122static struct sis_type sis_devs[] = { 123 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 124 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 125 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 126 { 0, 0, NULL } 127}; 128 129static int sis_detach(device_t); 130static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131static int sis_ifmedia_upd(struct ifnet *); 132static void sis_init(void *); 133static void sis_initl(struct sis_softc *); 134static void sis_intr(void *); 135static int sis_ioctl(struct ifnet *, u_long, caddr_t); 136static int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *); 137static void sis_start(struct ifnet *); 138static void sis_startl(struct ifnet *); 139static void sis_stop(struct sis_softc *); 140static void sis_watchdog(struct ifnet *); 141 142 143static struct resource_spec sis_res_spec[] = { 144#ifdef SIS_USEIOSPACE 145 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 146#else 147 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 148#endif 149 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 150 { -1, 0 } 151}; 152 153#define SIS_SETBIT(sc, reg, x) \ 154 CSR_WRITE_4(sc, reg, \ 155 CSR_READ_4(sc, reg) | (x)) 156 157#define SIS_CLRBIT(sc, reg, x) \ 158 CSR_WRITE_4(sc, reg, \ 159 CSR_READ_4(sc, reg) & ~(x)) 160 161#define SIO_SET(x) \ 162 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 163 164#define SIO_CLR(x) \ 165 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 166 167static void 168sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 169{ 170 struct sis_desc *r; 171 172 r = arg; 173 r->sis_next = segs->ds_addr; 174} 175 176static void 177sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 178{ 179 struct sis_desc *r; 180 181 r = arg; 182 r->sis_ptr = segs->ds_addr; 183} 184 185static void 186sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 187{ 188 u_int32_t *p; 189 190 p = arg; 191 *p = segs->ds_addr; 192} 193 194/* 195 * Routine to reverse the bits in a word. Stolen almost 196 * verbatim from /usr/games/fortune. 197 */ 198static uint16_t 199sis_reverse(uint16_t n) 200{ 201 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 202 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 203 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 204 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 205 206 return(n); 207} 208 209static void 210sis_delay(struct sis_softc *sc) 211{ 212 int idx; 213 214 for (idx = (300 / 33) + 1; idx > 0; idx--) 215 CSR_READ_4(sc, SIS_CSR); 216} 217 218static void 219sis_eeprom_idle(struct sis_softc *sc) 220{ 221 int i; 222 223 SIO_SET(SIS_EECTL_CSEL); 224 sis_delay(sc); 225 SIO_SET(SIS_EECTL_CLK); 226 sis_delay(sc); 227 228 for (i = 0; i < 25; i++) { 229 SIO_CLR(SIS_EECTL_CLK); 230 sis_delay(sc); 231 SIO_SET(SIS_EECTL_CLK); 232 sis_delay(sc); 233 } 234 235 SIO_CLR(SIS_EECTL_CLK); 236 sis_delay(sc); 237 SIO_CLR(SIS_EECTL_CSEL); 238 sis_delay(sc); 239 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 240} 241 242/* 243 * Send a read command and address to the EEPROM, check for ACK. 244 */ 245static void 246sis_eeprom_putbyte(struct sis_softc *sc, int addr) 247{ 248 int d, i; 249 250 d = addr | SIS_EECMD_READ; 251 252 /* 253 * Feed in each bit and stobe the clock. 254 */ 255 for (i = 0x400; i; i >>= 1) { 256 if (d & i) { 257 SIO_SET(SIS_EECTL_DIN); 258 } else { 259 SIO_CLR(SIS_EECTL_DIN); 260 } 261 sis_delay(sc); 262 SIO_SET(SIS_EECTL_CLK); 263 sis_delay(sc); 264 SIO_CLR(SIS_EECTL_CLK); 265 sis_delay(sc); 266 } 267} 268 269/* 270 * Read a word of data stored in the EEPROM at address 'addr.' 271 */ 272static void 273sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 274{ 275 int i; 276 u_int16_t word = 0; 277 278 /* Force EEPROM to idle state. */ 279 sis_eeprom_idle(sc); 280 281 /* Enter EEPROM access mode. */ 282 sis_delay(sc); 283 SIO_CLR(SIS_EECTL_CLK); 284 sis_delay(sc); 285 SIO_SET(SIS_EECTL_CSEL); 286 sis_delay(sc); 287 288 /* 289 * Send address of word we want to read. 290 */ 291 sis_eeprom_putbyte(sc, addr); 292 293 /* 294 * Start reading bits from EEPROM. 295 */ 296 for (i = 0x8000; i; i >>= 1) { 297 SIO_SET(SIS_EECTL_CLK); 298 sis_delay(sc); 299 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 300 word |= i; 301 sis_delay(sc); 302 SIO_CLR(SIS_EECTL_CLK); 303 sis_delay(sc); 304 } 305 306 /* Turn off EEPROM access mode. */ 307 sis_eeprom_idle(sc); 308 309 *dest = word; 310} 311 312/* 313 * Read a sequence of words from the EEPROM. 314 */ 315static void 316sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 317{ 318 int i; 319 u_int16_t word = 0, *ptr; 320 321 for (i = 0; i < cnt; i++) { 322 sis_eeprom_getword(sc, off + i, &word); 323 ptr = (u_int16_t *)(dest + (i * 2)); 324 if (swap) 325 *ptr = ntohs(word); 326 else 327 *ptr = word; 328 } 329} 330 331#if defined(__i386__) || defined(__amd64__) 332static device_t 333sis_find_bridge(device_t dev) 334{ 335 devclass_t pci_devclass; 336 device_t *pci_devices; 337 int pci_count = 0; 338 device_t *pci_children; 339 int pci_childcount = 0; 340 device_t *busp, *childp; 341 device_t child = NULL; 342 int i, j; 343 344 if ((pci_devclass = devclass_find("pci")) == NULL) 345 return(NULL); 346 347 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 348 349 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 350 pci_childcount = 0; 351 device_get_children(*busp, &pci_children, &pci_childcount); 352 for (j = 0, childp = pci_children; 353 j < pci_childcount; j++, childp++) { 354 if (pci_get_vendor(*childp) == SIS_VENDORID && 355 pci_get_device(*childp) == 0x0008) { 356 child = *childp; 357 goto done; 358 } 359 } 360 } 361 362done: 363 free(pci_devices, M_TEMP); 364 free(pci_children, M_TEMP); 365 return(child); 366} 367 368static void 369sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 370{ 371 device_t bridge; 372 u_int8_t reg; 373 int i; 374 bus_space_tag_t btag; 375 376 bridge = sis_find_bridge(dev); 377 if (bridge == NULL) 378 return; 379 reg = pci_read_config(bridge, 0x48, 1); 380 pci_write_config(bridge, 0x48, reg|0x40, 1); 381 382 /* XXX */ 383#if defined(__i386__) 384 btag = I386_BUS_SPACE_IO; 385#elif defined(__amd64__) 386 btag = AMD64_BUS_SPACE_IO; 387#endif 388 389 for (i = 0; i < cnt; i++) { 390 bus_space_write_1(btag, 0x0, 0x70, i + off); 391 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 392 } 393 394 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 395 return; 396} 397 398static void 399sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 400{ 401 u_int32_t filtsave, csrsave; 402 403 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 404 csrsave = CSR_READ_4(sc, SIS_CSR); 405 406 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 407 CSR_WRITE_4(sc, SIS_CSR, 0); 408 409 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 410 411 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 412 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 413 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 414 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 415 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 416 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 417 418 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 419 CSR_WRITE_4(sc, SIS_CSR, csrsave); 420 return; 421} 422#endif 423 424/* 425 * Sync the PHYs by setting data bit and strobing the clock 32 times. 426 */ 427static void 428sis_mii_sync(struct sis_softc *sc) 429{ 430 int i; 431 432 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 433 434 for (i = 0; i < 32; i++) { 435 SIO_SET(SIS_MII_CLK); 436 DELAY(1); 437 SIO_CLR(SIS_MII_CLK); 438 DELAY(1); 439 } 440} 441 442/* 443 * Clock a series of bits through the MII. 444 */ 445static void 446sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 447{ 448 int i; 449 450 SIO_CLR(SIS_MII_CLK); 451 452 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 453 if (bits & i) { 454 SIO_SET(SIS_MII_DATA); 455 } else { 456 SIO_CLR(SIS_MII_DATA); 457 } 458 DELAY(1); 459 SIO_CLR(SIS_MII_CLK); 460 DELAY(1); 461 SIO_SET(SIS_MII_CLK); 462 } 463} 464 465/* 466 * Read an PHY register through the MII. 467 */ 468static int 469sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 470{ 471 int i, ack; 472 473 /* 474 * Set up frame for RX. 475 */ 476 frame->mii_stdelim = SIS_MII_STARTDELIM; 477 frame->mii_opcode = SIS_MII_READOP; 478 frame->mii_turnaround = 0; 479 frame->mii_data = 0; 480 481 /* 482 * Turn on data xmit. 483 */ 484 SIO_SET(SIS_MII_DIR); 485 486 sis_mii_sync(sc); 487 488 /* 489 * Send command/address info. 490 */ 491 sis_mii_send(sc, frame->mii_stdelim, 2); 492 sis_mii_send(sc, frame->mii_opcode, 2); 493 sis_mii_send(sc, frame->mii_phyaddr, 5); 494 sis_mii_send(sc, frame->mii_regaddr, 5); 495 496 /* Idle bit */ 497 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 498 DELAY(1); 499 SIO_SET(SIS_MII_CLK); 500 DELAY(1); 501 502 /* Turn off xmit. */ 503 SIO_CLR(SIS_MII_DIR); 504 505 /* Check for ack */ 506 SIO_CLR(SIS_MII_CLK); 507 DELAY(1); 508 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 509 SIO_SET(SIS_MII_CLK); 510 DELAY(1); 511 512 /* 513 * Now try reading data bits. If the ack failed, we still 514 * need to clock through 16 cycles to keep the PHY(s) in sync. 515 */ 516 if (ack) { 517 for(i = 0; i < 16; i++) { 518 SIO_CLR(SIS_MII_CLK); 519 DELAY(1); 520 SIO_SET(SIS_MII_CLK); 521 DELAY(1); 522 } 523 goto fail; 524 } 525 526 for (i = 0x8000; i; i >>= 1) { 527 SIO_CLR(SIS_MII_CLK); 528 DELAY(1); 529 if (!ack) { 530 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 531 frame->mii_data |= i; 532 DELAY(1); 533 } 534 SIO_SET(SIS_MII_CLK); 535 DELAY(1); 536 } 537 538fail: 539 540 SIO_CLR(SIS_MII_CLK); 541 DELAY(1); 542 SIO_SET(SIS_MII_CLK); 543 DELAY(1); 544 545 if (ack) 546 return(1); 547 return(0); 548} 549 550/* 551 * Write to a PHY register through the MII. 552 */ 553static int 554sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 555{ 556 557 /* 558 * Set up frame for TX. 559 */ 560 561 frame->mii_stdelim = SIS_MII_STARTDELIM; 562 frame->mii_opcode = SIS_MII_WRITEOP; 563 frame->mii_turnaround = SIS_MII_TURNAROUND; 564 565 /* 566 * Turn on data output. 567 */ 568 SIO_SET(SIS_MII_DIR); 569 570 sis_mii_sync(sc); 571 572 sis_mii_send(sc, frame->mii_stdelim, 2); 573 sis_mii_send(sc, frame->mii_opcode, 2); 574 sis_mii_send(sc, frame->mii_phyaddr, 5); 575 sis_mii_send(sc, frame->mii_regaddr, 5); 576 sis_mii_send(sc, frame->mii_turnaround, 2); 577 sis_mii_send(sc, frame->mii_data, 16); 578 579 /* Idle bit. */ 580 SIO_SET(SIS_MII_CLK); 581 DELAY(1); 582 SIO_CLR(SIS_MII_CLK); 583 DELAY(1); 584 585 /* 586 * Turn off xmit. 587 */ 588 SIO_CLR(SIS_MII_DIR); 589 590 return(0); 591} 592 593static int 594sis_miibus_readreg(device_t dev, int phy, int reg) 595{ 596 struct sis_softc *sc; 597 struct sis_mii_frame frame; 598 599 sc = device_get_softc(dev); 600 601 if (sc->sis_type == SIS_TYPE_83815) { 602 if (phy != 0) 603 return(0); 604 /* 605 * The NatSemi chip can take a while after 606 * a reset to come ready, during which the BMSR 607 * returns a value of 0. This is *never* supposed 608 * to happen: some of the BMSR bits are meant to 609 * be hardwired in the on position, and this can 610 * confuse the miibus code a bit during the probe 611 * and attach phase. So we make an effort to check 612 * for this condition and wait for it to clear. 613 */ 614 if (!CSR_READ_4(sc, NS_BMSR)) 615 DELAY(1000); 616 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 617 } 618 619 /* 620 * Chipsets < SIS_635 seem not to be able to read/write 621 * through mdio. Use the enhanced PHY access register 622 * again for them. 623 */ 624 if (sc->sis_type == SIS_TYPE_900 && 625 sc->sis_rev < SIS_REV_635) { 626 int i, val = 0; 627 628 if (phy != 0) 629 return(0); 630 631 CSR_WRITE_4(sc, SIS_PHYCTL, 632 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 633 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 634 635 for (i = 0; i < SIS_TIMEOUT; i++) { 636 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 637 break; 638 } 639 640 if (i == SIS_TIMEOUT) { 641 device_printf(sc->sis_dev, "PHY failed to come ready\n"); 642 return(0); 643 } 644 645 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 646 647 if (val == 0xFFFF) 648 return(0); 649 650 return(val); 651 } else { 652 bzero((char *)&frame, sizeof(frame)); 653 654 frame.mii_phyaddr = phy; 655 frame.mii_regaddr = reg; 656 sis_mii_readreg(sc, &frame); 657 658 return(frame.mii_data); 659 } 660} 661 662static int 663sis_miibus_writereg(device_t dev, int phy, int reg, int data) 664{ 665 struct sis_softc *sc; 666 struct sis_mii_frame frame; 667 668 sc = device_get_softc(dev); 669 670 if (sc->sis_type == SIS_TYPE_83815) { 671 if (phy != 0) 672 return(0); 673 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 674 return(0); 675 } 676 677 /* 678 * Chipsets < SIS_635 seem not to be able to read/write 679 * through mdio. Use the enhanced PHY access register 680 * again for them. 681 */ 682 if (sc->sis_type == SIS_TYPE_900 && 683 sc->sis_rev < SIS_REV_635) { 684 int i; 685 686 if (phy != 0) 687 return(0); 688 689 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 690 (reg << 6) | SIS_PHYOP_WRITE); 691 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 692 693 for (i = 0; i < SIS_TIMEOUT; i++) { 694 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 695 break; 696 } 697 698 if (i == SIS_TIMEOUT) 699 device_printf(sc->sis_dev, "PHY failed to come ready\n"); 700 } else { 701 bzero((char *)&frame, sizeof(frame)); 702 703 frame.mii_phyaddr = phy; 704 frame.mii_regaddr = reg; 705 frame.mii_data = data; 706 sis_mii_writereg(sc, &frame); 707 } 708 return(0); 709} 710 711static void 712sis_miibus_statchg(device_t dev) 713{ 714 struct sis_softc *sc; 715 716 sc = device_get_softc(dev); 717 SIS_LOCK_ASSERT(sc); 718 sis_initl(sc); 719} 720 721static uint32_t 722sis_mchash(struct sis_softc *sc, const uint8_t *addr) 723{ 724 uint32_t crc; 725 726 /* Compute CRC for the address value. */ 727 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 728 729 /* 730 * return the filter bit position 731 * 732 * The NatSemi chip has a 512-bit filter, which is 733 * different than the SiS, so we special-case it. 734 */ 735 if (sc->sis_type == SIS_TYPE_83815) 736 return (crc >> 23); 737 else if (sc->sis_rev >= SIS_REV_635 || 738 sc->sis_rev == SIS_REV_900B) 739 return (crc >> 24); 740 else 741 return (crc >> 25); 742} 743 744static void 745sis_setmulti_ns(struct sis_softc *sc) 746{ 747 struct ifnet *ifp; 748 struct ifmultiaddr *ifma; 749 u_int32_t h = 0, i, filtsave; 750 int bit, index; 751 752 ifp = sc->sis_ifp; 753 754 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 755 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 756 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 757 return; 758 } 759 760 /* 761 * We have to explicitly enable the multicast hash table 762 * on the NatSemi chip if we want to use it, which we do. 763 */ 764 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 765 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 766 767 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 768 769 /* first, zot all the existing hash bits */ 770 for (i = 0; i < 32; i++) { 771 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 772 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 773 } 774 775 IF_ADDR_LOCK(ifp); 776 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 777 if (ifma->ifma_addr->sa_family != AF_LINK) 778 continue; 779 h = sis_mchash(sc, 780 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 781 index = h >> 3; 782 bit = h & 0x1F; 783 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 784 if (bit > 0xF) 785 bit -= 0x10; 786 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 787 } 788 IF_ADDR_UNLOCK(ifp); 789 790 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 791 792 return; 793} 794 795static void 796sis_setmulti_sis(struct sis_softc *sc) 797{ 798 struct ifnet *ifp; 799 struct ifmultiaddr *ifma; 800 u_int32_t h, i, n, ctl; 801 u_int16_t hashes[16]; 802 803 ifp = sc->sis_ifp; 804 805 /* hash table size */ 806 if (sc->sis_rev >= SIS_REV_635 || 807 sc->sis_rev == SIS_REV_900B) 808 n = 16; 809 else 810 n = 8; 811 812 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 813 814 if (ifp->if_flags & IFF_BROADCAST) 815 ctl |= SIS_RXFILTCTL_BROAD; 816 817 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 818 ctl |= SIS_RXFILTCTL_ALLMULTI; 819 if (ifp->if_flags & IFF_PROMISC) 820 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 821 for (i = 0; i < n; i++) 822 hashes[i] = ~0; 823 } else { 824 for (i = 0; i < n; i++) 825 hashes[i] = 0; 826 i = 0; 827 IF_ADDR_LOCK(ifp); 828 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 829 if (ifma->ifma_addr->sa_family != AF_LINK) 830 continue; 831 h = sis_mchash(sc, 832 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 833 hashes[h >> 4] |= 1 << (h & 0xf); 834 i++; 835 } 836 IF_ADDR_UNLOCK(ifp); 837 if (i > n) { 838 ctl |= SIS_RXFILTCTL_ALLMULTI; 839 for (i = 0; i < n; i++) 840 hashes[i] = ~0; 841 } 842 } 843 844 for (i = 0; i < n; i++) { 845 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 846 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 847 } 848 849 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 850} 851 852static void 853sis_reset(struct sis_softc *sc) 854{ 855 int i; 856 857 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 858 859 for (i = 0; i < SIS_TIMEOUT; i++) { 860 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 861 break; 862 } 863 864 if (i == SIS_TIMEOUT) 865 device_printf(sc->sis_dev, "reset never completed\n"); 866 867 /* Wait a little while for the chip to get its brains in order. */ 868 DELAY(1000); 869 870 /* 871 * If this is a NetSemi chip, make sure to clear 872 * PME mode. 873 */ 874 if (sc->sis_type == SIS_TYPE_83815) { 875 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 876 CSR_WRITE_4(sc, NS_CLKRUN, 0); 877 } 878 879 return; 880} 881 882/* 883 * Probe for an SiS chip. Check the PCI vendor and device 884 * IDs against our list and return a device name if we find a match. 885 */ 886static int 887sis_probe(device_t dev) 888{ 889 struct sis_type *t; 890 891 t = sis_devs; 892 893 while(t->sis_name != NULL) { 894 if ((pci_get_vendor(dev) == t->sis_vid) && 895 (pci_get_device(dev) == t->sis_did)) { 896 device_set_desc(dev, t->sis_name); 897 return (BUS_PROBE_DEFAULT); 898 } 899 t++; 900 } 901 902 return(ENXIO); 903} 904 905/* 906 * Attach the interface. Allocate softc structures, do ifmedia 907 * setup and ethernet/BPF attach. 908 */ 909static int 910sis_attach(device_t dev) 911{ 912 u_char eaddr[ETHER_ADDR_LEN]; 913 struct sis_softc *sc; 914 struct ifnet *ifp; 915 int error = 0, waittime = 0; 916 917 waittime = 0; 918 sc = device_get_softc(dev); 919 920 sc->sis_dev = dev; 921 922 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 923 MTX_DEF); 924 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 925 926 if (pci_get_device(dev) == SIS_DEVICEID_900) 927 sc->sis_type = SIS_TYPE_900; 928 if (pci_get_device(dev) == SIS_DEVICEID_7016) 929 sc->sis_type = SIS_TYPE_7016; 930 if (pci_get_vendor(dev) == NS_VENDORID) 931 sc->sis_type = SIS_TYPE_83815; 932 933 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 934 /* 935 * Map control/status registers. 936 */ 937 pci_enable_busmaster(dev); 938 939 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 940 if (error) { 941 device_printf(dev, "couldn't allocate resources\n"); 942 goto fail; 943 } 944 945 /* Reset the adapter. */ 946 sis_reset(sc); 947 948 if (sc->sis_type == SIS_TYPE_900 && 949 (sc->sis_rev == SIS_REV_635 || 950 sc->sis_rev == SIS_REV_900B)) { 951 SIO_SET(SIS_CFG_RND_CNT); 952 SIO_SET(SIS_CFG_PERR_DETECT); 953 } 954 955 /* 956 * Get station address from the EEPROM. 957 */ 958 switch (pci_get_vendor(dev)) { 959 case NS_VENDORID: 960 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 961 962 /* We can't update the device description, so spew */ 963 if (sc->sis_srr == NS_SRR_15C) 964 device_printf(dev, "Silicon Revision: DP83815C\n"); 965 else if (sc->sis_srr == NS_SRR_15D) 966 device_printf(dev, "Silicon Revision: DP83815D\n"); 967 else if (sc->sis_srr == NS_SRR_16A) 968 device_printf(dev, "Silicon Revision: DP83816A\n"); 969 else 970 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 971 972 /* 973 * Reading the MAC address out of the EEPROM on 974 * the NatSemi chip takes a bit more work than 975 * you'd expect. The address spans 4 16-bit words, 976 * with the first word containing only a single bit. 977 * You have to shift everything over one bit to 978 * get it aligned properly. Also, the bits are 979 * stored backwards (the LSB is really the MSB, 980 * and so on) so you have to reverse them in order 981 * to get the MAC address into the form we want. 982 * Why? Who the hell knows. 983 */ 984 { 985 u_int16_t tmp[4]; 986 987 sis_read_eeprom(sc, (caddr_t)&tmp, 988 NS_EE_NODEADDR, 4, 0); 989 990 /* Shift everything over one bit. */ 991 tmp[3] = tmp[3] >> 1; 992 tmp[3] |= tmp[2] << 15; 993 tmp[2] = tmp[2] >> 1; 994 tmp[2] |= tmp[1] << 15; 995 tmp[1] = tmp[1] >> 1; 996 tmp[1] |= tmp[0] << 15; 997 998 /* Now reverse all the bits. */ 999 tmp[3] = sis_reverse(tmp[3]); 1000 tmp[2] = sis_reverse(tmp[2]); 1001 tmp[1] = sis_reverse(tmp[1]); 1002 1003 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1004 } 1005 break; 1006 case SIS_VENDORID: 1007 default: 1008#if defined(__i386__) || defined(__amd64__) 1009 /* 1010 * If this is a SiS 630E chipset with an embedded 1011 * SiS 900 controller, we have to read the MAC address 1012 * from the APC CMOS RAM. Our method for doing this 1013 * is very ugly since we have to reach out and grab 1014 * ahold of hardware for which we cannot properly 1015 * allocate resources. This code is only compiled on 1016 * the i386 architecture since the SiS 630E chipset 1017 * is for x86 motherboards only. Note that there are 1018 * a lot of magic numbers in this hack. These are 1019 * taken from SiS's Linux driver. I'd like to replace 1020 * them with proper symbolic definitions, but that 1021 * requires some datasheets that I don't have access 1022 * to at the moment. 1023 */ 1024 if (sc->sis_rev == SIS_REV_630S || 1025 sc->sis_rev == SIS_REV_630E || 1026 sc->sis_rev == SIS_REV_630EA1) 1027 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1028 1029 else if (sc->sis_rev == SIS_REV_635 || 1030 sc->sis_rev == SIS_REV_630ET) 1031 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1032 else if (sc->sis_rev == SIS_REV_96x) { 1033 /* Allow to read EEPROM from LAN. It is shared 1034 * between a 1394 controller and the NIC and each 1035 * time we access it, we need to set SIS_EECMD_REQ. 1036 */ 1037 SIO_SET(SIS_EECMD_REQ); 1038 for (waittime = 0; waittime < SIS_TIMEOUT; 1039 waittime++) { 1040 /* Force EEPROM to idle state. */ 1041 sis_eeprom_idle(sc); 1042 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1043 sis_read_eeprom(sc, (caddr_t)&eaddr, 1044 SIS_EE_NODEADDR, 3, 0); 1045 break; 1046 } 1047 DELAY(1); 1048 } 1049 /* 1050 * Set SIS_EECTL_CLK to high, so a other master 1051 * can operate on the i2c bus. 1052 */ 1053 SIO_SET(SIS_EECTL_CLK); 1054 /* Refuse EEPROM access by LAN */ 1055 SIO_SET(SIS_EECMD_DONE); 1056 } else 1057#endif 1058 sis_read_eeprom(sc, (caddr_t)&eaddr, 1059 SIS_EE_NODEADDR, 3, 0); 1060 break; 1061 } 1062 1063 /* 1064 * Allocate the parent bus DMA tag appropriate for PCI. 1065 */ 1066#define SIS_NSEG_NEW 32 1067 error = bus_dma_tag_create(NULL, /* parent */ 1068 1, 0, /* alignment, boundary */ 1069 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1070 BUS_SPACE_MAXADDR, /* highaddr */ 1071 NULL, NULL, /* filter, filterarg */ 1072 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1073 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1074 BUS_DMA_ALLOCNOW, /* flags */ 1075 NULL, NULL, /* lockfunc, lockarg */ 1076 &sc->sis_parent_tag); 1077 if (error) 1078 goto fail; 1079 1080 /* 1081 * Now allocate a tag for the DMA descriptor lists and a chunk 1082 * of DMA-able memory based on the tag. Also obtain the physical 1083 * addresses of the RX and TX ring, which we'll need later. 1084 * All of our lists are allocated as a contiguous block 1085 * of memory. 1086 */ 1087 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1088 1, 0, /* alignment, boundary */ 1089 BUS_SPACE_MAXADDR, /* lowaddr */ 1090 BUS_SPACE_MAXADDR, /* highaddr */ 1091 NULL, NULL, /* filter, filterarg */ 1092 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1093 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1094 0, /* flags */ 1095 busdma_lock_mutex, /* lockfunc */ 1096 &Giant, /* lockarg */ 1097 &sc->sis_rx_tag); 1098 if (error) 1099 goto fail; 1100 1101 error = bus_dmamem_alloc(sc->sis_rx_tag, 1102 (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1103 &sc->sis_rx_dmamap); 1104 1105 if (error) { 1106 device_printf(dev, "no memory for rx list buffers!\n"); 1107 bus_dma_tag_destroy(sc->sis_rx_tag); 1108 sc->sis_rx_tag = NULL; 1109 goto fail; 1110 } 1111 1112 error = bus_dmamap_load(sc->sis_rx_tag, 1113 sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1114 sizeof(struct sis_desc), sis_dma_map_ring, 1115 &sc->sis_rx_paddr, 0); 1116 1117 if (error) { 1118 device_printf(dev, "cannot get address of the rx ring!\n"); 1119 bus_dmamem_free(sc->sis_rx_tag, 1120 sc->sis_rx_list, sc->sis_rx_dmamap); 1121 bus_dma_tag_destroy(sc->sis_rx_tag); 1122 sc->sis_rx_tag = NULL; 1123 goto fail; 1124 } 1125 1126 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1127 1, 0, /* alignment, boundary */ 1128 BUS_SPACE_MAXADDR, /* lowaddr */ 1129 BUS_SPACE_MAXADDR, /* highaddr */ 1130 NULL, NULL, /* filter, filterarg */ 1131 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1132 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1133 0, /* flags */ 1134 busdma_lock_mutex, /* lockfunc */ 1135 &Giant, /* lockarg */ 1136 &sc->sis_tx_tag); 1137 if (error) 1138 goto fail; 1139 1140 error = bus_dmamem_alloc(sc->sis_tx_tag, 1141 (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1142 &sc->sis_tx_dmamap); 1143 1144 if (error) { 1145 device_printf(dev, "no memory for tx list buffers!\n"); 1146 bus_dma_tag_destroy(sc->sis_tx_tag); 1147 sc->sis_tx_tag = NULL; 1148 goto fail; 1149 } 1150 1151 error = bus_dmamap_load(sc->sis_tx_tag, 1152 sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1153 sizeof(struct sis_desc), sis_dma_map_ring, 1154 &sc->sis_tx_paddr, 0); 1155 1156 if (error) { 1157 device_printf(dev, "cannot get address of the tx ring!\n"); 1158 bus_dmamem_free(sc->sis_tx_tag, 1159 sc->sis_tx_list, sc->sis_tx_dmamap); 1160 bus_dma_tag_destroy(sc->sis_tx_tag); 1161 sc->sis_tx_tag = NULL; 1162 goto fail; 1163 } 1164 1165 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1166 1, 0, /* alignment, boundary */ 1167 BUS_SPACE_MAXADDR, /* lowaddr */ 1168 BUS_SPACE_MAXADDR, /* highaddr */ 1169 NULL, NULL, /* filter, filterarg */ 1170 MCLBYTES, 1, /* maxsize,nsegments */ 1171 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1172 0, /* flags */ 1173 busdma_lock_mutex, /* lockfunc */ 1174 &Giant, /* lockarg */ 1175 &sc->sis_tag); 1176 if (error) 1177 goto fail; 1178 1179 /* 1180 * Obtain the physical addresses of the RX and TX 1181 * rings which we'll need later in the init routine. 1182 */ 1183 1184 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1185 if (ifp == NULL) { 1186 device_printf(dev, "can not if_alloc()\n"); 1187 error = ENOSPC; 1188 goto fail; 1189 } 1190 ifp->if_softc = sc; 1191 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1192 ifp->if_mtu = ETHERMTU; 1193 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1194 ifp->if_ioctl = sis_ioctl; 1195 ifp->if_start = sis_start; 1196 ifp->if_watchdog = sis_watchdog; 1197 ifp->if_init = sis_init; 1198 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1199 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1200 IFQ_SET_READY(&ifp->if_snd); 1201 1202 /* 1203 * Do MII setup. 1204 */ 1205 if (mii_phy_probe(dev, &sc->sis_miibus, 1206 sis_ifmedia_upd, sis_ifmedia_sts)) { 1207 device_printf(dev, "MII without any PHY!\n"); 1208 error = ENXIO; 1209 goto fail; 1210 } 1211 1212 /* 1213 * Call MI attach routine. 1214 */ 1215 ether_ifattach(ifp, eaddr); 1216 1217 /* 1218 * Tell the upper layer(s) we support long frames. 1219 */ 1220 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1221 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1222 ifp->if_capenable = ifp->if_capabilities; 1223#ifdef DEVICE_POLLING 1224 ifp->if_capabilities |= IFCAP_POLLING; 1225#endif 1226 1227 /* Hook interrupt last to avoid having to lock softc */ 1228 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1229 sis_intr, sc, &sc->sis_intrhand); 1230 1231 if (error) { 1232 device_printf(dev, "couldn't set up irq\n"); 1233 ether_ifdetach(ifp); 1234 goto fail; 1235 } 1236 1237fail: 1238 if (error) 1239 sis_detach(dev); 1240 1241 return(error); 1242} 1243 1244/* 1245 * Shutdown hardware and free up resources. This can be called any 1246 * time after the mutex has been initialized. It is called in both 1247 * the error case in attach and the normal detach case so it needs 1248 * to be careful about only freeing resources that have actually been 1249 * allocated. 1250 */ 1251static int 1252sis_detach(device_t dev) 1253{ 1254 struct sis_softc *sc; 1255 struct ifnet *ifp; 1256 1257 sc = device_get_softc(dev); 1258 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1259 ifp = sc->sis_ifp; 1260 1261#ifdef DEVICE_POLLING 1262 if (ifp->if_capenable & IFCAP_POLLING) 1263 ether_poll_deregister(ifp); 1264#endif 1265 1266 /* These should only be active if attach succeeded. */ 1267 if (device_is_attached(dev)) { 1268 SIS_LOCK(sc); 1269 sis_reset(sc); 1270 sis_stop(sc); 1271 SIS_UNLOCK(sc); 1272 callout_drain(&sc->sis_stat_ch); 1273 ether_ifdetach(ifp); 1274 } 1275 if (sc->sis_miibus) 1276 device_delete_child(dev, sc->sis_miibus); 1277 bus_generic_detach(dev); 1278 1279 if (sc->sis_intrhand) 1280 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1281 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1282 1283 if (ifp) 1284 if_free(ifp); 1285 1286 if (sc->sis_rx_tag) { 1287 bus_dmamap_unload(sc->sis_rx_tag, 1288 sc->sis_rx_dmamap); 1289 bus_dmamem_free(sc->sis_rx_tag, 1290 sc->sis_rx_list, sc->sis_rx_dmamap); 1291 bus_dma_tag_destroy(sc->sis_rx_tag); 1292 } 1293 if (sc->sis_tx_tag) { 1294 bus_dmamap_unload(sc->sis_tx_tag, 1295 sc->sis_tx_dmamap); 1296 bus_dmamem_free(sc->sis_tx_tag, 1297 sc->sis_tx_list, sc->sis_tx_dmamap); 1298 bus_dma_tag_destroy(sc->sis_tx_tag); 1299 } 1300 if (sc->sis_parent_tag) 1301 bus_dma_tag_destroy(sc->sis_parent_tag); 1302 if (sc->sis_tag) 1303 bus_dma_tag_destroy(sc->sis_tag); 1304 1305 mtx_destroy(&sc->sis_mtx); 1306 1307 return(0); 1308} 1309 1310/* 1311 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1312 * we arrange the descriptors in a closed ring, so that the last descriptor 1313 * points back to the first. 1314 */ 1315static int 1316sis_ring_init(struct sis_softc *sc) 1317{ 1318 int i, error; 1319 struct sis_desc *dp; 1320 1321 dp = &sc->sis_tx_list[0]; 1322 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 1323 if (i == (SIS_TX_LIST_CNT - 1)) 1324 dp->sis_nextdesc = &sc->sis_tx_list[0]; 1325 else 1326 dp->sis_nextdesc = dp + 1; 1327 bus_dmamap_load(sc->sis_tx_tag, 1328 sc->sis_tx_dmamap, 1329 dp->sis_nextdesc, sizeof(struct sis_desc), 1330 sis_dma_map_desc_next, dp, 0); 1331 dp->sis_mbuf = NULL; 1332 dp->sis_ptr = 0; 1333 dp->sis_ctl = 0; 1334 } 1335 1336 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1337 1338 bus_dmamap_sync(sc->sis_tx_tag, 1339 sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE); 1340 1341 dp = &sc->sis_rx_list[0]; 1342 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 1343 error = sis_newbuf(sc, dp, NULL); 1344 if (error) 1345 return(error); 1346 if (i == (SIS_RX_LIST_CNT - 1)) 1347 dp->sis_nextdesc = &sc->sis_rx_list[0]; 1348 else 1349 dp->sis_nextdesc = dp + 1; 1350 bus_dmamap_load(sc->sis_rx_tag, 1351 sc->sis_rx_dmamap, 1352 dp->sis_nextdesc, sizeof(struct sis_desc), 1353 sis_dma_map_desc_next, dp, 0); 1354 } 1355 1356 bus_dmamap_sync(sc->sis_rx_tag, 1357 sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1358 1359 sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 1360 1361 return(0); 1362} 1363 1364/* 1365 * Initialize an RX descriptor and attach an MBUF cluster. 1366 */ 1367static int 1368sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1369{ 1370 1371 if (c == NULL) 1372 return(EINVAL); 1373 1374 if (m == NULL) { 1375 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1376 if (m == NULL) 1377 return(ENOBUFS); 1378 } else 1379 m->m_data = m->m_ext.ext_buf; 1380 1381 c->sis_mbuf = m; 1382 c->sis_ctl = SIS_RXLEN; 1383 1384 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1385 bus_dmamap_load(sc->sis_tag, c->sis_map, 1386 mtod(m, void *), MCLBYTES, 1387 sis_dma_map_desc_ptr, c, 0); 1388 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD); 1389 1390 return(0); 1391} 1392 1393/* 1394 * A frame has been uploaded: pass the resulting mbuf chain up to 1395 * the higher level protocols. 1396 */ 1397static void 1398sis_rxeof(struct sis_softc *sc) 1399{ 1400 struct mbuf *m, *m0; 1401 struct ifnet *ifp; 1402 struct sis_desc *cur_rx; 1403 int total_len = 0; 1404 u_int32_t rxstat; 1405 1406 SIS_LOCK_ASSERT(sc); 1407 1408 ifp = sc->sis_ifp; 1409 1410 for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1411 cur_rx = cur_rx->sis_nextdesc) { 1412 1413#ifdef DEVICE_POLLING 1414 if (ifp->if_capenable & IFCAP_POLLING) { 1415 if (sc->rxcycles <= 0) 1416 break; 1417 sc->rxcycles--; 1418 } 1419#endif 1420 rxstat = cur_rx->sis_rxstat; 1421 bus_dmamap_sync(sc->sis_tag, 1422 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1423 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1424 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1425 m = cur_rx->sis_mbuf; 1426 cur_rx->sis_mbuf = NULL; 1427 total_len = SIS_RXBYTES(cur_rx); 1428 1429 /* 1430 * If an error occurs, update stats, clear the 1431 * status word and leave the mbuf cluster in place: 1432 * it should simply get re-used next time this descriptor 1433 * comes up in the ring. 1434 */ 1435 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1436 ifp->if_ierrors++; 1437 if (rxstat & SIS_RXSTAT_COLL) 1438 ifp->if_collisions++; 1439 sis_newbuf(sc, cur_rx, m); 1440 continue; 1441 } 1442 1443 /* No errors; receive the packet. */ 1444#ifdef __NO_STRICT_ALIGNMENT 1445 /* 1446 * On architectures without alignment problems we try to 1447 * allocate a new buffer for the receive ring, and pass up 1448 * the one where the packet is already, saving the expensive 1449 * copy done in m_devget(). 1450 * If we are on an architecture with alignment problems, or 1451 * if the allocation fails, then use m_devget and leave the 1452 * existing buffer in the receive ring. 1453 */ 1454 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1455 m->m_pkthdr.len = m->m_len = total_len; 1456 else 1457#endif 1458 { 1459 m0 = m_devget(mtod(m, char *), total_len, 1460 ETHER_ALIGN, ifp, NULL); 1461 sis_newbuf(sc, cur_rx, m); 1462 if (m0 == NULL) { 1463 ifp->if_ierrors++; 1464 continue; 1465 } 1466 m = m0; 1467 } 1468 1469 ifp->if_ipackets++; 1470 m->m_pkthdr.rcvif = ifp; 1471 1472 SIS_UNLOCK(sc); 1473 (*ifp->if_input)(ifp, m); 1474 SIS_LOCK(sc); 1475 } 1476 1477 sc->sis_rx_pdsc = cur_rx; 1478} 1479 1480static void 1481sis_rxeoc(struct sis_softc *sc) 1482{ 1483 1484 SIS_LOCK_ASSERT(sc); 1485 sis_rxeof(sc); 1486 sis_initl(sc); 1487} 1488 1489/* 1490 * A frame was downloaded to the chip. It's safe for us to clean up 1491 * the list buffers. 1492 */ 1493 1494static void 1495sis_txeof(struct sis_softc *sc) 1496{ 1497 struct ifnet *ifp; 1498 u_int32_t idx; 1499 1500 SIS_LOCK_ASSERT(sc); 1501 ifp = sc->sis_ifp; 1502 1503 /* 1504 * Go through our tx list and free mbufs for those 1505 * frames that have been transmitted. 1506 */ 1507 for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1508 sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1509 struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 1510 1511 if (SIS_OWNDESC(cur_tx)) 1512 break; 1513 1514 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1515 continue; 1516 1517 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1518 ifp->if_oerrors++; 1519 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1520 ifp->if_collisions++; 1521 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1522 ifp->if_collisions++; 1523 } 1524 1525 ifp->if_collisions += 1526 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1527 1528 ifp->if_opackets++; 1529 if (cur_tx->sis_mbuf != NULL) { 1530 m_freem(cur_tx->sis_mbuf); 1531 cur_tx->sis_mbuf = NULL; 1532 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1533 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1534 } 1535 } 1536 1537 if (idx != sc->sis_tx_cons) { 1538 /* we freed up some buffers */ 1539 sc->sis_tx_cons = idx; 1540 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1541 } 1542 1543 ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 1544 1545 return; 1546} 1547 1548static void 1549sis_tick(void *xsc) 1550{ 1551 struct sis_softc *sc; 1552 struct mii_data *mii; 1553 struct ifnet *ifp; 1554 1555 sc = xsc; 1556 SIS_LOCK_ASSERT(sc); 1557 sc->in_tick = 1; 1558 ifp = sc->sis_ifp; 1559 1560 mii = device_get_softc(sc->sis_miibus); 1561 mii_tick(mii); 1562 1563 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1564 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1565 sc->sis_link++; 1566 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1567 sis_startl(ifp); 1568 } 1569 1570 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1571 sc->in_tick = 0; 1572} 1573 1574#ifdef DEVICE_POLLING 1575static poll_handler_t sis_poll; 1576 1577static void 1578sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1579{ 1580 struct sis_softc *sc = ifp->if_softc; 1581 1582 SIS_LOCK(sc); 1583 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1584 SIS_UNLOCK(sc); 1585 return; 1586 } 1587 1588 /* 1589 * On the sis, reading the status register also clears it. 1590 * So before returning to intr mode we must make sure that all 1591 * possible pending sources of interrupts have been served. 1592 * In practice this means run to completion the *eof routines, 1593 * and then call the interrupt routine 1594 */ 1595 sc->rxcycles = count; 1596 sis_rxeof(sc); 1597 sis_txeof(sc); 1598 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1599 sis_startl(ifp); 1600 1601 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1602 u_int32_t status; 1603 1604 /* Reading the ISR register clears all interrupts. */ 1605 status = CSR_READ_4(sc, SIS_ISR); 1606 1607 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1608 sis_rxeoc(sc); 1609 1610 if (status & (SIS_ISR_RX_IDLE)) 1611 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1612 1613 if (status & SIS_ISR_SYSERR) { 1614 sis_reset(sc); 1615 sis_initl(sc); 1616 } 1617 } 1618 1619 SIS_UNLOCK(sc); 1620} 1621#endif /* DEVICE_POLLING */ 1622 1623static void 1624sis_intr(void *arg) 1625{ 1626 struct sis_softc *sc; 1627 struct ifnet *ifp; 1628 u_int32_t status; 1629 1630 sc = arg; 1631 ifp = sc->sis_ifp; 1632 1633 if (sc->sis_stopped) /* Most likely shared interrupt */ 1634 return; 1635 1636 SIS_LOCK(sc); 1637#ifdef DEVICE_POLLING 1638 if (ifp->if_capenable & IFCAP_POLLING) { 1639 SIS_UNLOCK(sc); 1640 return; 1641 } 1642#endif 1643 1644 /* Disable interrupts. */ 1645 CSR_WRITE_4(sc, SIS_IER, 0); 1646 1647 for (;;) { 1648 SIS_LOCK_ASSERT(sc); 1649 /* Reading the ISR register clears all interrupts. */ 1650 status = CSR_READ_4(sc, SIS_ISR); 1651 1652 if ((status & SIS_INTRS) == 0) 1653 break; 1654 1655 if (status & 1656 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1657 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1658 sis_txeof(sc); 1659 1660 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1661 sis_rxeof(sc); 1662 1663 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1664 sis_rxeoc(sc); 1665 1666 if (status & (SIS_ISR_RX_IDLE)) 1667 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1668 1669 if (status & SIS_ISR_SYSERR) { 1670 sis_reset(sc); 1671 sis_initl(sc); 1672 } 1673 } 1674 1675 /* Re-enable interrupts. */ 1676 CSR_WRITE_4(sc, SIS_IER, 1); 1677 1678 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1679 sis_startl(ifp); 1680 1681 SIS_UNLOCK(sc); 1682} 1683 1684/* 1685 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1686 * pointers to the fragment pointers. 1687 */ 1688static int 1689sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1690{ 1691 struct sis_desc *f = NULL; 1692 struct mbuf *m; 1693 int frag, cur, cnt = 0, chainlen = 0; 1694 1695 /* 1696 * If there's no way we can send any packets, return now. 1697 */ 1698 if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1699 return (ENOBUFS); 1700 1701 /* 1702 * Count the number of frags in this chain to see if 1703 * we need to m_defrag. Since the descriptor list is shared 1704 * by all packets, we'll m_defrag long chains so that they 1705 * do not use up the entire list, even if they would fit. 1706 */ 1707 1708 for (m = *m_head; m != NULL; m = m->m_next) 1709 chainlen++; 1710 1711 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1712 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1713 m = m_defrag(*m_head, M_DONTWAIT); 1714 if (m == NULL) 1715 return (ENOBUFS); 1716 *m_head = m; 1717 } 1718 1719 /* 1720 * Start packing the mbufs in this chain into 1721 * the fragment pointers. Stop when we run out 1722 * of fragments or hit the end of the mbuf chain. 1723 */ 1724 cur = frag = *txidx; 1725 1726 for (m = *m_head; m != NULL; m = m->m_next) { 1727 if (m->m_len != 0) { 1728 if ((SIS_TX_LIST_CNT - 1729 (sc->sis_tx_cnt + cnt)) < 2) 1730 return(ENOBUFS); 1731 f = &sc->sis_tx_list[frag]; 1732 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1733 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1734 bus_dmamap_load(sc->sis_tag, f->sis_map, 1735 mtod(m, void *), m->m_len, 1736 sis_dma_map_desc_ptr, f, 0); 1737 bus_dmamap_sync(sc->sis_tag, 1738 f->sis_map, BUS_DMASYNC_PREREAD); 1739 if (cnt != 0) 1740 f->sis_ctl |= SIS_CMDSTS_OWN; 1741 cur = frag; 1742 SIS_INC(frag, SIS_TX_LIST_CNT); 1743 cnt++; 1744 } 1745 } 1746 1747 if (m != NULL) 1748 return(ENOBUFS); 1749 1750 sc->sis_tx_list[cur].sis_mbuf = *m_head; 1751 sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1752 sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1753 sc->sis_tx_cnt += cnt; 1754 *txidx = frag; 1755 1756 return(0); 1757} 1758 1759/* 1760 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1761 * to the mbuf data regions directly in the transmit lists. We also save a 1762 * copy of the pointers since the transmit list fragment pointers are 1763 * physical addresses. 1764 */ 1765 1766static void 1767sis_start(struct ifnet *ifp) 1768{ 1769 struct sis_softc *sc; 1770 1771 sc = ifp->if_softc; 1772 SIS_LOCK(sc); 1773 sis_startl(ifp); 1774 SIS_UNLOCK(sc); 1775} 1776 1777static void 1778sis_startl(struct ifnet *ifp) 1779{ 1780 struct sis_softc *sc; 1781 struct mbuf *m_head = NULL; 1782 u_int32_t idx, queued = 0; 1783 1784 sc = ifp->if_softc; 1785 1786 SIS_LOCK_ASSERT(sc); 1787 1788 if (!sc->sis_link) 1789 return; 1790 1791 idx = sc->sis_tx_prod; 1792 1793 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1794 return; 1795 1796 while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1797 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1798 if (m_head == NULL) 1799 break; 1800 1801 if (sis_encap(sc, &m_head, &idx)) { 1802 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1803 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1804 break; 1805 } 1806 1807 queued++; 1808 1809 /* 1810 * If there's a BPF listener, bounce a copy of this frame 1811 * to him. 1812 */ 1813 BPF_MTAP(ifp, m_head); 1814 1815 } 1816 1817 if (queued) { 1818 /* Transmit */ 1819 sc->sis_tx_prod = idx; 1820 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1821 1822 /* 1823 * Set a timeout in case the chip goes out to lunch. 1824 */ 1825 ifp->if_timer = 5; 1826 } 1827} 1828 1829static void 1830sis_init(void *xsc) 1831{ 1832 struct sis_softc *sc = xsc; 1833 1834 SIS_LOCK(sc); 1835 sis_initl(sc); 1836 SIS_UNLOCK(sc); 1837} 1838 1839static void 1840sis_initl(struct sis_softc *sc) 1841{ 1842 struct ifnet *ifp = sc->sis_ifp; 1843 struct mii_data *mii; 1844 1845 SIS_LOCK_ASSERT(sc); 1846 1847 /* 1848 * Cancel pending I/O and free all RX/TX buffers. 1849 */ 1850 sis_stop(sc); 1851 sc->sis_stopped = 0; 1852 1853#ifdef notyet 1854 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1855 /* 1856 * Configure 400usec of interrupt holdoff. This is based 1857 * on emperical tests on a Soekris 4801. 1858 */ 1859 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1860 } 1861#endif 1862 1863 mii = device_get_softc(sc->sis_miibus); 1864 1865 /* Set MAC address */ 1866 if (sc->sis_type == SIS_TYPE_83815) { 1867 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1868 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1869 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]); 1870 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1871 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1872 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]); 1873 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1874 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1875 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]); 1876 } else { 1877 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1878 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1879 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]); 1880 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1881 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1882 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]); 1883 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1884 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1885 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]); 1886 } 1887 1888 /* Init circular TX/RX lists. */ 1889 if (sis_ring_init(sc) != 0) { 1890 device_printf(sc->sis_dev, 1891 "initialization failed: no memory for rx buffers\n"); 1892 sis_stop(sc); 1893 return; 1894 } 1895 1896 /* 1897 * Short Cable Receive Errors (MP21.E) 1898 * also: Page 78 of the DP83815 data sheet (september 2002 version) 1899 * recommends the following register settings "for optimum 1900 * performance." for rev 15C. The driver from NS also sets 1901 * the PHY_CR register for later versions. 1902 */ 1903 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 1904 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1905 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1906 if (sc->sis_srr == NS_SRR_15C) { 1907 /* set val for c2 */ 1908 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1909 /* load/kill c2 */ 1910 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1911 /* rais SD off, from 4 to c */ 1912 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1913 } 1914 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 1915 } 1916 1917 1918 /* 1919 * For the NatSemi chip, we have to explicitly enable the 1920 * reception of ARP frames, as well as turn on the 'perfect 1921 * match' filter where we store the station address, otherwise 1922 * we won't receive unicasts meant for this host. 1923 */ 1924 if (sc->sis_type == SIS_TYPE_83815) { 1925 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1926 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1927 } 1928 1929 /* If we want promiscuous mode, set the allframes bit. */ 1930 if (ifp->if_flags & IFF_PROMISC) { 1931 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1932 } else { 1933 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1934 } 1935 1936 /* 1937 * Set the capture broadcast bit to capture broadcast frames. 1938 */ 1939 if (ifp->if_flags & IFF_BROADCAST) { 1940 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1941 } else { 1942 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1943 } 1944 1945 /* 1946 * Load the multicast filter. 1947 */ 1948 if (sc->sis_type == SIS_TYPE_83815) 1949 sis_setmulti_ns(sc); 1950 else 1951 sis_setmulti_sis(sc); 1952 1953 /* Turn the receive filter on */ 1954 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1955 1956 /* 1957 * Load the address of the RX and TX lists. 1958 */ 1959 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 1960 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 1961 1962 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1963 * the PCI bus. When this bit is set, the Max DMA Burst Size 1964 * for TX/RX DMA should be no larger than 16 double words. 1965 */ 1966 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1967 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1968 } else { 1969 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1970 } 1971 1972 /* Accept Long Packets for VLAN support */ 1973 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1974 1975 /* Set TX configuration */ 1976 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1977 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1978 } else { 1979 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1980 } 1981 1982 /* Set full/half duplex mode. */ 1983 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1984 SIS_SETBIT(sc, SIS_TX_CFG, 1985 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1986 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1987 } else { 1988 SIS_CLRBIT(sc, SIS_TX_CFG, 1989 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1990 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1991 } 1992 1993 if (sc->sis_type == SIS_TYPE_83816) { 1994 /* 1995 * MPII03.D: Half Duplex Excessive Collisions. 1996 * Also page 49 in 83816 manual 1997 */ 1998 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 1999 } 2000 2001 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2002 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2003 uint32_t reg; 2004 2005 /* 2006 * Short Cable Receive Errors (MP21.E) 2007 */ 2008 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2009 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 2010 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 2011 DELAY(100000); 2012 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 2013 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 2014 device_printf(sc->sis_dev, 2015 "Applying short cable fix (reg=%x)\n", reg); 2016 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2017 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2018 SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20); 2019 } 2020 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2021 } 2022 2023 /* 2024 * Enable interrupts. 2025 */ 2026 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2027#ifdef DEVICE_POLLING 2028 /* 2029 * ... only enable interrupts if we are not polling, make sure 2030 * they are off otherwise. 2031 */ 2032 if (ifp->if_capenable & IFCAP_POLLING) 2033 CSR_WRITE_4(sc, SIS_IER, 0); 2034 else 2035#endif 2036 CSR_WRITE_4(sc, SIS_IER, 1); 2037 2038 /* Enable receiver and transmitter. */ 2039 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2040 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2041 2042#ifdef notdef 2043 mii_mediachg(mii); 2044#endif 2045 2046 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2047 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2048 2049 if (!sc->in_tick) 2050 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2051} 2052 2053/* 2054 * Set media options. 2055 */ 2056static int 2057sis_ifmedia_upd(struct ifnet *ifp) 2058{ 2059 struct sis_softc *sc; 2060 struct mii_data *mii; 2061 2062 sc = ifp->if_softc; 2063 2064 SIS_LOCK(sc); 2065 mii = device_get_softc(sc->sis_miibus); 2066 sc->sis_link = 0; 2067 if (mii->mii_instance) { 2068 struct mii_softc *miisc; 2069 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2070 mii_phy_reset(miisc); 2071 } 2072 mii_mediachg(mii); 2073 SIS_UNLOCK(sc); 2074 2075 return(0); 2076} 2077 2078/* 2079 * Report current media status. 2080 */ 2081static void 2082sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2083{ 2084 struct sis_softc *sc; 2085 struct mii_data *mii; 2086 2087 sc = ifp->if_softc; 2088 2089 SIS_LOCK(sc); 2090 mii = device_get_softc(sc->sis_miibus); 2091 mii_pollstat(mii); 2092 SIS_UNLOCK(sc); 2093 ifmr->ifm_active = mii->mii_media_active; 2094 ifmr->ifm_status = mii->mii_media_status; 2095} 2096 2097static int 2098sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2099{ 2100 struct sis_softc *sc = ifp->if_softc; 2101 struct ifreq *ifr = (struct ifreq *) data; 2102 struct mii_data *mii; 2103 int error = 0; 2104 2105 switch(command) { 2106 case SIOCSIFFLAGS: 2107 SIS_LOCK(sc); 2108 if (ifp->if_flags & IFF_UP) { 2109 sis_initl(sc); 2110 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2111 sis_stop(sc); 2112 } 2113 SIS_UNLOCK(sc); 2114 error = 0; 2115 break; 2116 case SIOCADDMULTI: 2117 case SIOCDELMULTI: 2118 SIS_LOCK(sc); 2119 if (sc->sis_type == SIS_TYPE_83815) 2120 sis_setmulti_ns(sc); 2121 else 2122 sis_setmulti_sis(sc); 2123 SIS_UNLOCK(sc); 2124 error = 0; 2125 break; 2126 case SIOCGIFMEDIA: 2127 case SIOCSIFMEDIA: 2128 mii = device_get_softc(sc->sis_miibus); 2129 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2130 break; 2131 case SIOCSIFCAP: 2132 /* ok, disable interrupts */ 2133#ifdef DEVICE_POLLING 2134 if (ifr->ifr_reqcap & IFCAP_POLLING && 2135 !(ifp->if_capenable & IFCAP_POLLING)) { 2136 error = ether_poll_register(sis_poll, ifp); 2137 if (error) 2138 return(error); 2139 SIS_LOCK(sc); 2140 /* Disable interrupts */ 2141 CSR_WRITE_4(sc, SIS_IER, 0); 2142 ifp->if_capenable |= IFCAP_POLLING; 2143 SIS_UNLOCK(sc); 2144 return (error); 2145 2146 } 2147 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 2148 ifp->if_capenable & IFCAP_POLLING) { 2149 error = ether_poll_deregister(ifp); 2150 /* Enable interrupts. */ 2151 SIS_LOCK(sc); 2152 CSR_WRITE_4(sc, SIS_IER, 1); 2153 ifp->if_capenable &= ~IFCAP_POLLING; 2154 SIS_UNLOCK(sc); 2155 return (error); 2156 } 2157#endif /* DEVICE_POLLING */ 2158 break; 2159 default: 2160 error = ether_ioctl(ifp, command, data); 2161 break; 2162 } 2163 2164 return(error); 2165} 2166 2167static void 2168sis_watchdog(struct ifnet *ifp) 2169{ 2170 struct sis_softc *sc; 2171 2172 sc = ifp->if_softc; 2173 2174 SIS_LOCK(sc); 2175 if (sc->sis_stopped) { 2176 SIS_UNLOCK(sc); 2177 return; 2178 } 2179 2180 ifp->if_oerrors++; 2181 if_printf(ifp, "watchdog timeout\n"); 2182 2183 sis_stop(sc); 2184 sis_reset(sc); 2185 sis_initl(sc); 2186 2187 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2188 sis_startl(ifp); 2189 2190 SIS_UNLOCK(sc); 2191} 2192 2193/* 2194 * Stop the adapter and free any mbufs allocated to the 2195 * RX and TX lists. 2196 */ 2197static void 2198sis_stop(struct sis_softc *sc) 2199{ 2200 int i; 2201 struct ifnet *ifp; 2202 struct sis_desc *dp; 2203 2204 if (sc->sis_stopped) 2205 return; 2206 SIS_LOCK_ASSERT(sc); 2207 ifp = sc->sis_ifp; 2208 ifp->if_timer = 0; 2209 2210 callout_stop(&sc->sis_stat_ch); 2211 2212 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2213 CSR_WRITE_4(sc, SIS_IER, 0); 2214 CSR_WRITE_4(sc, SIS_IMR, 0); 2215 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2216 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2217 DELAY(1000); 2218 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2219 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2220 2221 sc->sis_link = 0; 2222 2223 /* 2224 * Free data in the RX lists. 2225 */ 2226 dp = &sc->sis_rx_list[0]; 2227 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 2228 if (dp->sis_mbuf == NULL) 2229 continue; 2230 bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2231 bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2232 m_freem(dp->sis_mbuf); 2233 dp->sis_mbuf = NULL; 2234 } 2235 bzero(sc->sis_rx_list, SIS_RX_LIST_SZ); 2236 2237 /* 2238 * Free the TX list buffers. 2239 */ 2240 dp = &sc->sis_tx_list[0]; 2241 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 2242 if (dp->sis_mbuf == NULL) 2243 continue; 2244 bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2245 bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2246 m_freem(dp->sis_mbuf); 2247 dp->sis_mbuf = NULL; 2248 } 2249 2250 bzero(sc->sis_tx_list, SIS_TX_LIST_SZ); 2251 2252 sc->sis_stopped = 1; 2253} 2254 2255/* 2256 * Stop all chip I/O so that the kernel's probe routines don't 2257 * get confused by errant DMAs when rebooting. 2258 */ 2259static void 2260sis_shutdown(device_t dev) 2261{ 2262 struct sis_softc *sc; 2263 2264 sc = device_get_softc(dev); 2265 SIS_LOCK(sc); 2266 sis_reset(sc); 2267 sis_stop(sc); 2268 SIS_UNLOCK(sc); 2269} 2270 2271static device_method_t sis_methods[] = { 2272 /* Device interface */ 2273 DEVMETHOD(device_probe, sis_probe), 2274 DEVMETHOD(device_attach, sis_attach), 2275 DEVMETHOD(device_detach, sis_detach), 2276 DEVMETHOD(device_shutdown, sis_shutdown), 2277 2278 /* bus interface */ 2279 DEVMETHOD(bus_print_child, bus_generic_print_child), 2280 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2281 2282 /* MII interface */ 2283 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2284 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2285 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2286 2287 { 0, 0 } 2288}; 2289 2290static driver_t sis_driver = { 2291 "sis", 2292 sis_methods, 2293 sizeof(struct sis_softc) 2294}; 2295 2296static devclass_t sis_devclass; 2297 2298DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2299DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 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