if_sis.c revision 139717
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 139717 2005-01-05 10:26:12Z phk $"); 35 36/* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/module.h> 67#include <sys/socket.h> 68#include <sys/sysctl.h> 69 70#include <net/if.h> 71#include <net/if_arp.h> 72#include <net/ethernet.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75#include <net/if_types.h> 76#include <net/if_vlan_var.h> 77 78#include <net/bpf.h> 79 80#include <machine/bus_pio.h> 81#include <machine/bus_memio.h> 82#include <machine/bus.h> 83#include <machine/resource.h> 84#include <sys/bus.h> 85#include <sys/rman.h> 86 87#include <dev/mii/mii.h> 88#include <dev/mii/miivar.h> 89 90#include <dev/pci/pcireg.h> 91#include <dev/pci/pcivar.h> 92 93#define SIS_USEIOSPACE 94 95#include <pci/if_sisreg.h> 96 97MODULE_DEPEND(sis, pci, 1, 1, 1); 98MODULE_DEPEND(sis, ether, 1, 1, 1); 99MODULE_DEPEND(sis, miibus, 1, 1, 1); 100 101/* "controller miibus0" required. See GENERIC if you get errors here. */ 102#include "miibus_if.h" 103 104/* 105 * Various supported device vendors/types and their names. 106 */ 107static struct sis_type sis_devs[] = { 108 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 109 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 110 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 111 { 0, 0, NULL } 112}; 113 114static int sis_probe (device_t); 115static int sis_attach (device_t); 116static int sis_detach (device_t); 117 118static int sis_newbuf (struct sis_softc *, 119 struct sis_desc *, struct mbuf *); 120static int sis_encap (struct sis_softc *, 121 struct mbuf **, u_int32_t *); 122static void sis_rxeof (struct sis_softc *); 123static void sis_rxeoc (struct sis_softc *); 124static void sis_txeof (struct sis_softc *); 125static void sis_intr (void *); 126static void sis_tick (void *); 127static void sis_start (struct ifnet *); 128static void sis_startl (struct ifnet *); 129static int sis_ioctl (struct ifnet *, u_long, caddr_t); 130static void sis_init (void *); 131static void sis_initl (struct sis_softc *); 132static void sis_stop (struct sis_softc *); 133static void sis_watchdog (struct ifnet *); 134static void sis_shutdown (device_t); 135static int sis_ifmedia_upd (struct ifnet *); 136static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 137 138static u_int16_t sis_reverse (u_int16_t); 139static void sis_delay (struct sis_softc *); 140static void sis_eeprom_idle (struct sis_softc *); 141static void sis_eeprom_putbyte (struct sis_softc *, int); 142static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 143static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 144#ifdef __i386__ 145static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 146 int, int); 147static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 148static device_t sis_find_bridge (device_t); 149#endif 150 151static void sis_mii_sync (struct sis_softc *); 152static void sis_mii_send (struct sis_softc *, u_int32_t, int); 153static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 154static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 155static int sis_miibus_readreg (device_t, int, int); 156static int sis_miibus_writereg (device_t, int, int, int); 157static void sis_miibus_statchg (device_t); 158 159static void sis_setmulti_sis (struct sis_softc *); 160static void sis_setmulti_ns (struct sis_softc *); 161static uint32_t sis_mchash (struct sis_softc *, const uint8_t *); 162static void sis_reset (struct sis_softc *); 163static int sis_list_rx_init (struct sis_softc *); 164static int sis_list_tx_init (struct sis_softc *); 165 166static bus_dmamap_callback_t sis_dma_map_desc_ptr; 167static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 168static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 169#ifdef SIS_USEIOSPACE 170#define SIS_RES SYS_RES_IOPORT 171#define SIS_RID SIS_PCI_LOIO 172#else 173#define SIS_RES SYS_RES_MEMORY 174#define SIS_RID SIS_PCI_LOMEM 175#endif 176 177static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200}; 201 202static devclass_t sis_devclass; 203 204DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 205DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 206 207#define SIS_SETBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) | (x)) 210 211#define SIS_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_4(sc, reg, \ 213 CSR_READ_4(sc, reg) & ~(x)) 214 215#define SIO_SET(x) \ 216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 217 218#define SIO_CLR(x) \ 219 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 220 221static void 222sis_dma_map_desc_next(arg, segs, nseg, error) 223 void *arg; 224 bus_dma_segment_t *segs; 225 int nseg, error; 226{ 227 struct sis_desc *r; 228 229 r = arg; 230 r->sis_next = segs->ds_addr; 231 232 return; 233} 234 235static void 236sis_dma_map_desc_ptr(arg, segs, nseg, error) 237 void *arg; 238 bus_dma_segment_t *segs; 239 int nseg, error; 240{ 241 struct sis_desc *r; 242 243 r = arg; 244 r->sis_ptr = segs->ds_addr; 245 246 return; 247} 248 249static void 250sis_dma_map_ring(arg, segs, nseg, error) 251 void *arg; 252 bus_dma_segment_t *segs; 253 int nseg, error; 254{ 255 u_int32_t *p; 256 257 p = arg; 258 *p = segs->ds_addr; 259 260 return; 261} 262 263/* 264 * Routine to reverse the bits in a word. Stolen almost 265 * verbatim from /usr/games/fortune. 266 */ 267static u_int16_t 268sis_reverse(n) 269 u_int16_t n; 270{ 271 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 272 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 273 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 274 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 275 276 return(n); 277} 278 279static void 280sis_delay(sc) 281 struct sis_softc *sc; 282{ 283 int idx; 284 285 for (idx = (300 / 33) + 1; idx > 0; idx--) 286 CSR_READ_4(sc, SIS_CSR); 287 288 return; 289} 290 291static void 292sis_eeprom_idle(sc) 293 struct sis_softc *sc; 294{ 295 int i; 296 297 SIO_SET(SIS_EECTL_CSEL); 298 sis_delay(sc); 299 SIO_SET(SIS_EECTL_CLK); 300 sis_delay(sc); 301 302 for (i = 0; i < 25; i++) { 303 SIO_CLR(SIS_EECTL_CLK); 304 sis_delay(sc); 305 SIO_SET(SIS_EECTL_CLK); 306 sis_delay(sc); 307 } 308 309 SIO_CLR(SIS_EECTL_CLK); 310 sis_delay(sc); 311 SIO_CLR(SIS_EECTL_CSEL); 312 sis_delay(sc); 313 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 314 315 return; 316} 317 318/* 319 * Send a read command and address to the EEPROM, check for ACK. 320 */ 321static void 322sis_eeprom_putbyte(sc, addr) 323 struct sis_softc *sc; 324 int addr; 325{ 326 int d, i; 327 328 d = addr | SIS_EECMD_READ; 329 330 /* 331 * Feed in each bit and stobe the clock. 332 */ 333 for (i = 0x400; i; i >>= 1) { 334 if (d & i) { 335 SIO_SET(SIS_EECTL_DIN); 336 } else { 337 SIO_CLR(SIS_EECTL_DIN); 338 } 339 sis_delay(sc); 340 SIO_SET(SIS_EECTL_CLK); 341 sis_delay(sc); 342 SIO_CLR(SIS_EECTL_CLK); 343 sis_delay(sc); 344 } 345 346 return; 347} 348 349/* 350 * Read a word of data stored in the EEPROM at address 'addr.' 351 */ 352static void 353sis_eeprom_getword(sc, addr, dest) 354 struct sis_softc *sc; 355 int addr; 356 u_int16_t *dest; 357{ 358 int i; 359 u_int16_t word = 0; 360 361 /* Force EEPROM to idle state. */ 362 sis_eeprom_idle(sc); 363 364 /* Enter EEPROM access mode. */ 365 sis_delay(sc); 366 SIO_CLR(SIS_EECTL_CLK); 367 sis_delay(sc); 368 SIO_SET(SIS_EECTL_CSEL); 369 sis_delay(sc); 370 371 /* 372 * Send address of word we want to read. 373 */ 374 sis_eeprom_putbyte(sc, addr); 375 376 /* 377 * Start reading bits from EEPROM. 378 */ 379 for (i = 0x8000; i; i >>= 1) { 380 SIO_SET(SIS_EECTL_CLK); 381 sis_delay(sc); 382 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 383 word |= i; 384 sis_delay(sc); 385 SIO_CLR(SIS_EECTL_CLK); 386 sis_delay(sc); 387 } 388 389 /* Turn off EEPROM access mode. */ 390 sis_eeprom_idle(sc); 391 392 *dest = word; 393 394 return; 395} 396 397/* 398 * Read a sequence of words from the EEPROM. 399 */ 400static void 401sis_read_eeprom(sc, dest, off, cnt, swap) 402 struct sis_softc *sc; 403 caddr_t dest; 404 int off; 405 int cnt; 406 int swap; 407{ 408 int i; 409 u_int16_t word = 0, *ptr; 410 411 for (i = 0; i < cnt; i++) { 412 sis_eeprom_getword(sc, off + i, &word); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 if (swap) 415 *ptr = ntohs(word); 416 else 417 *ptr = word; 418 } 419 420 return; 421} 422 423#ifdef __i386__ 424static device_t 425sis_find_bridge(dev) 426 device_t dev; 427{ 428 devclass_t pci_devclass; 429 device_t *pci_devices; 430 int pci_count = 0; 431 device_t *pci_children; 432 int pci_childcount = 0; 433 device_t *busp, *childp; 434 device_t child = NULL; 435 int i, j; 436 437 if ((pci_devclass = devclass_find("pci")) == NULL) 438 return(NULL); 439 440 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 441 442 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 443 pci_childcount = 0; 444 device_get_children(*busp, &pci_children, &pci_childcount); 445 for (j = 0, childp = pci_children; 446 j < pci_childcount; j++, childp++) { 447 if (pci_get_vendor(*childp) == SIS_VENDORID && 448 pci_get_device(*childp) == 0x0008) { 449 child = *childp; 450 goto done; 451 } 452 } 453 } 454 455done: 456 free(pci_devices, M_TEMP); 457 free(pci_children, M_TEMP); 458 return(child); 459} 460 461static void 462sis_read_cmos(sc, dev, dest, off, cnt) 463 struct sis_softc *sc; 464 device_t dev; 465 caddr_t dest; 466 int off; 467 int cnt; 468{ 469 device_t bridge; 470 u_int8_t reg; 471 int i; 472 bus_space_tag_t btag; 473 474 bridge = sis_find_bridge(dev); 475 if (bridge == NULL) 476 return; 477 reg = pci_read_config(bridge, 0x48, 1); 478 pci_write_config(bridge, 0x48, reg|0x40, 1); 479 480 /* XXX */ 481 btag = I386_BUS_SPACE_IO; 482 483 for (i = 0; i < cnt; i++) { 484 bus_space_write_1(btag, 0x0, 0x70, i + off); 485 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 486 } 487 488 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 489 return; 490} 491 492static void 493sis_read_mac(sc, dev, dest) 494 struct sis_softc *sc; 495 device_t dev; 496 caddr_t dest; 497{ 498 u_int32_t filtsave, csrsave; 499 500 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 501 csrsave = CSR_READ_4(sc, SIS_CSR); 502 503 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 504 CSR_WRITE_4(sc, SIS_CSR, 0); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 507 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 509 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 511 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 513 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 514 515 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 516 CSR_WRITE_4(sc, SIS_CSR, csrsave); 517 return; 518} 519#endif 520 521/* 522 * Sync the PHYs by setting data bit and strobing the clock 32 times. 523 */ 524static void sis_mii_sync(sc) 525 struct sis_softc *sc; 526{ 527 int i; 528 529 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 530 531 for (i = 0; i < 32; i++) { 532 SIO_SET(SIS_MII_CLK); 533 DELAY(1); 534 SIO_CLR(SIS_MII_CLK); 535 DELAY(1); 536 } 537 538 return; 539} 540 541/* 542 * Clock a series of bits through the MII. 543 */ 544static void sis_mii_send(sc, bits, cnt) 545 struct sis_softc *sc; 546 u_int32_t bits; 547 int cnt; 548{ 549 int i; 550 551 SIO_CLR(SIS_MII_CLK); 552 553 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 554 if (bits & i) { 555 SIO_SET(SIS_MII_DATA); 556 } else { 557 SIO_CLR(SIS_MII_DATA); 558 } 559 DELAY(1); 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 SIO_SET(SIS_MII_CLK); 563 } 564} 565 566/* 567 * Read an PHY register through the MII. 568 */ 569static int sis_mii_readreg(sc, frame) 570 struct sis_softc *sc; 571 struct sis_mii_frame *frame; 572 573{ 574 int i, ack, s; 575 576 s = splimp(); 577 578 /* 579 * Set up frame for RX. 580 */ 581 frame->mii_stdelim = SIS_MII_STARTDELIM; 582 frame->mii_opcode = SIS_MII_READOP; 583 frame->mii_turnaround = 0; 584 frame->mii_data = 0; 585 586 /* 587 * Turn on data xmit. 588 */ 589 SIO_SET(SIS_MII_DIR); 590 591 sis_mii_sync(sc); 592 593 /* 594 * Send command/address info. 595 */ 596 sis_mii_send(sc, frame->mii_stdelim, 2); 597 sis_mii_send(sc, frame->mii_opcode, 2); 598 sis_mii_send(sc, frame->mii_phyaddr, 5); 599 sis_mii_send(sc, frame->mii_regaddr, 5); 600 601 /* Idle bit */ 602 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 603 DELAY(1); 604 SIO_SET(SIS_MII_CLK); 605 DELAY(1); 606 607 /* Turn off xmit. */ 608 SIO_CLR(SIS_MII_DIR); 609 610 /* Check for ack */ 611 SIO_CLR(SIS_MII_CLK); 612 DELAY(1); 613 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 614 SIO_SET(SIS_MII_CLK); 615 DELAY(1); 616 617 /* 618 * Now try reading data bits. If the ack failed, we still 619 * need to clock through 16 cycles to keep the PHY(s) in sync. 620 */ 621 if (ack) { 622 for(i = 0; i < 16; i++) { 623 SIO_CLR(SIS_MII_CLK); 624 DELAY(1); 625 SIO_SET(SIS_MII_CLK); 626 DELAY(1); 627 } 628 goto fail; 629 } 630 631 for (i = 0x8000; i; i >>= 1) { 632 SIO_CLR(SIS_MII_CLK); 633 DELAY(1); 634 if (!ack) { 635 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 636 frame->mii_data |= i; 637 DELAY(1); 638 } 639 SIO_SET(SIS_MII_CLK); 640 DELAY(1); 641 } 642 643fail: 644 645 SIO_CLR(SIS_MII_CLK); 646 DELAY(1); 647 SIO_SET(SIS_MII_CLK); 648 DELAY(1); 649 650 splx(s); 651 652 if (ack) 653 return(1); 654 return(0); 655} 656 657/* 658 * Write to a PHY register through the MII. 659 */ 660static int sis_mii_writereg(sc, frame) 661 struct sis_softc *sc; 662 struct sis_mii_frame *frame; 663 664{ 665 int s; 666 667 s = splimp(); 668 /* 669 * Set up frame for TX. 670 */ 671 672 frame->mii_stdelim = SIS_MII_STARTDELIM; 673 frame->mii_opcode = SIS_MII_WRITEOP; 674 frame->mii_turnaround = SIS_MII_TURNAROUND; 675 676 /* 677 * Turn on data output. 678 */ 679 SIO_SET(SIS_MII_DIR); 680 681 sis_mii_sync(sc); 682 683 sis_mii_send(sc, frame->mii_stdelim, 2); 684 sis_mii_send(sc, frame->mii_opcode, 2); 685 sis_mii_send(sc, frame->mii_phyaddr, 5); 686 sis_mii_send(sc, frame->mii_regaddr, 5); 687 sis_mii_send(sc, frame->mii_turnaround, 2); 688 sis_mii_send(sc, frame->mii_data, 16); 689 690 /* Idle bit. */ 691 SIO_SET(SIS_MII_CLK); 692 DELAY(1); 693 SIO_CLR(SIS_MII_CLK); 694 DELAY(1); 695 696 /* 697 * Turn off xmit. 698 */ 699 SIO_CLR(SIS_MII_DIR); 700 701 splx(s); 702 703 return(0); 704} 705 706static int 707sis_miibus_readreg(dev, phy, reg) 708 device_t dev; 709 int phy, reg; 710{ 711 struct sis_softc *sc; 712 struct sis_mii_frame frame; 713 714 sc = device_get_softc(dev); 715 716 if (sc->sis_type == SIS_TYPE_83815) { 717 if (phy != 0) 718 return(0); 719 /* 720 * The NatSemi chip can take a while after 721 * a reset to come ready, during which the BMSR 722 * returns a value of 0. This is *never* supposed 723 * to happen: some of the BMSR bits are meant to 724 * be hardwired in the on position, and this can 725 * confuse the miibus code a bit during the probe 726 * and attach phase. So we make an effort to check 727 * for this condition and wait for it to clear. 728 */ 729 if (!CSR_READ_4(sc, NS_BMSR)) 730 DELAY(1000); 731 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 732 } 733 734 /* 735 * Chipsets < SIS_635 seem not to be able to read/write 736 * through mdio. Use the enhanced PHY access register 737 * again for them. 738 */ 739 if (sc->sis_type == SIS_TYPE_900 && 740 sc->sis_rev < SIS_REV_635) { 741 int i, val = 0; 742 743 if (phy != 0) 744 return(0); 745 746 CSR_WRITE_4(sc, SIS_PHYCTL, 747 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 748 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 749 750 for (i = 0; i < SIS_TIMEOUT; i++) { 751 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 752 break; 753 } 754 755 if (i == SIS_TIMEOUT) { 756 printf("sis%d: PHY failed to come ready\n", 757 sc->sis_unit); 758 return(0); 759 } 760 761 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 762 763 if (val == 0xFFFF) 764 return(0); 765 766 return(val); 767 } else { 768 bzero((char *)&frame, sizeof(frame)); 769 770 frame.mii_phyaddr = phy; 771 frame.mii_regaddr = reg; 772 sis_mii_readreg(sc, &frame); 773 774 return(frame.mii_data); 775 } 776} 777 778static int 779sis_miibus_writereg(dev, phy, reg, data) 780 device_t dev; 781 int phy, reg, data; 782{ 783 struct sis_softc *sc; 784 struct sis_mii_frame frame; 785 786 sc = device_get_softc(dev); 787 788 if (sc->sis_type == SIS_TYPE_83815) { 789 if (phy != 0) 790 return(0); 791 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 792 return(0); 793 } 794 795 /* 796 * Chipsets < SIS_635 seem not to be able to read/write 797 * through mdio. Use the enhanced PHY access register 798 * again for them. 799 */ 800 if (sc->sis_type == SIS_TYPE_900 && 801 sc->sis_rev < SIS_REV_635) { 802 int i; 803 804 if (phy != 0) 805 return(0); 806 807 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 808 (reg << 6) | SIS_PHYOP_WRITE); 809 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 810 811 for (i = 0; i < SIS_TIMEOUT; i++) { 812 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 813 break; 814 } 815 816 if (i == SIS_TIMEOUT) 817 printf("sis%d: PHY failed to come ready\n", 818 sc->sis_unit); 819 } else { 820 bzero((char *)&frame, sizeof(frame)); 821 822 frame.mii_phyaddr = phy; 823 frame.mii_regaddr = reg; 824 frame.mii_data = data; 825 sis_mii_writereg(sc, &frame); 826 } 827 return(0); 828} 829 830static void 831sis_miibus_statchg(device_t dev) 832{ 833 struct sis_softc *sc; 834 835 sc = device_get_softc(dev); 836 SIS_LOCK_ASSERT(sc); 837 sis_initl(sc); 838} 839 840static u_int32_t 841sis_mchash(sc, addr) 842 struct sis_softc *sc; 843 const uint8_t *addr; 844{ 845 uint32_t crc; 846 847 /* Compute CRC for the address value. */ 848 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 849 850 /* 851 * return the filter bit position 852 * 853 * The NatSemi chip has a 512-bit filter, which is 854 * different than the SiS, so we special-case it. 855 */ 856 if (sc->sis_type == SIS_TYPE_83815) 857 return (crc >> 23); 858 else if (sc->sis_rev >= SIS_REV_635 || 859 sc->sis_rev == SIS_REV_900B) 860 return (crc >> 24); 861 else 862 return (crc >> 25); 863} 864 865static void 866sis_setmulti_ns(sc) 867 struct sis_softc *sc; 868{ 869 struct ifnet *ifp; 870 struct ifmultiaddr *ifma; 871 u_int32_t h = 0, i, filtsave; 872 int bit, index; 873 874 ifp = &sc->arpcom.ac_if; 875 876 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 877 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 878 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 879 return; 880 } 881 882 /* 883 * We have to explicitly enable the multicast hash table 884 * on the NatSemi chip if we want to use it, which we do. 885 */ 886 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 887 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 888 889 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 890 891 /* first, zot all the existing hash bits */ 892 for (i = 0; i < 32; i++) { 893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 894 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 895 } 896 897 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 898 if (ifma->ifma_addr->sa_family != AF_LINK) 899 continue; 900 h = sis_mchash(sc, 901 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 902 index = h >> 3; 903 bit = h & 0x1F; 904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 905 if (bit > 0xF) 906 bit -= 0x10; 907 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 908 } 909 910 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 911 912 return; 913} 914 915static void 916sis_setmulti_sis(sc) 917 struct sis_softc *sc; 918{ 919 struct ifnet *ifp; 920 struct ifmultiaddr *ifma; 921 u_int32_t h, i, n, ctl; 922 u_int16_t hashes[16]; 923 924 ifp = &sc->arpcom.ac_if; 925 926 /* hash table size */ 927 if (sc->sis_rev >= SIS_REV_635 || 928 sc->sis_rev == SIS_REV_900B) 929 n = 16; 930 else 931 n = 8; 932 933 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 934 935 if (ifp->if_flags & IFF_BROADCAST) 936 ctl |= SIS_RXFILTCTL_BROAD; 937 938 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 939 ctl |= SIS_RXFILTCTL_ALLMULTI; 940 if (ifp->if_flags & IFF_PROMISC) 941 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 942 for (i = 0; i < n; i++) 943 hashes[i] = ~0; 944 } else { 945 for (i = 0; i < n; i++) 946 hashes[i] = 0; 947 i = 0; 948 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 949 if (ifma->ifma_addr->sa_family != AF_LINK) 950 continue; 951 h = sis_mchash(sc, 952 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 953 hashes[h >> 4] |= 1 << (h & 0xf); 954 i++; 955 } 956 if (i > n) { 957 ctl |= SIS_RXFILTCTL_ALLMULTI; 958 for (i = 0; i < n; i++) 959 hashes[i] = ~0; 960 } 961 } 962 963 for (i = 0; i < n; i++) { 964 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 965 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 966 } 967 968 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 969} 970 971static void 972sis_reset(struct sis_softc *sc) 973{ 974 int i; 975 976 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 977 978 for (i = 0; i < SIS_TIMEOUT; i++) { 979 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 980 break; 981 } 982 983 if (i == SIS_TIMEOUT) 984 printf("sis%d: reset never completed\n", sc->sis_unit); 985 986 /* Wait a little while for the chip to get its brains in order. */ 987 DELAY(1000); 988 989 /* 990 * If this is a NetSemi chip, make sure to clear 991 * PME mode. 992 */ 993 if (sc->sis_type == SIS_TYPE_83815) { 994 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 995 CSR_WRITE_4(sc, NS_CLKRUN, 0); 996 } 997 998 return; 999} 1000 1001/* 1002 * Probe for an SiS chip. Check the PCI vendor and device 1003 * IDs against our list and return a device name if we find a match. 1004 */ 1005static int 1006sis_probe(dev) 1007 device_t dev; 1008{ 1009 struct sis_type *t; 1010 1011 t = sis_devs; 1012 1013 while(t->sis_name != NULL) { 1014 if ((pci_get_vendor(dev) == t->sis_vid) && 1015 (pci_get_device(dev) == t->sis_did)) { 1016 device_set_desc(dev, t->sis_name); 1017 return(0); 1018 } 1019 t++; 1020 } 1021 1022 return(ENXIO); 1023} 1024 1025/* 1026 * Attach the interface. Allocate softc structures, do ifmedia 1027 * setup and ethernet/BPF attach. 1028 */ 1029static int 1030sis_attach(dev) 1031 device_t dev; 1032{ 1033 u_char eaddr[ETHER_ADDR_LEN]; 1034 struct sis_softc *sc; 1035 struct ifnet *ifp; 1036 int unit, error = 0, rid, waittime = 0; 1037 1038 waittime = 0; 1039 sc = device_get_softc(dev); 1040 unit = device_get_unit(dev); 1041 1042 sc->sis_self = dev; 1043 1044 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1045 MTX_DEF | MTX_RECURSE); 1046 1047 if (pci_get_device(dev) == SIS_DEVICEID_900) 1048 sc->sis_type = SIS_TYPE_900; 1049 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1050 sc->sis_type = SIS_TYPE_7016; 1051 if (pci_get_vendor(dev) == NS_VENDORID) 1052 sc->sis_type = SIS_TYPE_83815; 1053 1054 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1055 /* 1056 * Map control/status registers. 1057 */ 1058 pci_enable_busmaster(dev); 1059 1060 rid = SIS_RID; 1061 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1062 1063 if (sc->sis_res == NULL) { 1064 printf("sis%d: couldn't map ports/memory\n", unit); 1065 error = ENXIO; 1066 goto fail; 1067 } 1068 1069 sc->sis_btag = rman_get_bustag(sc->sis_res); 1070 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1071 1072 /* Allocate interrupt */ 1073 rid = 0; 1074 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1075 RF_SHAREABLE | RF_ACTIVE); 1076 1077 if (sc->sis_irq == NULL) { 1078 printf("sis%d: couldn't map interrupt\n", unit); 1079 error = ENXIO; 1080 goto fail; 1081 } 1082 1083 /* Reset the adapter. */ 1084 sis_reset(sc); 1085 1086 if (sc->sis_type == SIS_TYPE_900 && 1087 (sc->sis_rev == SIS_REV_635 || 1088 sc->sis_rev == SIS_REV_900B)) { 1089 SIO_SET(SIS_CFG_RND_CNT); 1090 SIO_SET(SIS_CFG_PERR_DETECT); 1091 } 1092 1093 /* 1094 * Get station address from the EEPROM. 1095 */ 1096 switch (pci_get_vendor(dev)) { 1097 case NS_VENDORID: 1098 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1099 1100 /* We can't update the device description, so spew */ 1101 if (sc->sis_srr == NS_SRR_15C) 1102 device_printf(dev, "Silicon Revision: DP83815C\n"); 1103 else if (sc->sis_srr == NS_SRR_15D) 1104 device_printf(dev, "Silicon Revision: DP83815D\n"); 1105 else if (sc->sis_srr == NS_SRR_16A) 1106 device_printf(dev, "Silicon Revision: DP83816A\n"); 1107 else 1108 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1109 1110 /* 1111 * Reading the MAC address out of the EEPROM on 1112 * the NatSemi chip takes a bit more work than 1113 * you'd expect. The address spans 4 16-bit words, 1114 * with the first word containing only a single bit. 1115 * You have to shift everything over one bit to 1116 * get it aligned properly. Also, the bits are 1117 * stored backwards (the LSB is really the MSB, 1118 * and so on) so you have to reverse them in order 1119 * to get the MAC address into the form we want. 1120 * Why? Who the hell knows. 1121 */ 1122 { 1123 u_int16_t tmp[4]; 1124 1125 sis_read_eeprom(sc, (caddr_t)&tmp, 1126 NS_EE_NODEADDR, 4, 0); 1127 1128 /* Shift everything over one bit. */ 1129 tmp[3] = tmp[3] >> 1; 1130 tmp[3] |= tmp[2] << 15; 1131 tmp[2] = tmp[2] >> 1; 1132 tmp[2] |= tmp[1] << 15; 1133 tmp[1] = tmp[1] >> 1; 1134 tmp[1] |= tmp[0] << 15; 1135 1136 /* Now reverse all the bits. */ 1137 tmp[3] = sis_reverse(tmp[3]); 1138 tmp[2] = sis_reverse(tmp[2]); 1139 tmp[1] = sis_reverse(tmp[1]); 1140 1141 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1142 } 1143 break; 1144 case SIS_VENDORID: 1145 default: 1146#ifdef __i386__ 1147 /* 1148 * If this is a SiS 630E chipset with an embedded 1149 * SiS 900 controller, we have to read the MAC address 1150 * from the APC CMOS RAM. Our method for doing this 1151 * is very ugly since we have to reach out and grab 1152 * ahold of hardware for which we cannot properly 1153 * allocate resources. This code is only compiled on 1154 * the i386 architecture since the SiS 630E chipset 1155 * is for x86 motherboards only. Note that there are 1156 * a lot of magic numbers in this hack. These are 1157 * taken from SiS's Linux driver. I'd like to replace 1158 * them with proper symbolic definitions, but that 1159 * requires some datasheets that I don't have access 1160 * to at the moment. 1161 */ 1162 if (sc->sis_rev == SIS_REV_630S || 1163 sc->sis_rev == SIS_REV_630E || 1164 sc->sis_rev == SIS_REV_630EA1) 1165 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1166 1167 else if (sc->sis_rev == SIS_REV_635 || 1168 sc->sis_rev == SIS_REV_630ET) 1169 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1170 else if (sc->sis_rev == SIS_REV_96x) { 1171 /* Allow to read EEPROM from LAN. It is shared 1172 * between a 1394 controller and the NIC and each 1173 * time we access it, we need to set SIS_EECMD_REQ. 1174 */ 1175 SIO_SET(SIS_EECMD_REQ); 1176 for (waittime = 0; waittime < SIS_TIMEOUT; 1177 waittime++) { 1178 /* Force EEPROM to idle state. */ 1179 sis_eeprom_idle(sc); 1180 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1181 sis_read_eeprom(sc, (caddr_t)&eaddr, 1182 SIS_EE_NODEADDR, 3, 0); 1183 break; 1184 } 1185 DELAY(1); 1186 } 1187 /* 1188 * Set SIS_EECTL_CLK to high, so a other master 1189 * can operate on the i2c bus. 1190 */ 1191 SIO_SET(SIS_EECTL_CLK); 1192 /* Refuse EEPROM access by LAN */ 1193 SIO_SET(SIS_EECMD_DONE); 1194 } else 1195#endif 1196 sis_read_eeprom(sc, (caddr_t)&eaddr, 1197 SIS_EE_NODEADDR, 3, 0); 1198 break; 1199 } 1200 1201 sc->sis_unit = unit; 1202 if (debug_mpsafenet) 1203 callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1204 else 1205 callout_init(&sc->sis_stat_ch, 0); 1206 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1207 1208 /* 1209 * Allocate the parent bus DMA tag appropriate for PCI. 1210 */ 1211#define SIS_NSEG_NEW 32 1212 error = bus_dma_tag_create(NULL, /* parent */ 1213 1, 0, /* alignment, boundary */ 1214 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1215 BUS_SPACE_MAXADDR, /* highaddr */ 1216 NULL, NULL, /* filter, filterarg */ 1217 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1218 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1219 BUS_DMA_ALLOCNOW, /* flags */ 1220 NULL, NULL, /* lockfunc, lockarg */ 1221 &sc->sis_parent_tag); 1222 if (error) 1223 goto fail; 1224 1225 /* 1226 * Now allocate a tag for the DMA descriptor lists and a chunk 1227 * of DMA-able memory based on the tag. Also obtain the physical 1228 * addresses of the RX and TX ring, which we'll need later. 1229 * All of our lists are allocated as a contiguous block 1230 * of memory. 1231 */ 1232 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1233 1, 0, /* alignment, boundary */ 1234 BUS_SPACE_MAXADDR, /* lowaddr */ 1235 BUS_SPACE_MAXADDR, /* highaddr */ 1236 NULL, NULL, /* filter, filterarg */ 1237 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1238 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1239 0, /* flags */ 1240 busdma_lock_mutex, /* lockfunc */ 1241 &Giant, /* lockarg */ 1242 &sc->sis_rx_tag); 1243 if (error) 1244 goto fail; 1245 1246 error = bus_dmamem_alloc(sc->sis_rx_tag, 1247 (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1248 &sc->sis_rx_dmamap); 1249 1250 if (error) { 1251 printf("sis%d: no memory for rx list buffers!\n", unit); 1252 bus_dma_tag_destroy(sc->sis_rx_tag); 1253 sc->sis_rx_tag = NULL; 1254 goto fail; 1255 } 1256 1257 error = bus_dmamap_load(sc->sis_rx_tag, 1258 sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1259 sizeof(struct sis_desc), sis_dma_map_ring, 1260 &sc->sis_rx_paddr, 0); 1261 1262 if (error) { 1263 printf("sis%d: cannot get address of the rx ring!\n", unit); 1264 bus_dmamem_free(sc->sis_rx_tag, 1265 sc->sis_rx_list, sc->sis_rx_dmamap); 1266 bus_dma_tag_destroy(sc->sis_rx_tag); 1267 sc->sis_rx_tag = NULL; 1268 goto fail; 1269 } 1270 1271 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1272 1, 0, /* alignment, boundary */ 1273 BUS_SPACE_MAXADDR, /* lowaddr */ 1274 BUS_SPACE_MAXADDR, /* highaddr */ 1275 NULL, NULL, /* filter, filterarg */ 1276 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1277 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1278 0, /* flags */ 1279 busdma_lock_mutex, /* lockfunc */ 1280 &Giant, /* lockarg */ 1281 &sc->sis_tx_tag); 1282 if (error) 1283 goto fail; 1284 1285 error = bus_dmamem_alloc(sc->sis_tx_tag, 1286 (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1287 &sc->sis_tx_dmamap); 1288 1289 if (error) { 1290 printf("sis%d: no memory for tx list buffers!\n", unit); 1291 bus_dma_tag_destroy(sc->sis_tx_tag); 1292 sc->sis_tx_tag = NULL; 1293 goto fail; 1294 } 1295 1296 error = bus_dmamap_load(sc->sis_tx_tag, 1297 sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1298 sizeof(struct sis_desc), sis_dma_map_ring, 1299 &sc->sis_tx_paddr, 0); 1300 1301 if (error) { 1302 printf("sis%d: cannot get address of the tx ring!\n", unit); 1303 bus_dmamem_free(sc->sis_tx_tag, 1304 sc->sis_tx_list, sc->sis_tx_dmamap); 1305 bus_dma_tag_destroy(sc->sis_tx_tag); 1306 sc->sis_tx_tag = NULL; 1307 goto fail; 1308 } 1309 1310 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1311 1, 0, /* alignment, boundary */ 1312 BUS_SPACE_MAXADDR, /* lowaddr */ 1313 BUS_SPACE_MAXADDR, /* highaddr */ 1314 NULL, NULL, /* filter, filterarg */ 1315 MCLBYTES, 1, /* maxsize,nsegments */ 1316 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1317 0, /* flags */ 1318 busdma_lock_mutex, /* lockfunc */ 1319 &Giant, /* lockarg */ 1320 &sc->sis_tag); 1321 if (error) 1322 goto fail; 1323 1324 /* 1325 * Obtain the physical addresses of the RX and TX 1326 * rings which we'll need later in the init routine. 1327 */ 1328 1329 ifp = &sc->arpcom.ac_if; 1330 ifp->if_softc = sc; 1331 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1332 ifp->if_mtu = ETHERMTU; 1333 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1334 ifp->if_ioctl = sis_ioctl; 1335 ifp->if_start = sis_start; 1336 ifp->if_watchdog = sis_watchdog; 1337 ifp->if_init = sis_init; 1338 ifp->if_baudrate = 10000000; 1339 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1340 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1341 IFQ_SET_READY(&ifp->if_snd); 1342 1343 /* 1344 * Do MII setup. 1345 */ 1346 if (mii_phy_probe(dev, &sc->sis_miibus, 1347 sis_ifmedia_upd, sis_ifmedia_sts)) { 1348 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1349 error = ENXIO; 1350 goto fail; 1351 } 1352 1353 /* 1354 * Call MI attach routine. 1355 */ 1356 ether_ifattach(ifp, eaddr); 1357 1358 /* 1359 * Tell the upper layer(s) we support long frames. 1360 */ 1361 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1362 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1363 1364#ifdef DEVICE_POLLING 1365 ifp->if_capabilities |= IFCAP_POLLING; 1366#endif 1367 ifp->if_capenable = ifp->if_capabilities; 1368 1369 /* Hook interrupt last to avoid having to lock softc */ 1370 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1371 sis_intr, sc, &sc->sis_intrhand); 1372 1373 if (error) { 1374 printf("sis%d: couldn't set up irq\n", unit); 1375 ether_ifdetach(ifp); 1376 goto fail; 1377 } 1378 1379fail: 1380 if (error) 1381 sis_detach(dev); 1382 1383 return(error); 1384} 1385 1386/* 1387 * Shutdown hardware and free up resources. This can be called any 1388 * time after the mutex has been initialized. It is called in both 1389 * the error case in attach and the normal detach case so it needs 1390 * to be careful about only freeing resources that have actually been 1391 * allocated. 1392 */ 1393static int 1394sis_detach(dev) 1395 device_t dev; 1396{ 1397 struct sis_softc *sc; 1398 struct ifnet *ifp; 1399 1400 sc = device_get_softc(dev); 1401 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1402 SIS_LOCK(sc); 1403 ifp = &sc->arpcom.ac_if; 1404 1405 /* These should only be active if attach succeeded. */ 1406 if (device_is_attached(dev)) { 1407 sis_reset(sc); 1408 sis_stop(sc); 1409 ether_ifdetach(ifp); 1410 } 1411 if (sc->sis_miibus) 1412 device_delete_child(dev, sc->sis_miibus); 1413 bus_generic_detach(dev); 1414 1415 if (sc->sis_intrhand) 1416 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1417 if (sc->sis_irq) 1418 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1419 if (sc->sis_res) 1420 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1421 1422 if (sc->sis_rx_tag) { 1423 bus_dmamap_unload(sc->sis_rx_tag, 1424 sc->sis_rx_dmamap); 1425 bus_dmamem_free(sc->sis_rx_tag, 1426 sc->sis_rx_list, sc->sis_rx_dmamap); 1427 bus_dma_tag_destroy(sc->sis_rx_tag); 1428 } 1429 if (sc->sis_tx_tag) { 1430 bus_dmamap_unload(sc->sis_tx_tag, 1431 sc->sis_tx_dmamap); 1432 bus_dmamem_free(sc->sis_tx_tag, 1433 sc->sis_tx_list, sc->sis_tx_dmamap); 1434 bus_dma_tag_destroy(sc->sis_tx_tag); 1435 } 1436 if (sc->sis_parent_tag) 1437 bus_dma_tag_destroy(sc->sis_parent_tag); 1438 if (sc->sis_tag) 1439 bus_dma_tag_destroy(sc->sis_tag); 1440 1441 SIS_UNLOCK(sc); 1442 mtx_destroy(&sc->sis_mtx); 1443 1444 return(0); 1445} 1446 1447/* 1448 * Initialize the transmit descriptors. 1449 */ 1450static int 1451sis_list_tx_init(sc) 1452 struct sis_softc *sc; 1453{ 1454 int i, nexti; 1455 1456 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1457 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1458 sc->sis_tx_list[i].sis_nextdesc = 1459 &sc->sis_tx_list[nexti]; 1460 bus_dmamap_load(sc->sis_tx_tag, 1461 sc->sis_tx_dmamap, 1462 &sc->sis_tx_list[nexti], sizeof(struct sis_desc), 1463 sis_dma_map_desc_next, &sc->sis_tx_list[i], 0); 1464 sc->sis_tx_list[i].sis_mbuf = NULL; 1465 sc->sis_tx_list[i].sis_ptr = 0; 1466 sc->sis_tx_list[i].sis_ctl = 0; 1467 } 1468 1469 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1470 1471 bus_dmamap_sync(sc->sis_tx_tag, 1472 sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1473 1474 return(0); 1475} 1476 1477/* 1478 * Initialize the RX descriptors and allocate mbufs for them. Note that 1479 * we arrange the descriptors in a closed ring, so that the last descriptor 1480 * points back to the first. 1481 */ 1482static int 1483sis_list_rx_init(sc) 1484 struct sis_softc *sc; 1485{ 1486 int i,nexti; 1487 1488 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1489 if (sis_newbuf(sc, &sc->sis_rx_list[i], NULL) == ENOBUFS) 1490 return(ENOBUFS); 1491 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1492 sc->sis_rx_list[i].sis_nextdesc = 1493 &sc->sis_rx_list[nexti]; 1494 bus_dmamap_load(sc->sis_rx_tag, 1495 sc->sis_rx_dmamap, 1496 &sc->sis_rx_list[nexti], 1497 sizeof(struct sis_desc), sis_dma_map_desc_next, 1498 &sc->sis_rx_list[i], 0); 1499 } 1500 1501 bus_dmamap_sync(sc->sis_rx_tag, 1502 sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1503 1504 sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 1505 1506 return(0); 1507} 1508 1509/* 1510 * Initialize an RX descriptor and attach an MBUF cluster. 1511 */ 1512static int 1513sis_newbuf(sc, c, m) 1514 struct sis_softc *sc; 1515 struct sis_desc *c; 1516 struct mbuf *m; 1517{ 1518 1519 if (c == NULL) 1520 return(EINVAL); 1521 1522 if (m == NULL) { 1523 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1524 if (m == NULL) 1525 return(ENOBUFS); 1526 } else 1527 m->m_data = m->m_ext.ext_buf; 1528 1529 c->sis_mbuf = m; 1530 c->sis_ctl = SIS_RXLEN; 1531 1532 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1533 bus_dmamap_load(sc->sis_tag, c->sis_map, 1534 mtod(m, void *), MCLBYTES, 1535 sis_dma_map_desc_ptr, c, 0); 1536 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1537 1538 return(0); 1539} 1540 1541/* 1542 * A frame has been uploaded: pass the resulting mbuf chain up to 1543 * the higher level protocols. 1544 */ 1545static void 1546sis_rxeof(sc) 1547 struct sis_softc *sc; 1548{ 1549 struct mbuf *m; 1550 struct ifnet *ifp; 1551 struct sis_desc *cur_rx; 1552 int total_len = 0; 1553 u_int32_t rxstat; 1554 1555 SIS_LOCK_ASSERT(sc); 1556 1557 ifp = &sc->arpcom.ac_if; 1558 1559 for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1560 cur_rx = cur_rx->sis_nextdesc) { 1561 1562#ifdef DEVICE_POLLING 1563 if (ifp->if_flags & IFF_POLLING) { 1564 if (sc->rxcycles <= 0) 1565 break; 1566 sc->rxcycles--; 1567 } 1568#endif /* DEVICE_POLLING */ 1569 rxstat = cur_rx->sis_rxstat; 1570 bus_dmamap_sync(sc->sis_tag, 1571 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1572 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1573 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1574 m = cur_rx->sis_mbuf; 1575 cur_rx->sis_mbuf = NULL; 1576 total_len = SIS_RXBYTES(cur_rx); 1577 1578 /* 1579 * If an error occurs, update stats, clear the 1580 * status word and leave the mbuf cluster in place: 1581 * it should simply get re-used next time this descriptor 1582 * comes up in the ring. 1583 */ 1584 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1585 ifp->if_ierrors++; 1586 if (rxstat & SIS_RXSTAT_COLL) 1587 ifp->if_collisions++; 1588 sis_newbuf(sc, cur_rx, m); 1589 continue; 1590 } 1591 1592 /* No errors; receive the packet. */ 1593#ifdef __i386__ 1594 /* 1595 * On the x86 we do not have alignment problems, so try to 1596 * allocate a new buffer for the receive ring, and pass up 1597 * the one where the packet is already, saving the expensive 1598 * copy done in m_devget(). 1599 * If we are on an architecture with alignment problems, or 1600 * if the allocation fails, then use m_devget and leave the 1601 * existing buffer in the receive ring. 1602 */ 1603 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1604 m->m_pkthdr.len = m->m_len = total_len; 1605 else 1606#endif 1607 { 1608 struct mbuf *m0; 1609 m0 = m_devget(mtod(m, char *), total_len, 1610 ETHER_ALIGN, ifp, NULL); 1611 sis_newbuf(sc, cur_rx, m); 1612 if (m0 == NULL) { 1613 ifp->if_ierrors++; 1614 continue; 1615 } 1616 m = m0; 1617 } 1618 1619 ifp->if_ipackets++; 1620 m->m_pkthdr.rcvif = ifp; 1621 1622 SIS_UNLOCK(sc); 1623 (*ifp->if_input)(ifp, m); 1624 SIS_LOCK(sc); 1625 } 1626 1627 sc->sis_rx_pdsc = cur_rx; 1628 1629 return; 1630} 1631 1632static void 1633sis_rxeoc(struct sis_softc *sc) 1634{ 1635 1636 SIS_LOCK_ASSERT(sc); 1637 sis_rxeof(sc); 1638 sis_initl(sc); 1639} 1640 1641/* 1642 * A frame was downloaded to the chip. It's safe for us to clean up 1643 * the list buffers. 1644 */ 1645 1646static void 1647sis_txeof(sc) 1648 struct sis_softc *sc; 1649{ 1650 struct ifnet *ifp; 1651 u_int32_t idx; 1652 1653 SIS_LOCK_ASSERT(sc); 1654 ifp = &sc->arpcom.ac_if; 1655 1656 /* 1657 * Go through our tx list and free mbufs for those 1658 * frames that have been transmitted. 1659 */ 1660 for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1661 sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1662 struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 1663 1664 if (SIS_OWNDESC(cur_tx)) 1665 break; 1666 1667 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1668 continue; 1669 1670 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1671 ifp->if_oerrors++; 1672 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1673 ifp->if_collisions++; 1674 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1675 ifp->if_collisions++; 1676 } 1677 1678 ifp->if_collisions += 1679 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1680 1681 ifp->if_opackets++; 1682 if (cur_tx->sis_mbuf != NULL) { 1683 m_freem(cur_tx->sis_mbuf); 1684 cur_tx->sis_mbuf = NULL; 1685 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1686 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1687 } 1688 } 1689 1690 if (idx != sc->sis_tx_cons) { 1691 /* we freed up some buffers */ 1692 sc->sis_tx_cons = idx; 1693 ifp->if_flags &= ~IFF_OACTIVE; 1694 } 1695 1696 ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 1697 1698 return; 1699} 1700 1701static void 1702sis_tick(xsc) 1703 void *xsc; 1704{ 1705 struct sis_softc *sc; 1706 struct mii_data *mii; 1707 struct ifnet *ifp; 1708 1709 sc = xsc; 1710 SIS_LOCK(sc); 1711 sc->in_tick = 1; 1712 ifp = &sc->arpcom.ac_if; 1713 1714 mii = device_get_softc(sc->sis_miibus); 1715 mii_tick(mii); 1716 1717 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1718 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1719 sc->sis_link++; 1720 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1721 sis_startl(ifp); 1722 } 1723 1724 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1725 sc->in_tick = 0; 1726 SIS_UNLOCK(sc); 1727 1728 return; 1729} 1730 1731#ifdef DEVICE_POLLING 1732static poll_handler_t sis_poll; 1733 1734static void 1735sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1736{ 1737 struct sis_softc *sc = ifp->if_softc; 1738 1739 SIS_LOCK(sc); 1740 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1741 ether_poll_deregister(ifp); 1742 cmd = POLL_DEREGISTER; 1743 } 1744 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1745 CSR_WRITE_4(sc, SIS_IER, 1); 1746 goto done; 1747 } 1748 1749 /* 1750 * On the sis, reading the status register also clears it. 1751 * So before returning to intr mode we must make sure that all 1752 * possible pending sources of interrupts have been served. 1753 * In practice this means run to completion the *eof routines, 1754 * and then call the interrupt routine 1755 */ 1756 sc->rxcycles = count; 1757 sis_rxeof(sc); 1758 sis_txeof(sc); 1759 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1760 sis_startl(ifp); 1761 1762 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1763 u_int32_t status; 1764 1765 /* Reading the ISR register clears all interrupts. */ 1766 status = CSR_READ_4(sc, SIS_ISR); 1767 1768 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1769 sis_rxeoc(sc); 1770 1771 if (status & (SIS_ISR_RX_IDLE)) 1772 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1773 1774 if (status & SIS_ISR_SYSERR) { 1775 sis_reset(sc); 1776 sis_initl(sc); 1777 } 1778 } 1779done: 1780 SIS_UNLOCK(sc); 1781 return; 1782} 1783#endif /* DEVICE_POLLING */ 1784 1785static void 1786sis_intr(arg) 1787 void *arg; 1788{ 1789 struct sis_softc *sc; 1790 struct ifnet *ifp; 1791 u_int32_t status; 1792 1793 sc = arg; 1794 ifp = &sc->arpcom.ac_if; 1795 1796 SIS_LOCK(sc); 1797#ifdef DEVICE_POLLING 1798 if (ifp->if_flags & IFF_POLLING) 1799 goto done; 1800 if ((ifp->if_capenable & IFCAP_POLLING) && 1801 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1802 CSR_WRITE_4(sc, SIS_IER, 0); 1803 goto done; 1804 } 1805#endif /* DEVICE_POLLING */ 1806 1807 /* Supress unwanted interrupts */ 1808 if (!(ifp->if_flags & IFF_UP)) { 1809 sis_stop(sc); 1810 goto done; 1811 } 1812 1813 /* Disable interrupts. */ 1814 CSR_WRITE_4(sc, SIS_IER, 0); 1815 1816 for (;;) { 1817 SIS_LOCK_ASSERT(sc); 1818 /* Reading the ISR register clears all interrupts. */ 1819 status = CSR_READ_4(sc, SIS_ISR); 1820 1821 if ((status & SIS_INTRS) == 0) 1822 break; 1823 1824 if (status & 1825 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1826 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1827 sis_txeof(sc); 1828 1829 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1830 sis_rxeof(sc); 1831 1832 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1833 sis_rxeoc(sc); 1834 1835 if (status & (SIS_ISR_RX_IDLE)) 1836 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1837 1838 if (status & SIS_ISR_SYSERR) { 1839 sis_reset(sc); 1840 sis_initl(sc); 1841 } 1842 } 1843 1844 /* Re-enable interrupts. */ 1845 CSR_WRITE_4(sc, SIS_IER, 1); 1846 1847 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1848 sis_startl(ifp); 1849done: 1850 SIS_UNLOCK(sc); 1851 1852 return; 1853} 1854 1855/* 1856 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1857 * pointers to the fragment pointers. 1858 */ 1859static int 1860sis_encap(sc, m_head, txidx) 1861 struct sis_softc *sc; 1862 struct mbuf **m_head; 1863 u_int32_t *txidx; 1864{ 1865 struct sis_desc *f = NULL; 1866 struct mbuf *m; 1867 int frag, cur, cnt = 0, chainlen = 0; 1868 1869 /* 1870 * If there's no way we can send any packets, return now. 1871 */ 1872 if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1873 return (ENOBUFS); 1874 1875 /* 1876 * Count the number of frags in this chain to see if 1877 * we need to m_defrag. Since the descriptor list is shared 1878 * by all packets, we'll m_defrag long chains so that they 1879 * do not use up the entire list, even if they would fit. 1880 */ 1881 1882 for (m = *m_head; m != NULL; m = m->m_next) 1883 chainlen++; 1884 1885 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1886 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1887 m = m_defrag(*m_head, M_DONTWAIT); 1888 if (m == NULL) 1889 return (ENOBUFS); 1890 *m_head = m; 1891 } 1892 1893 /* 1894 * Start packing the mbufs in this chain into 1895 * the fragment pointers. Stop when we run out 1896 * of fragments or hit the end of the mbuf chain. 1897 */ 1898 cur = frag = *txidx; 1899 1900 for (m = *m_head; m != NULL; m = m->m_next) { 1901 if (m->m_len != 0) { 1902 if ((SIS_TX_LIST_CNT - 1903 (sc->sis_tx_cnt + cnt)) < 2) 1904 return(ENOBUFS); 1905 f = &sc->sis_tx_list[frag]; 1906 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1907 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1908 bus_dmamap_load(sc->sis_tag, f->sis_map, 1909 mtod(m, void *), m->m_len, 1910 sis_dma_map_desc_ptr, f, 0); 1911 bus_dmamap_sync(sc->sis_tag, 1912 f->sis_map, BUS_DMASYNC_PREREAD); 1913 if (cnt != 0) 1914 f->sis_ctl |= SIS_CMDSTS_OWN; 1915 cur = frag; 1916 SIS_INC(frag, SIS_TX_LIST_CNT); 1917 cnt++; 1918 } 1919 } 1920 1921 if (m != NULL) 1922 return(ENOBUFS); 1923 1924 sc->sis_tx_list[cur].sis_mbuf = *m_head; 1925 sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1926 sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1927 sc->sis_tx_cnt += cnt; 1928 *txidx = frag; 1929 1930 return(0); 1931} 1932 1933/* 1934 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1935 * to the mbuf data regions directly in the transmit lists. We also save a 1936 * copy of the pointers since the transmit list fragment pointers are 1937 * physical addresses. 1938 */ 1939 1940static void 1941sis_start(struct ifnet *ifp) 1942{ 1943 struct sis_softc *sc; 1944 1945 sc = ifp->if_softc; 1946 SIS_LOCK(sc); 1947 sis_startl(ifp); 1948 SIS_UNLOCK(sc); 1949} 1950 1951static void 1952sis_startl(struct ifnet *ifp) 1953{ 1954 struct sis_softc *sc; 1955 struct mbuf *m_head = NULL; 1956 u_int32_t idx, queued = 0; 1957 1958 sc = ifp->if_softc; 1959 1960 SIS_LOCK_ASSERT(sc); 1961 1962 if (!sc->sis_link) 1963 return; 1964 1965 idx = sc->sis_tx_prod; 1966 1967 if (ifp->if_flags & IFF_OACTIVE) 1968 return; 1969 1970 while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1971 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1972 if (m_head == NULL) 1973 break; 1974 1975 if (sis_encap(sc, &m_head, &idx)) { 1976 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1977 ifp->if_flags |= IFF_OACTIVE; 1978 break; 1979 } 1980 1981 queued++; 1982 1983 /* 1984 * If there's a BPF listener, bounce a copy of this frame 1985 * to him. 1986 */ 1987 BPF_MTAP(ifp, m_head); 1988 1989 } 1990 1991 if (queued) { 1992 /* Transmit */ 1993 sc->sis_tx_prod = idx; 1994 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1995 1996 /* 1997 * Set a timeout in case the chip goes out to lunch. 1998 */ 1999 ifp->if_timer = 5; 2000 } 2001} 2002 2003static void 2004sis_init(void *xsc) 2005{ 2006 struct sis_softc *sc = xsc; 2007 2008 SIS_LOCK(sc); 2009 sis_initl(sc); 2010 SIS_UNLOCK(sc); 2011} 2012 2013 2014static void 2015sis_initl(struct sis_softc *sc) 2016{ 2017 struct ifnet *ifp = &sc->arpcom.ac_if; 2018 struct mii_data *mii; 2019 2020 SIS_LOCK_ASSERT(sc); 2021 2022 /* 2023 * Cancel pending I/O and free all RX/TX buffers. 2024 */ 2025 sis_stop(sc); 2026 sc->sis_stopped = 0; 2027 2028#ifdef notyet 2029 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2030 /* 2031 * Configure 400usec of interrupt holdoff. This is based 2032 * on emperical tests on a Soekris 4801. 2033 */ 2034 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2035 } 2036#endif 2037 2038 mii = device_get_softc(sc->sis_miibus); 2039 2040 /* Set MAC address */ 2041 if (sc->sis_type == SIS_TYPE_83815) { 2042 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2043 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2044 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2045 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2046 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2047 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2048 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2049 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2050 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2051 } else { 2052 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2053 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2054 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2055 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2056 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2057 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2058 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2059 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2060 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2061 } 2062 2063 /* Init circular RX list. */ 2064 if (sis_list_rx_init(sc) == ENOBUFS) { 2065 printf("sis%d: initialization failed: no " 2066 "memory for rx buffers\n", sc->sis_unit); 2067 sis_stop(sc); 2068 return; 2069 } 2070 2071 /* 2072 * Init tx descriptors. 2073 */ 2074 sis_list_tx_init(sc); 2075 2076 /* 2077 * Page 78 of the DP83815 data sheet (september 2002 version) 2078 * recommends the following register settings "for optimum 2079 * performance." for rev 15C. The driver from NS also sets 2080 * the PHY_CR register for later versions. 2081 */ 2082 if (sc->sis_type == SIS_TYPE_83815) { 2083 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2084 /* DC speed = 01 */ 2085 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2086 if (sc->sis_srr == NS_SRR_15C) { 2087 /* set val for c2 */ 2088 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2089 /* load/kill c2 */ 2090 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2091 /* rais SD off, from 4 to c */ 2092 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2093 } 2094 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2095 } 2096 2097 2098 /* 2099 * For the NatSemi chip, we have to explicitly enable the 2100 * reception of ARP frames, as well as turn on the 'perfect 2101 * match' filter where we store the station address, otherwise 2102 * we won't receive unicasts meant for this host. 2103 */ 2104 if (sc->sis_type == SIS_TYPE_83815) { 2105 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2106 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2107 } 2108 2109 /* If we want promiscuous mode, set the allframes bit. */ 2110 if (ifp->if_flags & IFF_PROMISC) { 2111 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2112 } else { 2113 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2114 } 2115 2116 /* 2117 * Set the capture broadcast bit to capture broadcast frames. 2118 */ 2119 if (ifp->if_flags & IFF_BROADCAST) { 2120 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2121 } else { 2122 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2123 } 2124 2125 /* 2126 * Load the multicast filter. 2127 */ 2128 if (sc->sis_type == SIS_TYPE_83815) 2129 sis_setmulti_ns(sc); 2130 else 2131 sis_setmulti_sis(sc); 2132 2133 /* Turn the receive filter on */ 2134 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2135 2136 /* 2137 * Load the address of the RX and TX lists. 2138 */ 2139 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 2140 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 2141 2142 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2143 * the PCI bus. When this bit is set, the Max DMA Burst Size 2144 * for TX/RX DMA should be no larger than 16 double words. 2145 */ 2146 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2147 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2148 } else { 2149 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2150 } 2151 2152 /* Accept Long Packets for VLAN support */ 2153 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2154 2155 /* Set TX configuration */ 2156 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2157 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2158 } else { 2159 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2160 } 2161 2162 /* Set full/half duplex mode. */ 2163 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2164 SIS_SETBIT(sc, SIS_TX_CFG, 2165 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2166 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2167 } else { 2168 SIS_CLRBIT(sc, SIS_TX_CFG, 2169 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2170 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2171 } 2172 2173 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2174 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2175 uint32_t reg; 2176 2177 /* 2178 * Some DP83815s experience problems when used with short 2179 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2180 * sequence adjusts the DSP's signal attenuation to fix the 2181 * problem. 2182 */ 2183 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2184 2185 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2186 /* Allow coefficient to be read */ 2187 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2188 DELAY(100); 2189 reg = CSR_READ_4(sc, NS_PHY_TDATA); 2190 if ((reg & 0x0080) == 0 || 2191 (reg > 0xd8 && reg <= 0xff)) { 2192 device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2193 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2194 /* Adjust coefficient and prevent change */ 2195 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2196 } 2197 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2198 } 2199 2200 /* 2201 * Enable interrupts. 2202 */ 2203 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2204#ifdef DEVICE_POLLING 2205 /* 2206 * ... only enable interrupts if we are not polling, make sure 2207 * they are off otherwise. 2208 */ 2209 if (ifp->if_flags & IFF_POLLING) 2210 CSR_WRITE_4(sc, SIS_IER, 0); 2211 else 2212#endif /* DEVICE_POLLING */ 2213 CSR_WRITE_4(sc, SIS_IER, 1); 2214 2215 /* Enable receiver and transmitter. */ 2216 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2217 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2218 2219#ifdef notdef 2220 mii_mediachg(mii); 2221#endif 2222 2223 ifp->if_flags |= IFF_RUNNING; 2224 ifp->if_flags &= ~IFF_OACTIVE; 2225 2226 if (!sc->in_tick) 2227 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2228} 2229 2230/* 2231 * Set media options. 2232 */ 2233static int 2234sis_ifmedia_upd(ifp) 2235 struct ifnet *ifp; 2236{ 2237 struct sis_softc *sc; 2238 struct mii_data *mii; 2239 2240 sc = ifp->if_softc; 2241 2242 mii = device_get_softc(sc->sis_miibus); 2243 sc->sis_link = 0; 2244 if (mii->mii_instance) { 2245 struct mii_softc *miisc; 2246 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2247 mii_phy_reset(miisc); 2248 } 2249 mii_mediachg(mii); 2250 2251 return(0); 2252} 2253 2254/* 2255 * Report current media status. 2256 */ 2257static void 2258sis_ifmedia_sts(ifp, ifmr) 2259 struct ifnet *ifp; 2260 struct ifmediareq *ifmr; 2261{ 2262 struct sis_softc *sc; 2263 struct mii_data *mii; 2264 2265 sc = ifp->if_softc; 2266 2267 mii = device_get_softc(sc->sis_miibus); 2268 mii_pollstat(mii); 2269 ifmr->ifm_active = mii->mii_media_active; 2270 ifmr->ifm_status = mii->mii_media_status; 2271 2272 return; 2273} 2274 2275static int 2276sis_ioctl(ifp, command, data) 2277 struct ifnet *ifp; 2278 u_long command; 2279 caddr_t data; 2280{ 2281 struct sis_softc *sc = ifp->if_softc; 2282 struct ifreq *ifr = (struct ifreq *) data; 2283 struct mii_data *mii; 2284 int error = 0; 2285 2286 switch(command) { 2287 case SIOCSIFFLAGS: 2288 if (ifp->if_flags & IFF_UP) { 2289 sis_init(sc); 2290 } else { 2291 if (ifp->if_flags & IFF_RUNNING) { 2292 SIS_LOCK(sc); 2293 sis_stop(sc); 2294 SIS_UNLOCK(sc); 2295 } 2296 } 2297 error = 0; 2298 break; 2299 case SIOCADDMULTI: 2300 case SIOCDELMULTI: 2301 SIS_LOCK(sc); 2302 if (sc->sis_type == SIS_TYPE_83815) 2303 sis_setmulti_ns(sc); 2304 else 2305 sis_setmulti_sis(sc); 2306 SIS_UNLOCK(sc); 2307 error = 0; 2308 break; 2309 case SIOCGIFMEDIA: 2310 case SIOCSIFMEDIA: 2311 mii = device_get_softc(sc->sis_miibus); 2312 SIS_LOCK(sc); 2313 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2314 SIS_UNLOCK(sc); 2315 break; 2316 case SIOCSIFCAP: 2317 ifp->if_capenable &= ~IFCAP_POLLING; 2318 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2319 break; 2320 default: 2321 error = ether_ioctl(ifp, command, data); 2322 break; 2323 } 2324 2325 return(error); 2326} 2327 2328static void 2329sis_watchdog(ifp) 2330 struct ifnet *ifp; 2331{ 2332 struct sis_softc *sc; 2333 2334 sc = ifp->if_softc; 2335 2336 SIS_LOCK(sc); 2337 2338 ifp->if_oerrors++; 2339 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2340 2341 sis_stop(sc); 2342 sis_reset(sc); 2343 sis_initl(sc); 2344 2345 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2346 sis_startl(ifp); 2347 2348 SIS_UNLOCK(sc); 2349} 2350 2351/* 2352 * Stop the adapter and free any mbufs allocated to the 2353 * RX and TX lists. 2354 */ 2355static void 2356sis_stop(sc) 2357 struct sis_softc *sc; 2358{ 2359 int i; 2360 struct ifnet *ifp; 2361 2362 if (sc->sis_stopped) 2363 return; 2364 SIS_LOCK_ASSERT(sc); 2365 ifp = &sc->arpcom.ac_if; 2366 ifp->if_timer = 0; 2367 2368 callout_stop(&sc->sis_stat_ch); 2369 2370 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2371#ifdef DEVICE_POLLING 2372 ether_poll_deregister(ifp); 2373#endif 2374 CSR_WRITE_4(sc, SIS_IER, 0); 2375 CSR_WRITE_4(sc, SIS_IMR, 0); 2376 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2377 DELAY(1000); 2378 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2379 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2380 2381 sc->sis_link = 0; 2382 2383 /* 2384 * Free data in the RX lists. 2385 */ 2386 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2387 if (sc->sis_rx_list[i].sis_mbuf != NULL) { 2388 bus_dmamap_unload(sc->sis_tag, 2389 sc->sis_rx_list[i].sis_map); 2390 bus_dmamap_destroy(sc->sis_tag, 2391 sc->sis_rx_list[i].sis_map); 2392 m_freem(sc->sis_rx_list[i].sis_mbuf); 2393 sc->sis_rx_list[i].sis_mbuf = NULL; 2394 } 2395 } 2396 bzero(sc->sis_rx_list, 2397 sizeof(sc->sis_rx_list)); 2398 2399 /* 2400 * Free the TX list buffers. 2401 */ 2402 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2403 if (sc->sis_tx_list[i].sis_mbuf != NULL) { 2404 bus_dmamap_unload(sc->sis_tag, 2405 sc->sis_tx_list[i].sis_map); 2406 bus_dmamap_destroy(sc->sis_tag, 2407 sc->sis_tx_list[i].sis_map); 2408 m_freem(sc->sis_tx_list[i].sis_mbuf); 2409 sc->sis_tx_list[i].sis_mbuf = NULL; 2410 } 2411 } 2412 2413 bzero(sc->sis_tx_list, 2414 sizeof(sc->sis_tx_list)); 2415 2416 sc->sis_stopped = 1; 2417} 2418 2419/* 2420 * Stop all chip I/O so that the kernel's probe routines don't 2421 * get confused by errant DMAs when rebooting. 2422 */ 2423static void 2424sis_shutdown(device_t dev) 2425{ 2426 struct sis_softc *sc; 2427 2428 sc = device_get_softc(dev); 2429 SIS_LOCK(sc); 2430 sis_reset(sc); 2431 sis_stop(sc); 2432 SIS_UNLOCK(sc); 2433} 2434