if_sis.c revision 131253
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 131253 2004-06-28 20:07:03Z imp $"); 35 36/* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/module.h> 67#include <sys/socket.h> 68#include <sys/sysctl.h> 69 70#include <net/if.h> 71#include <net/if_arp.h> 72#include <net/ethernet.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75#include <net/if_types.h> 76#include <net/if_vlan_var.h> 77 78#include <net/bpf.h> 79 80#include <machine/bus_pio.h> 81#include <machine/bus_memio.h> 82#include <machine/bus.h> 83#include <machine/resource.h> 84#include <sys/bus.h> 85#include <sys/rman.h> 86 87#include <dev/mii/mii.h> 88#include <dev/mii/miivar.h> 89 90#include <dev/pci/pcireg.h> 91#include <dev/pci/pcivar.h> 92 93#define SIS_USEIOSPACE 94 95#include <pci/if_sisreg.h> 96 97MODULE_DEPEND(sis, pci, 1, 1, 1); 98MODULE_DEPEND(sis, ether, 1, 1, 1); 99MODULE_DEPEND(sis, miibus, 1, 1, 1); 100 101/* "controller miibus0" required. See GENERIC if you get errors here. */ 102#include "miibus_if.h" 103 104/* 105 * Various supported device vendors/types and their names. 106 */ 107static struct sis_type sis_devs[] = { 108 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 109 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 110 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 111 { 0, 0, NULL } 112}; 113 114static int sis_probe (device_t); 115static int sis_attach (device_t); 116static int sis_detach (device_t); 117 118static int sis_newbuf (struct sis_softc *, 119 struct sis_desc *, struct mbuf *); 120static int sis_encap (struct sis_softc *, 121 struct mbuf **, u_int32_t *); 122static void sis_rxeof (struct sis_softc *); 123static void sis_rxeoc (struct sis_softc *); 124static void sis_txeof (struct sis_softc *); 125static void sis_intr (void *); 126static void sis_tick (void *); 127static void sis_start (struct ifnet *); 128static int sis_ioctl (struct ifnet *, u_long, caddr_t); 129static void sis_init (void *); 130static void sis_stop (struct sis_softc *); 131static void sis_watchdog (struct ifnet *); 132static void sis_shutdown (device_t); 133static int sis_ifmedia_upd (struct ifnet *); 134static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 135 136static u_int16_t sis_reverse (u_int16_t); 137static void sis_delay (struct sis_softc *); 138static void sis_eeprom_idle (struct sis_softc *); 139static void sis_eeprom_putbyte (struct sis_softc *, int); 140static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 141static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 142#ifdef __i386__ 143static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 144 int, int); 145static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 146static device_t sis_find_bridge (device_t); 147#endif 148 149static void sis_mii_sync (struct sis_softc *); 150static void sis_mii_send (struct sis_softc *, u_int32_t, int); 151static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 152static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 153static int sis_miibus_readreg (device_t, int, int); 154static int sis_miibus_writereg (device_t, int, int, int); 155static void sis_miibus_statchg (device_t); 156 157static void sis_setmulti_sis (struct sis_softc *); 158static void sis_setmulti_ns (struct sis_softc *); 159static uint32_t sis_mchash (struct sis_softc *, const uint8_t *); 160static void sis_reset (struct sis_softc *); 161static int sis_list_rx_init (struct sis_softc *); 162static int sis_list_tx_init (struct sis_softc *); 163 164static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 165static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 166static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 167#ifdef SIS_USEIOSPACE 168#define SIS_RES SYS_RES_IOPORT 169#define SIS_RID SIS_PCI_LOIO 170#else 171#define SIS_RES SYS_RES_MEMORY 172#define SIS_RID SIS_PCI_LOMEM 173#endif 174 175static device_method_t sis_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, sis_probe), 178 DEVMETHOD(device_attach, sis_attach), 179 DEVMETHOD(device_detach, sis_detach), 180 DEVMETHOD(device_shutdown, sis_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 188 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 189 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 190 191 { 0, 0 } 192}; 193 194static driver_t sis_driver = { 195 "sis", 196 sis_methods, 197 sizeof(struct sis_softc) 198}; 199 200static devclass_t sis_devclass; 201 202DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 203DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 204 205#define SIS_SETBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, \ 207 CSR_READ_4(sc, reg) | (x)) 208 209#define SIS_CLRBIT(sc, reg, x) \ 210 CSR_WRITE_4(sc, reg, \ 211 CSR_READ_4(sc, reg) & ~(x)) 212 213#define SIO_SET(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 215 216#define SIO_CLR(x) \ 217 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 218 219static void 220sis_dma_map_desc_next(arg, segs, nseg, error) 221 void *arg; 222 bus_dma_segment_t *segs; 223 int nseg, error; 224{ 225 struct sis_desc *r; 226 227 r = arg; 228 r->sis_next = segs->ds_addr; 229 230 return; 231} 232 233static void 234sis_dma_map_desc_ptr(arg, segs, nseg, error) 235 void *arg; 236 bus_dma_segment_t *segs; 237 int nseg, error; 238{ 239 struct sis_desc *r; 240 241 r = arg; 242 r->sis_ptr = segs->ds_addr; 243 244 return; 245} 246 247static void 248sis_dma_map_ring(arg, segs, nseg, error) 249 void *arg; 250 bus_dma_segment_t *segs; 251 int nseg, error; 252{ 253 u_int32_t *p; 254 255 p = arg; 256 *p = segs->ds_addr; 257 258 return; 259} 260 261/* 262 * Routine to reverse the bits in a word. Stolen almost 263 * verbatim from /usr/games/fortune. 264 */ 265static u_int16_t 266sis_reverse(n) 267 u_int16_t n; 268{ 269 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 270 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 271 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 272 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 273 274 return(n); 275} 276 277static void 278sis_delay(sc) 279 struct sis_softc *sc; 280{ 281 int idx; 282 283 for (idx = (300 / 33) + 1; idx > 0; idx--) 284 CSR_READ_4(sc, SIS_CSR); 285 286 return; 287} 288 289static void 290sis_eeprom_idle(sc) 291 struct sis_softc *sc; 292{ 293 register int i; 294 295 SIO_SET(SIS_EECTL_CSEL); 296 sis_delay(sc); 297 SIO_SET(SIS_EECTL_CLK); 298 sis_delay(sc); 299 300 for (i = 0; i < 25; i++) { 301 SIO_CLR(SIS_EECTL_CLK); 302 sis_delay(sc); 303 SIO_SET(SIS_EECTL_CLK); 304 sis_delay(sc); 305 } 306 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_CLR(SIS_EECTL_CSEL); 310 sis_delay(sc); 311 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 312 313 return; 314} 315 316/* 317 * Send a read command and address to the EEPROM, check for ACK. 318 */ 319static void 320sis_eeprom_putbyte(sc, addr) 321 struct sis_softc *sc; 322 int addr; 323{ 324 register int d, i; 325 326 d = addr | SIS_EECMD_READ; 327 328 /* 329 * Feed in each bit and stobe the clock. 330 */ 331 for (i = 0x400; i; i >>= 1) { 332 if (d & i) { 333 SIO_SET(SIS_EECTL_DIN); 334 } else { 335 SIO_CLR(SIS_EECTL_DIN); 336 } 337 sis_delay(sc); 338 SIO_SET(SIS_EECTL_CLK); 339 sis_delay(sc); 340 SIO_CLR(SIS_EECTL_CLK); 341 sis_delay(sc); 342 } 343 344 return; 345} 346 347/* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350static void 351sis_eeprom_getword(sc, addr, dest) 352 struct sis_softc *sc; 353 int addr; 354 u_int16_t *dest; 355{ 356 register int i; 357 u_int16_t word = 0; 358 359 /* Force EEPROM to idle state. */ 360 sis_eeprom_idle(sc); 361 362 /* Enter EEPROM access mode. */ 363 sis_delay(sc); 364 SIO_CLR(SIS_EECTL_CLK); 365 sis_delay(sc); 366 SIO_SET(SIS_EECTL_CSEL); 367 sis_delay(sc); 368 369 /* 370 * Send address of word we want to read. 371 */ 372 sis_eeprom_putbyte(sc, addr); 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 for (i = 0x8000; i; i >>= 1) { 378 SIO_SET(SIS_EECTL_CLK); 379 sis_delay(sc); 380 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 381 word |= i; 382 sis_delay(sc); 383 SIO_CLR(SIS_EECTL_CLK); 384 sis_delay(sc); 385 } 386 387 /* Turn off EEPROM access mode. */ 388 sis_eeprom_idle(sc); 389 390 *dest = word; 391 392 return; 393} 394 395/* 396 * Read a sequence of words from the EEPROM. 397 */ 398static void 399sis_read_eeprom(sc, dest, off, cnt, swap) 400 struct sis_softc *sc; 401 caddr_t dest; 402 int off; 403 int cnt; 404 int swap; 405{ 406 int i; 407 u_int16_t word = 0, *ptr; 408 409 for (i = 0; i < cnt; i++) { 410 sis_eeprom_getword(sc, off + i, &word); 411 ptr = (u_int16_t *)(dest + (i * 2)); 412 if (swap) 413 *ptr = ntohs(word); 414 else 415 *ptr = word; 416 } 417 418 return; 419} 420 421#ifdef __i386__ 422static device_t 423sis_find_bridge(dev) 424 device_t dev; 425{ 426 devclass_t pci_devclass; 427 device_t *pci_devices; 428 int pci_count = 0; 429 device_t *pci_children; 430 int pci_childcount = 0; 431 device_t *busp, *childp; 432 device_t child = NULL; 433 int i, j; 434 435 if ((pci_devclass = devclass_find("pci")) == NULL) 436 return(NULL); 437 438 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 439 440 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 441 pci_childcount = 0; 442 device_get_children(*busp, &pci_children, &pci_childcount); 443 for (j = 0, childp = pci_children; 444 j < pci_childcount; j++, childp++) { 445 if (pci_get_vendor(*childp) == SIS_VENDORID && 446 pci_get_device(*childp) == 0x0008) { 447 child = *childp; 448 goto done; 449 } 450 } 451 } 452 453done: 454 free(pci_devices, M_TEMP); 455 free(pci_children, M_TEMP); 456 return(child); 457} 458 459static void 460sis_read_cmos(sc, dev, dest, off, cnt) 461 struct sis_softc *sc; 462 device_t dev; 463 caddr_t dest; 464 int off; 465 int cnt; 466{ 467 device_t bridge; 468 u_int8_t reg; 469 int i; 470 bus_space_tag_t btag; 471 472 bridge = sis_find_bridge(dev); 473 if (bridge == NULL) 474 return; 475 reg = pci_read_config(bridge, 0x48, 1); 476 pci_write_config(bridge, 0x48, reg|0x40, 1); 477 478 /* XXX */ 479 btag = I386_BUS_SPACE_IO; 480 481 for (i = 0; i < cnt; i++) { 482 bus_space_write_1(btag, 0x0, 0x70, i + off); 483 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 484 } 485 486 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 487 return; 488} 489 490static void 491sis_read_mac(sc, dev, dest) 492 struct sis_softc *sc; 493 device_t dev; 494 caddr_t dest; 495{ 496 u_int32_t filtsave, csrsave; 497 498 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 499 csrsave = CSR_READ_4(sc, SIS_CSR); 500 501 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 502 CSR_WRITE_4(sc, SIS_CSR, 0); 503 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 507 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 509 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 511 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 513 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 514 CSR_WRITE_4(sc, SIS_CSR, csrsave); 515 return; 516} 517#endif 518 519/* 520 * Sync the PHYs by setting data bit and strobing the clock 32 times. 521 */ 522static void sis_mii_sync(sc) 523 struct sis_softc *sc; 524{ 525 register int i; 526 527 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 528 529 for (i = 0; i < 32; i++) { 530 SIO_SET(SIS_MII_CLK); 531 DELAY(1); 532 SIO_CLR(SIS_MII_CLK); 533 DELAY(1); 534 } 535 536 return; 537} 538 539/* 540 * Clock a series of bits through the MII. 541 */ 542static void sis_mii_send(sc, bits, cnt) 543 struct sis_softc *sc; 544 u_int32_t bits; 545 int cnt; 546{ 547 int i; 548 549 SIO_CLR(SIS_MII_CLK); 550 551 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 552 if (bits & i) { 553 SIO_SET(SIS_MII_DATA); 554 } else { 555 SIO_CLR(SIS_MII_DATA); 556 } 557 DELAY(1); 558 SIO_CLR(SIS_MII_CLK); 559 DELAY(1); 560 SIO_SET(SIS_MII_CLK); 561 } 562} 563 564/* 565 * Read an PHY register through the MII. 566 */ 567static int sis_mii_readreg(sc, frame) 568 struct sis_softc *sc; 569 struct sis_mii_frame *frame; 570 571{ 572 int i, ack, s; 573 574 s = splimp(); 575 576 /* 577 * Set up frame for RX. 578 */ 579 frame->mii_stdelim = SIS_MII_STARTDELIM; 580 frame->mii_opcode = SIS_MII_READOP; 581 frame->mii_turnaround = 0; 582 frame->mii_data = 0; 583 584 /* 585 * Turn on data xmit. 586 */ 587 SIO_SET(SIS_MII_DIR); 588 589 sis_mii_sync(sc); 590 591 /* 592 * Send command/address info. 593 */ 594 sis_mii_send(sc, frame->mii_stdelim, 2); 595 sis_mii_send(sc, frame->mii_opcode, 2); 596 sis_mii_send(sc, frame->mii_phyaddr, 5); 597 sis_mii_send(sc, frame->mii_regaddr, 5); 598 599 /* Idle bit */ 600 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 601 DELAY(1); 602 SIO_SET(SIS_MII_CLK); 603 DELAY(1); 604 605 /* Turn off xmit. */ 606 SIO_CLR(SIS_MII_DIR); 607 608 /* Check for ack */ 609 SIO_CLR(SIS_MII_CLK); 610 DELAY(1); 611 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 612 SIO_SET(SIS_MII_CLK); 613 DELAY(1); 614 615 /* 616 * Now try reading data bits. If the ack failed, we still 617 * need to clock through 16 cycles to keep the PHY(s) in sync. 618 */ 619 if (ack) { 620 for(i = 0; i < 16; i++) { 621 SIO_CLR(SIS_MII_CLK); 622 DELAY(1); 623 SIO_SET(SIS_MII_CLK); 624 DELAY(1); 625 } 626 goto fail; 627 } 628 629 for (i = 0x8000; i; i >>= 1) { 630 SIO_CLR(SIS_MII_CLK); 631 DELAY(1); 632 if (!ack) { 633 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 634 frame->mii_data |= i; 635 DELAY(1); 636 } 637 SIO_SET(SIS_MII_CLK); 638 DELAY(1); 639 } 640 641fail: 642 643 SIO_CLR(SIS_MII_CLK); 644 DELAY(1); 645 SIO_SET(SIS_MII_CLK); 646 DELAY(1); 647 648 splx(s); 649 650 if (ack) 651 return(1); 652 return(0); 653} 654 655/* 656 * Write to a PHY register through the MII. 657 */ 658static int sis_mii_writereg(sc, frame) 659 struct sis_softc *sc; 660 struct sis_mii_frame *frame; 661 662{ 663 int s; 664 665 s = splimp(); 666 /* 667 * Set up frame for TX. 668 */ 669 670 frame->mii_stdelim = SIS_MII_STARTDELIM; 671 frame->mii_opcode = SIS_MII_WRITEOP; 672 frame->mii_turnaround = SIS_MII_TURNAROUND; 673 674 /* 675 * Turn on data output. 676 */ 677 SIO_SET(SIS_MII_DIR); 678 679 sis_mii_sync(sc); 680 681 sis_mii_send(sc, frame->mii_stdelim, 2); 682 sis_mii_send(sc, frame->mii_opcode, 2); 683 sis_mii_send(sc, frame->mii_phyaddr, 5); 684 sis_mii_send(sc, frame->mii_regaddr, 5); 685 sis_mii_send(sc, frame->mii_turnaround, 2); 686 sis_mii_send(sc, frame->mii_data, 16); 687 688 /* Idle bit. */ 689 SIO_SET(SIS_MII_CLK); 690 DELAY(1); 691 SIO_CLR(SIS_MII_CLK); 692 DELAY(1); 693 694 /* 695 * Turn off xmit. 696 */ 697 SIO_CLR(SIS_MII_DIR); 698 699 splx(s); 700 701 return(0); 702} 703 704static int 705sis_miibus_readreg(dev, phy, reg) 706 device_t dev; 707 int phy, reg; 708{ 709 struct sis_softc *sc; 710 struct sis_mii_frame frame; 711 712 sc = device_get_softc(dev); 713 714 if (sc->sis_type == SIS_TYPE_83815) { 715 if (phy != 0) 716 return(0); 717 /* 718 * The NatSemi chip can take a while after 719 * a reset to come ready, during which the BMSR 720 * returns a value of 0. This is *never* supposed 721 * to happen: some of the BMSR bits are meant to 722 * be hardwired in the on position, and this can 723 * confuse the miibus code a bit during the probe 724 * and attach phase. So we make an effort to check 725 * for this condition and wait for it to clear. 726 */ 727 if (!CSR_READ_4(sc, NS_BMSR)) 728 DELAY(1000); 729 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 730 } 731 732 /* 733 * Chipsets < SIS_635 seem not to be able to read/write 734 * through mdio. Use the enhanced PHY access register 735 * again for them. 736 */ 737 if (sc->sis_type == SIS_TYPE_900 && 738 sc->sis_rev < SIS_REV_635) { 739 int i, val = 0; 740 741 if (phy != 0) 742 return(0); 743 744 CSR_WRITE_4(sc, SIS_PHYCTL, 745 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 746 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 747 748 for (i = 0; i < SIS_TIMEOUT; i++) { 749 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 750 break; 751 } 752 753 if (i == SIS_TIMEOUT) { 754 printf("sis%d: PHY failed to come ready\n", 755 sc->sis_unit); 756 return(0); 757 } 758 759 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 760 761 if (val == 0xFFFF) 762 return(0); 763 764 return(val); 765 } else { 766 bzero((char *)&frame, sizeof(frame)); 767 768 frame.mii_phyaddr = phy; 769 frame.mii_regaddr = reg; 770 sis_mii_readreg(sc, &frame); 771 772 return(frame.mii_data); 773 } 774} 775 776static int 777sis_miibus_writereg(dev, phy, reg, data) 778 device_t dev; 779 int phy, reg, data; 780{ 781 struct sis_softc *sc; 782 struct sis_mii_frame frame; 783 784 sc = device_get_softc(dev); 785 786 if (sc->sis_type == SIS_TYPE_83815) { 787 if (phy != 0) 788 return(0); 789 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 790 return(0); 791 } 792 793 /* 794 * Chipsets < SIS_635 seem not to be able to read/write 795 * through mdio. Use the enhanced PHY access register 796 * again for them. 797 */ 798 if (sc->sis_type == SIS_TYPE_900 && 799 sc->sis_rev < SIS_REV_635) { 800 int i; 801 802 if (phy != 0) 803 return(0); 804 805 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 806 (reg << 6) | SIS_PHYOP_WRITE); 807 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 808 809 for (i = 0; i < SIS_TIMEOUT; i++) { 810 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 811 break; 812 } 813 814 if (i == SIS_TIMEOUT) 815 printf("sis%d: PHY failed to come ready\n", 816 sc->sis_unit); 817 } else { 818 bzero((char *)&frame, sizeof(frame)); 819 820 frame.mii_phyaddr = phy; 821 frame.mii_regaddr = reg; 822 frame.mii_data = data; 823 sis_mii_writereg(sc, &frame); 824 } 825 return(0); 826} 827 828static void 829sis_miibus_statchg(dev) 830 device_t dev; 831{ 832 struct sis_softc *sc; 833 834 sc = device_get_softc(dev); 835 sis_init(sc); 836 837 return; 838} 839 840static u_int32_t 841sis_mchash(sc, addr) 842 struct sis_softc *sc; 843 const uint8_t *addr; 844{ 845 uint32_t crc; 846 847 /* Compute CRC for the address value. */ 848 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 849 850 /* 851 * return the filter bit position 852 * 853 * The NatSemi chip has a 512-bit filter, which is 854 * different than the SiS, so we special-case it. 855 */ 856 if (sc->sis_type == SIS_TYPE_83815) 857 return (crc >> 23); 858 else if (sc->sis_rev >= SIS_REV_635 || 859 sc->sis_rev == SIS_REV_900B) 860 return (crc >> 24); 861 else 862 return (crc >> 25); 863} 864 865static void 866sis_setmulti_ns(sc) 867 struct sis_softc *sc; 868{ 869 struct ifnet *ifp; 870 struct ifmultiaddr *ifma; 871 u_int32_t h = 0, i, filtsave; 872 int bit, index; 873 874 ifp = &sc->arpcom.ac_if; 875 876 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 877 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 878 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 879 return; 880 } 881 882 /* 883 * We have to explicitly enable the multicast hash table 884 * on the NatSemi chip if we want to use it, which we do. 885 */ 886 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 887 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 888 889 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 890 891 /* first, zot all the existing hash bits */ 892 for (i = 0; i < 32; i++) { 893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 894 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 895 } 896 897 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 898 if (ifma->ifma_addr->sa_family != AF_LINK) 899 continue; 900 h = sis_mchash(sc, 901 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 902 index = h >> 3; 903 bit = h & 0x1F; 904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 905 if (bit > 0xF) 906 bit -= 0x10; 907 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 908 } 909 910 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 911 912 return; 913} 914 915static void 916sis_setmulti_sis(sc) 917 struct sis_softc *sc; 918{ 919 struct ifnet *ifp; 920 struct ifmultiaddr *ifma; 921 u_int32_t h, i, n, ctl; 922 u_int16_t hashes[16]; 923 924 ifp = &sc->arpcom.ac_if; 925 926 /* hash table size */ 927 if (sc->sis_rev >= SIS_REV_635 || 928 sc->sis_rev == SIS_REV_900B) 929 n = 16; 930 else 931 n = 8; 932 933 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 934 935 if (ifp->if_flags & IFF_BROADCAST) 936 ctl |= SIS_RXFILTCTL_BROAD; 937 938 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 939 ctl |= SIS_RXFILTCTL_ALLMULTI; 940 if (ifp->if_flags & IFF_PROMISC) 941 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 942 for (i = 0; i < n; i++) 943 hashes[i] = ~0; 944 } else { 945 for (i = 0; i < n; i++) 946 hashes[i] = 0; 947 i = 0; 948 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 949 if (ifma->ifma_addr->sa_family != AF_LINK) 950 continue; 951 h = sis_mchash(sc, 952 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 953 hashes[h >> 4] |= 1 << (h & 0xf); 954 i++; 955 } 956 if (i > n) { 957 ctl |= SIS_RXFILTCTL_ALLMULTI; 958 for (i = 0; i < n; i++) 959 hashes[i] = ~0; 960 } 961 } 962 963 for (i = 0; i < n; i++) { 964 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 965 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 966 } 967 968 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 969} 970 971static void 972sis_reset(sc) 973 struct sis_softc *sc; 974{ 975 register int i; 976 977 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 978 979 for (i = 0; i < SIS_TIMEOUT; i++) { 980 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 981 break; 982 } 983 984 if (i == SIS_TIMEOUT) 985 printf("sis%d: reset never completed\n", sc->sis_unit); 986 987 /* Wait a little while for the chip to get its brains in order. */ 988 DELAY(1000); 989 990 /* 991 * If this is a NetSemi chip, make sure to clear 992 * PME mode. 993 */ 994 if (sc->sis_type == SIS_TYPE_83815) { 995 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 996 CSR_WRITE_4(sc, NS_CLKRUN, 0); 997 } 998 999 return; 1000} 1001 1002/* 1003 * Probe for an SiS chip. Check the PCI vendor and device 1004 * IDs against our list and return a device name if we find a match. 1005 */ 1006static int 1007sis_probe(dev) 1008 device_t dev; 1009{ 1010 struct sis_type *t; 1011 1012 t = sis_devs; 1013 1014 while(t->sis_name != NULL) { 1015 if ((pci_get_vendor(dev) == t->sis_vid) && 1016 (pci_get_device(dev) == t->sis_did)) { 1017 device_set_desc(dev, t->sis_name); 1018 return(0); 1019 } 1020 t++; 1021 } 1022 1023 return(ENXIO); 1024} 1025 1026/* 1027 * Attach the interface. Allocate softc structures, do ifmedia 1028 * setup and ethernet/BPF attach. 1029 */ 1030static int 1031sis_attach(dev) 1032 device_t dev; 1033{ 1034 u_char eaddr[ETHER_ADDR_LEN]; 1035 struct sis_softc *sc; 1036 struct ifnet *ifp; 1037 int unit, error = 0, rid, waittime = 0; 1038 1039 waittime = 0; 1040 sc = device_get_softc(dev); 1041 unit = device_get_unit(dev); 1042 1043 sc->sis_self = dev; 1044 1045 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1046 MTX_DEF | MTX_RECURSE); 1047 1048 if (pci_get_device(dev) == SIS_DEVICEID_900) 1049 sc->sis_type = SIS_TYPE_900; 1050 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1051 sc->sis_type = SIS_TYPE_7016; 1052 if (pci_get_vendor(dev) == NS_VENDORID) 1053 sc->sis_type = SIS_TYPE_83815; 1054 1055 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1056 /* 1057 * Map control/status registers. 1058 */ 1059 pci_enable_busmaster(dev); 1060 1061 rid = SIS_RID; 1062 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1063 1064 if (sc->sis_res == NULL) { 1065 printf("sis%d: couldn't map ports/memory\n", unit); 1066 error = ENXIO; 1067 goto fail; 1068 } 1069 1070 sc->sis_btag = rman_get_bustag(sc->sis_res); 1071 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1072 1073 /* Allocate interrupt */ 1074 rid = 0; 1075 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1076 RF_SHAREABLE | RF_ACTIVE); 1077 1078 if (sc->sis_irq == NULL) { 1079 printf("sis%d: couldn't map interrupt\n", unit); 1080 error = ENXIO; 1081 goto fail; 1082 } 1083 1084 /* Reset the adapter. */ 1085 sis_reset(sc); 1086 1087 if (sc->sis_type == SIS_TYPE_900 && 1088 (sc->sis_rev == SIS_REV_635 || 1089 sc->sis_rev == SIS_REV_900B)) { 1090 SIO_SET(SIS_CFG_RND_CNT); 1091 SIO_SET(SIS_CFG_PERR_DETECT); 1092 } 1093 1094 /* 1095 * Get station address from the EEPROM. 1096 */ 1097 switch (pci_get_vendor(dev)) { 1098 case NS_VENDORID: 1099 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1100 1101 /* We can't update the device description, so spew */ 1102 if (sc->sis_srr == NS_SRR_15C) 1103 device_printf(dev, "Silicon Revision: DP83815C\n"); 1104 else if (sc->sis_srr == NS_SRR_15D) 1105 device_printf(dev, "Silicon Revision: DP83815D\n"); 1106 else if (sc->sis_srr == NS_SRR_16A) 1107 device_printf(dev, "Silicon Revision: DP83816A\n"); 1108 else 1109 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1110 1111 /* 1112 * Reading the MAC address out of the EEPROM on 1113 * the NatSemi chip takes a bit more work than 1114 * you'd expect. The address spans 4 16-bit words, 1115 * with the first word containing only a single bit. 1116 * You have to shift everything over one bit to 1117 * get it aligned properly. Also, the bits are 1118 * stored backwards (the LSB is really the MSB, 1119 * and so on) so you have to reverse them in order 1120 * to get the MAC address into the form we want. 1121 * Why? Who the hell knows. 1122 */ 1123 { 1124 u_int16_t tmp[4]; 1125 1126 sis_read_eeprom(sc, (caddr_t)&tmp, 1127 NS_EE_NODEADDR, 4, 0); 1128 1129 /* Shift everything over one bit. */ 1130 tmp[3] = tmp[3] >> 1; 1131 tmp[3] |= tmp[2] << 15; 1132 tmp[2] = tmp[2] >> 1; 1133 tmp[2] |= tmp[1] << 15; 1134 tmp[1] = tmp[1] >> 1; 1135 tmp[1] |= tmp[0] << 15; 1136 1137 /* Now reverse all the bits. */ 1138 tmp[3] = sis_reverse(tmp[3]); 1139 tmp[2] = sis_reverse(tmp[2]); 1140 tmp[1] = sis_reverse(tmp[1]); 1141 1142 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1143 } 1144 break; 1145 case SIS_VENDORID: 1146 default: 1147#ifdef __i386__ 1148 /* 1149 * If this is a SiS 630E chipset with an embedded 1150 * SiS 900 controller, we have to read the MAC address 1151 * from the APC CMOS RAM. Our method for doing this 1152 * is very ugly since we have to reach out and grab 1153 * ahold of hardware for which we cannot properly 1154 * allocate resources. This code is only compiled on 1155 * the i386 architecture since the SiS 630E chipset 1156 * is for x86 motherboards only. Note that there are 1157 * a lot of magic numbers in this hack. These are 1158 * taken from SiS's Linux driver. I'd like to replace 1159 * them with proper symbolic definitions, but that 1160 * requires some datasheets that I don't have access 1161 * to at the moment. 1162 */ 1163 if (sc->sis_rev == SIS_REV_630S || 1164 sc->sis_rev == SIS_REV_630E || 1165 sc->sis_rev == SIS_REV_630EA1) 1166 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1167 1168 else if (sc->sis_rev == SIS_REV_635 || 1169 sc->sis_rev == SIS_REV_630ET) 1170 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1171 else if (sc->sis_rev == SIS_REV_96x) { 1172 /* Allow to read EEPROM from LAN. It is shared 1173 * between a 1394 controller and the NIC and each 1174 * time we access it, we need to set SIS_EECMD_REQ. 1175 */ 1176 SIO_SET(SIS_EECMD_REQ); 1177 for (waittime = 0; waittime < SIS_TIMEOUT; 1178 waittime++) { 1179 /* Force EEPROM to idle state. */ 1180 sis_eeprom_idle(sc); 1181 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1182 sis_read_eeprom(sc, (caddr_t)&eaddr, 1183 SIS_EE_NODEADDR, 3, 0); 1184 break; 1185 } 1186 DELAY(1); 1187 } 1188 /* 1189 * Set SIS_EECTL_CLK to high, so a other master 1190 * can operate on the i2c bus. 1191 */ 1192 SIO_SET(SIS_EECTL_CLK); 1193 /* Refuse EEPROM access by LAN */ 1194 SIO_SET(SIS_EECMD_DONE); 1195 } else 1196#endif 1197 sis_read_eeprom(sc, (caddr_t)&eaddr, 1198 SIS_EE_NODEADDR, 3, 0); 1199 break; 1200 } 1201 1202 sc->sis_unit = unit; 1203 if (debug_mpsafenet) 1204 callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1205 else 1206 callout_init(&sc->sis_stat_ch, 0); 1207 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1208 1209 /* 1210 * Allocate the parent bus DMA tag appropriate for PCI. 1211 */ 1212#define SIS_NSEG_NEW 32 1213 error = bus_dma_tag_create(NULL, /* parent */ 1214 1, 0, /* alignment, boundary */ 1215 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1216 BUS_SPACE_MAXADDR, /* highaddr */ 1217 NULL, NULL, /* filter, filterarg */ 1218 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1219 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1220 BUS_DMA_ALLOCNOW, /* flags */ 1221 NULL, NULL, /* lockfunc, lockarg */ 1222 &sc->sis_parent_tag); 1223 if (error) 1224 goto fail; 1225 1226 /* 1227 * Now allocate a tag for the DMA descriptor lists and a chunk 1228 * of DMA-able memory based on the tag. Also obtain the physical 1229 * addresses of the RX and TX ring, which we'll need later. 1230 * All of our lists are allocated as a contiguous block 1231 * of memory. 1232 */ 1233 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1234 1, 0, /* alignment, boundary */ 1235 BUS_SPACE_MAXADDR, /* lowaddr */ 1236 BUS_SPACE_MAXADDR, /* highaddr */ 1237 NULL, NULL, /* filter, filterarg */ 1238 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1239 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1240 0, /* flags */ 1241 busdma_lock_mutex, /* lockfunc */ 1242 &Giant, /* lockarg */ 1243 &sc->sis_ldata.sis_rx_tag); 1244 if (error) 1245 goto fail; 1246 1247 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1248 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1249 &sc->sis_ldata.sis_rx_dmamap); 1250 1251 if (error) { 1252 printf("sis%d: no memory for rx list buffers!\n", unit); 1253 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1254 sc->sis_ldata.sis_rx_tag = NULL; 1255 goto fail; 1256 } 1257 1258 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1259 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1260 sizeof(struct sis_desc), sis_dma_map_ring, 1261 &sc->sis_cdata.sis_rx_paddr, 0); 1262 1263 if (error) { 1264 printf("sis%d: cannot get address of the rx ring!\n", unit); 1265 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1266 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1267 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1268 sc->sis_ldata.sis_rx_tag = NULL; 1269 goto fail; 1270 } 1271 1272 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1273 1, 0, /* alignment, boundary */ 1274 BUS_SPACE_MAXADDR, /* lowaddr */ 1275 BUS_SPACE_MAXADDR, /* highaddr */ 1276 NULL, NULL, /* filter, filterarg */ 1277 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1278 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1279 0, /* flags */ 1280 busdma_lock_mutex, /* lockfunc */ 1281 &Giant, /* lockarg */ 1282 &sc->sis_ldata.sis_tx_tag); 1283 if (error) 1284 goto fail; 1285 1286 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1287 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1288 &sc->sis_ldata.sis_tx_dmamap); 1289 1290 if (error) { 1291 printf("sis%d: no memory for tx list buffers!\n", unit); 1292 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1293 sc->sis_ldata.sis_tx_tag = NULL; 1294 goto fail; 1295 } 1296 1297 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1298 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1299 sizeof(struct sis_desc), sis_dma_map_ring, 1300 &sc->sis_cdata.sis_tx_paddr, 0); 1301 1302 if (error) { 1303 printf("sis%d: cannot get address of the tx ring!\n", unit); 1304 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1305 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1306 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1307 sc->sis_ldata.sis_tx_tag = NULL; 1308 goto fail; 1309 } 1310 1311 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1312 1, 0, /* alignment, boundary */ 1313 BUS_SPACE_MAXADDR, /* lowaddr */ 1314 BUS_SPACE_MAXADDR, /* highaddr */ 1315 NULL, NULL, /* filter, filterarg */ 1316 MCLBYTES, 1, /* maxsize,nsegments */ 1317 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1318 0, /* flags */ 1319 busdma_lock_mutex, /* lockfunc */ 1320 &Giant, /* lockarg */ 1321 &sc->sis_tag); 1322 if (error) 1323 goto fail; 1324 1325 /* 1326 * Obtain the physical addresses of the RX and TX 1327 * rings which we'll need later in the init routine. 1328 */ 1329 1330 ifp = &sc->arpcom.ac_if; 1331 ifp->if_softc = sc; 1332 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1333 ifp->if_mtu = ETHERMTU; 1334 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1335 ifp->if_ioctl = sis_ioctl; 1336 ifp->if_start = sis_start; 1337 ifp->if_watchdog = sis_watchdog; 1338 ifp->if_init = sis_init; 1339 ifp->if_baudrate = 10000000; 1340 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1341 1342 /* 1343 * Do MII setup. 1344 */ 1345 if (mii_phy_probe(dev, &sc->sis_miibus, 1346 sis_ifmedia_upd, sis_ifmedia_sts)) { 1347 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1348 error = ENXIO; 1349 goto fail; 1350 } 1351 1352 /* 1353 * Call MI attach routine. 1354 */ 1355 ether_ifattach(ifp, eaddr); 1356 1357 /* 1358 * Tell the upper layer(s) we support long frames. 1359 */ 1360 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1361 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1362 1363#ifdef DEVICE_POLLING 1364 ifp->if_capabilities |= IFCAP_POLLING; 1365#endif 1366 ifp->if_capenable = ifp->if_capabilities; 1367 1368 /* Hook interrupt last to avoid having to lock softc */ 1369 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1370 sis_intr, sc, &sc->sis_intrhand); 1371 1372 if (error) { 1373 printf("sis%d: couldn't set up irq\n", unit); 1374 ether_ifdetach(ifp); 1375 goto fail; 1376 } 1377 1378fail: 1379 if (error) 1380 sis_detach(dev); 1381 1382 return(error); 1383} 1384 1385/* 1386 * Shutdown hardware and free up resources. This can be called any 1387 * time after the mutex has been initialized. It is called in both 1388 * the error case in attach and the normal detach case so it needs 1389 * to be careful about only freeing resources that have actually been 1390 * allocated. 1391 */ 1392static int 1393sis_detach(dev) 1394 device_t dev; 1395{ 1396 struct sis_softc *sc; 1397 struct ifnet *ifp; 1398 1399 sc = device_get_softc(dev); 1400 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1401 SIS_LOCK(sc); 1402 ifp = &sc->arpcom.ac_if; 1403 1404 /* These should only be active if attach succeeded. */ 1405 if (device_is_attached(dev)) { 1406 sis_reset(sc); 1407 sis_stop(sc); 1408 ether_ifdetach(ifp); 1409 } 1410 if (sc->sis_miibus) 1411 device_delete_child(dev, sc->sis_miibus); 1412 bus_generic_detach(dev); 1413 1414 if (sc->sis_intrhand) 1415 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1416 if (sc->sis_irq) 1417 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1418 if (sc->sis_res) 1419 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1420 1421 if (sc->sis_ldata.sis_rx_tag) { 1422 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1423 sc->sis_ldata.sis_rx_dmamap); 1424 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1425 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1426 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1427 } 1428 if (sc->sis_ldata.sis_tx_tag) { 1429 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1430 sc->sis_ldata.sis_tx_dmamap); 1431 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1432 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1433 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1434 } 1435 if (sc->sis_parent_tag) 1436 bus_dma_tag_destroy(sc->sis_parent_tag); 1437 if (sc->sis_tag) 1438 bus_dma_tag_destroy(sc->sis_tag); 1439 1440 SIS_UNLOCK(sc); 1441 mtx_destroy(&sc->sis_mtx); 1442 1443 return(0); 1444} 1445 1446/* 1447 * Initialize the transmit descriptors. 1448 */ 1449static int 1450sis_list_tx_init(sc) 1451 struct sis_softc *sc; 1452{ 1453 struct sis_list_data *ld; 1454 struct sis_ring_data *cd; 1455 int i, nexti; 1456 1457 cd = &sc->sis_cdata; 1458 ld = &sc->sis_ldata; 1459 1460 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1461 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1462 ld->sis_tx_list[i].sis_nextdesc = 1463 &ld->sis_tx_list[nexti]; 1464 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1465 sc->sis_ldata.sis_tx_dmamap, 1466 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1467 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1468 ld->sis_tx_list[i].sis_mbuf = NULL; 1469 ld->sis_tx_list[i].sis_ptr = 0; 1470 ld->sis_tx_list[i].sis_ctl = 0; 1471 } 1472 1473 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1474 1475 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1476 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1477 1478 return(0); 1479} 1480 1481/* 1482 * Initialize the RX descriptors and allocate mbufs for them. Note that 1483 * we arrange the descriptors in a closed ring, so that the last descriptor 1484 * points back to the first. 1485 */ 1486static int 1487sis_list_rx_init(sc) 1488 struct sis_softc *sc; 1489{ 1490 struct sis_list_data *ld; 1491 struct sis_ring_data *cd; 1492 int i,nexti; 1493 1494 ld = &sc->sis_ldata; 1495 cd = &sc->sis_cdata; 1496 1497 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1498 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1499 return(ENOBUFS); 1500 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1501 ld->sis_rx_list[i].sis_nextdesc = 1502 &ld->sis_rx_list[nexti]; 1503 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1504 sc->sis_ldata.sis_rx_dmamap, 1505 &ld->sis_rx_list[nexti], 1506 sizeof(struct sis_desc), sis_dma_map_desc_next, 1507 &ld->sis_rx_list[i], 0); 1508 } 1509 1510 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1511 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1512 1513 cd->sis_rx_prod = 0; 1514 1515 return(0); 1516} 1517 1518/* 1519 * Initialize an RX descriptor and attach an MBUF cluster. 1520 */ 1521static int 1522sis_newbuf(sc, c, m) 1523 struct sis_softc *sc; 1524 struct sis_desc *c; 1525 struct mbuf *m; 1526{ 1527 1528 if (c == NULL) 1529 return(EINVAL); 1530 1531 if (m == NULL) { 1532 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1533 if (m == NULL) 1534 return(ENOBUFS); 1535 } else 1536 m->m_data = m->m_ext.ext_buf; 1537 1538 c->sis_mbuf = m; 1539 c->sis_ctl = SIS_RXLEN; 1540 1541 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1542 bus_dmamap_load(sc->sis_tag, c->sis_map, 1543 mtod(m, void *), MCLBYTES, 1544 sis_dma_map_desc_ptr, c, 0); 1545 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1546 1547 return(0); 1548} 1549 1550/* 1551 * A frame has been uploaded: pass the resulting mbuf chain up to 1552 * the higher level protocols. 1553 */ 1554static void 1555sis_rxeof(sc) 1556 struct sis_softc *sc; 1557{ 1558 struct mbuf *m; 1559 struct ifnet *ifp; 1560 struct sis_desc *cur_rx; 1561 int i, total_len = 0; 1562 u_int32_t rxstat; 1563 1564 SIS_LOCK_ASSERT(sc); 1565 1566 ifp = &sc->arpcom.ac_if; 1567 i = sc->sis_cdata.sis_rx_prod; 1568 1569 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1570 1571#ifdef DEVICE_POLLING 1572 if (ifp->if_flags & IFF_POLLING) { 1573 if (sc->rxcycles <= 0) 1574 break; 1575 sc->rxcycles--; 1576 } 1577#endif /* DEVICE_POLLING */ 1578 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1579 rxstat = cur_rx->sis_rxstat; 1580 bus_dmamap_sync(sc->sis_tag, 1581 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1582 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1583 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1584 m = cur_rx->sis_mbuf; 1585 cur_rx->sis_mbuf = NULL; 1586 total_len = SIS_RXBYTES(cur_rx); 1587 SIS_INC(i, SIS_RX_LIST_CNT); 1588 1589 /* 1590 * If an error occurs, update stats, clear the 1591 * status word and leave the mbuf cluster in place: 1592 * it should simply get re-used next time this descriptor 1593 * comes up in the ring. 1594 */ 1595 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1596 ifp->if_ierrors++; 1597 if (rxstat & SIS_RXSTAT_COLL) 1598 ifp->if_collisions++; 1599 sis_newbuf(sc, cur_rx, m); 1600 continue; 1601 } 1602 1603 /* No errors; receive the packet. */ 1604#ifdef __i386__ 1605 /* 1606 * On the x86 we do not have alignment problems, so try to 1607 * allocate a new buffer for the receive ring, and pass up 1608 * the one where the packet is already, saving the expensive 1609 * copy done in m_devget(). 1610 * If we are on an architecture with alignment problems, or 1611 * if the allocation fails, then use m_devget and leave the 1612 * existing buffer in the receive ring. 1613 */ 1614 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1615 m->m_pkthdr.len = m->m_len = total_len; 1616 else 1617#endif 1618 { 1619 struct mbuf *m0; 1620 m0 = m_devget(mtod(m, char *), total_len, 1621 ETHER_ALIGN, ifp, NULL); 1622 sis_newbuf(sc, cur_rx, m); 1623 if (m0 == NULL) { 1624 ifp->if_ierrors++; 1625 continue; 1626 } 1627 m = m0; 1628 } 1629 1630 ifp->if_ipackets++; 1631 m->m_pkthdr.rcvif = ifp; 1632 1633 SIS_UNLOCK(sc); 1634 (*ifp->if_input)(ifp, m); 1635 SIS_LOCK(sc); 1636 } 1637 1638 sc->sis_cdata.sis_rx_prod = i; 1639 1640 return; 1641} 1642 1643static void 1644sis_rxeoc(sc) 1645 struct sis_softc *sc; 1646{ 1647 sis_rxeof(sc); 1648 sis_init(sc); 1649 return; 1650} 1651 1652/* 1653 * A frame was downloaded to the chip. It's safe for us to clean up 1654 * the list buffers. 1655 */ 1656 1657static void 1658sis_txeof(sc) 1659 struct sis_softc *sc; 1660{ 1661 struct ifnet *ifp; 1662 u_int32_t idx; 1663 1664 ifp = &sc->arpcom.ac_if; 1665 1666 /* 1667 * Go through our tx list and free mbufs for those 1668 * frames that have been transmitted. 1669 */ 1670 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1671 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1672 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1673 1674 if (SIS_OWNDESC(cur_tx)) 1675 break; 1676 1677 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1678 continue; 1679 1680 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1681 ifp->if_oerrors++; 1682 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1683 ifp->if_collisions++; 1684 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1685 ifp->if_collisions++; 1686 } 1687 1688 ifp->if_collisions += 1689 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1690 1691 ifp->if_opackets++; 1692 if (cur_tx->sis_mbuf != NULL) { 1693 m_freem(cur_tx->sis_mbuf); 1694 cur_tx->sis_mbuf = NULL; 1695 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1696 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1697 } 1698 } 1699 1700 if (idx != sc->sis_cdata.sis_tx_cons) { 1701 /* we freed up some buffers */ 1702 sc->sis_cdata.sis_tx_cons = idx; 1703 ifp->if_flags &= ~IFF_OACTIVE; 1704 } 1705 1706 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1707 1708 return; 1709} 1710 1711static void 1712sis_tick(xsc) 1713 void *xsc; 1714{ 1715 struct sis_softc *sc; 1716 struct mii_data *mii; 1717 struct ifnet *ifp; 1718 1719 sc = xsc; 1720 SIS_LOCK(sc); 1721 sc->in_tick = 1; 1722 ifp = &sc->arpcom.ac_if; 1723 1724 mii = device_get_softc(sc->sis_miibus); 1725 mii_tick(mii); 1726 1727 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1728 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1729 sc->sis_link++; 1730 if (ifp->if_snd.ifq_head != NULL) 1731 sis_start(ifp); 1732 } 1733 1734 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1735 sc->in_tick = 0; 1736 SIS_UNLOCK(sc); 1737 1738 return; 1739} 1740 1741#ifdef DEVICE_POLLING 1742static poll_handler_t sis_poll; 1743 1744static void 1745sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1746{ 1747 struct sis_softc *sc = ifp->if_softc; 1748 1749 SIS_LOCK(sc); 1750 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1751 ether_poll_deregister(ifp); 1752 cmd = POLL_DEREGISTER; 1753 } 1754 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1755 CSR_WRITE_4(sc, SIS_IER, 1); 1756 goto done; 1757 } 1758 1759 /* 1760 * On the sis, reading the status register also clears it. 1761 * So before returning to intr mode we must make sure that all 1762 * possible pending sources of interrupts have been served. 1763 * In practice this means run to completion the *eof routines, 1764 * and then call the interrupt routine 1765 */ 1766 sc->rxcycles = count; 1767 sis_rxeof(sc); 1768 sis_txeof(sc); 1769 if (ifp->if_snd.ifq_head != NULL) 1770 sis_start(ifp); 1771 1772 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1773 u_int32_t status; 1774 1775 /* Reading the ISR register clears all interrupts. */ 1776 status = CSR_READ_4(sc, SIS_ISR); 1777 1778 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1779 sis_rxeoc(sc); 1780 1781 if (status & (SIS_ISR_RX_IDLE)) 1782 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1783 1784 if (status & SIS_ISR_SYSERR) { 1785 sis_reset(sc); 1786 sis_init(sc); 1787 } 1788 } 1789done: 1790 SIS_UNLOCK(sc); 1791 return; 1792} 1793#endif /* DEVICE_POLLING */ 1794 1795static void 1796sis_intr(arg) 1797 void *arg; 1798{ 1799 struct sis_softc *sc; 1800 struct ifnet *ifp; 1801 u_int32_t status; 1802 1803 sc = arg; 1804 ifp = &sc->arpcom.ac_if; 1805 1806 SIS_LOCK(sc); 1807#ifdef DEVICE_POLLING 1808 if (ifp->if_flags & IFF_POLLING) 1809 goto done; 1810 if ((ifp->if_capenable & IFCAP_POLLING) && 1811 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1812 CSR_WRITE_4(sc, SIS_IER, 0); 1813 goto done; 1814 } 1815#endif /* DEVICE_POLLING */ 1816 1817 /* Supress unwanted interrupts */ 1818 if (!(ifp->if_flags & IFF_UP)) { 1819 sis_stop(sc); 1820 goto done; 1821 } 1822 1823 /* Disable interrupts. */ 1824 CSR_WRITE_4(sc, SIS_IER, 0); 1825 1826 for (;;) { 1827 /* Reading the ISR register clears all interrupts. */ 1828 status = CSR_READ_4(sc, SIS_ISR); 1829 1830 if ((status & SIS_INTRS) == 0) 1831 break; 1832 1833 if (status & 1834 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1835 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1836 sis_txeof(sc); 1837 1838 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1839 sis_rxeof(sc); 1840 1841 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1842 sis_rxeoc(sc); 1843 1844 if (status & (SIS_ISR_RX_IDLE)) 1845 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1846 1847 if (status & SIS_ISR_SYSERR) { 1848 sis_reset(sc); 1849 sis_init(sc); 1850 } 1851 } 1852 1853 /* Re-enable interrupts. */ 1854 CSR_WRITE_4(sc, SIS_IER, 1); 1855 1856 if (ifp->if_snd.ifq_head != NULL) 1857 sis_start(ifp); 1858done: 1859 SIS_UNLOCK(sc); 1860 1861 return; 1862} 1863 1864/* 1865 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1866 * pointers to the fragment pointers. 1867 */ 1868static int 1869sis_encap(sc, m_head, txidx) 1870 struct sis_softc *sc; 1871 struct mbuf **m_head; 1872 u_int32_t *txidx; 1873{ 1874 struct sis_desc *f = NULL; 1875 struct mbuf *m; 1876 int frag, cur, cnt = 0, chainlen = 0; 1877 1878 /* 1879 * If there's no way we can send any packets, return now. 1880 */ 1881 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1882 return (ENOBUFS); 1883 1884 /* 1885 * Count the number of frags in this chain to see if 1886 * we need to m_defrag. Since the descriptor list is shared 1887 * by all packets, we'll m_defrag long chains so that they 1888 * do not use up the entire list, even if they would fit. 1889 */ 1890 1891 for (m = *m_head; m != NULL; m = m->m_next) 1892 chainlen++; 1893 1894 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1895 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1896 m = m_defrag(*m_head, M_DONTWAIT); 1897 if (m == NULL) 1898 return (ENOBUFS); 1899 *m_head = m; 1900 } 1901 1902 /* 1903 * Start packing the mbufs in this chain into 1904 * the fragment pointers. Stop when we run out 1905 * of fragments or hit the end of the mbuf chain. 1906 */ 1907 cur = frag = *txidx; 1908 1909 for (m = *m_head; m != NULL; m = m->m_next) { 1910 if (m->m_len != 0) { 1911 if ((SIS_TX_LIST_CNT - 1912 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1913 return(ENOBUFS); 1914 f = &sc->sis_ldata.sis_tx_list[frag]; 1915 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1916 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1917 bus_dmamap_load(sc->sis_tag, f->sis_map, 1918 mtod(m, void *), m->m_len, 1919 sis_dma_map_desc_ptr, f, 0); 1920 bus_dmamap_sync(sc->sis_tag, 1921 f->sis_map, BUS_DMASYNC_PREREAD); 1922 if (cnt != 0) 1923 f->sis_ctl |= SIS_CMDSTS_OWN; 1924 cur = frag; 1925 SIS_INC(frag, SIS_TX_LIST_CNT); 1926 cnt++; 1927 } 1928 } 1929 1930 if (m != NULL) 1931 return(ENOBUFS); 1932 1933 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = *m_head; 1934 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1935 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1936 sc->sis_cdata.sis_tx_cnt += cnt; 1937 *txidx = frag; 1938 1939 return(0); 1940} 1941 1942/* 1943 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1944 * to the mbuf data regions directly in the transmit lists. We also save a 1945 * copy of the pointers since the transmit list fragment pointers are 1946 * physical addresses. 1947 */ 1948 1949static void 1950sis_start(ifp) 1951 struct ifnet *ifp; 1952{ 1953 struct sis_softc *sc; 1954 struct mbuf *m_head = NULL; 1955 u_int32_t idx; 1956 1957 sc = ifp->if_softc; 1958 SIS_LOCK(sc); 1959 1960 if (!sc->sis_link) { 1961 SIS_UNLOCK(sc); 1962 return; 1963 } 1964 1965 idx = sc->sis_cdata.sis_tx_prod; 1966 1967 if (ifp->if_flags & IFF_OACTIVE) { 1968 SIS_UNLOCK(sc); 1969 return; 1970 } 1971 1972 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1973 IF_DEQUEUE(&ifp->if_snd, m_head); 1974 if (m_head == NULL) 1975 break; 1976 1977 if (sis_encap(sc, &m_head, &idx)) { 1978 IF_PREPEND(&ifp->if_snd, m_head); 1979 ifp->if_flags |= IFF_OACTIVE; 1980 break; 1981 } 1982 1983 /* 1984 * If there's a BPF listener, bounce a copy of this frame 1985 * to him. 1986 */ 1987 BPF_MTAP(ifp, m_head); 1988 1989 } 1990 1991 /* Transmit */ 1992 sc->sis_cdata.sis_tx_prod = idx; 1993 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1994 1995 /* 1996 * Set a timeout in case the chip goes out to lunch. 1997 */ 1998 ifp->if_timer = 5; 1999 2000 SIS_UNLOCK(sc); 2001 2002 return; 2003} 2004 2005static void 2006sis_init(xsc) 2007 void *xsc; 2008{ 2009 struct sis_softc *sc = xsc; 2010 struct ifnet *ifp = &sc->arpcom.ac_if; 2011 struct mii_data *mii; 2012 2013 SIS_LOCK(sc); 2014 2015 /* 2016 * Cancel pending I/O and free all RX/TX buffers. 2017 */ 2018 sis_stop(sc); 2019 sc->sis_stopped = 0; 2020 2021#ifdef notyet 2022 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2023 /* 2024 * Configure 400usec of interrupt holdoff. This is based 2025 * on emperical tests on a Soekris 4801. 2026 */ 2027 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2028 } 2029#endif 2030 2031 mii = device_get_softc(sc->sis_miibus); 2032 2033 /* Set MAC address */ 2034 if (sc->sis_type == SIS_TYPE_83815) { 2035 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2036 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2037 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2038 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2039 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2040 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2041 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2042 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2043 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2044 } else { 2045 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2046 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2047 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2048 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2049 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2050 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2051 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2052 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2053 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2054 } 2055 2056 /* Init circular RX list. */ 2057 if (sis_list_rx_init(sc) == ENOBUFS) { 2058 printf("sis%d: initialization failed: no " 2059 "memory for rx buffers\n", sc->sis_unit); 2060 sis_stop(sc); 2061 SIS_UNLOCK(sc); 2062 return; 2063 } 2064 2065 /* 2066 * Init tx descriptors. 2067 */ 2068 sis_list_tx_init(sc); 2069 2070 /* 2071 * Page 78 of the DP83815 data sheet (september 2002 version) 2072 * recommends the following register settings "for optimum 2073 * performance." for rev 15C. The driver from NS also sets 2074 * the PHY_CR register for later versions. 2075 */ 2076 if (sc->sis_type == SIS_TYPE_83815) { 2077 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2078 /* DC speed = 01 */ 2079 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2080 if (sc->sis_srr == NS_SRR_15C) { 2081 /* set val for c2 */ 2082 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2083 /* load/kill c2 */ 2084 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2085 /* rais SD off, from 4 to c */ 2086 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2087 } 2088 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2089 } 2090 2091 2092 /* 2093 * For the NatSemi chip, we have to explicitly enable the 2094 * reception of ARP frames, as well as turn on the 'perfect 2095 * match' filter where we store the station address, otherwise 2096 * we won't receive unicasts meant for this host. 2097 */ 2098 if (sc->sis_type == SIS_TYPE_83815) { 2099 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2100 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2101 } 2102 2103 /* If we want promiscuous mode, set the allframes bit. */ 2104 if (ifp->if_flags & IFF_PROMISC) { 2105 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2106 } else { 2107 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2108 } 2109 2110 /* 2111 * Set the capture broadcast bit to capture broadcast frames. 2112 */ 2113 if (ifp->if_flags & IFF_BROADCAST) { 2114 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2115 } else { 2116 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2117 } 2118 2119 /* 2120 * Load the multicast filter. 2121 */ 2122 if (sc->sis_type == SIS_TYPE_83815) 2123 sis_setmulti_ns(sc); 2124 else 2125 sis_setmulti_sis(sc); 2126 2127 /* Turn the receive filter on */ 2128 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2129 2130 /* 2131 * Load the address of the RX and TX lists. 2132 */ 2133 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2134 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2135 2136 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2137 * the PCI bus. When this bit is set, the Max DMA Burst Size 2138 * for TX/RX DMA should be no larger than 16 double words. 2139 */ 2140 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2141 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2142 } else { 2143 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2144 } 2145 2146 /* Accept Long Packets for VLAN support */ 2147 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2148 2149 /* Set TX configuration */ 2150 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2151 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2152 } else { 2153 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2154 } 2155 2156 /* Set full/half duplex mode. */ 2157 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2158 SIS_SETBIT(sc, SIS_TX_CFG, 2159 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2160 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2161 } else { 2162 SIS_CLRBIT(sc, SIS_TX_CFG, 2163 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2164 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2165 } 2166 2167 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2168 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2169 uint32_t reg; 2170 2171 /* 2172 * Some DP83815s experience problems when used with short 2173 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2174 * sequence adjusts the DSP's signal attenuation to fix the 2175 * problem. 2176 */ 2177 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2178 2179 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2180 /* Allow coefficient to be read */ 2181 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2182 DELAY(100); 2183 reg = CSR_READ_4(sc, NS_PHY_TDATA); 2184 if ((reg & 0x0080) == 0 || 2185 (reg > 0xd8 && reg <= 0xff)) { 2186 device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2187 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2188 /* Adjust coefficient and prevent change */ 2189 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2190 } 2191 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2192 } 2193 2194 /* 2195 * Enable interrupts. 2196 */ 2197 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2198#ifdef DEVICE_POLLING 2199 /* 2200 * ... only enable interrupts if we are not polling, make sure 2201 * they are off otherwise. 2202 */ 2203 if (ifp->if_flags & IFF_POLLING) 2204 CSR_WRITE_4(sc, SIS_IER, 0); 2205 else 2206#endif /* DEVICE_POLLING */ 2207 CSR_WRITE_4(sc, SIS_IER, 1); 2208 2209 /* Enable receiver and transmitter. */ 2210 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2211 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2212 2213#ifdef notdef 2214 mii_mediachg(mii); 2215#endif 2216 2217 ifp->if_flags |= IFF_RUNNING; 2218 ifp->if_flags &= ~IFF_OACTIVE; 2219 2220 if (!sc->in_tick) 2221 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2222 2223 SIS_UNLOCK(sc); 2224 2225 return; 2226} 2227 2228/* 2229 * Set media options. 2230 */ 2231static int 2232sis_ifmedia_upd(ifp) 2233 struct ifnet *ifp; 2234{ 2235 struct sis_softc *sc; 2236 struct mii_data *mii; 2237 2238 sc = ifp->if_softc; 2239 2240 mii = device_get_softc(sc->sis_miibus); 2241 sc->sis_link = 0; 2242 if (mii->mii_instance) { 2243 struct mii_softc *miisc; 2244 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2245 mii_phy_reset(miisc); 2246 } 2247 mii_mediachg(mii); 2248 2249 return(0); 2250} 2251 2252/* 2253 * Report current media status. 2254 */ 2255static void 2256sis_ifmedia_sts(ifp, ifmr) 2257 struct ifnet *ifp; 2258 struct ifmediareq *ifmr; 2259{ 2260 struct sis_softc *sc; 2261 struct mii_data *mii; 2262 2263 sc = ifp->if_softc; 2264 2265 mii = device_get_softc(sc->sis_miibus); 2266 mii_pollstat(mii); 2267 ifmr->ifm_active = mii->mii_media_active; 2268 ifmr->ifm_status = mii->mii_media_status; 2269 2270 return; 2271} 2272 2273static int 2274sis_ioctl(ifp, command, data) 2275 struct ifnet *ifp; 2276 u_long command; 2277 caddr_t data; 2278{ 2279 struct sis_softc *sc = ifp->if_softc; 2280 struct ifreq *ifr = (struct ifreq *) data; 2281 struct mii_data *mii; 2282 int error = 0; 2283 2284 switch(command) { 2285 case SIOCSIFFLAGS: 2286 if (ifp->if_flags & IFF_UP) { 2287 sis_init(sc); 2288 } else { 2289 if (ifp->if_flags & IFF_RUNNING) 2290 sis_stop(sc); 2291 } 2292 error = 0; 2293 break; 2294 case SIOCADDMULTI: 2295 case SIOCDELMULTI: 2296 SIS_LOCK(sc); 2297 if (sc->sis_type == SIS_TYPE_83815) 2298 sis_setmulti_ns(sc); 2299 else 2300 sis_setmulti_sis(sc); 2301 SIS_UNLOCK(sc); 2302 error = 0; 2303 break; 2304 case SIOCGIFMEDIA: 2305 case SIOCSIFMEDIA: 2306 mii = device_get_softc(sc->sis_miibus); 2307 SIS_LOCK(sc); 2308 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2309 SIS_UNLOCK(sc); 2310 break; 2311 case SIOCSIFCAP: 2312 ifp->if_capenable &= ~IFCAP_POLLING; 2313 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2314 break; 2315 default: 2316 error = ether_ioctl(ifp, command, data); 2317 break; 2318 } 2319 2320 return(error); 2321} 2322 2323static void 2324sis_watchdog(ifp) 2325 struct ifnet *ifp; 2326{ 2327 struct sis_softc *sc; 2328 2329 sc = ifp->if_softc; 2330 2331 SIS_LOCK(sc); 2332 2333 ifp->if_oerrors++; 2334 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2335 2336 sis_stop(sc); 2337 sis_reset(sc); 2338 sis_init(sc); 2339 2340 if (ifp->if_snd.ifq_head != NULL) 2341 sis_start(ifp); 2342 2343 SIS_UNLOCK(sc); 2344 2345 return; 2346} 2347 2348/* 2349 * Stop the adapter and free any mbufs allocated to the 2350 * RX and TX lists. 2351 */ 2352static void 2353sis_stop(sc) 2354 struct sis_softc *sc; 2355{ 2356 register int i; 2357 struct ifnet *ifp; 2358 2359 if (sc->sis_stopped) 2360 return; 2361 SIS_LOCK(sc); 2362 ifp = &sc->arpcom.ac_if; 2363 ifp->if_timer = 0; 2364 2365 callout_stop(&sc->sis_stat_ch); 2366 2367 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2368#ifdef DEVICE_POLLING 2369 ether_poll_deregister(ifp); 2370#endif 2371 CSR_WRITE_4(sc, SIS_IER, 0); 2372 CSR_WRITE_4(sc, SIS_IMR, 0); 2373 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2374 DELAY(1000); 2375 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2376 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2377 2378 sc->sis_link = 0; 2379 2380 /* 2381 * Free data in the RX lists. 2382 */ 2383 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2384 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2385 bus_dmamap_unload(sc->sis_tag, 2386 sc->sis_ldata.sis_rx_list[i].sis_map); 2387 bus_dmamap_destroy(sc->sis_tag, 2388 sc->sis_ldata.sis_rx_list[i].sis_map); 2389 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2390 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2391 } 2392 } 2393 bzero(sc->sis_ldata.sis_rx_list, 2394 sizeof(sc->sis_ldata.sis_rx_list)); 2395 2396 /* 2397 * Free the TX list buffers. 2398 */ 2399 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2400 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2401 bus_dmamap_unload(sc->sis_tag, 2402 sc->sis_ldata.sis_tx_list[i].sis_map); 2403 bus_dmamap_destroy(sc->sis_tag, 2404 sc->sis_ldata.sis_tx_list[i].sis_map); 2405 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2406 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2407 } 2408 } 2409 2410 bzero(sc->sis_ldata.sis_tx_list, 2411 sizeof(sc->sis_ldata.sis_tx_list)); 2412 2413 sc->sis_stopped = 1; 2414 SIS_UNLOCK(sc); 2415 2416 return; 2417} 2418 2419/* 2420 * Stop all chip I/O so that the kernel's probe routines don't 2421 * get confused by errant DMAs when rebooting. 2422 */ 2423static void 2424sis_shutdown(dev) 2425 device_t dev; 2426{ 2427 struct sis_softc *sc; 2428 2429 sc = device_get_softc(dev); 2430 SIS_LOCK(sc); 2431 sis_reset(sc); 2432 sis_stop(sc); 2433 SIS_UNLOCK(sc); 2434 2435 return; 2436} 2437