if_sis.c revision 118089
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 35 * available from http://www.sis.com.tw. 36 * 37 * This driver also supports the NatSemi DP83815. Datasheets are 38 * available from http://www.national.com. 39 * 40 * Written by Bill Paul <wpaul@ee.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 47 * simple TX and RX descriptors of 3 longwords in size. The receiver 48 * has a single perfect filter entry for the station address and a 49 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 50 * transceiver while the 7016 requires an external transceiver chip. 51 * Both chips offer the standard bit-bang MII interface as well as 52 * an enchanced PHY interface which simplifies accessing MII registers. 53 * 54 * The only downside to this chipset is that RX descriptors must be 55 * longword aligned. 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 118089 2003-07-27 14:38:54Z mux $"); 60 61#include <sys/param.h> 62#include <sys/systm.h> 63#include <sys/sockio.h> 64#include <sys/mbuf.h> 65#include <sys/malloc.h> 66#include <sys/kernel.h> 67#include <sys/socket.h> 68#include <sys/sysctl.h> 69 70#include <net/if.h> 71#include <net/if_arp.h> 72#include <net/ethernet.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75#include <net/if_types.h> 76#include <net/if_vlan_var.h> 77 78#include <net/bpf.h> 79 80#include <machine/bus_pio.h> 81#include <machine/bus_memio.h> 82#include <machine/bus.h> 83#include <machine/resource.h> 84#include <sys/bus.h> 85#include <sys/rman.h> 86 87#include <dev/mii/mii.h> 88#include <dev/mii/miivar.h> 89 90#include <pci/pcireg.h> 91#include <pci/pcivar.h> 92 93#define SIS_USEIOSPACE 94 95#include <pci/if_sisreg.h> 96 97MODULE_DEPEND(sis, pci, 1, 1, 1); 98MODULE_DEPEND(sis, ether, 1, 1, 1); 99MODULE_DEPEND(sis, miibus, 1, 1, 1); 100 101/* "controller miibus0" required. See GENERIC if you get errors here. */ 102#include "miibus_if.h" 103 104/* 105 * Various supported device vendors/types and their names. 106 */ 107static struct sis_type sis_devs[] = { 108 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 109 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 110 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 111 { 0, 0, NULL } 112}; 113 114static int sis_probe (device_t); 115static int sis_attach (device_t); 116static int sis_detach (device_t); 117 118static int sis_newbuf (struct sis_softc *, 119 struct sis_desc *, struct mbuf *); 120static int sis_encap (struct sis_softc *, 121 struct mbuf *, u_int32_t *); 122static void sis_rxeof (struct sis_softc *); 123static void sis_rxeoc (struct sis_softc *); 124static void sis_txeof (struct sis_softc *); 125static void sis_intr (void *); 126static void sis_tick (void *); 127static void sis_start (struct ifnet *); 128static int sis_ioctl (struct ifnet *, u_long, caddr_t); 129static void sis_init (void *); 130static void sis_stop (struct sis_softc *); 131static void sis_watchdog (struct ifnet *); 132static void sis_shutdown (device_t); 133static int sis_ifmedia_upd (struct ifnet *); 134static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 135 136static u_int16_t sis_reverse (u_int16_t); 137static void sis_delay (struct sis_softc *); 138static void sis_eeprom_idle (struct sis_softc *); 139static void sis_eeprom_putbyte (struct sis_softc *, int); 140static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 141static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 142#ifdef __i386__ 143static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 144 int, int); 145static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 146static device_t sis_find_bridge (device_t); 147#endif 148 149static void sis_mii_sync (struct sis_softc *); 150static void sis_mii_send (struct sis_softc *, u_int32_t, int); 151static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 152static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 153static int sis_miibus_readreg (device_t, int, int); 154static int sis_miibus_writereg (device_t, int, int, int); 155static void sis_miibus_statchg (device_t); 156 157static void sis_setmulti_sis (struct sis_softc *); 158static void sis_setmulti_ns (struct sis_softc *); 159static u_int32_t sis_crc (struct sis_softc *, caddr_t); 160static void sis_reset (struct sis_softc *); 161static int sis_list_rx_init (struct sis_softc *); 162static int sis_list_tx_init (struct sis_softc *); 163 164static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 165static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 166static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 167#ifdef SIS_USEIOSPACE 168#define SIS_RES SYS_RES_IOPORT 169#define SIS_RID SIS_PCI_LOIO 170#else 171#define SIS_RES SYS_RES_MEMORY 172#define SIS_RID SIS_PCI_LOMEM 173#endif 174 175static device_method_t sis_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, sis_probe), 178 DEVMETHOD(device_attach, sis_attach), 179 DEVMETHOD(device_detach, sis_detach), 180 DEVMETHOD(device_shutdown, sis_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 188 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 189 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 190 191 { 0, 0 } 192}; 193 194static driver_t sis_driver = { 195 "sis", 196 sis_methods, 197 sizeof(struct sis_softc) 198}; 199 200static devclass_t sis_devclass; 201 202DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 203DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 204 205#define SIS_SETBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, \ 207 CSR_READ_4(sc, reg) | (x)) 208 209#define SIS_CLRBIT(sc, reg, x) \ 210 CSR_WRITE_4(sc, reg, \ 211 CSR_READ_4(sc, reg) & ~(x)) 212 213#define SIO_SET(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 215 216#define SIO_CLR(x) \ 217 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 218 219static void 220sis_dma_map_desc_next(arg, segs, nseg, error) 221 void *arg; 222 bus_dma_segment_t *segs; 223 int nseg, error; 224{ 225 struct sis_desc *r; 226 227 r = arg; 228 r->sis_next = segs->ds_addr; 229 230 return; 231} 232 233static void 234sis_dma_map_desc_ptr(arg, segs, nseg, error) 235 void *arg; 236 bus_dma_segment_t *segs; 237 int nseg, error; 238{ 239 struct sis_desc *r; 240 241 r = arg; 242 r->sis_ptr = segs->ds_addr; 243 244 return; 245} 246 247static void 248sis_dma_map_ring(arg, segs, nseg, error) 249 void *arg; 250 bus_dma_segment_t *segs; 251 int nseg, error; 252{ 253 u_int32_t *p; 254 255 p = arg; 256 *p = segs->ds_addr; 257 258 return; 259} 260 261/* 262 * Routine to reverse the bits in a word. Stolen almost 263 * verbatim from /usr/games/fortune. 264 */ 265static u_int16_t 266sis_reverse(n) 267 u_int16_t n; 268{ 269 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 270 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 271 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 272 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 273 274 return(n); 275} 276 277static void 278sis_delay(sc) 279 struct sis_softc *sc; 280{ 281 int idx; 282 283 for (idx = (300 / 33) + 1; idx > 0; idx--) 284 CSR_READ_4(sc, SIS_CSR); 285 286 return; 287} 288 289static void 290sis_eeprom_idle(sc) 291 struct sis_softc *sc; 292{ 293 register int i; 294 295 SIO_SET(SIS_EECTL_CSEL); 296 sis_delay(sc); 297 SIO_SET(SIS_EECTL_CLK); 298 sis_delay(sc); 299 300 for (i = 0; i < 25; i++) { 301 SIO_CLR(SIS_EECTL_CLK); 302 sis_delay(sc); 303 SIO_SET(SIS_EECTL_CLK); 304 sis_delay(sc); 305 } 306 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_CLR(SIS_EECTL_CSEL); 310 sis_delay(sc); 311 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 312 313 return; 314} 315 316/* 317 * Send a read command and address to the EEPROM, check for ACK. 318 */ 319static void 320sis_eeprom_putbyte(sc, addr) 321 struct sis_softc *sc; 322 int addr; 323{ 324 register int d, i; 325 326 d = addr | SIS_EECMD_READ; 327 328 /* 329 * Feed in each bit and stobe the clock. 330 */ 331 for (i = 0x400; i; i >>= 1) { 332 if (d & i) { 333 SIO_SET(SIS_EECTL_DIN); 334 } else { 335 SIO_CLR(SIS_EECTL_DIN); 336 } 337 sis_delay(sc); 338 SIO_SET(SIS_EECTL_CLK); 339 sis_delay(sc); 340 SIO_CLR(SIS_EECTL_CLK); 341 sis_delay(sc); 342 } 343 344 return; 345} 346 347/* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350static void 351sis_eeprom_getword(sc, addr, dest) 352 struct sis_softc *sc; 353 int addr; 354 u_int16_t *dest; 355{ 356 register int i; 357 u_int16_t word = 0; 358 359 /* Force EEPROM to idle state. */ 360 sis_eeprom_idle(sc); 361 362 /* Enter EEPROM access mode. */ 363 sis_delay(sc); 364 SIO_CLR(SIS_EECTL_CLK); 365 sis_delay(sc); 366 SIO_SET(SIS_EECTL_CSEL); 367 sis_delay(sc); 368 369 /* 370 * Send address of word we want to read. 371 */ 372 sis_eeprom_putbyte(sc, addr); 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 for (i = 0x8000; i; i >>= 1) { 378 SIO_SET(SIS_EECTL_CLK); 379 sis_delay(sc); 380 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 381 word |= i; 382 sis_delay(sc); 383 SIO_CLR(SIS_EECTL_CLK); 384 sis_delay(sc); 385 } 386 387 /* Turn off EEPROM access mode. */ 388 sis_eeprom_idle(sc); 389 390 *dest = word; 391 392 return; 393} 394 395/* 396 * Read a sequence of words from the EEPROM. 397 */ 398static void 399sis_read_eeprom(sc, dest, off, cnt, swap) 400 struct sis_softc *sc; 401 caddr_t dest; 402 int off; 403 int cnt; 404 int swap; 405{ 406 int i; 407 u_int16_t word = 0, *ptr; 408 409 for (i = 0; i < cnt; i++) { 410 sis_eeprom_getword(sc, off + i, &word); 411 ptr = (u_int16_t *)(dest + (i * 2)); 412 if (swap) 413 *ptr = ntohs(word); 414 else 415 *ptr = word; 416 } 417 418 return; 419} 420 421#ifdef __i386__ 422static device_t 423sis_find_bridge(dev) 424 device_t dev; 425{ 426 devclass_t pci_devclass; 427 device_t *pci_devices; 428 int pci_count = 0; 429 device_t *pci_children; 430 int pci_childcount = 0; 431 device_t *busp, *childp; 432 device_t child = NULL; 433 int i, j; 434 435 if ((pci_devclass = devclass_find("pci")) == NULL) 436 return(NULL); 437 438 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 439 440 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 441 pci_childcount = 0; 442 device_get_children(*busp, &pci_children, &pci_childcount); 443 for (j = 0, childp = pci_children; 444 j < pci_childcount; j++, childp++) { 445 if (pci_get_vendor(*childp) == SIS_VENDORID && 446 pci_get_device(*childp) == 0x0008) { 447 child = *childp; 448 goto done; 449 } 450 } 451 } 452 453done: 454 free(pci_devices, M_TEMP); 455 free(pci_children, M_TEMP); 456 return(child); 457} 458 459static void 460sis_read_cmos(sc, dev, dest, off, cnt) 461 struct sis_softc *sc; 462 device_t dev; 463 caddr_t dest; 464 int off; 465 int cnt; 466{ 467 device_t bridge; 468 u_int8_t reg; 469 int i; 470 bus_space_tag_t btag; 471 472 bridge = sis_find_bridge(dev); 473 if (bridge == NULL) 474 return; 475 reg = pci_read_config(bridge, 0x48, 1); 476 pci_write_config(bridge, 0x48, reg|0x40, 1); 477 478 /* XXX */ 479 btag = I386_BUS_SPACE_IO; 480 481 for (i = 0; i < cnt; i++) { 482 bus_space_write_1(btag, 0x0, 0x70, i + off); 483 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 484 } 485 486 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 487 return; 488} 489 490static void 491sis_read_mac(sc, dev, dest) 492 struct sis_softc *sc; 493 device_t dev; 494 caddr_t dest; 495{ 496 u_int32_t filtsave, csrsave; 497 498 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 499 csrsave = CSR_READ_4(sc, SIS_CSR); 500 501 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 502 CSR_WRITE_4(sc, SIS_CSR, 0); 503 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 507 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 509 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 511 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 513 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 514 CSR_WRITE_4(sc, SIS_CSR, csrsave); 515 return; 516} 517#endif 518 519/* 520 * Sync the PHYs by setting data bit and strobing the clock 32 times. 521 */ 522static void sis_mii_sync(sc) 523 struct sis_softc *sc; 524{ 525 register int i; 526 527 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 528 529 for (i = 0; i < 32; i++) { 530 SIO_SET(SIS_MII_CLK); 531 DELAY(1); 532 SIO_CLR(SIS_MII_CLK); 533 DELAY(1); 534 } 535 536 return; 537} 538 539/* 540 * Clock a series of bits through the MII. 541 */ 542static void sis_mii_send(sc, bits, cnt) 543 struct sis_softc *sc; 544 u_int32_t bits; 545 int cnt; 546{ 547 int i; 548 549 SIO_CLR(SIS_MII_CLK); 550 551 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 552 if (bits & i) { 553 SIO_SET(SIS_MII_DATA); 554 } else { 555 SIO_CLR(SIS_MII_DATA); 556 } 557 DELAY(1); 558 SIO_CLR(SIS_MII_CLK); 559 DELAY(1); 560 SIO_SET(SIS_MII_CLK); 561 } 562} 563 564/* 565 * Read an PHY register through the MII. 566 */ 567static int sis_mii_readreg(sc, frame) 568 struct sis_softc *sc; 569 struct sis_mii_frame *frame; 570 571{ 572 int i, ack, s; 573 574 s = splimp(); 575 576 /* 577 * Set up frame for RX. 578 */ 579 frame->mii_stdelim = SIS_MII_STARTDELIM; 580 frame->mii_opcode = SIS_MII_READOP; 581 frame->mii_turnaround = 0; 582 frame->mii_data = 0; 583 584 /* 585 * Turn on data xmit. 586 */ 587 SIO_SET(SIS_MII_DIR); 588 589 sis_mii_sync(sc); 590 591 /* 592 * Send command/address info. 593 */ 594 sis_mii_send(sc, frame->mii_stdelim, 2); 595 sis_mii_send(sc, frame->mii_opcode, 2); 596 sis_mii_send(sc, frame->mii_phyaddr, 5); 597 sis_mii_send(sc, frame->mii_regaddr, 5); 598 599 /* Idle bit */ 600 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 601 DELAY(1); 602 SIO_SET(SIS_MII_CLK); 603 DELAY(1); 604 605 /* Turn off xmit. */ 606 SIO_CLR(SIS_MII_DIR); 607 608 /* Check for ack */ 609 SIO_CLR(SIS_MII_CLK); 610 DELAY(1); 611 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 612 SIO_SET(SIS_MII_CLK); 613 DELAY(1); 614 615 /* 616 * Now try reading data bits. If the ack failed, we still 617 * need to clock through 16 cycles to keep the PHY(s) in sync. 618 */ 619 if (ack) { 620 for(i = 0; i < 16; i++) { 621 SIO_CLR(SIS_MII_CLK); 622 DELAY(1); 623 SIO_SET(SIS_MII_CLK); 624 DELAY(1); 625 } 626 goto fail; 627 } 628 629 for (i = 0x8000; i; i >>= 1) { 630 SIO_CLR(SIS_MII_CLK); 631 DELAY(1); 632 if (!ack) { 633 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 634 frame->mii_data |= i; 635 DELAY(1); 636 } 637 SIO_SET(SIS_MII_CLK); 638 DELAY(1); 639 } 640 641fail: 642 643 SIO_CLR(SIS_MII_CLK); 644 DELAY(1); 645 SIO_SET(SIS_MII_CLK); 646 DELAY(1); 647 648 splx(s); 649 650 if (ack) 651 return(1); 652 return(0); 653} 654 655/* 656 * Write to a PHY register through the MII. 657 */ 658static int sis_mii_writereg(sc, frame) 659 struct sis_softc *sc; 660 struct sis_mii_frame *frame; 661 662{ 663 int s; 664 665 s = splimp(); 666 /* 667 * Set up frame for TX. 668 */ 669 670 frame->mii_stdelim = SIS_MII_STARTDELIM; 671 frame->mii_opcode = SIS_MII_WRITEOP; 672 frame->mii_turnaround = SIS_MII_TURNAROUND; 673 674 /* 675 * Turn on data output. 676 */ 677 SIO_SET(SIS_MII_DIR); 678 679 sis_mii_sync(sc); 680 681 sis_mii_send(sc, frame->mii_stdelim, 2); 682 sis_mii_send(sc, frame->mii_opcode, 2); 683 sis_mii_send(sc, frame->mii_phyaddr, 5); 684 sis_mii_send(sc, frame->mii_regaddr, 5); 685 sis_mii_send(sc, frame->mii_turnaround, 2); 686 sis_mii_send(sc, frame->mii_data, 16); 687 688 /* Idle bit. */ 689 SIO_SET(SIS_MII_CLK); 690 DELAY(1); 691 SIO_CLR(SIS_MII_CLK); 692 DELAY(1); 693 694 /* 695 * Turn off xmit. 696 */ 697 SIO_CLR(SIS_MII_DIR); 698 699 splx(s); 700 701 return(0); 702} 703 704static int 705sis_miibus_readreg(dev, phy, reg) 706 device_t dev; 707 int phy, reg; 708{ 709 struct sis_softc *sc; 710 struct sis_mii_frame frame; 711 712 sc = device_get_softc(dev); 713 714 if (sc->sis_type == SIS_TYPE_83815) { 715 if (phy != 0) 716 return(0); 717 /* 718 * The NatSemi chip can take a while after 719 * a reset to come ready, during which the BMSR 720 * returns a value of 0. This is *never* supposed 721 * to happen: some of the BMSR bits are meant to 722 * be hardwired in the on position, and this can 723 * confuse the miibus code a bit during the probe 724 * and attach phase. So we make an effort to check 725 * for this condition and wait for it to clear. 726 */ 727 if (!CSR_READ_4(sc, NS_BMSR)) 728 DELAY(1000); 729 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 730 } 731 732 /* 733 * Chipsets < SIS_635 seem not to be able to read/write 734 * through mdio. Use the enhanced PHY access register 735 * again for them. 736 */ 737 if (sc->sis_type == SIS_TYPE_900 && 738 sc->sis_rev < SIS_REV_635) { 739 int i, val = 0; 740 741 if (phy != 0) 742 return(0); 743 744 CSR_WRITE_4(sc, SIS_PHYCTL, 745 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 746 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 747 748 for (i = 0; i < SIS_TIMEOUT; i++) { 749 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 750 break; 751 } 752 753 if (i == SIS_TIMEOUT) { 754 printf("sis%d: PHY failed to come ready\n", 755 sc->sis_unit); 756 return(0); 757 } 758 759 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 760 761 if (val == 0xFFFF) 762 return(0); 763 764 return(val); 765 } else { 766 bzero((char *)&frame, sizeof(frame)); 767 768 frame.mii_phyaddr = phy; 769 frame.mii_regaddr = reg; 770 sis_mii_readreg(sc, &frame); 771 772 return(frame.mii_data); 773 } 774} 775 776static int 777sis_miibus_writereg(dev, phy, reg, data) 778 device_t dev; 779 int phy, reg, data; 780{ 781 struct sis_softc *sc; 782 struct sis_mii_frame frame; 783 784 sc = device_get_softc(dev); 785 786 if (sc->sis_type == SIS_TYPE_83815) { 787 if (phy != 0) 788 return(0); 789 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 790 return(0); 791 } 792 793 /* 794 * Chipsets < SIS_635 seem not to be able to read/write 795 * through mdio. Use the enhanced PHY access register 796 * again for them. 797 */ 798 if (sc->sis_type == SIS_TYPE_900 && 799 sc->sis_rev < SIS_REV_635) { 800 int i; 801 802 if (phy != 0) 803 return(0); 804 805 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 806 (reg << 6) | SIS_PHYOP_WRITE); 807 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 808 809 for (i = 0; i < SIS_TIMEOUT; i++) { 810 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 811 break; 812 } 813 814 if (i == SIS_TIMEOUT) 815 printf("sis%d: PHY failed to come ready\n", 816 sc->sis_unit); 817 } else { 818 bzero((char *)&frame, sizeof(frame)); 819 820 frame.mii_phyaddr = phy; 821 frame.mii_regaddr = reg; 822 frame.mii_data = data; 823 sis_mii_writereg(sc, &frame); 824 } 825 return(0); 826} 827 828static void 829sis_miibus_statchg(dev) 830 device_t dev; 831{ 832 struct sis_softc *sc; 833 834 sc = device_get_softc(dev); 835 sis_init(sc); 836 837 return; 838} 839 840static u_int32_t 841sis_crc(sc, addr) 842 struct sis_softc *sc; 843 caddr_t addr; 844{ 845 u_int32_t crc, carry; 846 int i, j; 847 u_int8_t c; 848 849 /* Compute CRC for the address value. */ 850 crc = 0xFFFFFFFF; /* initial value */ 851 852 for (i = 0; i < 6; i++) { 853 c = *(addr + i); 854 for (j = 0; j < 8; j++) { 855 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 856 crc <<= 1; 857 c >>= 1; 858 if (carry) 859 crc = (crc ^ 0x04c11db6) | carry; 860 } 861 } 862 863 /* 864 * return the filter bit position 865 * 866 * The NatSemi chip has a 512-bit filter, which is 867 * different than the SiS, so we special-case it. 868 */ 869 if (sc->sis_type == SIS_TYPE_83815) 870 return (crc >> 23); 871 else if (sc->sis_rev >= SIS_REV_635 || 872 sc->sis_rev == SIS_REV_900B) 873 return (crc >> 24); 874 else 875 return (crc >> 25); 876} 877 878static void 879sis_setmulti_ns(sc) 880 struct sis_softc *sc; 881{ 882 struct ifnet *ifp; 883 struct ifmultiaddr *ifma; 884 u_int32_t h = 0, i, filtsave; 885 int bit, index; 886 887 ifp = &sc->arpcom.ac_if; 888 889 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 890 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 891 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 892 return; 893 } 894 895 /* 896 * We have to explicitly enable the multicast hash table 897 * on the NatSemi chip if we want to use it, which we do. 898 */ 899 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 900 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 901 902 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 903 904 /* first, zot all the existing hash bits */ 905 for (i = 0; i < 32; i++) { 906 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 907 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 908 } 909 910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 911 if (ifma->ifma_addr->sa_family != AF_LINK) 912 continue; 913 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 914 index = h >> 3; 915 bit = h & 0x1F; 916 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 917 if (bit > 0xF) 918 bit -= 0x10; 919 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 920 } 921 922 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 923 924 return; 925} 926 927static void 928sis_setmulti_sis(sc) 929 struct sis_softc *sc; 930{ 931 struct ifnet *ifp; 932 struct ifmultiaddr *ifma; 933 u_int32_t h, i, n, ctl; 934 u_int16_t hashes[16]; 935 936 ifp = &sc->arpcom.ac_if; 937 938 /* hash table size */ 939 if (sc->sis_rev >= SIS_REV_635 || 940 sc->sis_rev == SIS_REV_900B) 941 n = 16; 942 else 943 n = 8; 944 945 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 946 947 if (ifp->if_flags & IFF_BROADCAST) 948 ctl |= SIS_RXFILTCTL_BROAD; 949 950 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 951 ctl |= SIS_RXFILTCTL_ALLMULTI; 952 if (ifp->if_flags & IFF_PROMISC) 953 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 954 for (i = 0; i < n; i++) 955 hashes[i] = ~0; 956 } else { 957 for (i = 0; i < n; i++) 958 hashes[i] = 0; 959 i = 0; 960 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 961 if (ifma->ifma_addr->sa_family != AF_LINK) 962 continue; 963 h = sis_crc(sc, 964 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 965 hashes[h >> 4] |= 1 << (h & 0xf); 966 i++; 967 } 968 if (i > n) { 969 ctl |= SIS_RXFILTCTL_ALLMULTI; 970 for (i = 0; i < n; i++) 971 hashes[i] = ~0; 972 } 973 } 974 975 for (i = 0; i < n; i++) { 976 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 977 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 978 } 979 980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 981} 982 983static void 984sis_reset(sc) 985 struct sis_softc *sc; 986{ 987 register int i; 988 989 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 990 991 for (i = 0; i < SIS_TIMEOUT; i++) { 992 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 993 break; 994 } 995 996 if (i == SIS_TIMEOUT) 997 printf("sis%d: reset never completed\n", sc->sis_unit); 998 999 /* Wait a little while for the chip to get its brains in order. */ 1000 DELAY(1000); 1001 1002 /* 1003 * If this is a NetSemi chip, make sure to clear 1004 * PME mode. 1005 */ 1006 if (sc->sis_type == SIS_TYPE_83815) { 1007 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 1008 CSR_WRITE_4(sc, NS_CLKRUN, 0); 1009 } 1010 1011 return; 1012} 1013 1014/* 1015 * Probe for an SiS chip. Check the PCI vendor and device 1016 * IDs against our list and return a device name if we find a match. 1017 */ 1018static int 1019sis_probe(dev) 1020 device_t dev; 1021{ 1022 struct sis_type *t; 1023 1024 t = sis_devs; 1025 1026 while(t->sis_name != NULL) { 1027 if ((pci_get_vendor(dev) == t->sis_vid) && 1028 (pci_get_device(dev) == t->sis_did)) { 1029 device_set_desc(dev, t->sis_name); 1030 return(0); 1031 } 1032 t++; 1033 } 1034 1035 return(ENXIO); 1036} 1037 1038/* 1039 * Attach the interface. Allocate softc structures, do ifmedia 1040 * setup and ethernet/BPF attach. 1041 */ 1042static int 1043sis_attach(dev) 1044 device_t dev; 1045{ 1046 u_char eaddr[ETHER_ADDR_LEN]; 1047 struct sis_softc *sc; 1048 struct ifnet *ifp; 1049 int unit, error = 0, rid, waittime = 0; 1050 1051 waittime = 0; 1052 sc = device_get_softc(dev); 1053 unit = device_get_unit(dev); 1054 1055 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1056 MTX_DEF | MTX_RECURSE); 1057 1058 if (pci_get_device(dev) == SIS_DEVICEID_900) 1059 sc->sis_type = SIS_TYPE_900; 1060 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1061 sc->sis_type = SIS_TYPE_7016; 1062 if (pci_get_vendor(dev) == NS_VENDORID) 1063 sc->sis_type = SIS_TYPE_83815; 1064 1065 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1066#ifndef BURN_BRIDGES 1067 /* 1068 * Handle power management nonsense. 1069 */ 1070 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1071 u_int32_t iobase, membase, irq; 1072 1073 /* Save important PCI config data. */ 1074 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1075 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1076 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1077 1078 /* Reset the power state. */ 1079 printf("sis%d: chip is in D%d power mode " 1080 "-- setting to D0\n", unit, 1081 pci_get_powerstate(dev)); 1082 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1083 1084 /* Restore PCI config data. */ 1085 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1086 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1087 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1088 } 1089#endif 1090 /* 1091 * Map control/status registers. 1092 */ 1093 pci_enable_busmaster(dev); 1094 1095 rid = SIS_RID; 1096 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1097 0, ~0, 1, RF_ACTIVE); 1098 1099 if (sc->sis_res == NULL) { 1100 printf("sis%d: couldn't map ports/memory\n", unit); 1101 error = ENXIO; 1102 goto fail; 1103 } 1104 1105 sc->sis_btag = rman_get_bustag(sc->sis_res); 1106 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1107 1108 /* Allocate interrupt */ 1109 rid = 0; 1110 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1111 RF_SHAREABLE | RF_ACTIVE); 1112 1113 if (sc->sis_irq == NULL) { 1114 printf("sis%d: couldn't map interrupt\n", unit); 1115 error = ENXIO; 1116 goto fail; 1117 } 1118 1119 /* Reset the adapter. */ 1120 sis_reset(sc); 1121 1122 if (sc->sis_type == SIS_TYPE_900 && 1123 (sc->sis_rev == SIS_REV_635 || 1124 sc->sis_rev == SIS_REV_900B)) { 1125 SIO_SET(SIS_CFG_RND_CNT); 1126 SIO_SET(SIS_CFG_PERR_DETECT); 1127 } 1128 1129 /* 1130 * Get station address from the EEPROM. 1131 */ 1132 switch (pci_get_vendor(dev)) { 1133 case NS_VENDORID: 1134 /* 1135 * Reading the MAC address out of the EEPROM on 1136 * the NatSemi chip takes a bit more work than 1137 * you'd expect. The address spans 4 16-bit words, 1138 * with the first word containing only a single bit. 1139 * You have to shift everything over one bit to 1140 * get it aligned properly. Also, the bits are 1141 * stored backwards (the LSB is really the MSB, 1142 * and so on) so you have to reverse them in order 1143 * to get the MAC address into the form we want. 1144 * Why? Who the hell knows. 1145 */ 1146 { 1147 u_int16_t tmp[4]; 1148 1149 sis_read_eeprom(sc, (caddr_t)&tmp, 1150 NS_EE_NODEADDR, 4, 0); 1151 1152 /* Shift everything over one bit. */ 1153 tmp[3] = tmp[3] >> 1; 1154 tmp[3] |= tmp[2] << 15; 1155 tmp[2] = tmp[2] >> 1; 1156 tmp[2] |= tmp[1] << 15; 1157 tmp[1] = tmp[1] >> 1; 1158 tmp[1] |= tmp[0] << 15; 1159 1160 /* Now reverse all the bits. */ 1161 tmp[3] = sis_reverse(tmp[3]); 1162 tmp[2] = sis_reverse(tmp[2]); 1163 tmp[1] = sis_reverse(tmp[1]); 1164 1165 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1166 } 1167 break; 1168 case SIS_VENDORID: 1169 default: 1170#ifdef __i386__ 1171 /* 1172 * If this is a SiS 630E chipset with an embedded 1173 * SiS 900 controller, we have to read the MAC address 1174 * from the APC CMOS RAM. Our method for doing this 1175 * is very ugly since we have to reach out and grab 1176 * ahold of hardware for which we cannot properly 1177 * allocate resources. This code is only compiled on 1178 * the i386 architecture since the SiS 630E chipset 1179 * is for x86 motherboards only. Note that there are 1180 * a lot of magic numbers in this hack. These are 1181 * taken from SiS's Linux driver. I'd like to replace 1182 * them with proper symbolic definitions, but that 1183 * requires some datasheets that I don't have access 1184 * to at the moment. 1185 */ 1186 if (sc->sis_rev == SIS_REV_630S || 1187 sc->sis_rev == SIS_REV_630E || 1188 sc->sis_rev == SIS_REV_630EA1) 1189 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1190 1191 else if (sc->sis_rev == SIS_REV_635 || 1192 sc->sis_rev == SIS_REV_630ET) 1193 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1194 else if (sc->sis_rev == SIS_REV_96x) { 1195 /* Allow to read EEPROM from LAN. It is shared 1196 * between a 1394 controller and the NIC and each 1197 * time we access it, we need to set SIS_EECMD_REQ. 1198 */ 1199 SIO_SET(SIS_EECMD_REQ); 1200 for (waittime = 0; waittime < SIS_TIMEOUT; 1201 waittime++) { 1202 /* Force EEPROM to idle state. */ 1203 sis_eeprom_idle(sc); 1204 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1205 sis_read_eeprom(sc, (caddr_t)&eaddr, 1206 SIS_EE_NODEADDR, 3, 0); 1207 break; 1208 } 1209 DELAY(1); 1210 } 1211 /* 1212 * Set SIS_EECTL_CLK to high, so a other master 1213 * can operate on the i2c bus. 1214 */ 1215 SIO_SET(SIS_EECTL_CLK); 1216 /* Refuse EEPROM access by LAN */ 1217 SIO_SET(SIS_EECMD_DONE); 1218 } else 1219#endif 1220 sis_read_eeprom(sc, (caddr_t)&eaddr, 1221 SIS_EE_NODEADDR, 3, 0); 1222 break; 1223 } 1224 1225 /* 1226 * A SiS chip was detected. Inform the world. 1227 */ 1228 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1229 1230 sc->sis_unit = unit; 1231 callout_handle_init(&sc->sis_stat_ch); 1232 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1233 1234 /* 1235 * Allocate the parent bus DMA tag appropriate for PCI. 1236 */ 1237#define SIS_NSEG_NEW 32 1238 error = bus_dma_tag_create(NULL, /* parent */ 1239 1, 0, /* alignment, boundary */ 1240 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1241 BUS_SPACE_MAXADDR, /* highaddr */ 1242 NULL, NULL, /* filter, filterarg */ 1243 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1244 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1245 BUS_DMA_ALLOCNOW, /* flags */ 1246 NULL, NULL, /* lockfunc, lockarg */ 1247 &sc->sis_parent_tag); 1248 if (error) 1249 goto fail; 1250 1251 /* 1252 * Now allocate a tag for the DMA descriptor lists and a chunk 1253 * of DMA-able memory based on the tag. Also obtain the physical 1254 * addresses of the RX and TX ring, which we'll need later. 1255 * All of our lists are allocated as a contiguous block 1256 * of memory. 1257 */ 1258 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1259 1, 0, /* alignment, boundary */ 1260 BUS_SPACE_MAXADDR, /* lowaddr */ 1261 BUS_SPACE_MAXADDR, /* highaddr */ 1262 NULL, NULL, /* filter, filterarg */ 1263 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1264 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1265 0, /* flags */ 1266 busdma_lock_mutex, /* lockfunc */ 1267 &Giant, /* lockarg */ 1268 &sc->sis_ldata.sis_rx_tag); 1269 if (error) 1270 goto fail; 1271 1272 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1273 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1274 &sc->sis_ldata.sis_rx_dmamap); 1275 1276 if (error) { 1277 printf("sis%d: no memory for rx list buffers!\n", unit); 1278 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1279 sc->sis_ldata.sis_rx_tag = NULL; 1280 goto fail; 1281 } 1282 1283 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1284 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1285 sizeof(struct sis_desc), sis_dma_map_ring, 1286 &sc->sis_cdata.sis_rx_paddr, 0); 1287 1288 if (error) { 1289 printf("sis%d: cannot get address of the rx ring!\n", unit); 1290 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1291 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1292 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1293 sc->sis_ldata.sis_rx_tag = NULL; 1294 goto fail; 1295 } 1296 1297 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1298 1, 0, /* alignment, boundary */ 1299 BUS_SPACE_MAXADDR, /* lowaddr */ 1300 BUS_SPACE_MAXADDR, /* highaddr */ 1301 NULL, NULL, /* filter, filterarg */ 1302 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1303 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1304 0, /* flags */ 1305 busdma_lock_mutex, /* lockfunc */ 1306 &Giant, /* lockarg */ 1307 &sc->sis_ldata.sis_tx_tag); 1308 if (error) 1309 goto fail; 1310 1311 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1312 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1313 &sc->sis_ldata.sis_tx_dmamap); 1314 1315 if (error) { 1316 printf("sis%d: no memory for tx list buffers!\n", unit); 1317 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1318 sc->sis_ldata.sis_tx_tag = NULL; 1319 goto fail; 1320 } 1321 1322 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1323 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1324 sizeof(struct sis_desc), sis_dma_map_ring, 1325 &sc->sis_cdata.sis_tx_paddr, 0); 1326 1327 if (error) { 1328 printf("sis%d: cannot get address of the tx ring!\n", unit); 1329 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1330 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1331 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1332 sc->sis_ldata.sis_tx_tag = NULL; 1333 goto fail; 1334 } 1335 1336 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1337 1, 0, /* alignment, boundary */ 1338 BUS_SPACE_MAXADDR, /* lowaddr */ 1339 BUS_SPACE_MAXADDR, /* highaddr */ 1340 NULL, NULL, /* filter, filterarg */ 1341 MCLBYTES, 1, /* maxsize,nsegments */ 1342 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1343 0, /* flags */ 1344 busdma_lock_mutex, /* lockfunc */ 1345 &Giant, /* lockarg */ 1346 &sc->sis_tag); 1347 if (error) 1348 goto fail; 1349 1350 /* 1351 * Obtain the physical addresses of the RX and TX 1352 * rings which we'll need later in the init routine. 1353 */ 1354 1355 ifp = &sc->arpcom.ac_if; 1356 ifp->if_softc = sc; 1357 ifp->if_unit = unit; 1358 ifp->if_name = "sis"; 1359 ifp->if_mtu = ETHERMTU; 1360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1361 ifp->if_ioctl = sis_ioctl; 1362 ifp->if_output = ether_output; 1363 ifp->if_start = sis_start; 1364 ifp->if_watchdog = sis_watchdog; 1365 ifp->if_init = sis_init; 1366 ifp->if_baudrate = 10000000; 1367 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1368 1369 /* 1370 * Do MII setup. 1371 */ 1372 if (mii_phy_probe(dev, &sc->sis_miibus, 1373 sis_ifmedia_upd, sis_ifmedia_sts)) { 1374 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1375 error = ENXIO; 1376 goto fail; 1377 } 1378 1379 /* 1380 * Call MI attach routine. 1381 */ 1382 ether_ifattach(ifp, eaddr); 1383 1384 /* 1385 * Tell the upper layer(s) we support long frames. 1386 */ 1387 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1388 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1389 1390 /* Hook interrupt last to avoid having to lock softc */ 1391 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1392 sis_intr, sc, &sc->sis_intrhand); 1393 1394 if (error) { 1395 printf("sis%d: couldn't set up irq\n", unit); 1396 ether_ifdetach(ifp); 1397 goto fail; 1398 } 1399 1400fail: 1401 if (error) 1402 sis_detach(dev); 1403 1404 return(error); 1405} 1406 1407/* 1408 * Shutdown hardware and free up resources. This can be called any 1409 * time after the mutex has been initialized. It is called in both 1410 * the error case in attach and the normal detach case so it needs 1411 * to be careful about only freeing resources that have actually been 1412 * allocated. 1413 */ 1414static int 1415sis_detach(dev) 1416 device_t dev; 1417{ 1418 struct sis_softc *sc; 1419 struct ifnet *ifp; 1420 1421 sc = device_get_softc(dev); 1422 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1423 SIS_LOCK(sc); 1424 ifp = &sc->arpcom.ac_if; 1425 1426 /* These should only be active if attach succeeded. */ 1427 if (device_is_attached(dev)) { 1428 sis_reset(sc); 1429 sis_stop(sc); 1430 ether_ifdetach(ifp); 1431 } 1432 if (sc->sis_miibus) 1433 device_delete_child(dev, sc->sis_miibus); 1434 bus_generic_detach(dev); 1435 1436 if (sc->sis_intrhand) 1437 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1438 if (sc->sis_irq) 1439 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1440 if (sc->sis_res) 1441 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1442 1443 if (sc->sis_ldata.sis_rx_tag) { 1444 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1445 sc->sis_ldata.sis_rx_dmamap); 1446 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1447 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1448 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1449 } 1450 if (sc->sis_ldata.sis_tx_tag) { 1451 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1452 sc->sis_ldata.sis_tx_dmamap); 1453 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1454 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1455 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1456 } 1457 if (sc->sis_parent_tag) 1458 bus_dma_tag_destroy(sc->sis_parent_tag); 1459 if (sc->sis_tag) 1460 bus_dma_tag_destroy(sc->sis_tag); 1461 1462 SIS_UNLOCK(sc); 1463 mtx_destroy(&sc->sis_mtx); 1464 1465 return(0); 1466} 1467 1468/* 1469 * Initialize the transmit descriptors. 1470 */ 1471static int 1472sis_list_tx_init(sc) 1473 struct sis_softc *sc; 1474{ 1475 struct sis_list_data *ld; 1476 struct sis_ring_data *cd; 1477 int i, nexti; 1478 1479 cd = &sc->sis_cdata; 1480 ld = &sc->sis_ldata; 1481 1482 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1483 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1484 ld->sis_tx_list[i].sis_nextdesc = 1485 &ld->sis_tx_list[nexti]; 1486 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1487 sc->sis_ldata.sis_tx_dmamap, 1488 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1489 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1490 ld->sis_tx_list[i].sis_mbuf = NULL; 1491 ld->sis_tx_list[i].sis_ptr = 0; 1492 ld->sis_tx_list[i].sis_ctl = 0; 1493 } 1494 1495 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1496 1497 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1498 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1499 1500 return(0); 1501} 1502 1503/* 1504 * Initialize the RX descriptors and allocate mbufs for them. Note that 1505 * we arrange the descriptors in a closed ring, so that the last descriptor 1506 * points back to the first. 1507 */ 1508static int 1509sis_list_rx_init(sc) 1510 struct sis_softc *sc; 1511{ 1512 struct sis_list_data *ld; 1513 struct sis_ring_data *cd; 1514 int i,nexti; 1515 1516 ld = &sc->sis_ldata; 1517 cd = &sc->sis_cdata; 1518 1519 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1520 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1521 return(ENOBUFS); 1522 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1523 ld->sis_rx_list[i].sis_nextdesc = 1524 &ld->sis_rx_list[nexti]; 1525 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1526 sc->sis_ldata.sis_rx_dmamap, 1527 &ld->sis_rx_list[nexti], 1528 sizeof(struct sis_desc), sis_dma_map_desc_next, 1529 &ld->sis_rx_list[i], 0); 1530 } 1531 1532 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1533 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1534 1535 cd->sis_rx_prod = 0; 1536 1537 return(0); 1538} 1539 1540/* 1541 * Initialize an RX descriptor and attach an MBUF cluster. 1542 */ 1543static int 1544sis_newbuf(sc, c, m) 1545 struct sis_softc *sc; 1546 struct sis_desc *c; 1547 struct mbuf *m; 1548{ 1549 1550 if (c == NULL) 1551 return(EINVAL); 1552 1553 if (m == NULL) { 1554 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1555 if (m == NULL) 1556 return(ENOBUFS); 1557 } else 1558 m->m_data = m->m_ext.ext_buf; 1559 1560 c->sis_mbuf = m; 1561 c->sis_ctl = SIS_RXLEN; 1562 1563 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1564 bus_dmamap_load(sc->sis_tag, c->sis_map, 1565 mtod(m, void *), MCLBYTES, 1566 sis_dma_map_desc_ptr, c, 0); 1567 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1568 1569 return(0); 1570} 1571 1572/* 1573 * A frame has been uploaded: pass the resulting mbuf chain up to 1574 * the higher level protocols. 1575 */ 1576static void 1577sis_rxeof(sc) 1578 struct sis_softc *sc; 1579{ 1580 struct mbuf *m; 1581 struct ifnet *ifp; 1582 struct sis_desc *cur_rx; 1583 int i, total_len = 0; 1584 u_int32_t rxstat; 1585 1586 ifp = &sc->arpcom.ac_if; 1587 i = sc->sis_cdata.sis_rx_prod; 1588 1589 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1590 1591#ifdef DEVICE_POLLING 1592 if (ifp->if_flags & IFF_POLLING) { 1593 if (sc->rxcycles <= 0) 1594 break; 1595 sc->rxcycles--; 1596 } 1597#endif /* DEVICE_POLLING */ 1598 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1599 rxstat = cur_rx->sis_rxstat; 1600 bus_dmamap_sync(sc->sis_tag, 1601 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1602 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1603 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1604 m = cur_rx->sis_mbuf; 1605 cur_rx->sis_mbuf = NULL; 1606 total_len = SIS_RXBYTES(cur_rx); 1607 SIS_INC(i, SIS_RX_LIST_CNT); 1608 1609 /* 1610 * If an error occurs, update stats, clear the 1611 * status word and leave the mbuf cluster in place: 1612 * it should simply get re-used next time this descriptor 1613 * comes up in the ring. 1614 */ 1615 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1616 ifp->if_ierrors++; 1617 if (rxstat & SIS_RXSTAT_COLL) 1618 ifp->if_collisions++; 1619 sis_newbuf(sc, cur_rx, m); 1620 continue; 1621 } 1622 1623 /* No errors; receive the packet. */ 1624#ifdef __i386__ 1625 /* 1626 * On the x86 we do not have alignment problems, so try to 1627 * allocate a new buffer for the receive ring, and pass up 1628 * the one where the packet is already, saving the expensive 1629 * copy done in m_devget(). 1630 * If we are on an architecture with alignment problems, or 1631 * if the allocation fails, then use m_devget and leave the 1632 * existing buffer in the receive ring. 1633 */ 1634 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1635 m->m_pkthdr.len = m->m_len = total_len; 1636 else 1637#endif 1638 { 1639 struct mbuf *m0; 1640 m0 = m_devget(mtod(m, char *), total_len, 1641 ETHER_ALIGN, ifp, NULL); 1642 sis_newbuf(sc, cur_rx, m); 1643 if (m0 == NULL) { 1644 ifp->if_ierrors++; 1645 continue; 1646 } 1647 m = m0; 1648 } 1649 1650 ifp->if_ipackets++; 1651 m->m_pkthdr.rcvif = ifp; 1652 1653 (*ifp->if_input)(ifp, m); 1654 } 1655 1656 sc->sis_cdata.sis_rx_prod = i; 1657 1658 return; 1659} 1660 1661static void 1662sis_rxeoc(sc) 1663 struct sis_softc *sc; 1664{ 1665 sis_rxeof(sc); 1666 sis_init(sc); 1667 return; 1668} 1669 1670/* 1671 * A frame was downloaded to the chip. It's safe for us to clean up 1672 * the list buffers. 1673 */ 1674 1675static void 1676sis_txeof(sc) 1677 struct sis_softc *sc; 1678{ 1679 struct ifnet *ifp; 1680 u_int32_t idx; 1681 1682 ifp = &sc->arpcom.ac_if; 1683 1684 /* 1685 * Go through our tx list and free mbufs for those 1686 * frames that have been transmitted. 1687 */ 1688 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1689 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1690 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1691 1692 if (SIS_OWNDESC(cur_tx)) 1693 break; 1694 1695 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1696 continue; 1697 1698 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1699 ifp->if_oerrors++; 1700 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1701 ifp->if_collisions++; 1702 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1703 ifp->if_collisions++; 1704 } 1705 1706 ifp->if_collisions += 1707 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1708 1709 ifp->if_opackets++; 1710 if (cur_tx->sis_mbuf != NULL) { 1711 m_freem(cur_tx->sis_mbuf); 1712 cur_tx->sis_mbuf = NULL; 1713 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1714 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1715 } 1716 } 1717 1718 if (idx != sc->sis_cdata.sis_tx_cons) { 1719 /* we freed up some buffers */ 1720 sc->sis_cdata.sis_tx_cons = idx; 1721 ifp->if_flags &= ~IFF_OACTIVE; 1722 } 1723 1724 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1725 1726 return; 1727} 1728 1729static void 1730sis_tick(xsc) 1731 void *xsc; 1732{ 1733 struct sis_softc *sc; 1734 struct mii_data *mii; 1735 struct ifnet *ifp; 1736 1737 sc = xsc; 1738 SIS_LOCK(sc); 1739 sc->in_tick = 1; 1740 ifp = &sc->arpcom.ac_if; 1741 1742 mii = device_get_softc(sc->sis_miibus); 1743 mii_tick(mii); 1744 1745 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1746 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1747 sc->sis_link++; 1748 if (ifp->if_snd.ifq_head != NULL) 1749 sis_start(ifp); 1750 } 1751 1752 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1753 sc->in_tick = 0; 1754 SIS_UNLOCK(sc); 1755 1756 return; 1757} 1758 1759#ifdef DEVICE_POLLING 1760static poll_handler_t sis_poll; 1761 1762static void 1763sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1764{ 1765 struct sis_softc *sc = ifp->if_softc; 1766 1767 SIS_LOCK(sc); 1768 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1769 CSR_WRITE_4(sc, SIS_IER, 1); 1770 goto done; 1771 } 1772 1773 /* 1774 * On the sis, reading the status register also clears it. 1775 * So before returning to intr mode we must make sure that all 1776 * possible pending sources of interrupts have been served. 1777 * In practice this means run to completion the *eof routines, 1778 * and then call the interrupt routine 1779 */ 1780 sc->rxcycles = count; 1781 sis_rxeof(sc); 1782 sis_txeof(sc); 1783 if (ifp->if_snd.ifq_head != NULL) 1784 sis_start(ifp); 1785 1786 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1787 u_int32_t status; 1788 1789 /* Reading the ISR register clears all interrupts. */ 1790 status = CSR_READ_4(sc, SIS_ISR); 1791 1792 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1793 sis_rxeoc(sc); 1794 1795 if (status & (SIS_ISR_RX_IDLE)) 1796 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1797 1798 if (status & SIS_ISR_SYSERR) { 1799 sis_reset(sc); 1800 sis_init(sc); 1801 } 1802 } 1803done: 1804 SIS_UNLOCK(sc); 1805 return; 1806} 1807#endif /* DEVICE_POLLING */ 1808 1809static void 1810sis_intr(arg) 1811 void *arg; 1812{ 1813 struct sis_softc *sc; 1814 struct ifnet *ifp; 1815 u_int32_t status; 1816 1817 sc = arg; 1818 ifp = &sc->arpcom.ac_if; 1819 1820 SIS_LOCK(sc); 1821#ifdef DEVICE_POLLING 1822 if (ifp->if_flags & IFF_POLLING) 1823 goto done; 1824 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1825 CSR_WRITE_4(sc, SIS_IER, 0); 1826 goto done; 1827 } 1828#endif /* DEVICE_POLLING */ 1829 1830 /* Supress unwanted interrupts */ 1831 if (!(ifp->if_flags & IFF_UP)) { 1832 sis_stop(sc); 1833 goto done; 1834 } 1835 1836 /* Disable interrupts. */ 1837 CSR_WRITE_4(sc, SIS_IER, 0); 1838 1839 for (;;) { 1840 /* Reading the ISR register clears all interrupts. */ 1841 status = CSR_READ_4(sc, SIS_ISR); 1842 1843 if ((status & SIS_INTRS) == 0) 1844 break; 1845 1846 if (status & 1847 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1848 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1849 sis_txeof(sc); 1850 1851 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1852 sis_rxeof(sc); 1853 1854 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1855 sis_rxeoc(sc); 1856 1857 if (status & (SIS_ISR_RX_IDLE)) 1858 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1859 1860 if (status & SIS_ISR_SYSERR) { 1861 sis_reset(sc); 1862 sis_init(sc); 1863 } 1864 } 1865 1866 /* Re-enable interrupts. */ 1867 CSR_WRITE_4(sc, SIS_IER, 1); 1868 1869 if (ifp->if_snd.ifq_head != NULL) 1870 sis_start(ifp); 1871done: 1872 SIS_UNLOCK(sc); 1873 1874 return; 1875} 1876 1877/* 1878 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1879 * pointers to the fragment pointers. 1880 */ 1881static int 1882sis_encap(sc, m_head, txidx) 1883 struct sis_softc *sc; 1884 struct mbuf *m_head; 1885 u_int32_t *txidx; 1886{ 1887 struct sis_desc *f = NULL; 1888 struct mbuf *m; 1889 int frag, cur, cnt = 0, chainlen = 0; 1890 1891 /* 1892 * If there's no way we can send any packets, return now. 1893 */ 1894 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1895 return (ENOBUFS); 1896 1897 /* 1898 * Count the number of frags in this chain to see if 1899 * we need to m_defrag. Since the descriptor list is shared 1900 * by all packets, we'll m_defrag long chains so that they 1901 * do not use up the entire list, even if they would fit. 1902 */ 1903 1904 for (m = m_head; m != NULL; m = m->m_next) 1905 chainlen++; 1906 1907 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1908 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1909 m = m_defrag(m_head, M_DONTWAIT); 1910 if (m == NULL) 1911 return (ENOBUFS); 1912 m_head = m; 1913 } 1914 1915 /* 1916 * Start packing the mbufs in this chain into 1917 * the fragment pointers. Stop when we run out 1918 * of fragments or hit the end of the mbuf chain. 1919 */ 1920 m = m_head; 1921 cur = frag = *txidx; 1922 1923 for (m = m_head; m != NULL; m = m->m_next) { 1924 if (m->m_len != 0) { 1925 if ((SIS_TX_LIST_CNT - 1926 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1927 return(ENOBUFS); 1928 f = &sc->sis_ldata.sis_tx_list[frag]; 1929 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1930 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1931 bus_dmamap_load(sc->sis_tag, f->sis_map, 1932 mtod(m, void *), m->m_len, 1933 sis_dma_map_desc_ptr, f, 0); 1934 bus_dmamap_sync(sc->sis_tag, 1935 f->sis_map, BUS_DMASYNC_PREREAD); 1936 if (cnt != 0) 1937 f->sis_ctl |= SIS_CMDSTS_OWN; 1938 cur = frag; 1939 SIS_INC(frag, SIS_TX_LIST_CNT); 1940 cnt++; 1941 } 1942 } 1943 1944 if (m != NULL) 1945 return(ENOBUFS); 1946 1947 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1948 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1949 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1950 sc->sis_cdata.sis_tx_cnt += cnt; 1951 *txidx = frag; 1952 1953 return(0); 1954} 1955 1956/* 1957 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1958 * to the mbuf data regions directly in the transmit lists. We also save a 1959 * copy of the pointers since the transmit list fragment pointers are 1960 * physical addresses. 1961 */ 1962 1963static void 1964sis_start(ifp) 1965 struct ifnet *ifp; 1966{ 1967 struct sis_softc *sc; 1968 struct mbuf *m_head = NULL; 1969 u_int32_t idx; 1970 1971 sc = ifp->if_softc; 1972 SIS_LOCK(sc); 1973 1974 if (!sc->sis_link) { 1975 SIS_UNLOCK(sc); 1976 return; 1977 } 1978 1979 idx = sc->sis_cdata.sis_tx_prod; 1980 1981 if (ifp->if_flags & IFF_OACTIVE) { 1982 SIS_UNLOCK(sc); 1983 return; 1984 } 1985 1986 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1987 IF_DEQUEUE(&ifp->if_snd, m_head); 1988 if (m_head == NULL) 1989 break; 1990 1991 if (sis_encap(sc, m_head, &idx)) { 1992 IF_PREPEND(&ifp->if_snd, m_head); 1993 ifp->if_flags |= IFF_OACTIVE; 1994 break; 1995 } 1996 1997 /* 1998 * If there's a BPF listener, bounce a copy of this frame 1999 * to him. 2000 */ 2001 BPF_MTAP(ifp, m_head); 2002 2003 } 2004 2005 /* Transmit */ 2006 sc->sis_cdata.sis_tx_prod = idx; 2007 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 2008 2009 /* 2010 * Set a timeout in case the chip goes out to lunch. 2011 */ 2012 ifp->if_timer = 5; 2013 2014 SIS_UNLOCK(sc); 2015 2016 return; 2017} 2018 2019static void 2020sis_init(xsc) 2021 void *xsc; 2022{ 2023 struct sis_softc *sc = xsc; 2024 struct ifnet *ifp = &sc->arpcom.ac_if; 2025 struct mii_data *mii; 2026 2027 SIS_LOCK(sc); 2028 2029 /* 2030 * Cancel pending I/O and free all RX/TX buffers. 2031 */ 2032 sis_stop(sc); 2033 2034 mii = device_get_softc(sc->sis_miibus); 2035 2036 /* Set MAC address */ 2037 if (sc->sis_type == SIS_TYPE_83815) { 2038 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2039 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2040 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2041 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2042 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2043 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2044 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2045 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2046 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2047 } else { 2048 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2049 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2050 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2051 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2052 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2053 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2054 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2055 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2056 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2057 } 2058 2059 /* Init circular RX list. */ 2060 if (sis_list_rx_init(sc) == ENOBUFS) { 2061 printf("sis%d: initialization failed: no " 2062 "memory for rx buffers\n", sc->sis_unit); 2063 sis_stop(sc); 2064 SIS_UNLOCK(sc); 2065 return; 2066 } 2067 2068 /* 2069 * Init tx descriptors. 2070 */ 2071 sis_list_tx_init(sc); 2072 2073 /* 2074 * For the NatSemi chip, we have to explicitly enable the 2075 * reception of ARP frames, as well as turn on the 'perfect 2076 * match' filter where we store the station address, otherwise 2077 * we won't receive unicasts meant for this host. 2078 */ 2079 if (sc->sis_type == SIS_TYPE_83815) { 2080 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2081 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2082 } 2083 2084 /* If we want promiscuous mode, set the allframes bit. */ 2085 if (ifp->if_flags & IFF_PROMISC) { 2086 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2087 } else { 2088 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2089 } 2090 2091 /* 2092 * Set the capture broadcast bit to capture broadcast frames. 2093 */ 2094 if (ifp->if_flags & IFF_BROADCAST) { 2095 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2096 } else { 2097 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2098 } 2099 2100 /* 2101 * Load the multicast filter. 2102 */ 2103 if (sc->sis_type == SIS_TYPE_83815) 2104 sis_setmulti_ns(sc); 2105 else 2106 sis_setmulti_sis(sc); 2107 2108 /* Turn the receive filter on */ 2109 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2110 2111 /* 2112 * Load the address of the RX and TX lists. 2113 */ 2114 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2115 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2116 2117 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2118 * the PCI bus. When this bit is set, the Max DMA Burst Size 2119 * for TX/RX DMA should be no larger than 16 double words. 2120 */ 2121 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2122 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2123 } else { 2124 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2125 } 2126 2127 2128 /* Accept Long Packets for VLAN support */ 2129 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2130 2131 /* Set TX configuration */ 2132 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2133 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2134 } else { 2135 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2136 } 2137 2138 /* Set full/half duplex mode. */ 2139 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2140 SIS_SETBIT(sc, SIS_TX_CFG, 2141 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2142 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2143 } else { 2144 SIS_CLRBIT(sc, SIS_TX_CFG, 2145 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2146 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2147 } 2148 2149 /* 2150 * Enable interrupts. 2151 */ 2152 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2153#ifdef DEVICE_POLLING 2154 /* 2155 * ... only enable interrupts if we are not polling, make sure 2156 * they are off otherwise. 2157 */ 2158 if (ifp->if_flags & IFF_POLLING) 2159 CSR_WRITE_4(sc, SIS_IER, 0); 2160 else 2161#endif /* DEVICE_POLLING */ 2162 CSR_WRITE_4(sc, SIS_IER, 1); 2163 2164 /* Enable receiver and transmitter. */ 2165 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2166 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2167 2168#ifdef notdef 2169 mii_mediachg(mii); 2170#endif 2171 2172 /* 2173 * Page 75 of the DP83815 manual recommends the 2174 * following register settings "for optimum 2175 * performance." Note however that at least three 2176 * of the registers are listed as "reserved" in 2177 * the register map, so who knows what they do. 2178 */ 2179 if (sc->sis_type == SIS_TYPE_83815) { 2180 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2181 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2182 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2183 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2184 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2185 } 2186 2187 ifp->if_flags |= IFF_RUNNING; 2188 ifp->if_flags &= ~IFF_OACTIVE; 2189 2190 if (!sc->in_tick) 2191 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 2192 2193 SIS_UNLOCK(sc); 2194 2195 return; 2196} 2197 2198/* 2199 * Set media options. 2200 */ 2201static int 2202sis_ifmedia_upd(ifp) 2203 struct ifnet *ifp; 2204{ 2205 struct sis_softc *sc; 2206 struct mii_data *mii; 2207 2208 sc = ifp->if_softc; 2209 2210 mii = device_get_softc(sc->sis_miibus); 2211 sc->sis_link = 0; 2212 if (mii->mii_instance) { 2213 struct mii_softc *miisc; 2214 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2215 mii_phy_reset(miisc); 2216 } 2217 mii_mediachg(mii); 2218 2219 return(0); 2220} 2221 2222/* 2223 * Report current media status. 2224 */ 2225static void 2226sis_ifmedia_sts(ifp, ifmr) 2227 struct ifnet *ifp; 2228 struct ifmediareq *ifmr; 2229{ 2230 struct sis_softc *sc; 2231 struct mii_data *mii; 2232 2233 sc = ifp->if_softc; 2234 2235 mii = device_get_softc(sc->sis_miibus); 2236 mii_pollstat(mii); 2237 ifmr->ifm_active = mii->mii_media_active; 2238 ifmr->ifm_status = mii->mii_media_status; 2239 2240 return; 2241} 2242 2243static int 2244sis_ioctl(ifp, command, data) 2245 struct ifnet *ifp; 2246 u_long command; 2247 caddr_t data; 2248{ 2249 struct sis_softc *sc = ifp->if_softc; 2250 struct ifreq *ifr = (struct ifreq *) data; 2251 struct mii_data *mii; 2252 int error = 0; 2253 2254 switch(command) { 2255 case SIOCSIFFLAGS: 2256 if (ifp->if_flags & IFF_UP) { 2257 sis_init(sc); 2258 } else { 2259 if (ifp->if_flags & IFF_RUNNING) 2260 sis_stop(sc); 2261 } 2262 error = 0; 2263 break; 2264 case SIOCADDMULTI: 2265 case SIOCDELMULTI: 2266 SIS_LOCK(sc); 2267 if (sc->sis_type == SIS_TYPE_83815) 2268 sis_setmulti_ns(sc); 2269 else 2270 sis_setmulti_sis(sc); 2271 SIS_UNLOCK(sc); 2272 error = 0; 2273 break; 2274 case SIOCGIFMEDIA: 2275 case SIOCSIFMEDIA: 2276 mii = device_get_softc(sc->sis_miibus); 2277 SIS_LOCK(sc); 2278 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2279 SIS_UNLOCK(sc); 2280 break; 2281 default: 2282 error = ether_ioctl(ifp, command, data); 2283 break; 2284 } 2285 2286 return(error); 2287} 2288 2289static void 2290sis_watchdog(ifp) 2291 struct ifnet *ifp; 2292{ 2293 struct sis_softc *sc; 2294 2295 sc = ifp->if_softc; 2296 2297 SIS_LOCK(sc); 2298 2299 ifp->if_oerrors++; 2300 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2301 2302 sis_stop(sc); 2303 sis_reset(sc); 2304 sis_init(sc); 2305 2306 if (ifp->if_snd.ifq_head != NULL) 2307 sis_start(ifp); 2308 2309 SIS_UNLOCK(sc); 2310 2311 return; 2312} 2313 2314/* 2315 * Stop the adapter and free any mbufs allocated to the 2316 * RX and TX lists. 2317 */ 2318static void 2319sis_stop(sc) 2320 struct sis_softc *sc; 2321{ 2322 register int i; 2323 struct ifnet *ifp; 2324 2325 SIS_LOCK(sc); 2326 ifp = &sc->arpcom.ac_if; 2327 ifp->if_timer = 0; 2328 2329 untimeout(sis_tick, sc, sc->sis_stat_ch); 2330 2331 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2332#ifdef DEVICE_POLLING 2333 ether_poll_deregister(ifp); 2334#endif 2335 CSR_WRITE_4(sc, SIS_IER, 0); 2336 CSR_WRITE_4(sc, SIS_IMR, 0); 2337 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2338 DELAY(1000); 2339 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2340 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2341 2342 sc->sis_link = 0; 2343 2344 /* 2345 * Free data in the RX lists. 2346 */ 2347 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2348 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2349 bus_dmamap_unload(sc->sis_tag, 2350 sc->sis_ldata.sis_rx_list[i].sis_map); 2351 bus_dmamap_destroy(sc->sis_tag, 2352 sc->sis_ldata.sis_rx_list[i].sis_map); 2353 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2354 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2355 } 2356 } 2357 bzero(sc->sis_ldata.sis_rx_list, 2358 sizeof(sc->sis_ldata.sis_rx_list)); 2359 2360 /* 2361 * Free the TX list buffers. 2362 */ 2363 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2364 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2365 bus_dmamap_unload(sc->sis_tag, 2366 sc->sis_ldata.sis_tx_list[i].sis_map); 2367 bus_dmamap_destroy(sc->sis_tag, 2368 sc->sis_ldata.sis_tx_list[i].sis_map); 2369 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2370 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2371 } 2372 } 2373 2374 bzero(sc->sis_ldata.sis_tx_list, 2375 sizeof(sc->sis_ldata.sis_tx_list)); 2376 2377 SIS_UNLOCK(sc); 2378 2379 return; 2380} 2381 2382/* 2383 * Stop all chip I/O so that the kernel's probe routines don't 2384 * get confused by errant DMAs when rebooting. 2385 */ 2386static void 2387sis_shutdown(dev) 2388 device_t dev; 2389{ 2390 struct sis_softc *sc; 2391 2392 sc = device_get_softc(dev); 2393 SIS_LOCK(sc); 2394 sis_reset(sc); 2395 sis_stop(sc); 2396 SIS_UNLOCK(sc); 2397 2398 return; 2399} 2400