if_sis.c revision 113038
146432Sphk/* 246432Sphk * Copyright (c) 1997, 1998, 1999 346432Sphk * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 446432Sphk * 546432Sphk * Redistribution and use in source and binary forms, with or without 646432Sphk * modification, are permitted provided that the following conditions 746432Sphk * are met: 846432Sphk * 1. Redistributions of source code must retain the above copyright 946432Sphk * notice, this list of conditions and the following disclaimer. 10117280Scharnier * 2. Redistributions in binary form must reproduce the above copyright 11117280Scharnier * notice, this list of conditions and the following disclaimer in the 12117280Scharnier * documentation and/or other materials provided with the distribution. 13112705Smaxim * 3. All advertising materials mentioning features or use of this software 1446155Sphk * must display the following acknowledgement: 1578723Sdd * This product includes software developed by Bill Paul. 1646155Sphk * 4. Neither the name of the author nor the names of any co-contributors 1778723Sdd * may be used to endorse or promote products derived from this software 1846155Sphk * without specific prior written permission. 1978723Sdd * 20129848Smaxim * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21112705Smaxim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22112705Smaxim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23133743Smaxim * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24112705Smaxim * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2578723Sdd * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2678723Sdd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2778723Sdd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2878723Sdd * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2978723Sdd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30112705Smaxim * THE POSSIBILITY OF SUCH DAMAGE. 31133743Smaxim * 32112705Smaxim * $FreeBSD: head/sys/pci/if_sis.c 113038 2003-04-03 21:36:33Z obrien $ 33129848Smaxim */ 34129848Smaxim 35129848Smaxim/* 36129848Smaxim * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37129848Smaxim * available from http://www.sis.com.tw. 38129848Smaxim * 39129848Smaxim * This driver also supports the NatSemi DP83815. Datasheets are 40129848Smaxim * available from http://www.national.com. 41129848Smaxim * 42129848Smaxim * Written by Bill Paul <wpaul@ee.columbia.edu> 43129848Smaxim * Electrical Engineering Department 44129848Smaxim * Columbia University, New York City 45129848Smaxim */ 46129848Smaxim 47129848Smaxim/* 48129848Smaxim * The SiS 900 is a fairly simple chip. It uses bus master DMA with 4946155Sphk * simple TX and RX descriptors of 3 longwords in size. The receiver 5046155Sphk * has a single perfect filter entry for the station address and a 5146155Sphk * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52137808Sdelphij * transceiver while the 7016 requires an external transceiver chip. 5346155Sphk * Both chips offer the standard bit-bang MII interface as well as 54137808Sdelphij * an enchanced PHY interface which simplifies accessing MII registers. 5546155Sphk * 56136051Sstefanf * The only downside to this chipset is that RX descriptors must be 57153056Sphilip * longword aligned. 58153056Sphilip */ 59133743Smaxim 60137807Sdelphij#include <sys/cdefs.h> 61153056Sphilip__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 113038 2003-04-03 21:36:33Z obrien $"); 6246155Sphk 63153056Sphilip#include <sys/param.h> 64153056Sphilip#include <sys/systm.h> 65153056Sphilip#include <sys/sockio.h> 66112705Smaxim#include <sys/mbuf.h> 67153056Sphilip#include <sys/malloc.h> 68112705Smaxim#include <sys/kernel.h> 69113277Smike#include <sys/socket.h> 70113277Smike#include <sys/sysctl.h> 71113277Smike 72153056Sphilip#include <net/if.h> 73153056Sphilip#include <net/if_arp.h> 74153056Sphilip#include <net/ethernet.h> 75153056Sphilip#include <net/if_dl.h> 76112705Smaxim#include <net/if_media.h> 77112705Smaxim#include <net/if_types.h> 78129848Smaxim#include <net/if_vlan_var.h> 79112705Smaxim 80129848Smaxim#include <net/bpf.h> 81129848Smaxim 82129848Smaxim#include <machine/bus_pio.h> 83129848Smaxim#include <machine/bus_memio.h> 84133743Smaxim#include <machine/bus.h> 85133743Smaxim#include <machine/resource.h> 86133743Smaxim#include <sys/bus.h> 87112705Smaxim#include <sys/rman.h> 88112705Smaxim 89112705Smaxim#include <dev/mii/mii.h> 90113277Smike#include <dev/mii/miivar.h> 91112705Smaxim 92112705Smaxim#include <pci/pcireg.h> 93112705Smaxim#include <pci/pcivar.h> 94112705Smaxim 95129848Smaxim#define SIS_USEIOSPACE 96129848Smaxim 97133743Smaxim#include <pci/if_sisreg.h> 98133743Smaxim 99129848SmaximMODULE_DEPEND(sis, miibus, 1, 1, 1); 100129848Smaxim 101131182Spjd/* "controller miibus0" required. See GENERIC if you get errors here. */ 102131182Spjd#include "miibus_if.h" 103131182Spjd 104131182Spjd/* 10551399Sphk * Various supported device vendors/types and their names. 10651399Sphk */ 107131182Spjdstatic struct sis_type sis_devs[] = { 108112705Smaxim { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 109112972Smaxim { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 110112972Smaxim { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 11146432Sphk { 0, 0, NULL } 112153056Sphilip}; 113153056Sphilip 114153056Sphilipstatic int sis_probe (device_t); 115153056Sphilipstatic int sis_attach (device_t); 116153056Sphilipstatic int sis_detach (device_t); 117113277Smike 118113277Smikestatic int sis_newbuf (struct sis_softc *, 119112972Smaxim struct sis_desc *, struct mbuf *); 120113804Smikestatic int sis_encap (struct sis_softc *, 121113277Smike struct mbuf *, u_int32_t *); 122113804Smikestatic void sis_rxeof (struct sis_softc *); 123113804Smikestatic void sis_rxeoc (struct sis_softc *); 124153056Sphilipstatic void sis_txeof (struct sis_softc *); 125153056Sphilipstatic void sis_intr (void *); 126153056Sphilipstatic void sis_tick (void *); 127153056Sphilipstatic void sis_start (struct ifnet *); 128153056Sphilipstatic int sis_ioctl (struct ifnet *, u_long, caddr_t); 129153056Sphilipstatic void sis_init (void *); 130153056Sphilipstatic void sis_stop (struct sis_softc *); 131153056Sphilipstatic void sis_watchdog (struct ifnet *); 132153056Sphilipstatic void sis_shutdown (device_t); 133112705Smaximstatic int sis_ifmedia_upd (struct ifnet *); 134129848Smaximstatic void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 135129848Smaxim 136133743Smaximstatic u_int16_t sis_reverse (u_int16_t); 137133743Smaximstatic void sis_delay (struct sis_softc *); 138133743Smaximstatic void sis_eeprom_idle (struct sis_softc *); 139133743Smaximstatic void sis_eeprom_putbyte (struct sis_softc *, int); 140112972Smaximstatic void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 141112972Smaximstatic void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 142112972Smaxim#ifdef __i386__ 143112972Smaximstatic void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 144112972Smaxim int, int); 145157790Smaximstatic void sis_read_mac (struct sis_softc *, device_t, caddr_t); 146112972Smaximstatic device_t sis_find_bridge (device_t); 147113206Smaxim#endif 148112705Smaxim 149133743Smaximstatic void sis_mii_sync (struct sis_softc *); 150133743Smaximstatic void sis_mii_send (struct sis_softc *, u_int32_t, int); 151133743Smaximstatic int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 152133743Smaximstatic int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 153133743Smaximstatic int sis_miibus_readreg (device_t, int, int); 154133743Smaximstatic int sis_miibus_writereg (device_t, int, int, int); 155133743Smaximstatic void sis_miibus_statchg (device_t); 156133743Smaxim 157133743Smaximstatic void sis_setmulti_sis (struct sis_softc *); 158133743Smaximstatic void sis_setmulti_ns (struct sis_softc *); 159133743Smaximstatic u_int32_t sis_crc (struct sis_softc *, caddr_t); 160133743Smaximstatic void sis_reset (struct sis_softc *); 161133743Smaximstatic int sis_list_rx_init (struct sis_softc *); 162112972Smaximstatic int sis_list_tx_init (struct sis_softc *); 163112972Smaxim 164113277Smikestatic void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 16546155Sphkstatic void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 166112705Smaximstatic void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 167112705Smaxim#ifdef SIS_USEIOSPACE 168112705Smaxim#define SIS_RES SYS_RES_IOPORT 169112705Smaxim#define SIS_RID SIS_PCI_LOIO 170112705Smaxim#else 171129848Smaxim#define SIS_RES SYS_RES_MEMORY 172153056Sphilip#define SIS_RID SIS_PCI_LOMEM 173129848Smaxim#endif 174112972Smaxim 175112705Smaximstatic device_method_t sis_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, sis_probe), 178 DEVMETHOD(device_attach, sis_attach), 179 DEVMETHOD(device_detach, sis_detach), 180 DEVMETHOD(device_shutdown, sis_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 188 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 189 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 190 191 { 0, 0 } 192}; 193 194static driver_t sis_driver = { 195 "sis", 196 sis_methods, 197 sizeof(struct sis_softc) 198}; 199 200static devclass_t sis_devclass; 201 202DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 203DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 204 205#define SIS_SETBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, \ 207 CSR_READ_4(sc, reg) | (x)) 208 209#define SIS_CLRBIT(sc, reg, x) \ 210 CSR_WRITE_4(sc, reg, \ 211 CSR_READ_4(sc, reg) & ~(x)) 212 213#define SIO_SET(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 215 216#define SIO_CLR(x) \ 217 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 218 219static void 220sis_dma_map_desc_next(arg, segs, nseg, error) 221 void *arg; 222 bus_dma_segment_t *segs; 223 int nseg, error; 224{ 225 struct sis_desc *r; 226 227 r = arg; 228 r->sis_next = segs->ds_addr; 229 230 return; 231} 232 233static void 234sis_dma_map_desc_ptr(arg, segs, nseg, error) 235 void *arg; 236 bus_dma_segment_t *segs; 237 int nseg, error; 238{ 239 struct sis_desc *r; 240 241 r = arg; 242 r->sis_ptr = segs->ds_addr; 243 244 return; 245} 246 247static void 248sis_dma_map_ring(arg, segs, nseg, error) 249 void *arg; 250 bus_dma_segment_t *segs; 251 int nseg, error; 252{ 253 u_int32_t *p; 254 255 p = arg; 256 *p = segs->ds_addr; 257 258 return; 259} 260 261/* 262 * Routine to reverse the bits in a word. Stolen almost 263 * verbatim from /usr/games/fortune. 264 */ 265static u_int16_t 266sis_reverse(n) 267 u_int16_t n; 268{ 269 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 270 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 271 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 272 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 273 274 return(n); 275} 276 277static void 278sis_delay(sc) 279 struct sis_softc *sc; 280{ 281 int idx; 282 283 for (idx = (300 / 33) + 1; idx > 0; idx--) 284 CSR_READ_4(sc, SIS_CSR); 285 286 return; 287} 288 289static void 290sis_eeprom_idle(sc) 291 struct sis_softc *sc; 292{ 293 register int i; 294 295 SIO_SET(SIS_EECTL_CSEL); 296 sis_delay(sc); 297 SIO_SET(SIS_EECTL_CLK); 298 sis_delay(sc); 299 300 for (i = 0; i < 25; i++) { 301 SIO_CLR(SIS_EECTL_CLK); 302 sis_delay(sc); 303 SIO_SET(SIS_EECTL_CLK); 304 sis_delay(sc); 305 } 306 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_CLR(SIS_EECTL_CSEL); 310 sis_delay(sc); 311 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 312 313 return; 314} 315 316/* 317 * Send a read command and address to the EEPROM, check for ACK. 318 */ 319static void 320sis_eeprom_putbyte(sc, addr) 321 struct sis_softc *sc; 322 int addr; 323{ 324 register int d, i; 325 326 d = addr | SIS_EECMD_READ; 327 328 /* 329 * Feed in each bit and stobe the clock. 330 */ 331 for (i = 0x400; i; i >>= 1) { 332 if (d & i) { 333 SIO_SET(SIS_EECTL_DIN); 334 } else { 335 SIO_CLR(SIS_EECTL_DIN); 336 } 337 sis_delay(sc); 338 SIO_SET(SIS_EECTL_CLK); 339 sis_delay(sc); 340 SIO_CLR(SIS_EECTL_CLK); 341 sis_delay(sc); 342 } 343 344 return; 345} 346 347/* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350static void 351sis_eeprom_getword(sc, addr, dest) 352 struct sis_softc *sc; 353 int addr; 354 u_int16_t *dest; 355{ 356 register int i; 357 u_int16_t word = 0; 358 359 /* Force EEPROM to idle state. */ 360 sis_eeprom_idle(sc); 361 362 /* Enter EEPROM access mode. */ 363 sis_delay(sc); 364 SIO_CLR(SIS_EECTL_CLK); 365 sis_delay(sc); 366 SIO_SET(SIS_EECTL_CSEL); 367 sis_delay(sc); 368 369 /* 370 * Send address of word we want to read. 371 */ 372 sis_eeprom_putbyte(sc, addr); 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 for (i = 0x8000; i; i >>= 1) { 378 SIO_SET(SIS_EECTL_CLK); 379 sis_delay(sc); 380 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 381 word |= i; 382 sis_delay(sc); 383 SIO_CLR(SIS_EECTL_CLK); 384 sis_delay(sc); 385 } 386 387 /* Turn off EEPROM access mode. */ 388 sis_eeprom_idle(sc); 389 390 *dest = word; 391 392 return; 393} 394 395/* 396 * Read a sequence of words from the EEPROM. 397 */ 398static void 399sis_read_eeprom(sc, dest, off, cnt, swap) 400 struct sis_softc *sc; 401 caddr_t dest; 402 int off; 403 int cnt; 404 int swap; 405{ 406 int i; 407 u_int16_t word = 0, *ptr; 408 409 for (i = 0; i < cnt; i++) { 410 sis_eeprom_getword(sc, off + i, &word); 411 ptr = (u_int16_t *)(dest + (i * 2)); 412 if (swap) 413 *ptr = ntohs(word); 414 else 415 *ptr = word; 416 } 417 418 return; 419} 420 421#ifdef __i386__ 422static device_t 423sis_find_bridge(dev) 424 device_t dev; 425{ 426 devclass_t pci_devclass; 427 device_t *pci_devices; 428 int pci_count = 0; 429 device_t *pci_children; 430 int pci_childcount = 0; 431 device_t *busp, *childp; 432 device_t child = NULL; 433 int i, j; 434 435 if ((pci_devclass = devclass_find("pci")) == NULL) 436 return(NULL); 437 438 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 439 440 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 441 pci_childcount = 0; 442 device_get_children(*busp, &pci_children, &pci_childcount); 443 for (j = 0, childp = pci_children; 444 j < pci_childcount; j++, childp++) { 445 if (pci_get_vendor(*childp) == SIS_VENDORID && 446 pci_get_device(*childp) == 0x0008) { 447 child = *childp; 448 goto done; 449 } 450 } 451 } 452 453done: 454 free(pci_devices, M_TEMP); 455 free(pci_children, M_TEMP); 456 return(child); 457} 458 459static void 460sis_read_cmos(sc, dev, dest, off, cnt) 461 struct sis_softc *sc; 462 device_t dev; 463 caddr_t dest; 464 int off; 465 int cnt; 466{ 467 device_t bridge; 468 u_int8_t reg; 469 int i; 470 bus_space_tag_t btag; 471 472 bridge = sis_find_bridge(dev); 473 if (bridge == NULL) 474 return; 475 reg = pci_read_config(bridge, 0x48, 1); 476 pci_write_config(bridge, 0x48, reg|0x40, 1); 477 478 /* XXX */ 479 btag = I386_BUS_SPACE_IO; 480 481 for (i = 0; i < cnt; i++) { 482 bus_space_write_1(btag, 0x0, 0x70, i + off); 483 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 484 } 485 486 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 487 return; 488} 489 490static void 491sis_read_mac(sc, dev, dest) 492 struct sis_softc *sc; 493 device_t dev; 494 caddr_t dest; 495{ 496 u_int32_t filtsave, csrsave; 497 498 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 499 csrsave = CSR_READ_4(sc, SIS_CSR); 500 501 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 502 CSR_WRITE_4(sc, SIS_CSR, 0); 503 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 507 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 509 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 511 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 513 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 514 CSR_WRITE_4(sc, SIS_CSR, csrsave); 515 return; 516} 517#endif 518 519/* 520 * Sync the PHYs by setting data bit and strobing the clock 32 times. 521 */ 522static void sis_mii_sync(sc) 523 struct sis_softc *sc; 524{ 525 register int i; 526 527 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 528 529 for (i = 0; i < 32; i++) { 530 SIO_SET(SIS_MII_CLK); 531 DELAY(1); 532 SIO_CLR(SIS_MII_CLK); 533 DELAY(1); 534 } 535 536 return; 537} 538 539/* 540 * Clock a series of bits through the MII. 541 */ 542static void sis_mii_send(sc, bits, cnt) 543 struct sis_softc *sc; 544 u_int32_t bits; 545 int cnt; 546{ 547 int i; 548 549 SIO_CLR(SIS_MII_CLK); 550 551 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 552 if (bits & i) { 553 SIO_SET(SIS_MII_DATA); 554 } else { 555 SIO_CLR(SIS_MII_DATA); 556 } 557 DELAY(1); 558 SIO_CLR(SIS_MII_CLK); 559 DELAY(1); 560 SIO_SET(SIS_MII_CLK); 561 } 562} 563 564/* 565 * Read an PHY register through the MII. 566 */ 567static int sis_mii_readreg(sc, frame) 568 struct sis_softc *sc; 569 struct sis_mii_frame *frame; 570 571{ 572 int i, ack, s; 573 574 s = splimp(); 575 576 /* 577 * Set up frame for RX. 578 */ 579 frame->mii_stdelim = SIS_MII_STARTDELIM; 580 frame->mii_opcode = SIS_MII_READOP; 581 frame->mii_turnaround = 0; 582 frame->mii_data = 0; 583 584 /* 585 * Turn on data xmit. 586 */ 587 SIO_SET(SIS_MII_DIR); 588 589 sis_mii_sync(sc); 590 591 /* 592 * Send command/address info. 593 */ 594 sis_mii_send(sc, frame->mii_stdelim, 2); 595 sis_mii_send(sc, frame->mii_opcode, 2); 596 sis_mii_send(sc, frame->mii_phyaddr, 5); 597 sis_mii_send(sc, frame->mii_regaddr, 5); 598 599 /* Idle bit */ 600 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 601 DELAY(1); 602 SIO_SET(SIS_MII_CLK); 603 DELAY(1); 604 605 /* Turn off xmit. */ 606 SIO_CLR(SIS_MII_DIR); 607 608 /* Check for ack */ 609 SIO_CLR(SIS_MII_CLK); 610 DELAY(1); 611 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 612 SIO_SET(SIS_MII_CLK); 613 DELAY(1); 614 615 /* 616 * Now try reading data bits. If the ack failed, we still 617 * need to clock through 16 cycles to keep the PHY(s) in sync. 618 */ 619 if (ack) { 620 for(i = 0; i < 16; i++) { 621 SIO_CLR(SIS_MII_CLK); 622 DELAY(1); 623 SIO_SET(SIS_MII_CLK); 624 DELAY(1); 625 } 626 goto fail; 627 } 628 629 for (i = 0x8000; i; i >>= 1) { 630 SIO_CLR(SIS_MII_CLK); 631 DELAY(1); 632 if (!ack) { 633 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 634 frame->mii_data |= i; 635 DELAY(1); 636 } 637 SIO_SET(SIS_MII_CLK); 638 DELAY(1); 639 } 640 641fail: 642 643 SIO_CLR(SIS_MII_CLK); 644 DELAY(1); 645 SIO_SET(SIS_MII_CLK); 646 DELAY(1); 647 648 splx(s); 649 650 if (ack) 651 return(1); 652 return(0); 653} 654 655/* 656 * Write to a PHY register through the MII. 657 */ 658static int sis_mii_writereg(sc, frame) 659 struct sis_softc *sc; 660 struct sis_mii_frame *frame; 661 662{ 663 int s; 664 665 s = splimp(); 666 /* 667 * Set up frame for TX. 668 */ 669 670 frame->mii_stdelim = SIS_MII_STARTDELIM; 671 frame->mii_opcode = SIS_MII_WRITEOP; 672 frame->mii_turnaround = SIS_MII_TURNAROUND; 673 674 /* 675 * Turn on data output. 676 */ 677 SIO_SET(SIS_MII_DIR); 678 679 sis_mii_sync(sc); 680 681 sis_mii_send(sc, frame->mii_stdelim, 2); 682 sis_mii_send(sc, frame->mii_opcode, 2); 683 sis_mii_send(sc, frame->mii_phyaddr, 5); 684 sis_mii_send(sc, frame->mii_regaddr, 5); 685 sis_mii_send(sc, frame->mii_turnaround, 2); 686 sis_mii_send(sc, frame->mii_data, 16); 687 688 /* Idle bit. */ 689 SIO_SET(SIS_MII_CLK); 690 DELAY(1); 691 SIO_CLR(SIS_MII_CLK); 692 DELAY(1); 693 694 /* 695 * Turn off xmit. 696 */ 697 SIO_CLR(SIS_MII_DIR); 698 699 splx(s); 700 701 return(0); 702} 703 704static int 705sis_miibus_readreg(dev, phy, reg) 706 device_t dev; 707 int phy, reg; 708{ 709 struct sis_softc *sc; 710 struct sis_mii_frame frame; 711 712 sc = device_get_softc(dev); 713 714 if (sc->sis_type == SIS_TYPE_83815) { 715 if (phy != 0) 716 return(0); 717 /* 718 * The NatSemi chip can take a while after 719 * a reset to come ready, during which the BMSR 720 * returns a value of 0. This is *never* supposed 721 * to happen: some of the BMSR bits are meant to 722 * be hardwired in the on position, and this can 723 * confuse the miibus code a bit during the probe 724 * and attach phase. So we make an effort to check 725 * for this condition and wait for it to clear. 726 */ 727 if (!CSR_READ_4(sc, NS_BMSR)) 728 DELAY(1000); 729 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 730 } 731 732 /* 733 * Chipsets < SIS_635 seem not to be able to read/write 734 * through mdio. Use the enhanced PHY access register 735 * again for them. 736 */ 737 if (sc->sis_type == SIS_TYPE_900 && 738 sc->sis_rev < SIS_REV_635) { 739 int i, val = 0; 740 741 if (phy != 0) 742 return(0); 743 744 CSR_WRITE_4(sc, SIS_PHYCTL, 745 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 746 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 747 748 for (i = 0; i < SIS_TIMEOUT; i++) { 749 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 750 break; 751 } 752 753 if (i == SIS_TIMEOUT) { 754 printf("sis%d: PHY failed to come ready\n", 755 sc->sis_unit); 756 return(0); 757 } 758 759 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 760 761 if (val == 0xFFFF) 762 return(0); 763 764 return(val); 765 } else { 766 bzero((char *)&frame, sizeof(frame)); 767 768 frame.mii_phyaddr = phy; 769 frame.mii_regaddr = reg; 770 sis_mii_readreg(sc, &frame); 771 772 return(frame.mii_data); 773 } 774} 775 776static int 777sis_miibus_writereg(dev, phy, reg, data) 778 device_t dev; 779 int phy, reg, data; 780{ 781 struct sis_softc *sc; 782 struct sis_mii_frame frame; 783 784 sc = device_get_softc(dev); 785 786 if (sc->sis_type == SIS_TYPE_83815) { 787 if (phy != 0) 788 return(0); 789 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 790 return(0); 791 } 792 793 /* 794 * Chipsets < SIS_635 seem not to be able to read/write 795 * through mdio. Use the enhanced PHY access register 796 * again for them. 797 */ 798 if (sc->sis_type == SIS_TYPE_900 && 799 sc->sis_rev < SIS_REV_635) { 800 int i; 801 802 if (phy != 0) 803 return(0); 804 805 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 806 (reg << 6) | SIS_PHYOP_WRITE); 807 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 808 809 for (i = 0; i < SIS_TIMEOUT; i++) { 810 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 811 break; 812 } 813 814 if (i == SIS_TIMEOUT) 815 printf("sis%d: PHY failed to come ready\n", 816 sc->sis_unit); 817 } else { 818 bzero((char *)&frame, sizeof(frame)); 819 820 frame.mii_phyaddr = phy; 821 frame.mii_regaddr = reg; 822 frame.mii_data = data; 823 sis_mii_writereg(sc, &frame); 824 } 825 return(0); 826} 827 828static void 829sis_miibus_statchg(dev) 830 device_t dev; 831{ 832 struct sis_softc *sc; 833 834 sc = device_get_softc(dev); 835 sis_init(sc); 836 837 return; 838} 839 840static u_int32_t 841sis_crc(sc, addr) 842 struct sis_softc *sc; 843 caddr_t addr; 844{ 845 u_int32_t crc, carry; 846 int i, j; 847 u_int8_t c; 848 849 /* Compute CRC for the address value. */ 850 crc = 0xFFFFFFFF; /* initial value */ 851 852 for (i = 0; i < 6; i++) { 853 c = *(addr + i); 854 for (j = 0; j < 8; j++) { 855 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 856 crc <<= 1; 857 c >>= 1; 858 if (carry) 859 crc = (crc ^ 0x04c11db6) | carry; 860 } 861 } 862 863 /* 864 * return the filter bit position 865 * 866 * The NatSemi chip has a 512-bit filter, which is 867 * different than the SiS, so we special-case it. 868 */ 869 if (sc->sis_type == SIS_TYPE_83815) 870 return (crc >> 23); 871 else if (sc->sis_rev >= SIS_REV_635 || 872 sc->sis_rev == SIS_REV_900B) 873 return (crc >> 24); 874 else 875 return (crc >> 25); 876} 877 878static void 879sis_setmulti_ns(sc) 880 struct sis_softc *sc; 881{ 882 struct ifnet *ifp; 883 struct ifmultiaddr *ifma; 884 u_int32_t h = 0, i, filtsave; 885 int bit, index; 886 887 ifp = &sc->arpcom.ac_if; 888 889 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 890 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 891 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 892 return; 893 } 894 895 /* 896 * We have to explicitly enable the multicast hash table 897 * on the NatSemi chip if we want to use it, which we do. 898 */ 899 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 900 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 901 902 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 903 904 /* first, zot all the existing hash bits */ 905 for (i = 0; i < 32; i++) { 906 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 907 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 908 } 909 910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 911 if (ifma->ifma_addr->sa_family != AF_LINK) 912 continue; 913 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 914 index = h >> 3; 915 bit = h & 0x1F; 916 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 917 if (bit > 0xF) 918 bit -= 0x10; 919 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 920 } 921 922 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 923 924 return; 925} 926 927static void 928sis_setmulti_sis(sc) 929 struct sis_softc *sc; 930{ 931 struct ifnet *ifp; 932 struct ifmultiaddr *ifma; 933 u_int32_t h, i, n, ctl; 934 u_int16_t hashes[16]; 935 936 ifp = &sc->arpcom.ac_if; 937 938 /* hash table size */ 939 if (sc->sis_rev >= SIS_REV_635 || 940 sc->sis_rev == SIS_REV_900B) 941 n = 16; 942 else 943 n = 8; 944 945 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 946 947 if (ifp->if_flags & IFF_BROADCAST) 948 ctl |= SIS_RXFILTCTL_BROAD; 949 950 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 951 ctl |= SIS_RXFILTCTL_ALLMULTI; 952 if (ifp->if_flags & IFF_PROMISC) 953 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 954 for (i = 0; i < n; i++) 955 hashes[i] = ~0; 956 } else { 957 for (i = 0; i < n; i++) 958 hashes[i] = 0; 959 i = 0; 960 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 961 if (ifma->ifma_addr->sa_family != AF_LINK) 962 continue; 963 h = sis_crc(sc, 964 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 965 hashes[h >> 4] |= 1 << (h & 0xf); 966 i++; 967 } 968 if (i > n) { 969 ctl |= SIS_RXFILTCTL_ALLMULTI; 970 for (i = 0; i < n; i++) 971 hashes[i] = ~0; 972 } 973 } 974 975 for (i = 0; i < n; i++) { 976 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 977 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 978 } 979 980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 981} 982 983static void 984sis_reset(sc) 985 struct sis_softc *sc; 986{ 987 register int i; 988 989 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 990 991 for (i = 0; i < SIS_TIMEOUT; i++) { 992 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 993 break; 994 } 995 996 if (i == SIS_TIMEOUT) 997 printf("sis%d: reset never completed\n", sc->sis_unit); 998 999 /* Wait a little while for the chip to get its brains in order. */ 1000 DELAY(1000); 1001 1002 /* 1003 * If this is a NetSemi chip, make sure to clear 1004 * PME mode. 1005 */ 1006 if (sc->sis_type == SIS_TYPE_83815) { 1007 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 1008 CSR_WRITE_4(sc, NS_CLKRUN, 0); 1009 } 1010 1011 return; 1012} 1013 1014/* 1015 * Probe for an SiS chip. Check the PCI vendor and device 1016 * IDs against our list and return a device name if we find a match. 1017 */ 1018static int 1019sis_probe(dev) 1020 device_t dev; 1021{ 1022 struct sis_type *t; 1023 1024 t = sis_devs; 1025 1026 while(t->sis_name != NULL) { 1027 if ((pci_get_vendor(dev) == t->sis_vid) && 1028 (pci_get_device(dev) == t->sis_did)) { 1029 device_set_desc(dev, t->sis_name); 1030 return(0); 1031 } 1032 t++; 1033 } 1034 1035 return(ENXIO); 1036} 1037 1038/* 1039 * Attach the interface. Allocate softc structures, do ifmedia 1040 * setup and ethernet/BPF attach. 1041 */ 1042static int 1043sis_attach(dev) 1044 device_t dev; 1045{ 1046 u_char eaddr[ETHER_ADDR_LEN]; 1047 u_int32_t command; 1048 struct sis_softc *sc; 1049 struct ifnet *ifp; 1050 int unit, error = 0, rid, waittime = 0; 1051 1052 waittime = 0; 1053 sc = device_get_softc(dev); 1054 unit = device_get_unit(dev); 1055 1056 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1057 MTX_DEF | MTX_RECURSE); 1058 1059 if (pci_get_device(dev) == SIS_DEVICEID_900) 1060 sc->sis_type = SIS_TYPE_900; 1061 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1062 sc->sis_type = SIS_TYPE_7016; 1063 if (pci_get_vendor(dev) == NS_VENDORID) 1064 sc->sis_type = SIS_TYPE_83815; 1065 1066 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1067 1068 /* 1069 * Handle power management nonsense. 1070 */ 1071 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1072 u_int32_t iobase, membase, irq; 1073 1074 /* Save important PCI config data. */ 1075 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1076 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1077 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1078 1079 /* Reset the power state. */ 1080 printf("sis%d: chip is in D%d power mode " 1081 "-- setting to D0\n", unit, 1082 pci_get_powerstate(dev)); 1083 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1084 1085 /* Restore PCI config data. */ 1086 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1087 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1088 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1089 } 1090 1091 /* 1092 * Map control/status registers. 1093 */ 1094 pci_enable_busmaster(dev); 1095 pci_enable_io(dev, SYS_RES_IOPORT); 1096 pci_enable_io(dev, SYS_RES_MEMORY); 1097 command = pci_read_config(dev, PCIR_COMMAND, 4); 1098 1099#ifdef SIS_USEIOSPACE 1100 if (!(command & PCIM_CMD_PORTEN)) { 1101 printf("sis%d: failed to enable I/O ports!\n", unit); 1102 error = ENXIO; 1103 goto fail; 1104 } 1105#else 1106 if (!(command & PCIM_CMD_MEMEN)) { 1107 printf("sis%d: failed to enable memory mapping!\n", unit); 1108 error = ENXIO; 1109 goto fail; 1110 } 1111#endif 1112 1113 rid = SIS_RID; 1114 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1115 0, ~0, 1, RF_ACTIVE); 1116 1117 if (sc->sis_res == NULL) { 1118 printf("sis%d: couldn't map ports/memory\n", unit); 1119 error = ENXIO; 1120 goto fail; 1121 } 1122 1123 sc->sis_btag = rman_get_bustag(sc->sis_res); 1124 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1125 1126 /* Allocate interrupt */ 1127 rid = 0; 1128 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1129 RF_SHAREABLE | RF_ACTIVE); 1130 1131 if (sc->sis_irq == NULL) { 1132 printf("sis%d: couldn't map interrupt\n", unit); 1133 error = ENXIO; 1134 goto fail; 1135 } 1136 1137 /* Reset the adapter. */ 1138 sis_reset(sc); 1139 1140 if (sc->sis_type == SIS_TYPE_900 && 1141 (sc->sis_rev == SIS_REV_635 || 1142 sc->sis_rev == SIS_REV_900B)) { 1143 SIO_SET(SIS_CFG_RND_CNT); 1144 SIO_SET(SIS_CFG_PERR_DETECT); 1145 } 1146 1147 /* 1148 * Get station address from the EEPROM. 1149 */ 1150 switch (pci_get_vendor(dev)) { 1151 case NS_VENDORID: 1152 /* 1153 * Reading the MAC address out of the EEPROM on 1154 * the NatSemi chip takes a bit more work than 1155 * you'd expect. The address spans 4 16-bit words, 1156 * with the first word containing only a single bit. 1157 * You have to shift everything over one bit to 1158 * get it aligned properly. Also, the bits are 1159 * stored backwards (the LSB is really the MSB, 1160 * and so on) so you have to reverse them in order 1161 * to get the MAC address into the form we want. 1162 * Why? Who the hell knows. 1163 */ 1164 { 1165 u_int16_t tmp[4]; 1166 1167 sis_read_eeprom(sc, (caddr_t)&tmp, 1168 NS_EE_NODEADDR, 4, 0); 1169 1170 /* Shift everything over one bit. */ 1171 tmp[3] = tmp[3] >> 1; 1172 tmp[3] |= tmp[2] << 15; 1173 tmp[2] = tmp[2] >> 1; 1174 tmp[2] |= tmp[1] << 15; 1175 tmp[1] = tmp[1] >> 1; 1176 tmp[1] |= tmp[0] << 15; 1177 1178 /* Now reverse all the bits. */ 1179 tmp[3] = sis_reverse(tmp[3]); 1180 tmp[2] = sis_reverse(tmp[2]); 1181 tmp[1] = sis_reverse(tmp[1]); 1182 1183 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1184 } 1185 break; 1186 case SIS_VENDORID: 1187 default: 1188#ifdef __i386__ 1189 /* 1190 * If this is a SiS 630E chipset with an embedded 1191 * SiS 900 controller, we have to read the MAC address 1192 * from the APC CMOS RAM. Our method for doing this 1193 * is very ugly since we have to reach out and grab 1194 * ahold of hardware for which we cannot properly 1195 * allocate resources. This code is only compiled on 1196 * the i386 architecture since the SiS 630E chipset 1197 * is for x86 motherboards only. Note that there are 1198 * a lot of magic numbers in this hack. These are 1199 * taken from SiS's Linux driver. I'd like to replace 1200 * them with proper symbolic definitions, but that 1201 * requires some datasheets that I don't have access 1202 * to at the moment. 1203 */ 1204 if (sc->sis_rev == SIS_REV_630S || 1205 sc->sis_rev == SIS_REV_630E || 1206 sc->sis_rev == SIS_REV_630EA1) 1207 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1208 1209 else if (sc->sis_rev == SIS_REV_635 || 1210 sc->sis_rev == SIS_REV_630ET) 1211 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1212 else if (sc->sis_rev == SIS_REV_96x) { 1213 /* Allow to read EEPROM from LAN. It is shared 1214 * between a 1394 controller and the NIC and each 1215 * time we access it, we need to set SIS_EECMD_REQ. 1216 */ 1217 SIO_SET(SIS_EECMD_REQ); 1218 for (waittime = 0; waittime < SIS_TIMEOUT; 1219 waittime++) { 1220 /* Force EEPROM to idle state. */ 1221 sis_eeprom_idle(sc); 1222 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1223 sis_read_eeprom(sc, (caddr_t)&eaddr, 1224 SIS_EE_NODEADDR, 3, 0); 1225 break; 1226 } 1227 DELAY(1); 1228 } 1229 /* 1230 * Set SIS_EECTL_CLK to high, so a other master 1231 * can operate on the i2c bus. 1232 */ 1233 SIO_SET(SIS_EECTL_CLK); 1234 /* Refuse EEPROM access by LAN */ 1235 SIO_SET(SIS_EECMD_DONE); 1236 } else 1237#endif 1238 sis_read_eeprom(sc, (caddr_t)&eaddr, 1239 SIS_EE_NODEADDR, 3, 0); 1240 break; 1241 } 1242 1243 /* 1244 * A SiS chip was detected. Inform the world. 1245 */ 1246 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1247 1248 sc->sis_unit = unit; 1249 callout_handle_init(&sc->sis_stat_ch); 1250 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1251 1252 /* 1253 * Allocate the parent bus DMA tag appropriate for PCI. 1254 */ 1255#define SIS_NSEG_NEW 32 1256 error = bus_dma_tag_create(NULL, /* parent */ 1257 1, 0, /* alignment, boundary */ 1258 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1259 BUS_SPACE_MAXADDR, /* highaddr */ 1260 NULL, NULL, /* filter, filterarg */ 1261 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1262 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1263 BUS_DMA_ALLOCNOW, /* flags */ 1264 &sc->sis_parent_tag); 1265 if (error) 1266 goto fail; 1267 1268 /* 1269 * Now allocate a tag for the DMA descriptor lists and a chunk 1270 * of DMA-able memory based on the tag. Also obtain the physical 1271 * addresses of the RX and TX ring, which we'll need later. 1272 * All of our lists are allocated as a contiguous block 1273 * of memory. 1274 */ 1275 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1276 1, 0, /* alignment, boundary */ 1277 BUS_SPACE_MAXADDR, /* lowaddr */ 1278 BUS_SPACE_MAXADDR, /* highaddr */ 1279 NULL, NULL, /* filter, filterarg */ 1280 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1281 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1282 0, /* flags */ 1283 &sc->sis_ldata.sis_rx_tag); 1284 if (error) 1285 goto fail; 1286 1287 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1288 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1289 &sc->sis_ldata.sis_rx_dmamap); 1290 1291 if (error) { 1292 printf("sis%d: no memory for rx list buffers!\n", unit); 1293 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1294 sc->sis_ldata.sis_rx_tag = NULL; 1295 goto fail; 1296 } 1297 1298 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1299 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1300 sizeof(struct sis_desc), sis_dma_map_ring, 1301 &sc->sis_cdata.sis_rx_paddr, 0); 1302 1303 if (error) { 1304 printf("sis%d: cannot get address of the rx ring!\n", unit); 1305 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1306 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1307 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1308 sc->sis_ldata.sis_rx_tag = NULL; 1309 goto fail; 1310 } 1311 1312 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1313 1, 0, /* alignment, boundary */ 1314 BUS_SPACE_MAXADDR, /* lowaddr */ 1315 BUS_SPACE_MAXADDR, /* highaddr */ 1316 NULL, NULL, /* filter, filterarg */ 1317 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1318 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1319 0, /* flags */ 1320 &sc->sis_ldata.sis_tx_tag); 1321 if (error) 1322 goto fail; 1323 1324 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1325 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1326 &sc->sis_ldata.sis_tx_dmamap); 1327 1328 if (error) { 1329 printf("sis%d: no memory for tx list buffers!\n", unit); 1330 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1331 sc->sis_ldata.sis_tx_tag = NULL; 1332 goto fail; 1333 } 1334 1335 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1336 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1337 sizeof(struct sis_desc), sis_dma_map_ring, 1338 &sc->sis_cdata.sis_tx_paddr, 0); 1339 1340 if (error) { 1341 printf("sis%d: cannot get address of the tx ring!\n", unit); 1342 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1343 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1344 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1345 sc->sis_ldata.sis_tx_tag = NULL; 1346 goto fail; 1347 } 1348 1349 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1350 1, 0, /* alignment, boundary */ 1351 BUS_SPACE_MAXADDR, /* lowaddr */ 1352 BUS_SPACE_MAXADDR, /* highaddr */ 1353 NULL, NULL, /* filter, filterarg */ 1354 MCLBYTES, 1, /* maxsize,nsegments */ 1355 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1356 0, /* flags */ 1357 &sc->sis_tag); 1358 if (error) 1359 goto fail; 1360 1361 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1362 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1363 1364 /* 1365 * Obtain the physical addresses of the RX and TX 1366 * rings which we'll need later in the init routine. 1367 */ 1368 1369 ifp = &sc->arpcom.ac_if; 1370 ifp->if_softc = sc; 1371 ifp->if_unit = unit; 1372 ifp->if_name = "sis"; 1373 ifp->if_mtu = ETHERMTU; 1374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1375 ifp->if_ioctl = sis_ioctl; 1376 ifp->if_output = ether_output; 1377 ifp->if_start = sis_start; 1378 ifp->if_watchdog = sis_watchdog; 1379 ifp->if_init = sis_init; 1380 ifp->if_baudrate = 10000000; 1381 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1382 1383 /* 1384 * Do MII setup. 1385 */ 1386 if (mii_phy_probe(dev, &sc->sis_miibus, 1387 sis_ifmedia_upd, sis_ifmedia_sts)) { 1388 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1389 error = ENXIO; 1390 goto fail; 1391 } 1392 1393 callout_handle_init(&sc->sis_stat_ch); 1394 1395 /* 1396 * Call MI attach routine. 1397 */ 1398 ether_ifattach(ifp, eaddr); 1399 1400 /* 1401 * Tell the upper layer(s) we support long frames. 1402 */ 1403 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1404 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1405 1406 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1407 sis_intr, sc, &sc->sis_intrhand); 1408 1409 if (error) { 1410 printf("sis%d: couldn't set up irq\n", unit); 1411 goto fail; 1412 } 1413 1414fail: 1415 if (error) 1416 sis_detach(dev); 1417 1418 return(error); 1419} 1420 1421static int 1422sis_detach(dev) 1423 device_t dev; 1424{ 1425 struct sis_softc *sc; 1426 struct ifnet *ifp; 1427 1428 sc = device_get_softc(dev); 1429 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1430 SIS_LOCK(sc); 1431 ifp = &sc->arpcom.ac_if; 1432 1433 if (device_is_alive(dev)) { 1434 if (bus_child_present(dev)) { 1435 sis_reset(sc); 1436 sis_stop(sc); 1437 } 1438 ether_ifdetach(ifp); 1439 device_delete_child(dev, sc->sis_miibus); 1440 bus_generic_detach(dev); 1441 } 1442 1443 if (sc->sis_intrhand) 1444 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1445 if (sc->sis_irq) 1446 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1447 if (sc->sis_res) 1448 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1449 1450 if (sc->sis_ldata.sis_rx_tag) { 1451 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1452 sc->sis_ldata.sis_rx_dmamap); 1453 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1454 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1455 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1456 } 1457 if (sc->sis_ldata.sis_tx_tag) { 1458 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1459 sc->sis_ldata.sis_tx_dmamap); 1460 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1461 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1462 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1463 } 1464 if (sc->sis_parent_tag) 1465 bus_dma_tag_destroy(sc->sis_parent_tag); 1466 if (sc->sis_tag) 1467 bus_dma_tag_destroy(sc->sis_tag); 1468 1469 SIS_UNLOCK(sc); 1470 mtx_destroy(&sc->sis_mtx); 1471 1472 return(0); 1473} 1474 1475/* 1476 * Initialize the transmit descriptors. 1477 */ 1478static int 1479sis_list_tx_init(sc) 1480 struct sis_softc *sc; 1481{ 1482 struct sis_list_data *ld; 1483 struct sis_ring_data *cd; 1484 int i, nexti; 1485 1486 cd = &sc->sis_cdata; 1487 ld = &sc->sis_ldata; 1488 1489 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1490 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1491 ld->sis_tx_list[i].sis_nextdesc = 1492 &ld->sis_tx_list[nexti]; 1493 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1494 sc->sis_ldata.sis_tx_dmamap, 1495 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1496 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1497 ld->sis_tx_list[i].sis_mbuf = NULL; 1498 ld->sis_tx_list[i].sis_ptr = 0; 1499 ld->sis_tx_list[i].sis_ctl = 0; 1500 } 1501 1502 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1503 1504 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1505 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1506 1507 return(0); 1508} 1509 1510/* 1511 * Initialize the RX descriptors and allocate mbufs for them. Note that 1512 * we arrange the descriptors in a closed ring, so that the last descriptor 1513 * points back to the first. 1514 */ 1515static int 1516sis_list_rx_init(sc) 1517 struct sis_softc *sc; 1518{ 1519 struct sis_list_data *ld; 1520 struct sis_ring_data *cd; 1521 int i,nexti; 1522 1523 ld = &sc->sis_ldata; 1524 cd = &sc->sis_cdata; 1525 1526 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1527 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1528 return(ENOBUFS); 1529 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1530 ld->sis_rx_list[i].sis_nextdesc = 1531 &ld->sis_rx_list[nexti]; 1532 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1533 sc->sis_ldata.sis_rx_dmamap, 1534 &ld->sis_rx_list[nexti], 1535 sizeof(struct sis_desc), sis_dma_map_desc_next, 1536 &ld->sis_rx_list[i], 0); 1537 } 1538 1539 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1540 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1541 1542 cd->sis_rx_prod = 0; 1543 1544 return(0); 1545} 1546 1547/* 1548 * Initialize an RX descriptor and attach an MBUF cluster. 1549 */ 1550static int 1551sis_newbuf(sc, c, m) 1552 struct sis_softc *sc; 1553 struct sis_desc *c; 1554 struct mbuf *m; 1555{ 1556 1557 if (c == NULL) 1558 return(EINVAL); 1559 1560 if (m == NULL) { 1561 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1562 if (m == NULL) 1563 return(ENOBUFS); 1564 } else 1565 m->m_data = m->m_ext.ext_buf; 1566 1567 c->sis_mbuf = m; 1568 c->sis_ctl = SIS_RXLEN; 1569 1570 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1571 bus_dmamap_load(sc->sis_tag, c->sis_map, 1572 mtod(m, void *), MCLBYTES, 1573 sis_dma_map_desc_ptr, c, 0); 1574 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1575 1576 return(0); 1577} 1578 1579/* 1580 * A frame has been uploaded: pass the resulting mbuf chain up to 1581 * the higher level protocols. 1582 */ 1583static void 1584sis_rxeof(sc) 1585 struct sis_softc *sc; 1586{ 1587 struct mbuf *m; 1588 struct ifnet *ifp; 1589 struct sis_desc *cur_rx; 1590 int i, total_len = 0; 1591 u_int32_t rxstat; 1592 1593 ifp = &sc->arpcom.ac_if; 1594 i = sc->sis_cdata.sis_rx_prod; 1595 1596 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1597 1598#ifdef DEVICE_POLLING 1599 if (ifp->if_flags & IFF_POLLING) { 1600 if (sc->rxcycles <= 0) 1601 break; 1602 sc->rxcycles--; 1603 } 1604#endif /* DEVICE_POLLING */ 1605 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1606 rxstat = cur_rx->sis_rxstat; 1607 bus_dmamap_sync(sc->sis_tag, 1608 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1609 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1610 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1611 m = cur_rx->sis_mbuf; 1612 cur_rx->sis_mbuf = NULL; 1613 total_len = SIS_RXBYTES(cur_rx); 1614 SIS_INC(i, SIS_RX_LIST_CNT); 1615 1616 /* 1617 * If an error occurs, update stats, clear the 1618 * status word and leave the mbuf cluster in place: 1619 * it should simply get re-used next time this descriptor 1620 * comes up in the ring. 1621 */ 1622 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1623 ifp->if_ierrors++; 1624 if (rxstat & SIS_RXSTAT_COLL) 1625 ifp->if_collisions++; 1626 sis_newbuf(sc, cur_rx, m); 1627 continue; 1628 } 1629 1630 /* No errors; receive the packet. */ 1631#ifdef __i386__ 1632 /* 1633 * On the x86 we do not have alignment problems, so try to 1634 * allocate a new buffer for the receive ring, and pass up 1635 * the one where the packet is already, saving the expensive 1636 * copy done in m_devget(). 1637 * If we are on an architecture with alignment problems, or 1638 * if the allocation fails, then use m_devget and leave the 1639 * existing buffer in the receive ring. 1640 */ 1641 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1642 m->m_pkthdr.len = m->m_len = total_len; 1643 else 1644#endif 1645 { 1646 struct mbuf *m0; 1647 m0 = m_devget(mtod(m, char *), total_len, 1648 ETHER_ALIGN, ifp, NULL); 1649 sis_newbuf(sc, cur_rx, m); 1650 if (m0 == NULL) { 1651 ifp->if_ierrors++; 1652 continue; 1653 } 1654 m = m0; 1655 } 1656 1657 ifp->if_ipackets++; 1658 m->m_pkthdr.rcvif = ifp; 1659 1660 (*ifp->if_input)(ifp, m); 1661 } 1662 1663 sc->sis_cdata.sis_rx_prod = i; 1664 1665 return; 1666} 1667 1668static void 1669sis_rxeoc(sc) 1670 struct sis_softc *sc; 1671{ 1672 sis_rxeof(sc); 1673 sis_init(sc); 1674 return; 1675} 1676 1677/* 1678 * A frame was downloaded to the chip. It's safe for us to clean up 1679 * the list buffers. 1680 */ 1681 1682static void 1683sis_txeof(sc) 1684 struct sis_softc *sc; 1685{ 1686 struct ifnet *ifp; 1687 u_int32_t idx; 1688 1689 ifp = &sc->arpcom.ac_if; 1690 1691 /* 1692 * Go through our tx list and free mbufs for those 1693 * frames that have been transmitted. 1694 */ 1695 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1696 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1697 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1698 1699 if (SIS_OWNDESC(cur_tx)) 1700 break; 1701 1702 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1703 continue; 1704 1705 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1706 ifp->if_oerrors++; 1707 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1708 ifp->if_collisions++; 1709 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1710 ifp->if_collisions++; 1711 } 1712 1713 ifp->if_collisions += 1714 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1715 1716 ifp->if_opackets++; 1717 if (cur_tx->sis_mbuf != NULL) { 1718 m_freem(cur_tx->sis_mbuf); 1719 cur_tx->sis_mbuf = NULL; 1720 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1721 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1722 } 1723 } 1724 1725 if (idx != sc->sis_cdata.sis_tx_cons) { 1726 /* we freed up some buffers */ 1727 sc->sis_cdata.sis_tx_cons = idx; 1728 ifp->if_flags &= ~IFF_OACTIVE; 1729 } 1730 1731 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1732 1733 return; 1734} 1735 1736static void 1737sis_tick(xsc) 1738 void *xsc; 1739{ 1740 struct sis_softc *sc; 1741 struct mii_data *mii; 1742 struct ifnet *ifp; 1743 1744 sc = xsc; 1745 SIS_LOCK(sc); 1746 ifp = &sc->arpcom.ac_if; 1747 1748 mii = device_get_softc(sc->sis_miibus); 1749 mii_tick(mii); 1750 1751 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1752 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1753 sc->sis_link++; 1754 if (ifp->if_snd.ifq_head != NULL) 1755 sis_start(ifp); 1756 } 1757 1758 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1759 1760 SIS_UNLOCK(sc); 1761 1762 return; 1763} 1764 1765#ifdef DEVICE_POLLING 1766static poll_handler_t sis_poll; 1767 1768static void 1769sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1770{ 1771 struct sis_softc *sc = ifp->if_softc; 1772 1773 SIS_LOCK(sc); 1774 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1775 CSR_WRITE_4(sc, SIS_IER, 1); 1776 goto done; 1777 } 1778 1779 /* 1780 * On the sis, reading the status register also clears it. 1781 * So before returning to intr mode we must make sure that all 1782 * possible pending sources of interrupts have been served. 1783 * In practice this means run to completion the *eof routines, 1784 * and then call the interrupt routine 1785 */ 1786 sc->rxcycles = count; 1787 sis_rxeof(sc); 1788 sis_txeof(sc); 1789 if (ifp->if_snd.ifq_head != NULL) 1790 sis_start(ifp); 1791 1792 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1793 u_int32_t status; 1794 1795 /* Reading the ISR register clears all interrupts. */ 1796 status = CSR_READ_4(sc, SIS_ISR); 1797 1798 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1799 sis_rxeoc(sc); 1800 1801 if (status & (SIS_ISR_RX_IDLE)) 1802 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1803 1804 if (status & SIS_ISR_SYSERR) { 1805 sis_reset(sc); 1806 sis_init(sc); 1807 } 1808 } 1809done: 1810 SIS_UNLOCK(sc); 1811 return; 1812} 1813#endif /* DEVICE_POLLING */ 1814 1815static void 1816sis_intr(arg) 1817 void *arg; 1818{ 1819 struct sis_softc *sc; 1820 struct ifnet *ifp; 1821 u_int32_t status; 1822 1823 sc = arg; 1824 ifp = &sc->arpcom.ac_if; 1825 1826 SIS_LOCK(sc); 1827#ifdef DEVICE_POLLING 1828 if (ifp->if_flags & IFF_POLLING) 1829 goto done; 1830 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1831 CSR_WRITE_4(sc, SIS_IER, 0); 1832 goto done; 1833 } 1834#endif /* DEVICE_POLLING */ 1835 1836 /* Supress unwanted interrupts */ 1837 if (!(ifp->if_flags & IFF_UP)) { 1838 sis_stop(sc); 1839 goto done; 1840 } 1841 1842 /* Disable interrupts. */ 1843 CSR_WRITE_4(sc, SIS_IER, 0); 1844 1845 for (;;) { 1846 /* Reading the ISR register clears all interrupts. */ 1847 status = CSR_READ_4(sc, SIS_ISR); 1848 1849 if ((status & SIS_INTRS) == 0) 1850 break; 1851 1852 if (status & 1853 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1854 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1855 sis_txeof(sc); 1856 1857 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1858 sis_rxeof(sc); 1859 1860 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1861 sis_rxeoc(sc); 1862 1863 if (status & (SIS_ISR_RX_IDLE)) 1864 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1865 1866 if (status & SIS_ISR_SYSERR) { 1867 sis_reset(sc); 1868 sis_init(sc); 1869 } 1870 } 1871 1872 /* Re-enable interrupts. */ 1873 CSR_WRITE_4(sc, SIS_IER, 1); 1874 1875 if (ifp->if_snd.ifq_head != NULL) 1876 sis_start(ifp); 1877done: 1878 SIS_UNLOCK(sc); 1879 1880 return; 1881} 1882 1883/* 1884 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1885 * pointers to the fragment pointers. 1886 */ 1887static int 1888sis_encap(sc, m_head, txidx) 1889 struct sis_softc *sc; 1890 struct mbuf *m_head; 1891 u_int32_t *txidx; 1892{ 1893 struct sis_desc *f = NULL; 1894 struct mbuf *m; 1895 int frag, cur, cnt = 0, chainlen = 0; 1896 1897 /* 1898 * If there's no way we can send any packets, return now. 1899 */ 1900 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1901 return (ENOBUFS); 1902 1903 /* 1904 * Count the number of frags in this chain to see if 1905 * we need to m_defrag. Since the descriptor list is shared 1906 * by all packets, we'll m_defrag long chains so that they 1907 * do not use up the entire list, even if they would fit. 1908 */ 1909 1910 for (m = m_head; m != NULL; m = m->m_next) 1911 chainlen++; 1912 1913 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1914 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1915 m = m_defrag(m_head, M_DONTWAIT); 1916 if (m == NULL) 1917 return (ENOBUFS); 1918 m_head = m; 1919 } 1920 1921 /* 1922 * Start packing the mbufs in this chain into 1923 * the fragment pointers. Stop when we run out 1924 * of fragments or hit the end of the mbuf chain. 1925 */ 1926 m = m_head; 1927 cur = frag = *txidx; 1928 1929 for (m = m_head; m != NULL; m = m->m_next) { 1930 if (m->m_len != 0) { 1931 if ((SIS_TX_LIST_CNT - 1932 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1933 return(ENOBUFS); 1934 f = &sc->sis_ldata.sis_tx_list[frag]; 1935 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1936 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1937 bus_dmamap_load(sc->sis_tag, f->sis_map, 1938 mtod(m, void *), m->m_len, 1939 sis_dma_map_desc_ptr, f, 0); 1940 bus_dmamap_sync(sc->sis_tag, 1941 f->sis_map, BUS_DMASYNC_PREREAD); 1942 if (cnt != 0) 1943 f->sis_ctl |= SIS_CMDSTS_OWN; 1944 cur = frag; 1945 SIS_INC(frag, SIS_TX_LIST_CNT); 1946 cnt++; 1947 } 1948 } 1949 1950 if (m != NULL) 1951 return(ENOBUFS); 1952 1953 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1954 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1955 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1956 sc->sis_cdata.sis_tx_cnt += cnt; 1957 *txidx = frag; 1958 1959 return(0); 1960} 1961 1962/* 1963 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1964 * to the mbuf data regions directly in the transmit lists. We also save a 1965 * copy of the pointers since the transmit list fragment pointers are 1966 * physical addresses. 1967 */ 1968 1969static void 1970sis_start(ifp) 1971 struct ifnet *ifp; 1972{ 1973 struct sis_softc *sc; 1974 struct mbuf *m_head = NULL; 1975 u_int32_t idx; 1976 1977 sc = ifp->if_softc; 1978 SIS_LOCK(sc); 1979 1980 if (!sc->sis_link) { 1981 SIS_UNLOCK(sc); 1982 return; 1983 } 1984 1985 idx = sc->sis_cdata.sis_tx_prod; 1986 1987 if (ifp->if_flags & IFF_OACTIVE) { 1988 SIS_UNLOCK(sc); 1989 return; 1990 } 1991 1992 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1993 IF_DEQUEUE(&ifp->if_snd, m_head); 1994 if (m_head == NULL) 1995 break; 1996 1997 if (sis_encap(sc, m_head, &idx)) { 1998 IF_PREPEND(&ifp->if_snd, m_head); 1999 ifp->if_flags |= IFF_OACTIVE; 2000 break; 2001 } 2002 2003 /* 2004 * If there's a BPF listener, bounce a copy of this frame 2005 * to him. 2006 */ 2007 BPF_MTAP(ifp, m_head); 2008 2009 } 2010 2011 /* Transmit */ 2012 sc->sis_cdata.sis_tx_prod = idx; 2013 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 2014 2015 /* 2016 * Set a timeout in case the chip goes out to lunch. 2017 */ 2018 ifp->if_timer = 5; 2019 2020 SIS_UNLOCK(sc); 2021 2022 return; 2023} 2024 2025static void 2026sis_init(xsc) 2027 void *xsc; 2028{ 2029 struct sis_softc *sc = xsc; 2030 struct ifnet *ifp = &sc->arpcom.ac_if; 2031 struct mii_data *mii; 2032 2033 SIS_LOCK(sc); 2034 2035 /* 2036 * Cancel pending I/O and free all RX/TX buffers. 2037 */ 2038 sis_stop(sc); 2039 2040 mii = device_get_softc(sc->sis_miibus); 2041 2042 /* Set MAC address */ 2043 if (sc->sis_type == SIS_TYPE_83815) { 2044 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2045 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2046 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2047 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2048 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2049 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2050 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2051 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2052 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2053 } else { 2054 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2055 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2056 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2057 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2058 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2059 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2060 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2061 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2062 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2063 } 2064 2065 /* Init circular RX list. */ 2066 if (sis_list_rx_init(sc) == ENOBUFS) { 2067 printf("sis%d: initialization failed: no " 2068 "memory for rx buffers\n", sc->sis_unit); 2069 sis_stop(sc); 2070 SIS_UNLOCK(sc); 2071 return; 2072 } 2073 2074 /* 2075 * Init tx descriptors. 2076 */ 2077 sis_list_tx_init(sc); 2078 2079 /* 2080 * For the NatSemi chip, we have to explicitly enable the 2081 * reception of ARP frames, as well as turn on the 'perfect 2082 * match' filter where we store the station address, otherwise 2083 * we won't receive unicasts meant for this host. 2084 */ 2085 if (sc->sis_type == SIS_TYPE_83815) { 2086 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2087 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2088 } 2089 2090 /* If we want promiscuous mode, set the allframes bit. */ 2091 if (ifp->if_flags & IFF_PROMISC) { 2092 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2093 } else { 2094 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2095 } 2096 2097 /* 2098 * Set the capture broadcast bit to capture broadcast frames. 2099 */ 2100 if (ifp->if_flags & IFF_BROADCAST) { 2101 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2102 } else { 2103 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2104 } 2105 2106 /* 2107 * Load the multicast filter. 2108 */ 2109 if (sc->sis_type == SIS_TYPE_83815) 2110 sis_setmulti_ns(sc); 2111 else 2112 sis_setmulti_sis(sc); 2113 2114 /* Turn the receive filter on */ 2115 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2116 2117 /* 2118 * Load the address of the RX and TX lists. 2119 */ 2120 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2121 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2122 2123 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2124 * the PCI bus. When this bit is set, the Max DMA Burst Size 2125 * for TX/RX DMA should be no larger than 16 double words. 2126 */ 2127 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2128 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2129 } else { 2130 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2131 } 2132 2133 2134 /* Accept Long Packets for VLAN support */ 2135 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2136 2137 /* Set TX configuration */ 2138 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2139 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2140 } else { 2141 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2142 } 2143 2144 /* Set full/half duplex mode. */ 2145 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2146 SIS_SETBIT(sc, SIS_TX_CFG, 2147 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2148 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2149 } else { 2150 SIS_CLRBIT(sc, SIS_TX_CFG, 2151 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2152 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2153 } 2154 2155 /* 2156 * Enable interrupts. 2157 */ 2158 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2159#ifdef DEVICE_POLLING 2160 /* 2161 * ... only enable interrupts if we are not polling, make sure 2162 * they are off otherwise. 2163 */ 2164 if (ifp->if_flags & IFF_POLLING) 2165 CSR_WRITE_4(sc, SIS_IER, 0); 2166 else 2167#endif /* DEVICE_POLLING */ 2168 CSR_WRITE_4(sc, SIS_IER, 1); 2169 2170 /* Enable receiver and transmitter. */ 2171 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2172 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2173 2174#ifdef notdef 2175 mii_mediachg(mii); 2176#endif 2177 2178 /* 2179 * Page 75 of the DP83815 manual recommends the 2180 * following register settings "for optimum 2181 * performance." Note however that at least three 2182 * of the registers are listed as "reserved" in 2183 * the register map, so who knows what they do. 2184 */ 2185 if (sc->sis_type == SIS_TYPE_83815) { 2186 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2187 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2188 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2189 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2190 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2191 } 2192 2193 ifp->if_flags |= IFF_RUNNING; 2194 ifp->if_flags &= ~IFF_OACTIVE; 2195 2196 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 2197 2198 SIS_UNLOCK(sc); 2199 2200 return; 2201} 2202 2203/* 2204 * Set media options. 2205 */ 2206static int 2207sis_ifmedia_upd(ifp) 2208 struct ifnet *ifp; 2209{ 2210 struct sis_softc *sc; 2211 struct mii_data *mii; 2212 2213 sc = ifp->if_softc; 2214 2215 mii = device_get_softc(sc->sis_miibus); 2216 sc->sis_link = 0; 2217 if (mii->mii_instance) { 2218 struct mii_softc *miisc; 2219 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2220 mii_phy_reset(miisc); 2221 } 2222 mii_mediachg(mii); 2223 2224 return(0); 2225} 2226 2227/* 2228 * Report current media status. 2229 */ 2230static void 2231sis_ifmedia_sts(ifp, ifmr) 2232 struct ifnet *ifp; 2233 struct ifmediareq *ifmr; 2234{ 2235 struct sis_softc *sc; 2236 struct mii_data *mii; 2237 2238 sc = ifp->if_softc; 2239 2240 mii = device_get_softc(sc->sis_miibus); 2241 mii_pollstat(mii); 2242 ifmr->ifm_active = mii->mii_media_active; 2243 ifmr->ifm_status = mii->mii_media_status; 2244 2245 return; 2246} 2247 2248static int 2249sis_ioctl(ifp, command, data) 2250 struct ifnet *ifp; 2251 u_long command; 2252 caddr_t data; 2253{ 2254 struct sis_softc *sc = ifp->if_softc; 2255 struct ifreq *ifr = (struct ifreq *) data; 2256 struct mii_data *mii; 2257 int error = 0; 2258 2259 switch(command) { 2260 case SIOCSIFFLAGS: 2261 if (ifp->if_flags & IFF_UP) { 2262 sis_init(sc); 2263 } else { 2264 if (ifp->if_flags & IFF_RUNNING) 2265 sis_stop(sc); 2266 } 2267 error = 0; 2268 break; 2269 case SIOCADDMULTI: 2270 case SIOCDELMULTI: 2271 SIS_LOCK(sc); 2272 if (sc->sis_type == SIS_TYPE_83815) 2273 sis_setmulti_ns(sc); 2274 else 2275 sis_setmulti_sis(sc); 2276 SIS_UNLOCK(sc); 2277 error = 0; 2278 break; 2279 case SIOCGIFMEDIA: 2280 case SIOCSIFMEDIA: 2281 mii = device_get_softc(sc->sis_miibus); 2282 SIS_LOCK(sc); 2283 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2284 SIS_UNLOCK(sc); 2285 break; 2286 default: 2287 error = ether_ioctl(ifp, command, data); 2288 break; 2289 } 2290 2291 return(error); 2292} 2293 2294static void 2295sis_watchdog(ifp) 2296 struct ifnet *ifp; 2297{ 2298 struct sis_softc *sc; 2299 2300 sc = ifp->if_softc; 2301 2302 SIS_LOCK(sc); 2303 2304 ifp->if_oerrors++; 2305 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2306 2307 sis_stop(sc); 2308 sis_reset(sc); 2309 sis_init(sc); 2310 2311 if (ifp->if_snd.ifq_head != NULL) 2312 sis_start(ifp); 2313 2314 SIS_UNLOCK(sc); 2315 2316 return; 2317} 2318 2319/* 2320 * Stop the adapter and free any mbufs allocated to the 2321 * RX and TX lists. 2322 */ 2323static void 2324sis_stop(sc) 2325 struct sis_softc *sc; 2326{ 2327 register int i; 2328 struct ifnet *ifp; 2329 2330 SIS_LOCK(sc); 2331 ifp = &sc->arpcom.ac_if; 2332 ifp->if_timer = 0; 2333 2334 untimeout(sis_tick, sc, sc->sis_stat_ch); 2335 2336 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2337#ifdef DEVICE_POLLING 2338 ether_poll_deregister(ifp); 2339#endif 2340 CSR_WRITE_4(sc, SIS_IER, 0); 2341 CSR_WRITE_4(sc, SIS_IMR, 0); 2342 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2343 DELAY(1000); 2344 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2345 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2346 2347 sc->sis_link = 0; 2348 2349 /* 2350 * Free data in the RX lists. 2351 */ 2352 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2353 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2354 bus_dmamap_unload(sc->sis_tag, 2355 sc->sis_ldata.sis_rx_list[i].sis_map); 2356 bus_dmamap_destroy(sc->sis_tag, 2357 sc->sis_ldata.sis_rx_list[i].sis_map); 2358 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2359 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2360 } 2361 } 2362 bzero(sc->sis_ldata.sis_rx_list, 2363 sizeof(sc->sis_ldata.sis_rx_list)); 2364 2365 /* 2366 * Free the TX list buffers. 2367 */ 2368 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2369 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2370 bus_dmamap_unload(sc->sis_tag, 2371 sc->sis_ldata.sis_tx_list[i].sis_map); 2372 bus_dmamap_destroy(sc->sis_tag, 2373 sc->sis_ldata.sis_tx_list[i].sis_map); 2374 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2375 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2376 } 2377 } 2378 2379 bzero(sc->sis_ldata.sis_tx_list, 2380 sizeof(sc->sis_ldata.sis_tx_list)); 2381 2382 SIS_UNLOCK(sc); 2383 2384 return; 2385} 2386 2387/* 2388 * Stop all chip I/O so that the kernel's probe routines don't 2389 * get confused by errant DMAs when rebooting. 2390 */ 2391static void 2392sis_shutdown(dev) 2393 device_t dev; 2394{ 2395 struct sis_softc *sc; 2396 2397 sc = device_get_softc(dev); 2398 SIS_LOCK(sc); 2399 sis_reset(sc); 2400 sis_stop(sc); 2401 SIS_UNLOCK(sc); 2402 2403 return; 2404} 2405