if_sis.c revision 122689
150974Swpaul/* 250974Swpaul * Copyright (c) 1997, 1998, 1999 350974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 450974Swpaul * 550974Swpaul * Redistribution and use in source and binary forms, with or without 650974Swpaul * modification, are permitted provided that the following conditions 750974Swpaul * are met: 850974Swpaul * 1. Redistributions of source code must retain the above copyright 950974Swpaul * notice, this list of conditions and the following disclaimer. 1050974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150974Swpaul * notice, this list of conditions and the following disclaimer in the 1250974Swpaul * documentation and/or other materials provided with the distribution. 1350974Swpaul * 3. All advertising materials mentioning features or use of this software 1450974Swpaul * must display the following acknowledgement: 1550974Swpaul * This product includes software developed by Bill Paul. 1650974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750974Swpaul * may be used to endorse or promote products derived from this software 1850974Swpaul * without specific prior written permission. 1950974Swpaul * 2050974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150974Swpaul */ 3250974Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 122689 2003-11-14 19:00:32Z sam $"); 35122678Sobrien 3650974Swpaul/* 3750974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3850974Swpaul * available from http://www.sis.com.tw. 3950974Swpaul * 4064963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4164963Swpaul * available from http://www.national.com. 4264963Swpaul * 4350974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4450974Swpaul * Electrical Engineering Department 4550974Swpaul * Columbia University, New York City 4650974Swpaul */ 4750974Swpaul/* 4850974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 4950974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5050974Swpaul * has a single perfect filter entry for the station address and a 5150974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5250974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5350974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5450974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5550974Swpaul * 5650974Swpaul * The only downside to this chipset is that RX descriptors must be 5750974Swpaul * longword aligned. 5850974Swpaul */ 5950974Swpaul 6050974Swpaul#include <sys/param.h> 6150974Swpaul#include <sys/systm.h> 6250974Swpaul#include <sys/sockio.h> 6350974Swpaul#include <sys/mbuf.h> 6450974Swpaul#include <sys/malloc.h> 6550974Swpaul#include <sys/kernel.h> 6650974Swpaul#include <sys/socket.h> 6787059Sluigi#include <sys/sysctl.h> 6850974Swpaul 6950974Swpaul#include <net/if.h> 7050974Swpaul#include <net/if_arp.h> 7150974Swpaul#include <net/ethernet.h> 7250974Swpaul#include <net/if_dl.h> 7350974Swpaul#include <net/if_media.h> 7487390Sjhay#include <net/if_types.h> 7587390Sjhay#include <net/if_vlan_var.h> 7650974Swpaul 7750974Swpaul#include <net/bpf.h> 7850974Swpaul 7950974Swpaul#include <machine/bus_pio.h> 8050974Swpaul#include <machine/bus_memio.h> 8150974Swpaul#include <machine/bus.h> 8250974Swpaul#include <machine/resource.h> 8350974Swpaul#include <sys/bus.h> 8450974Swpaul#include <sys/rman.h> 8550974Swpaul 8650974Swpaul#include <dev/mii/mii.h> 8750974Swpaul#include <dev/mii/miivar.h> 8850974Swpaul 89119288Simp#include <dev/pci/pcireg.h> 90119288Simp#include <dev/pci/pcivar.h> 9150974Swpaul 9250974Swpaul#define SIS_USEIOSPACE 9350974Swpaul 9450974Swpaul#include <pci/if_sisreg.h> 9550974Swpaul 96113506SmdoddMODULE_DEPEND(sis, pci, 1, 1, 1); 97113506SmdoddMODULE_DEPEND(sis, ether, 1, 1, 1); 9859758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 9959758Speter 10051089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 10150974Swpaul#include "miibus_if.h" 10250974Swpaul 10350974Swpaul/* 10450974Swpaul * Various supported device vendors/types and their names. 10550974Swpaul */ 10650974Swpaulstatic struct sis_type sis_devs[] = { 10750974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 10850974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 109119712Sphk { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 11050974Swpaul { 0, 0, NULL } 11150974Swpaul}; 11250974Swpaul 11392739Salfredstatic int sis_probe (device_t); 11492739Salfredstatic int sis_attach (device_t); 11592739Salfredstatic int sis_detach (device_t); 11650974Swpaul 11792739Salfredstatic int sis_newbuf (struct sis_softc *, 11892739Salfred struct sis_desc *, struct mbuf *); 11992739Salfredstatic int sis_encap (struct sis_softc *, 120121262Ssilby struct mbuf **, u_int32_t *); 12192739Salfredstatic void sis_rxeof (struct sis_softc *); 12292739Salfredstatic void sis_rxeoc (struct sis_softc *); 12392739Salfredstatic void sis_txeof (struct sis_softc *); 12492739Salfredstatic void sis_intr (void *); 12592739Salfredstatic void sis_tick (void *); 12692739Salfredstatic void sis_start (struct ifnet *); 12792739Salfredstatic int sis_ioctl (struct ifnet *, u_long, caddr_t); 12892739Salfredstatic void sis_init (void *); 12992739Salfredstatic void sis_stop (struct sis_softc *); 13092739Salfredstatic void sis_watchdog (struct ifnet *); 13192739Salfredstatic void sis_shutdown (device_t); 13292739Salfredstatic int sis_ifmedia_upd (struct ifnet *); 13392739Salfredstatic void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 13450974Swpaul 13592739Salfredstatic u_int16_t sis_reverse (u_int16_t); 13692739Salfredstatic void sis_delay (struct sis_softc *); 13792739Salfredstatic void sis_eeprom_idle (struct sis_softc *); 13892739Salfredstatic void sis_eeprom_putbyte (struct sis_softc *, int); 13992739Salfredstatic void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 14092739Salfredstatic void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 14172197Swpaul#ifdef __i386__ 14292739Salfredstatic void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 14392739Salfred int, int); 14492739Salfredstatic void sis_read_mac (struct sis_softc *, device_t, caddr_t); 14592739Salfredstatic device_t sis_find_bridge (device_t); 14672197Swpaul#endif 14772197Swpaul 148109060Smbrstatic void sis_mii_sync (struct sis_softc *); 149109060Smbrstatic void sis_mii_send (struct sis_softc *, u_int32_t, int); 150109060Smbrstatic int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 151109060Smbrstatic int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 15292739Salfredstatic int sis_miibus_readreg (device_t, int, int); 15392739Salfredstatic int sis_miibus_writereg (device_t, int, int, int); 15492739Salfredstatic void sis_miibus_statchg (device_t); 15550974Swpaul 15692739Salfredstatic void sis_setmulti_sis (struct sis_softc *); 15792739Salfredstatic void sis_setmulti_ns (struct sis_softc *); 158122625Sobrienstatic u_int32_t sis_mchash (struct sis_softc *, caddr_t); 15992739Salfredstatic void sis_reset (struct sis_softc *); 16092739Salfredstatic int sis_list_rx_init (struct sis_softc *); 16192739Salfredstatic int sis_list_tx_init (struct sis_softc *); 16250974Swpaul 16392739Salfredstatic void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 16492739Salfredstatic void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 16592739Salfredstatic void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 16650974Swpaul#ifdef SIS_USEIOSPACE 16750974Swpaul#define SIS_RES SYS_RES_IOPORT 16850974Swpaul#define SIS_RID SIS_PCI_LOIO 16950974Swpaul#else 17051030Swpaul#define SIS_RES SYS_RES_MEMORY 17151030Swpaul#define SIS_RID SIS_PCI_LOMEM 17250974Swpaul#endif 17350974Swpaul 17450974Swpaulstatic device_method_t sis_methods[] = { 17550974Swpaul /* Device interface */ 17650974Swpaul DEVMETHOD(device_probe, sis_probe), 17750974Swpaul DEVMETHOD(device_attach, sis_attach), 17850974Swpaul DEVMETHOD(device_detach, sis_detach), 17950974Swpaul DEVMETHOD(device_shutdown, sis_shutdown), 18050974Swpaul 18150974Swpaul /* bus interface */ 18250974Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 18350974Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 18450974Swpaul 18550974Swpaul /* MII interface */ 18650974Swpaul DEVMETHOD(miibus_readreg, sis_miibus_readreg), 18750974Swpaul DEVMETHOD(miibus_writereg, sis_miibus_writereg), 18850974Swpaul DEVMETHOD(miibus_statchg, sis_miibus_statchg), 18950974Swpaul 19050974Swpaul { 0, 0 } 19150974Swpaul}; 19250974Swpaul 19350974Swpaulstatic driver_t sis_driver = { 19451455Swpaul "sis", 19550974Swpaul sis_methods, 19650974Swpaul sizeof(struct sis_softc) 19750974Swpaul}; 19850974Swpaul 19950974Swpaulstatic devclass_t sis_devclass; 20050974Swpaul 201113506SmdoddDRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 20251473SwpaulDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 20350974Swpaul 20450974Swpaul#define SIS_SETBIT(sc, reg, x) \ 20550974Swpaul CSR_WRITE_4(sc, reg, \ 20650974Swpaul CSR_READ_4(sc, reg) | (x)) 20750974Swpaul 20850974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 20950974Swpaul CSR_WRITE_4(sc, reg, \ 21050974Swpaul CSR_READ_4(sc, reg) & ~(x)) 21150974Swpaul 21250974Swpaul#define SIO_SET(x) \ 21350974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 21450974Swpaul 21550974Swpaul#define SIO_CLR(x) \ 21650974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 21750974Swpaul 21881713Swpaulstatic void 21981713Swpaulsis_dma_map_desc_next(arg, segs, nseg, error) 22081713Swpaul void *arg; 22181713Swpaul bus_dma_segment_t *segs; 22281713Swpaul int nseg, error; 22381713Swpaul{ 22481713Swpaul struct sis_desc *r; 22581713Swpaul 22681713Swpaul r = arg; 22781713Swpaul r->sis_next = segs->ds_addr; 22881713Swpaul 22981713Swpaul return; 23081713Swpaul} 23181713Swpaul 23281713Swpaulstatic void 23381713Swpaulsis_dma_map_desc_ptr(arg, segs, nseg, error) 23481713Swpaul void *arg; 23581713Swpaul bus_dma_segment_t *segs; 23681713Swpaul int nseg, error; 23781713Swpaul{ 23881713Swpaul struct sis_desc *r; 23981713Swpaul 24081713Swpaul r = arg; 24181713Swpaul r->sis_ptr = segs->ds_addr; 24281713Swpaul 24381713Swpaul return; 24481713Swpaul} 24581713Swpaul 24681713Swpaulstatic void 24781713Swpaulsis_dma_map_ring(arg, segs, nseg, error) 24881713Swpaul void *arg; 24981713Swpaul bus_dma_segment_t *segs; 25081713Swpaul int nseg, error; 25181713Swpaul{ 25281713Swpaul u_int32_t *p; 25381713Swpaul 25481713Swpaul p = arg; 25581713Swpaul *p = segs->ds_addr; 25681713Swpaul 25781713Swpaul return; 25881713Swpaul} 25981713Swpaul 26062672Swpaul/* 26162672Swpaul * Routine to reverse the bits in a word. Stolen almost 26262672Swpaul * verbatim from /usr/games/fortune. 26362672Swpaul */ 264102334Salfredstatic u_int16_t 265102334Salfredsis_reverse(n) 26662672Swpaul u_int16_t n; 26762672Swpaul{ 26862672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 26962672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 27062672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 27162672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 27262672Swpaul 27362672Swpaul return(n); 27462672Swpaul} 27562672Swpaul 276102334Salfredstatic void 277102334Salfredsis_delay(sc) 27850974Swpaul struct sis_softc *sc; 27950974Swpaul{ 28050974Swpaul int idx; 28150974Swpaul 28250974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 28350974Swpaul CSR_READ_4(sc, SIS_CSR); 28450974Swpaul 28550974Swpaul return; 28650974Swpaul} 28750974Swpaul 288102334Salfredstatic void 289102334Salfredsis_eeprom_idle(sc) 29050974Swpaul struct sis_softc *sc; 29150974Swpaul{ 29250974Swpaul register int i; 29350974Swpaul 29450974Swpaul SIO_SET(SIS_EECTL_CSEL); 29550974Swpaul sis_delay(sc); 29650974Swpaul SIO_SET(SIS_EECTL_CLK); 29750974Swpaul sis_delay(sc); 29850974Swpaul 29950974Swpaul for (i = 0; i < 25; i++) { 30050974Swpaul SIO_CLR(SIS_EECTL_CLK); 30150974Swpaul sis_delay(sc); 30250974Swpaul SIO_SET(SIS_EECTL_CLK); 30350974Swpaul sis_delay(sc); 30450974Swpaul } 30550974Swpaul 30650974Swpaul SIO_CLR(SIS_EECTL_CLK); 30750974Swpaul sis_delay(sc); 30850974Swpaul SIO_CLR(SIS_EECTL_CSEL); 30950974Swpaul sis_delay(sc); 31050974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 31150974Swpaul 31250974Swpaul return; 31350974Swpaul} 31450974Swpaul 31550974Swpaul/* 31650974Swpaul * Send a read command and address to the EEPROM, check for ACK. 31750974Swpaul */ 318102334Salfredstatic void 319102334Salfredsis_eeprom_putbyte(sc, addr) 32050974Swpaul struct sis_softc *sc; 32150974Swpaul int addr; 32250974Swpaul{ 32350974Swpaul register int d, i; 32450974Swpaul 32550974Swpaul d = addr | SIS_EECMD_READ; 32650974Swpaul 32750974Swpaul /* 32850974Swpaul * Feed in each bit and stobe the clock. 32950974Swpaul */ 33050974Swpaul for (i = 0x400; i; i >>= 1) { 33150974Swpaul if (d & i) { 33250974Swpaul SIO_SET(SIS_EECTL_DIN); 33350974Swpaul } else { 33450974Swpaul SIO_CLR(SIS_EECTL_DIN); 33550974Swpaul } 33650974Swpaul sis_delay(sc); 33750974Swpaul SIO_SET(SIS_EECTL_CLK); 33850974Swpaul sis_delay(sc); 33950974Swpaul SIO_CLR(SIS_EECTL_CLK); 34050974Swpaul sis_delay(sc); 34150974Swpaul } 34250974Swpaul 34350974Swpaul return; 34450974Swpaul} 34550974Swpaul 34650974Swpaul/* 34750974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 34850974Swpaul */ 349102334Salfredstatic void 350102334Salfredsis_eeprom_getword(sc, addr, dest) 35150974Swpaul struct sis_softc *sc; 35250974Swpaul int addr; 35350974Swpaul u_int16_t *dest; 35450974Swpaul{ 35550974Swpaul register int i; 35650974Swpaul u_int16_t word = 0; 35750974Swpaul 35850974Swpaul /* Force EEPROM to idle state. */ 35950974Swpaul sis_eeprom_idle(sc); 36050974Swpaul 36150974Swpaul /* Enter EEPROM access mode. */ 36250974Swpaul sis_delay(sc); 36362672Swpaul SIO_CLR(SIS_EECTL_CLK); 36462672Swpaul sis_delay(sc); 36550974Swpaul SIO_SET(SIS_EECTL_CSEL); 36650974Swpaul sis_delay(sc); 36750974Swpaul 36850974Swpaul /* 36950974Swpaul * Send address of word we want to read. 37050974Swpaul */ 37150974Swpaul sis_eeprom_putbyte(sc, addr); 37250974Swpaul 37350974Swpaul /* 37450974Swpaul * Start reading bits from EEPROM. 37550974Swpaul */ 37650974Swpaul for (i = 0x8000; i; i >>= 1) { 37750974Swpaul SIO_SET(SIS_EECTL_CLK); 37850974Swpaul sis_delay(sc); 37950974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 38050974Swpaul word |= i; 38150974Swpaul sis_delay(sc); 38250974Swpaul SIO_CLR(SIS_EECTL_CLK); 38350974Swpaul sis_delay(sc); 38450974Swpaul } 38550974Swpaul 38650974Swpaul /* Turn off EEPROM access mode. */ 38750974Swpaul sis_eeprom_idle(sc); 38850974Swpaul 38950974Swpaul *dest = word; 39050974Swpaul 39150974Swpaul return; 39250974Swpaul} 39350974Swpaul 39450974Swpaul/* 39550974Swpaul * Read a sequence of words from the EEPROM. 39650974Swpaul */ 397102334Salfredstatic void 398102334Salfredsis_read_eeprom(sc, dest, off, cnt, swap) 39950974Swpaul struct sis_softc *sc; 40050974Swpaul caddr_t dest; 40150974Swpaul int off; 40250974Swpaul int cnt; 40350974Swpaul int swap; 40450974Swpaul{ 40550974Swpaul int i; 40650974Swpaul u_int16_t word = 0, *ptr; 40750974Swpaul 40850974Swpaul for (i = 0; i < cnt; i++) { 40950974Swpaul sis_eeprom_getword(sc, off + i, &word); 41050974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 41150974Swpaul if (swap) 41250974Swpaul *ptr = ntohs(word); 41350974Swpaul else 41450974Swpaul *ptr = word; 41550974Swpaul } 41650974Swpaul 41750974Swpaul return; 41850974Swpaul} 41950974Swpaul 42072197Swpaul#ifdef __i386__ 421102334Salfredstatic device_t 422102334Salfredsis_find_bridge(dev) 42372197Swpaul device_t dev; 42472197Swpaul{ 42572197Swpaul devclass_t pci_devclass; 42672197Swpaul device_t *pci_devices; 42772197Swpaul int pci_count = 0; 42872197Swpaul device_t *pci_children; 42972197Swpaul int pci_childcount = 0; 43072197Swpaul device_t *busp, *childp; 43187994Sarchie device_t child = NULL; 43272197Swpaul int i, j; 43372197Swpaul 43472197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 43572197Swpaul return(NULL); 43672197Swpaul 43772197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 43872197Swpaul 43972197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 44072197Swpaul pci_childcount = 0; 44172197Swpaul device_get_children(*busp, &pci_children, &pci_childcount); 44272197Swpaul for (j = 0, childp = pci_children; 44372197Swpaul j < pci_childcount; j++, childp++) { 44472197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 44572197Swpaul pci_get_device(*childp) == 0x0008) { 44687994Sarchie child = *childp; 44787994Sarchie goto done; 44872197Swpaul } 44972197Swpaul } 45072197Swpaul } 45172197Swpaul 45287994Sarchiedone: 45372197Swpaul free(pci_devices, M_TEMP); 45472197Swpaul free(pci_children, M_TEMP); 45587994Sarchie return(child); 45672197Swpaul} 45772197Swpaul 458102334Salfredstatic void 459102334Salfredsis_read_cmos(sc, dev, dest, off, cnt) 46072197Swpaul struct sis_softc *sc; 46172197Swpaul device_t dev; 46272197Swpaul caddr_t dest; 46372197Swpaul int off; 46472197Swpaul int cnt; 46572197Swpaul{ 46672197Swpaul device_t bridge; 46772197Swpaul u_int8_t reg; 46872197Swpaul int i; 46972197Swpaul bus_space_tag_t btag; 47072197Swpaul 47172197Swpaul bridge = sis_find_bridge(dev); 47272197Swpaul if (bridge == NULL) 47372197Swpaul return; 47472197Swpaul reg = pci_read_config(bridge, 0x48, 1); 47572197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 47672197Swpaul 47772197Swpaul /* XXX */ 47872197Swpaul btag = I386_BUS_SPACE_IO; 47972197Swpaul 48072197Swpaul for (i = 0; i < cnt; i++) { 48172197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 48272197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 48372197Swpaul } 48472197Swpaul 48572197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 48672197Swpaul return; 48772197Swpaul} 48889296Swpaul 489102334Salfredstatic void 490102334Salfredsis_read_mac(sc, dev, dest) 49189296Swpaul struct sis_softc *sc; 49289296Swpaul device_t dev; 49389296Swpaul caddr_t dest; 49489296Swpaul{ 49589296Swpaul u_int32_t filtsave, csrsave; 49689296Swpaul 49789296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 49889296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 49989296Swpaul 50089296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 50189296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 50289296Swpaul 50389296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 50489296Swpaul 50589296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 50689296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 50789296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 50889296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 50989296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 51089296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51189296Swpaul 51289296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 51389296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 51489296Swpaul return; 51589296Swpaul} 51672197Swpaul#endif 51772197Swpaul 518109060Smbr/* 519109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 520109060Smbr */ 521109060Smbrstatic void sis_mii_sync(sc) 522109060Smbr struct sis_softc *sc; 523109060Smbr{ 524109060Smbr register int i; 525109060Smbr 526109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 527109060Smbr 528109060Smbr for (i = 0; i < 32; i++) { 529109060Smbr SIO_SET(SIS_MII_CLK); 530109060Smbr DELAY(1); 531109060Smbr SIO_CLR(SIS_MII_CLK); 532109060Smbr DELAY(1); 533109060Smbr } 534109060Smbr 535109060Smbr return; 536109060Smbr} 537109060Smbr 538109060Smbr/* 539109060Smbr * Clock a series of bits through the MII. 540109060Smbr */ 541109060Smbrstatic void sis_mii_send(sc, bits, cnt) 542109060Smbr struct sis_softc *sc; 543109060Smbr u_int32_t bits; 544109060Smbr int cnt; 545109060Smbr{ 546109060Smbr int i; 547109060Smbr 548109060Smbr SIO_CLR(SIS_MII_CLK); 549109060Smbr 550109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 551109060Smbr if (bits & i) { 552109060Smbr SIO_SET(SIS_MII_DATA); 553109060Smbr } else { 554109060Smbr SIO_CLR(SIS_MII_DATA); 555109060Smbr } 556109060Smbr DELAY(1); 557109060Smbr SIO_CLR(SIS_MII_CLK); 558109060Smbr DELAY(1); 559109060Smbr SIO_SET(SIS_MII_CLK); 560109060Smbr } 561109060Smbr} 562109060Smbr 563109060Smbr/* 564109060Smbr * Read an PHY register through the MII. 565109060Smbr */ 566109060Smbrstatic int sis_mii_readreg(sc, frame) 567109060Smbr struct sis_softc *sc; 568109060Smbr struct sis_mii_frame *frame; 569109060Smbr 570109060Smbr{ 571109060Smbr int i, ack, s; 572109060Smbr 573109060Smbr s = splimp(); 574109060Smbr 575109060Smbr /* 576109060Smbr * Set up frame for RX. 577109060Smbr */ 578109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 579109060Smbr frame->mii_opcode = SIS_MII_READOP; 580109060Smbr frame->mii_turnaround = 0; 581109060Smbr frame->mii_data = 0; 582109060Smbr 583109060Smbr /* 584109060Smbr * Turn on data xmit. 585109060Smbr */ 586109060Smbr SIO_SET(SIS_MII_DIR); 587109060Smbr 588109060Smbr sis_mii_sync(sc); 589109060Smbr 590109060Smbr /* 591109060Smbr * Send command/address info. 592109060Smbr */ 593109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 594109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 595109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 596109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 597109060Smbr 598109060Smbr /* Idle bit */ 599109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 600109060Smbr DELAY(1); 601109060Smbr SIO_SET(SIS_MII_CLK); 602109060Smbr DELAY(1); 603109060Smbr 604109060Smbr /* Turn off xmit. */ 605109060Smbr SIO_CLR(SIS_MII_DIR); 606109060Smbr 607109060Smbr /* Check for ack */ 608109060Smbr SIO_CLR(SIS_MII_CLK); 609109060Smbr DELAY(1); 610109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 611109060Smbr SIO_SET(SIS_MII_CLK); 612109060Smbr DELAY(1); 613109060Smbr 614109060Smbr /* 615109060Smbr * Now try reading data bits. If the ack failed, we still 616109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 617109060Smbr */ 618109060Smbr if (ack) { 619109060Smbr for(i = 0; i < 16; i++) { 620109060Smbr SIO_CLR(SIS_MII_CLK); 621109060Smbr DELAY(1); 622109060Smbr SIO_SET(SIS_MII_CLK); 623109060Smbr DELAY(1); 624109060Smbr } 625109060Smbr goto fail; 626109060Smbr } 627109060Smbr 628109060Smbr for (i = 0x8000; i; i >>= 1) { 629109060Smbr SIO_CLR(SIS_MII_CLK); 630109060Smbr DELAY(1); 631109060Smbr if (!ack) { 632109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 633109060Smbr frame->mii_data |= i; 634109060Smbr DELAY(1); 635109060Smbr } 636109060Smbr SIO_SET(SIS_MII_CLK); 637109060Smbr DELAY(1); 638109060Smbr } 639109060Smbr 640109060Smbrfail: 641109060Smbr 642109060Smbr SIO_CLR(SIS_MII_CLK); 643109060Smbr DELAY(1); 644109060Smbr SIO_SET(SIS_MII_CLK); 645109060Smbr DELAY(1); 646109060Smbr 647109060Smbr splx(s); 648109060Smbr 649109060Smbr if (ack) 650109060Smbr return(1); 651109060Smbr return(0); 652109060Smbr} 653109060Smbr 654109060Smbr/* 655109060Smbr * Write to a PHY register through the MII. 656109060Smbr */ 657109060Smbrstatic int sis_mii_writereg(sc, frame) 658109060Smbr struct sis_softc *sc; 659109060Smbr struct sis_mii_frame *frame; 660109060Smbr 661109060Smbr{ 662109060Smbr int s; 663109060Smbr 664109060Smbr s = splimp(); 665109060Smbr /* 666109060Smbr * Set up frame for TX. 667109060Smbr */ 668109060Smbr 669109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 670109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 671109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 672109060Smbr 673109060Smbr /* 674109060Smbr * Turn on data output. 675109060Smbr */ 676109060Smbr SIO_SET(SIS_MII_DIR); 677109060Smbr 678109060Smbr sis_mii_sync(sc); 679109060Smbr 680109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 681109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 682109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 683109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 684109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 685109060Smbr sis_mii_send(sc, frame->mii_data, 16); 686109060Smbr 687109060Smbr /* Idle bit. */ 688109060Smbr SIO_SET(SIS_MII_CLK); 689109060Smbr DELAY(1); 690109060Smbr SIO_CLR(SIS_MII_CLK); 691109060Smbr DELAY(1); 692109060Smbr 693109060Smbr /* 694109060Smbr * Turn off xmit. 695109060Smbr */ 696109060Smbr SIO_CLR(SIS_MII_DIR); 697109060Smbr 698109060Smbr splx(s); 699109060Smbr 700109060Smbr return(0); 701109060Smbr} 702109060Smbr 703102334Salfredstatic int 704102334Salfredsis_miibus_readreg(dev, phy, reg) 70550974Swpaul device_t dev; 70650974Swpaul int phy, reg; 70750974Swpaul{ 70850974Swpaul struct sis_softc *sc; 709109060Smbr struct sis_mii_frame frame; 71050974Swpaul 71150974Swpaul sc = device_get_softc(dev); 71250974Swpaul 71362672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 71462672Swpaul if (phy != 0) 71562672Swpaul return(0); 71662672Swpaul /* 71762672Swpaul * The NatSemi chip can take a while after 71862672Swpaul * a reset to come ready, during which the BMSR 71962672Swpaul * returns a value of 0. This is *never* supposed 72062672Swpaul * to happen: some of the BMSR bits are meant to 72162672Swpaul * be hardwired in the on position, and this can 72262672Swpaul * confuse the miibus code a bit during the probe 72362672Swpaul * and attach phase. So we make an effort to check 72462672Swpaul * for this condition and wait for it to clear. 72562672Swpaul */ 72662672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 72762672Swpaul DELAY(1000); 728109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 72962672Swpaul } 73062672Swpaul 731109976Smbr /* 732109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 733109976Smbr * through mdio. Use the enhanced PHY access register 734109976Smbr * again for them. 735109976Smbr */ 73689296Swpaul if (sc->sis_type == SIS_TYPE_900 && 737109976Smbr sc->sis_rev < SIS_REV_635) { 738109976Smbr int i, val = 0; 73950974Swpaul 740109976Smbr if (phy != 0) 741109976Smbr return(0); 74250974Swpaul 743109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, 744109976Smbr (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 745109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 74650974Swpaul 747109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 748109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 749109976Smbr break; 750109976Smbr } 751109976Smbr 752109976Smbr if (i == SIS_TIMEOUT) { 753109976Smbr printf("sis%d: PHY failed to come ready\n", 754109976Smbr sc->sis_unit); 755109976Smbr return(0); 756109976Smbr } 757109976Smbr 758109976Smbr val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 759109976Smbr 760109976Smbr if (val == 0xFFFF) 761109976Smbr return(0); 762109976Smbr 763109976Smbr return(val); 764109976Smbr } else { 765109976Smbr bzero((char *)&frame, sizeof(frame)); 766109976Smbr 767109976Smbr frame.mii_phyaddr = phy; 768109976Smbr frame.mii_regaddr = reg; 769109976Smbr sis_mii_readreg(sc, &frame); 770109976Smbr 771109976Smbr return(frame.mii_data); 772109976Smbr } 77350974Swpaul} 77450974Swpaul 775102334Salfredstatic int 776102334Salfredsis_miibus_writereg(dev, phy, reg, data) 77750974Swpaul device_t dev; 77850974Swpaul int phy, reg, data; 77950974Swpaul{ 78050974Swpaul struct sis_softc *sc; 781109060Smbr struct sis_mii_frame frame; 78250974Swpaul 78350974Swpaul sc = device_get_softc(dev); 78450974Swpaul 78562672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 78662672Swpaul if (phy != 0) 78762672Swpaul return(0); 78862672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 78962672Swpaul return(0); 79062672Swpaul } 79162672Swpaul 792109976Smbr /* 793109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 794109976Smbr * through mdio. Use the enhanced PHY access register 795109976Smbr * again for them. 796109976Smbr */ 797109976Smbr if (sc->sis_type == SIS_TYPE_900 && 798109976Smbr sc->sis_rev < SIS_REV_635) { 799109976Smbr int i; 80050974Swpaul 801109976Smbr if (phy != 0) 802109976Smbr return(0); 80350974Swpaul 804109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 805109976Smbr (reg << 6) | SIS_PHYOP_WRITE); 806109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 80750974Swpaul 808109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 809109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 810109976Smbr break; 811109976Smbr } 81250974Swpaul 813109976Smbr if (i == SIS_TIMEOUT) 814109976Smbr printf("sis%d: PHY failed to come ready\n", 815109976Smbr sc->sis_unit); 816109976Smbr } else { 817109976Smbr bzero((char *)&frame, sizeof(frame)); 818109976Smbr 819109976Smbr frame.mii_phyaddr = phy; 820109976Smbr frame.mii_regaddr = reg; 821109976Smbr frame.mii_data = data; 822109976Smbr sis_mii_writereg(sc, &frame); 823109976Smbr } 82450974Swpaul return(0); 82550974Swpaul} 82650974Swpaul 827102334Salfredstatic void 828102334Salfredsis_miibus_statchg(dev) 82950974Swpaul device_t dev; 83050974Swpaul{ 83150974Swpaul struct sis_softc *sc; 83250974Swpaul 83350974Swpaul sc = device_get_softc(dev); 83464963Swpaul sis_init(sc); 83550974Swpaul 83650974Swpaul return; 83750974Swpaul} 83850974Swpaul 839102334Salfredstatic u_int32_t 840122625Sobriensis_mchash(sc, addr) 84162672Swpaul struct sis_softc *sc; 84250974Swpaul caddr_t addr; 84350974Swpaul{ 84450974Swpaul u_int32_t crc, carry; 845122625Sobrien int idx, bit; 846122625Sobrien u_int8_t data; 84750974Swpaul 84850974Swpaul /* Compute CRC for the address value. */ 84950974Swpaul crc = 0xFFFFFFFF; /* initial value */ 85050974Swpaul 851122625Sobrien for (idx = 0; idx < 6; idx++) { 852122625Sobrien for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 853122625Sobrien carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 85450974Swpaul crc <<= 1; 85550974Swpaul if (carry) 85650974Swpaul crc = (crc ^ 0x04c11db6) | carry; 85750974Swpaul } 85850974Swpaul } 85950974Swpaul 86062672Swpaul /* 86162672Swpaul * return the filter bit position 86262672Swpaul * 86362672Swpaul * The NatSemi chip has a 512-bit filter, which is 86462672Swpaul * different than the SiS, so we special-case it. 86562672Swpaul */ 86662672Swpaul if (sc->sis_type == SIS_TYPE_83815) 867109060Smbr return (crc >> 23); 868109976Smbr else if (sc->sis_rev >= SIS_REV_635 || 869109976Smbr sc->sis_rev == SIS_REV_900B) 870109060Smbr return (crc >> 24); 871109976Smbr else 872109976Smbr return (crc >> 25); 87350974Swpaul} 87450974Swpaul 875102334Salfredstatic void 876102334Salfredsis_setmulti_ns(sc) 87750974Swpaul struct sis_softc *sc; 87850974Swpaul{ 87950974Swpaul struct ifnet *ifp; 88050974Swpaul struct ifmultiaddr *ifma; 88150974Swpaul u_int32_t h = 0, i, filtsave; 88262672Swpaul int bit, index; 88350974Swpaul 88450974Swpaul ifp = &sc->arpcom.ac_if; 88550974Swpaul 88650974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 88762672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 88850974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 88950974Swpaul return; 89050974Swpaul } 89150974Swpaul 89262672Swpaul /* 89362672Swpaul * We have to explicitly enable the multicast hash table 89462672Swpaul * on the NatSemi chip if we want to use it, which we do. 89562672Swpaul */ 89662672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 89750974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 89850974Swpaul 89950974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 90050974Swpaul 90150974Swpaul /* first, zot all the existing hash bits */ 90262672Swpaul for (i = 0; i < 32; i++) { 90362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 90462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 90562672Swpaul } 90662672Swpaul 90772084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 90862672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 90962672Swpaul continue; 910122625Sobrien h = sis_mchash(sc, 911122625Sobrien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 91262672Swpaul index = h >> 3; 91362672Swpaul bit = h & 0x1F; 91462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 91562672Swpaul if (bit > 0xF) 91662672Swpaul bit -= 0x10; 91762672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 91862672Swpaul } 91962672Swpaul 92062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 92162672Swpaul 92262672Swpaul return; 92362672Swpaul} 92462672Swpaul 925102334Salfredstatic void 926102334Salfredsis_setmulti_sis(sc) 92762672Swpaul struct sis_softc *sc; 92862672Swpaul{ 92962672Swpaul struct ifnet *ifp; 93062672Swpaul struct ifmultiaddr *ifma; 931109060Smbr u_int32_t h, i, n, ctl; 932109060Smbr u_int16_t hashes[16]; 93362672Swpaul 93462672Swpaul ifp = &sc->arpcom.ac_if; 93562672Swpaul 936109060Smbr /* hash table size */ 937109976Smbr if (sc->sis_rev >= SIS_REV_635 || 938109976Smbr sc->sis_rev == SIS_REV_900B) 939109976Smbr n = 16; 940109976Smbr else 941109976Smbr n = 8; 94262672Swpaul 943109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 94462672Swpaul 945109060Smbr if (ifp->if_flags & IFF_BROADCAST) 946109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 94762672Swpaul 948109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 949109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 950109060Smbr if (ifp->if_flags & IFF_PROMISC) 951109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 952109060Smbr for (i = 0; i < n; i++) 953109060Smbr hashes[i] = ~0; 954109060Smbr } else { 955109060Smbr for (i = 0; i < n; i++) 956109060Smbr hashes[i] = 0; 957109060Smbr i = 0; 958109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 959109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 960109060Smbr continue; 961122625Sobrien h = sis_mchash(sc, 962109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 963109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 964109060Smbr i++; 965109060Smbr } 966109060Smbr if (i > n) { 967109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 968109060Smbr for (i = 0; i < n; i++) 969109060Smbr hashes[i] = ~0; 970109060Smbr } 97150974Swpaul } 97250974Swpaul 973109060Smbr for (i = 0; i < n; i++) { 974109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 975109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 97650974Swpaul } 97750974Swpaul 978109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 97950974Swpaul} 98050974Swpaul 981102334Salfredstatic void 982102334Salfredsis_reset(sc) 98350974Swpaul struct sis_softc *sc; 98450974Swpaul{ 98550974Swpaul register int i; 98650974Swpaul 98750974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 98850974Swpaul 98950974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 99050974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 99150974Swpaul break; 99250974Swpaul } 99350974Swpaul 99450974Swpaul if (i == SIS_TIMEOUT) 99550974Swpaul printf("sis%d: reset never completed\n", sc->sis_unit); 99650974Swpaul 99750974Swpaul /* Wait a little while for the chip to get its brains in order. */ 99850974Swpaul DELAY(1000); 99972813Swpaul 100072813Swpaul /* 100172813Swpaul * If this is a NetSemi chip, make sure to clear 100272813Swpaul * PME mode. 100372813Swpaul */ 100472813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 100572813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 100672813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 100772813Swpaul } 100872813Swpaul 100950974Swpaul return; 101050974Swpaul} 101150974Swpaul 101250974Swpaul/* 101350974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 101450974Swpaul * IDs against our list and return a device name if we find a match. 101550974Swpaul */ 1016102334Salfredstatic int 1017102334Salfredsis_probe(dev) 101850974Swpaul device_t dev; 101950974Swpaul{ 102050974Swpaul struct sis_type *t; 102150974Swpaul 102250974Swpaul t = sis_devs; 102350974Swpaul 102450974Swpaul while(t->sis_name != NULL) { 102550974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 102650974Swpaul (pci_get_device(dev) == t->sis_did)) { 102750974Swpaul device_set_desc(dev, t->sis_name); 102850974Swpaul return(0); 102950974Swpaul } 103050974Swpaul t++; 103150974Swpaul } 103250974Swpaul 103350974Swpaul return(ENXIO); 103450974Swpaul} 103550974Swpaul 103650974Swpaul/* 103750974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 103850974Swpaul * setup and ethernet/BPF attach. 103950974Swpaul */ 1040102334Salfredstatic int 1041102334Salfredsis_attach(dev) 104250974Swpaul device_t dev; 104350974Swpaul{ 104450974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 104550974Swpaul struct sis_softc *sc; 104650974Swpaul struct ifnet *ifp; 1047109061Smbr int unit, error = 0, rid, waittime = 0; 104850974Swpaul 1049109061Smbr waittime = 0; 105050974Swpaul sc = device_get_softc(dev); 105150974Swpaul unit = device_get_unit(dev); 105250974Swpaul 1053119712Sphk sc->sis_self = dev; 1054119712Sphk 105593818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 105693818Sjhb MTX_DEF | MTX_RECURSE); 105769583Swpaul 105850974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 105950974Swpaul sc->sis_type = SIS_TYPE_900; 106050974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 106150974Swpaul sc->sis_type = SIS_TYPE_7016; 106262672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 106362672Swpaul sc->sis_type = SIS_TYPE_83815; 106450974Swpaul 106589296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1066117208Simp#ifndef BURN_BRIDGES 106750974Swpaul /* 106850974Swpaul * Handle power management nonsense. 106950974Swpaul */ 107072813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 107172813Swpaul u_int32_t iobase, membase, irq; 107250974Swpaul 107372813Swpaul /* Save important PCI config data. */ 107472813Swpaul iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 107572813Swpaul membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 107672813Swpaul irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 107750974Swpaul 107872813Swpaul /* Reset the power state. */ 107972813Swpaul printf("sis%d: chip is in D%d power mode " 108072813Swpaul "-- setting to D0\n", unit, 108172813Swpaul pci_get_powerstate(dev)); 108272813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 108350974Swpaul 108472813Swpaul /* Restore PCI config data. */ 108572813Swpaul pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 108672813Swpaul pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 108772813Swpaul pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 108850974Swpaul } 1089117208Simp#endif 109050974Swpaul /* 109150974Swpaul * Map control/status registers. 109250974Swpaul */ 109372813Swpaul pci_enable_busmaster(dev); 109450974Swpaul 109550974Swpaul rid = SIS_RID; 109650974Swpaul sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 109750974Swpaul 0, ~0, 1, RF_ACTIVE); 109850974Swpaul 109950974Swpaul if (sc->sis_res == NULL) { 110050974Swpaul printf("sis%d: couldn't map ports/memory\n", unit); 110150974Swpaul error = ENXIO; 110250974Swpaul goto fail; 110350974Swpaul } 110450974Swpaul 110550974Swpaul sc->sis_btag = rman_get_bustag(sc->sis_res); 110650974Swpaul sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 110750974Swpaul 110850974Swpaul /* Allocate interrupt */ 110950974Swpaul rid = 0; 111050974Swpaul sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 111150974Swpaul RF_SHAREABLE | RF_ACTIVE); 111250974Swpaul 111350974Swpaul if (sc->sis_irq == NULL) { 111450974Swpaul printf("sis%d: couldn't map interrupt\n", unit); 111550974Swpaul error = ENXIO; 111650974Swpaul goto fail; 111750974Swpaul } 111850974Swpaul 111950974Swpaul /* Reset the adapter. */ 112050974Swpaul sis_reset(sc); 112150974Swpaul 1122109976Smbr if (sc->sis_type == SIS_TYPE_900 && 1123109976Smbr (sc->sis_rev == SIS_REV_635 || 1124109976Smbr sc->sis_rev == SIS_REV_900B)) { 1125109976Smbr SIO_SET(SIS_CFG_RND_CNT); 1126109976Smbr SIO_SET(SIS_CFG_PERR_DETECT); 1127109976Smbr } 1128109976Smbr 112950974Swpaul /* 113050974Swpaul * Get station address from the EEPROM. 113150974Swpaul */ 113262672Swpaul switch (pci_get_vendor(dev)) { 113362672Swpaul case NS_VENDORID: 1134119712Sphk sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1135119712Sphk 1136119712Sphk /* We can't update the device description, so spew */ 1137119712Sphk if (sc->sis_srr == NS_SRR_15C) 1138119712Sphk device_printf(dev, "Silicon Revision: DP83815C\n"); 1139119712Sphk else if (sc->sis_srr == NS_SRR_15D) 1140119712Sphk device_printf(dev, "Silicon Revision: DP83815D\n"); 1141119712Sphk else if (sc->sis_srr == NS_SRR_16A) 1142119712Sphk device_printf(dev, "Silicon Revision: DP83816A\n"); 1143119712Sphk else 1144119712Sphk device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1145119712Sphk 114662672Swpaul /* 114762672Swpaul * Reading the MAC address out of the EEPROM on 114862672Swpaul * the NatSemi chip takes a bit more work than 114962672Swpaul * you'd expect. The address spans 4 16-bit words, 115062672Swpaul * with the first word containing only a single bit. 115162672Swpaul * You have to shift everything over one bit to 115262672Swpaul * get it aligned properly. Also, the bits are 115362672Swpaul * stored backwards (the LSB is really the MSB, 115462672Swpaul * and so on) so you have to reverse them in order 115562672Swpaul * to get the MAC address into the form we want. 115662672Swpaul * Why? Who the hell knows. 115762672Swpaul */ 115862672Swpaul { 115962672Swpaul u_int16_t tmp[4]; 116050974Swpaul 116162672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 116262672Swpaul NS_EE_NODEADDR, 4, 0); 116362672Swpaul 116462672Swpaul /* Shift everything over one bit. */ 116562672Swpaul tmp[3] = tmp[3] >> 1; 116662681Swpaul tmp[3] |= tmp[2] << 15; 116762672Swpaul tmp[2] = tmp[2] >> 1; 116862681Swpaul tmp[2] |= tmp[1] << 15; 116962672Swpaul tmp[1] = tmp[1] >> 1; 117062681Swpaul tmp[1] |= tmp[0] << 15; 117162672Swpaul 117262672Swpaul /* Now reverse all the bits. */ 117362672Swpaul tmp[3] = sis_reverse(tmp[3]); 117462672Swpaul tmp[2] = sis_reverse(tmp[2]); 117562672Swpaul tmp[1] = sis_reverse(tmp[1]); 117662672Swpaul 117762672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 117862672Swpaul } 117962672Swpaul break; 118062672Swpaul case SIS_VENDORID: 118162672Swpaul default: 118272197Swpaul#ifdef __i386__ 118372197Swpaul /* 118472197Swpaul * If this is a SiS 630E chipset with an embedded 118572197Swpaul * SiS 900 controller, we have to read the MAC address 118672197Swpaul * from the APC CMOS RAM. Our method for doing this 118772197Swpaul * is very ugly since we have to reach out and grab 118872197Swpaul * ahold of hardware for which we cannot properly 118972197Swpaul * allocate resources. This code is only compiled on 119072197Swpaul * the i386 architecture since the SiS 630E chipset 119172197Swpaul * is for x86 motherboards only. Note that there are 119272197Swpaul * a lot of magic numbers in this hack. These are 119372197Swpaul * taken from SiS's Linux driver. I'd like to replace 119472197Swpaul * them with proper symbolic definitions, but that 119572197Swpaul * requires some datasheets that I don't have access 119672197Swpaul * to at the moment. 119772197Swpaul */ 119889296Swpaul if (sc->sis_rev == SIS_REV_630S || 119989296Swpaul sc->sis_rev == SIS_REV_630E || 120090328Sambrisko sc->sis_rev == SIS_REV_630EA1) 120172197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 120289296Swpaul 120390328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 120490328Sambrisko sc->sis_rev == SIS_REV_630ET) 120589296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1206109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1207109061Smbr /* Allow to read EEPROM from LAN. It is shared 1208109061Smbr * between a 1394 controller and the NIC and each 1209109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1210109061Smbr */ 1211109061Smbr SIO_SET(SIS_EECMD_REQ); 1212109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1213109061Smbr waittime++) { 1214109061Smbr /* Force EEPROM to idle state. */ 1215109061Smbr sis_eeprom_idle(sc); 1216109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1217109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1218109061Smbr SIS_EE_NODEADDR, 3, 0); 1219109061Smbr break; 1220109061Smbr } 1221109061Smbr DELAY(1); 1222109061Smbr } 1223109061Smbr /* 1224109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1225109061Smbr * can operate on the i2c bus. 1226109061Smbr */ 1227109061Smbr SIO_SET(SIS_EECTL_CLK); 1228109061Smbr /* Refuse EEPROM access by LAN */ 1229109061Smbr SIO_SET(SIS_EECMD_DONE); 1230109061Smbr } else 123172197Swpaul#endif 123272197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 123372197Swpaul SIS_EE_NODEADDR, 3, 0); 123462672Swpaul break; 123562672Swpaul } 123662672Swpaul 123750974Swpaul /* 123850974Swpaul * A SiS chip was detected. Inform the world. 123950974Swpaul */ 124050974Swpaul printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 124150974Swpaul 124250974Swpaul sc->sis_unit = unit; 1243119785Ssam callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 124450974Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 124550974Swpaul 124681713Swpaul /* 124781713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 124881713Swpaul */ 124981713Swpaul#define SIS_NSEG_NEW 32 125081713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 125181713Swpaul 1, 0, /* alignment, boundary */ 125281713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 125381713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 125481713Swpaul NULL, NULL, /* filter, filterarg */ 125581713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 125681713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 125781713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1258117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 125981713Swpaul &sc->sis_parent_tag); 1260112872Snjl if (error) 1261112872Snjl goto fail; 126250974Swpaul 126381713Swpaul /* 1264112872Snjl * Now allocate a tag for the DMA descriptor lists and a chunk 1265112872Snjl * of DMA-able memory based on the tag. Also obtain the physical 1266112872Snjl * addresses of the RX and TX ring, which we'll need later. 126781713Swpaul * All of our lists are allocated as a contiguous block 126881713Swpaul * of memory. 126981713Swpaul */ 127081713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 127181713Swpaul 1, 0, /* alignment, boundary */ 127281713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 127381713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 127481713Swpaul NULL, NULL, /* filter, filterarg */ 127581713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 127681713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 127781713Swpaul 0, /* flags */ 1278117126Sscottl busdma_lock_mutex, /* lockfunc */ 1279117126Sscottl &Giant, /* lockarg */ 128081713Swpaul &sc->sis_ldata.sis_rx_tag); 1281112872Snjl if (error) 1282112872Snjl goto fail; 128381713Swpaul 1284112872Snjl error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1285118089Smux (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1286112872Snjl &sc->sis_ldata.sis_rx_dmamap); 1287112872Snjl 1288112872Snjl if (error) { 1289112872Snjl printf("sis%d: no memory for rx list buffers!\n", unit); 1290112872Snjl bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1291112872Snjl sc->sis_ldata.sis_rx_tag = NULL; 1292112872Snjl goto fail; 1293112872Snjl } 1294112872Snjl 1295112872Snjl error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1296112872Snjl sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1297112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1298112872Snjl &sc->sis_cdata.sis_rx_paddr, 0); 1299112872Snjl 1300112872Snjl if (error) { 1301112872Snjl printf("sis%d: cannot get address of the rx ring!\n", unit); 1302112872Snjl bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1303112872Snjl sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1304112872Snjl bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1305112872Snjl sc->sis_ldata.sis_rx_tag = NULL; 1306112872Snjl goto fail; 1307112872Snjl } 1308112872Snjl 130981713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 131081713Swpaul 1, 0, /* alignment, boundary */ 131181713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 131281713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 131381713Swpaul NULL, NULL, /* filter, filterarg */ 131481713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 131581713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 131681713Swpaul 0, /* flags */ 1317117126Sscottl busdma_lock_mutex, /* lockfunc */ 1318117126Sscottl &Giant, /* lockarg */ 131981713Swpaul &sc->sis_ldata.sis_tx_tag); 1320112872Snjl if (error) 1321112872Snjl goto fail; 132281713Swpaul 132381713Swpaul error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1324118089Smux (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 132581713Swpaul &sc->sis_ldata.sis_tx_dmamap); 132681713Swpaul 132781713Swpaul if (error) { 1328112872Snjl printf("sis%d: no memory for tx list buffers!\n", unit); 132981713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1330112872Snjl sc->sis_ldata.sis_tx_tag = NULL; 133150974Swpaul goto fail; 133250974Swpaul } 133350974Swpaul 1334112872Snjl error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1335112872Snjl sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1336112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1337112872Snjl &sc->sis_cdata.sis_tx_paddr, 0); 133881713Swpaul 133981713Swpaul if (error) { 1340112872Snjl printf("sis%d: cannot get address of the tx ring!\n", unit); 1341112872Snjl bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 134281713Swpaul sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 134381713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1344112872Snjl sc->sis_ldata.sis_tx_tag = NULL; 134581713Swpaul goto fail; 134681713Swpaul } 134781713Swpaul 1348112872Snjl error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1349112872Snjl 1, 0, /* alignment, boundary */ 1350112872Snjl BUS_SPACE_MAXADDR, /* lowaddr */ 1351112872Snjl BUS_SPACE_MAXADDR, /* highaddr */ 1352112872Snjl NULL, NULL, /* filter, filterarg */ 1353112872Snjl MCLBYTES, 1, /* maxsize,nsegments */ 1354112872Snjl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1355112872Snjl 0, /* flags */ 1356117126Sscottl busdma_lock_mutex, /* lockfunc */ 1357117126Sscottl &Giant, /* lockarg */ 1358112872Snjl &sc->sis_tag); 1359112872Snjl if (error) 1360112872Snjl goto fail; 136181713Swpaul 136281713Swpaul /* 136381713Swpaul * Obtain the physical addresses of the RX and TX 136481713Swpaul * rings which we'll need later in the init routine. 136581713Swpaul */ 136681713Swpaul 136750974Swpaul ifp = &sc->arpcom.ac_if; 136850974Swpaul ifp->if_softc = sc; 1369121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 137050974Swpaul ifp->if_mtu = ETHERMTU; 137150974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 137250974Swpaul ifp->if_ioctl = sis_ioctl; 137350974Swpaul ifp->if_output = ether_output; 137450974Swpaul ifp->if_start = sis_start; 137550974Swpaul ifp->if_watchdog = sis_watchdog; 137650974Swpaul ifp->if_init = sis_init; 137750974Swpaul ifp->if_baudrate = 10000000; 137850974Swpaul ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 137950974Swpaul 138050974Swpaul /* 138150974Swpaul * Do MII setup. 138250974Swpaul */ 138350974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 138450974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 138550974Swpaul printf("sis%d: MII without any PHY!\n", sc->sis_unit); 138650974Swpaul error = ENXIO; 138750974Swpaul goto fail; 138850974Swpaul } 138950974Swpaul 139050974Swpaul /* 139163090Sarchie * Call MI attach routine. 139250974Swpaul */ 1393106936Ssam ether_ifattach(ifp, eaddr); 139487390Sjhay 139587390Sjhay /* 139687390Sjhay * Tell the upper layer(s) we support long frames. 139787390Sjhay */ 139887390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1399106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 140087390Sjhay 1401113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1402121697Ssam error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1403112872Snjl sis_intr, sc, &sc->sis_intrhand); 140450974Swpaul 1405112872Snjl if (error) { 1406112872Snjl printf("sis%d: couldn't set up irq\n", unit); 1407113609Snjl ether_ifdetach(ifp); 1408112872Snjl goto fail; 1409112872Snjl } 1410112872Snjl 141150974Swpaulfail: 1412112872Snjl if (error) 1413112872Snjl sis_detach(dev); 1414112872Snjl 141550974Swpaul return(error); 141650974Swpaul} 141750974Swpaul 1418113609Snjl/* 1419113609Snjl * Shutdown hardware and free up resources. This can be called any 1420113609Snjl * time after the mutex has been initialized. It is called in both 1421113609Snjl * the error case in attach and the normal detach case so it needs 1422113609Snjl * to be careful about only freeing resources that have actually been 1423113609Snjl * allocated. 1424113609Snjl */ 1425102334Salfredstatic int 1426102334Salfredsis_detach(dev) 142750974Swpaul device_t dev; 142850974Swpaul{ 142950974Swpaul struct sis_softc *sc; 143050974Swpaul struct ifnet *ifp; 143150974Swpaul 143250974Swpaul sc = device_get_softc(dev); 1433112880Sjhb KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 143467087Swpaul SIS_LOCK(sc); 143550974Swpaul ifp = &sc->arpcom.ac_if; 143650974Swpaul 1437118089Smux /* These should only be active if attach succeeded. */ 1438113812Simp if (device_is_attached(dev)) { 1439113609Snjl sis_reset(sc); 1440113609Snjl sis_stop(sc); 1441112872Snjl ether_ifdetach(ifp); 1442113609Snjl } 1443113609Snjl if (sc->sis_miibus) 1444112872Snjl device_delete_child(dev, sc->sis_miibus); 1445113609Snjl bus_generic_detach(dev); 144650974Swpaul 1447112872Snjl if (sc->sis_intrhand) 1448112872Snjl bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1449112872Snjl if (sc->sis_irq) 1450112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1451112872Snjl if (sc->sis_res) 1452112872Snjl bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 145350974Swpaul 1454112872Snjl if (sc->sis_ldata.sis_rx_tag) { 1455112872Snjl bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1456112872Snjl sc->sis_ldata.sis_rx_dmamap); 1457112872Snjl bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1458112872Snjl sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1459112872Snjl bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1460112872Snjl } 1461112872Snjl if (sc->sis_ldata.sis_tx_tag) { 1462112872Snjl bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1463112872Snjl sc->sis_ldata.sis_tx_dmamap); 1464112872Snjl bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1465112872Snjl sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1466112872Snjl bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1467112872Snjl } 1468112872Snjl if (sc->sis_parent_tag) 1469112872Snjl bus_dma_tag_destroy(sc->sis_parent_tag); 1470112872Snjl if (sc->sis_tag) 1471112872Snjl bus_dma_tag_destroy(sc->sis_tag); 147250974Swpaul 147367087Swpaul SIS_UNLOCK(sc); 147467087Swpaul mtx_destroy(&sc->sis_mtx); 147550974Swpaul 147650974Swpaul return(0); 147750974Swpaul} 147850974Swpaul 147950974Swpaul/* 148050974Swpaul * Initialize the transmit descriptors. 148150974Swpaul */ 1482102334Salfredstatic int 1483102334Salfredsis_list_tx_init(sc) 148450974Swpaul struct sis_softc *sc; 148550974Swpaul{ 148650974Swpaul struct sis_list_data *ld; 148750974Swpaul struct sis_ring_data *cd; 148887059Sluigi int i, nexti; 148950974Swpaul 149050974Swpaul cd = &sc->sis_cdata; 149181713Swpaul ld = &sc->sis_ldata; 149250974Swpaul 149350974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 149487102Sluigi nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 149550974Swpaul ld->sis_tx_list[i].sis_nextdesc = 149687059Sluigi &ld->sis_tx_list[nexti]; 149781713Swpaul bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 149881713Swpaul sc->sis_ldata.sis_tx_dmamap, 149987059Sluigi &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 150081713Swpaul sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 150150974Swpaul ld->sis_tx_list[i].sis_mbuf = NULL; 150250974Swpaul ld->sis_tx_list[i].sis_ptr = 0; 150350974Swpaul ld->sis_tx_list[i].sis_ctl = 0; 150450974Swpaul } 150550974Swpaul 150650974Swpaul cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 150750974Swpaul 150881713Swpaul bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 150981713Swpaul sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 151081713Swpaul 151150974Swpaul return(0); 151250974Swpaul} 151350974Swpaul 151450974Swpaul/* 151550974Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 151650974Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 151750974Swpaul * points back to the first. 151850974Swpaul */ 1519102334Salfredstatic int 1520102334Salfredsis_list_rx_init(sc) 152150974Swpaul struct sis_softc *sc; 152250974Swpaul{ 152350974Swpaul struct sis_list_data *ld; 152450974Swpaul struct sis_ring_data *cd; 152587059Sluigi int i,nexti; 152650974Swpaul 152781713Swpaul ld = &sc->sis_ldata; 152850974Swpaul cd = &sc->sis_cdata; 152950974Swpaul 153050974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 153150974Swpaul if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 153250974Swpaul return(ENOBUFS); 153387102Sluigi nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 153450974Swpaul ld->sis_rx_list[i].sis_nextdesc = 153587059Sluigi &ld->sis_rx_list[nexti]; 153681713Swpaul bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 153781713Swpaul sc->sis_ldata.sis_rx_dmamap, 153887059Sluigi &ld->sis_rx_list[nexti], 153981713Swpaul sizeof(struct sis_desc), sis_dma_map_desc_next, 154081713Swpaul &ld->sis_rx_list[i], 0); 154150974Swpaul } 154250974Swpaul 154381713Swpaul bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 154481713Swpaul sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 154581713Swpaul 154650974Swpaul cd->sis_rx_prod = 0; 154750974Swpaul 154850974Swpaul return(0); 154950974Swpaul} 155050974Swpaul 155150974Swpaul/* 155250974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 155350974Swpaul */ 1554102334Salfredstatic int 1555102334Salfredsis_newbuf(sc, c, m) 155650974Swpaul struct sis_softc *sc; 155750974Swpaul struct sis_desc *c; 155850974Swpaul struct mbuf *m; 155950974Swpaul{ 156050974Swpaul 156181713Swpaul if (c == NULL) 156281713Swpaul return(EINVAL); 156381713Swpaul 156450974Swpaul if (m == NULL) { 1565111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1566101340Sluigi if (m == NULL) 156750974Swpaul return(ENOBUFS); 1568101340Sluigi } else 1569101340Sluigi m->m_data = m->m_ext.ext_buf; 157050974Swpaul 1571101340Sluigi c->sis_mbuf = m; 157250974Swpaul c->sis_ctl = SIS_RXLEN; 157350974Swpaul 157481713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 157581713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1576101464Sluigi mtod(m, void *), MCLBYTES, 157781713Swpaul sis_dma_map_desc_ptr, c, 0); 157881713Swpaul bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 157981713Swpaul 158050974Swpaul return(0); 158150974Swpaul} 158250974Swpaul 158350974Swpaul/* 158450974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 158550974Swpaul * the higher level protocols. 158650974Swpaul */ 1587102334Salfredstatic void 1588102334Salfredsis_rxeof(sc) 158950974Swpaul struct sis_softc *sc; 159050974Swpaul{ 159150974Swpaul struct mbuf *m; 159250974Swpaul struct ifnet *ifp; 159350974Swpaul struct sis_desc *cur_rx; 159450974Swpaul int i, total_len = 0; 159550974Swpaul u_int32_t rxstat; 159650974Swpaul 1597122689Ssam SIS_LOCK_ASSERT(sc); 1598122689Ssam 159950974Swpaul ifp = &sc->arpcom.ac_if; 160050974Swpaul i = sc->sis_cdata.sis_rx_prod; 160150974Swpaul 160281713Swpaul while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 160350974Swpaul 160487902Sluigi#ifdef DEVICE_POLLING 1605102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 160687902Sluigi if (sc->rxcycles <= 0) 160787902Sluigi break; 160887902Sluigi sc->rxcycles--; 160987902Sluigi } 161087902Sluigi#endif /* DEVICE_POLLING */ 161181713Swpaul cur_rx = &sc->sis_ldata.sis_rx_list[i]; 161250974Swpaul rxstat = cur_rx->sis_rxstat; 161381713Swpaul bus_dmamap_sync(sc->sis_tag, 161481713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 161581713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 161681713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 161750974Swpaul m = cur_rx->sis_mbuf; 161850974Swpaul cur_rx->sis_mbuf = NULL; 161950974Swpaul total_len = SIS_RXBYTES(cur_rx); 162050974Swpaul SIS_INC(i, SIS_RX_LIST_CNT); 162150974Swpaul 162250974Swpaul /* 162350974Swpaul * If an error occurs, update stats, clear the 162450974Swpaul * status word and leave the mbuf cluster in place: 162550974Swpaul * it should simply get re-used next time this descriptor 162650974Swpaul * comes up in the ring. 162750974Swpaul */ 162850974Swpaul if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 162950974Swpaul ifp->if_ierrors++; 163050974Swpaul if (rxstat & SIS_RXSTAT_COLL) 163150974Swpaul ifp->if_collisions++; 163250974Swpaul sis_newbuf(sc, cur_rx, m); 163350974Swpaul continue; 163450974Swpaul } 163550974Swpaul 163650974Swpaul /* No errors; receive the packet. */ 163787059Sluigi#ifdef __i386__ 163887059Sluigi /* 163987059Sluigi * On the x86 we do not have alignment problems, so try to 164087059Sluigi * allocate a new buffer for the receive ring, and pass up 164187059Sluigi * the one where the packet is already, saving the expensive 164287059Sluigi * copy done in m_devget(). 164387059Sluigi * If we are on an architecture with alignment problems, or 164487059Sluigi * if the allocation fails, then use m_devget and leave the 164587059Sluigi * existing buffer in the receive ring. 164687059Sluigi */ 1647101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 164887059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1649101464Sluigi else 165087059Sluigi#endif 165187059Sluigi { 165287059Sluigi struct mbuf *m0; 165387059Sluigi m0 = m_devget(mtod(m, char *), total_len, 165487059Sluigi ETHER_ALIGN, ifp, NULL); 165587059Sluigi sis_newbuf(sc, cur_rx, m); 165687059Sluigi if (m0 == NULL) { 165787059Sluigi ifp->if_ierrors++; 165887059Sluigi continue; 165987059Sluigi } 166087059Sluigi m = m0; 166150974Swpaul } 166250974Swpaul 166350974Swpaul ifp->if_ipackets++; 1664106936Ssam m->m_pkthdr.rcvif = ifp; 1665106936Ssam 1666122689Ssam SIS_UNLOCK(sc); 1667106936Ssam (*ifp->if_input)(ifp, m); 1668122689Ssam SIS_LOCK(sc); 166950974Swpaul } 167050974Swpaul 167150974Swpaul sc->sis_cdata.sis_rx_prod = i; 167250974Swpaul 167350974Swpaul return; 167450974Swpaul} 167550974Swpaul 1676105219Sphkstatic void 1677102334Salfredsis_rxeoc(sc) 167850974Swpaul struct sis_softc *sc; 167950974Swpaul{ 168050974Swpaul sis_rxeof(sc); 168150974Swpaul sis_init(sc); 168250974Swpaul return; 168350974Swpaul} 168450974Swpaul 168550974Swpaul/* 168650974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 168750974Swpaul * the list buffers. 168850974Swpaul */ 168950974Swpaul 1690102334Salfredstatic void 1691102334Salfredsis_txeof(sc) 169250974Swpaul struct sis_softc *sc; 169350974Swpaul{ 169450974Swpaul struct ifnet *ifp; 169550974Swpaul u_int32_t idx; 169650974Swpaul 169750974Swpaul ifp = &sc->arpcom.ac_if; 169850974Swpaul 169950974Swpaul /* 170050974Swpaul * Go through our tx list and free mbufs for those 170150974Swpaul * frames that have been transmitted. 170250974Swpaul */ 170399163Sluigi for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 170499163Sluigi sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 170599163Sluigi struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 170650974Swpaul 170750974Swpaul if (SIS_OWNDESC(cur_tx)) 170850974Swpaul break; 170950974Swpaul 171099163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 171150974Swpaul continue; 171250974Swpaul 171350974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 171450974Swpaul ifp->if_oerrors++; 171550974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 171650974Swpaul ifp->if_collisions++; 171750974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 171850974Swpaul ifp->if_collisions++; 171950974Swpaul } 172050974Swpaul 172150974Swpaul ifp->if_collisions += 172250974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 172350974Swpaul 172450974Swpaul ifp->if_opackets++; 172550974Swpaul if (cur_tx->sis_mbuf != NULL) { 172650974Swpaul m_freem(cur_tx->sis_mbuf); 172750974Swpaul cur_tx->sis_mbuf = NULL; 172881713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 172981713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 173050974Swpaul } 173199163Sluigi } 173250974Swpaul 173399163Sluigi if (idx != sc->sis_cdata.sis_tx_cons) { 173499163Sluigi /* we freed up some buffers */ 173599163Sluigi sc->sis_cdata.sis_tx_cons = idx; 173699163Sluigi ifp->if_flags &= ~IFF_OACTIVE; 173750974Swpaul } 173850974Swpaul 173999163Sluigi ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 174050974Swpaul 174150974Swpaul return; 174250974Swpaul} 174350974Swpaul 1744102334Salfredstatic void 1745102334Salfredsis_tick(xsc) 174650974Swpaul void *xsc; 174750974Swpaul{ 174850974Swpaul struct sis_softc *sc; 174950974Swpaul struct mii_data *mii; 175064963Swpaul struct ifnet *ifp; 175150974Swpaul 175250974Swpaul sc = xsc; 175367087Swpaul SIS_LOCK(sc); 1754117858Scognet sc->in_tick = 1; 175564963Swpaul ifp = &sc->arpcom.ac_if; 175664963Swpaul 175750974Swpaul mii = device_get_softc(sc->sis_miibus); 175850974Swpaul mii_tick(mii); 175964963Swpaul 176084147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 176184147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 176284147Sjlemon sc->sis_link++; 176384147Sjlemon if (ifp->if_snd.ifq_head != NULL) 176484147Sjlemon sis_start(ifp); 176564963Swpaul } 176664963Swpaul 1767119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1768117858Scognet sc->in_tick = 0; 176967087Swpaul SIS_UNLOCK(sc); 177050974Swpaul 177150974Swpaul return; 177250974Swpaul} 177350974Swpaul 177487902Sluigi#ifdef DEVICE_POLLING 177587902Sluigistatic poll_handler_t sis_poll; 177687902Sluigi 177787902Sluigistatic void 177887902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 177987902Sluigi{ 178087973Speter struct sis_softc *sc = ifp->if_softc; 178187973Speter 178287902Sluigi SIS_LOCK(sc); 178387902Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 178487902Sluigi CSR_WRITE_4(sc, SIS_IER, 1); 178587902Sluigi goto done; 178687902Sluigi } 178787902Sluigi 178887902Sluigi /* 178987902Sluigi * On the sis, reading the status register also clears it. 179087902Sluigi * So before returning to intr mode we must make sure that all 179187902Sluigi * possible pending sources of interrupts have been served. 179287902Sluigi * In practice this means run to completion the *eof routines, 179387902Sluigi * and then call the interrupt routine 179487902Sluigi */ 179587902Sluigi sc->rxcycles = count; 179687902Sluigi sis_rxeof(sc); 179787902Sluigi sis_txeof(sc); 179887902Sluigi if (ifp->if_snd.ifq_head != NULL) 179987902Sluigi sis_start(ifp); 180087902Sluigi 180187902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 180287902Sluigi u_int32_t status; 180387902Sluigi 180487902Sluigi /* Reading the ISR register clears all interrupts. */ 180587902Sluigi status = CSR_READ_4(sc, SIS_ISR); 180687902Sluigi 180787902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 180887902Sluigi sis_rxeoc(sc); 180987902Sluigi 181087902Sluigi if (status & (SIS_ISR_RX_IDLE)) 181187902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 181287902Sluigi 181387902Sluigi if (status & SIS_ISR_SYSERR) { 181487902Sluigi sis_reset(sc); 181587902Sluigi sis_init(sc); 181687902Sluigi } 181787902Sluigi } 181887902Sluigidone: 181987902Sluigi SIS_UNLOCK(sc); 182087902Sluigi return; 182187902Sluigi} 182287902Sluigi#endif /* DEVICE_POLLING */ 182387902Sluigi 1824102334Salfredstatic void 1825102334Salfredsis_intr(arg) 182650974Swpaul void *arg; 182750974Swpaul{ 182850974Swpaul struct sis_softc *sc; 182950974Swpaul struct ifnet *ifp; 183050974Swpaul u_int32_t status; 183150974Swpaul 183250974Swpaul sc = arg; 183350974Swpaul ifp = &sc->arpcom.ac_if; 183450974Swpaul 183586984Sluigi SIS_LOCK(sc); 183687902Sluigi#ifdef DEVICE_POLLING 1837102052Ssobomax if (ifp->if_flags & IFF_POLLING) 183887902Sluigi goto done; 183987902Sluigi if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 184087902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 184187902Sluigi goto done; 184287902Sluigi } 184387902Sluigi#endif /* DEVICE_POLLING */ 184487902Sluigi 184550974Swpaul /* Supress unwanted interrupts */ 184650974Swpaul if (!(ifp->if_flags & IFF_UP)) { 184750974Swpaul sis_stop(sc); 184886984Sluigi goto done; 184950974Swpaul } 185050974Swpaul 185150974Swpaul /* Disable interrupts. */ 185250974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 185350974Swpaul 185450974Swpaul for (;;) { 185550974Swpaul /* Reading the ISR register clears all interrupts. */ 185650974Swpaul status = CSR_READ_4(sc, SIS_ISR); 185750974Swpaul 185850974Swpaul if ((status & SIS_INTRS) == 0) 185950974Swpaul break; 186050974Swpaul 186186984Sluigi if (status & 186286984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 186386984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 186450974Swpaul sis_txeof(sc); 186550974Swpaul 186686984Sluigi if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 186750974Swpaul sis_rxeof(sc); 186850974Swpaul 186986984Sluigi if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 187050974Swpaul sis_rxeoc(sc); 187150974Swpaul 187286984Sluigi if (status & (SIS_ISR_RX_IDLE)) 187386984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 187486984Sluigi 187550974Swpaul if (status & SIS_ISR_SYSERR) { 187650974Swpaul sis_reset(sc); 187750974Swpaul sis_init(sc); 187850974Swpaul } 187950974Swpaul } 188050974Swpaul 188150974Swpaul /* Re-enable interrupts. */ 188250974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 188350974Swpaul 188450974Swpaul if (ifp->if_snd.ifq_head != NULL) 188550974Swpaul sis_start(ifp); 188686984Sluigidone: 188767087Swpaul SIS_UNLOCK(sc); 188867087Swpaul 188950974Swpaul return; 189050974Swpaul} 189150974Swpaul 189250974Swpaul/* 189350974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 189450974Swpaul * pointers to the fragment pointers. 189550974Swpaul */ 1896102334Salfredstatic int 1897102334Salfredsis_encap(sc, m_head, txidx) 189850974Swpaul struct sis_softc *sc; 1899121262Ssilby struct mbuf **m_head; 190050974Swpaul u_int32_t *txidx; 190150974Swpaul{ 190250974Swpaul struct sis_desc *f = NULL; 190350974Swpaul struct mbuf *m; 1904112808Ssilby int frag, cur, cnt = 0, chainlen = 0; 190550974Swpaul 190650974Swpaul /* 1907112808Ssilby * If there's no way we can send any packets, return now. 1908112808Ssilby */ 1909112808Ssilby if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1910112808Ssilby return (ENOBUFS); 1911112808Ssilby 1912112808Ssilby /* 1913112808Ssilby * Count the number of frags in this chain to see if 1914112808Ssilby * we need to m_defrag. Since the descriptor list is shared 1915112808Ssilby * by all packets, we'll m_defrag long chains so that they 1916112808Ssilby * do not use up the entire list, even if they would fit. 1917112808Ssilby */ 1918112808Ssilby 1919121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) 1920112808Ssilby chainlen++; 1921112808Ssilby 1922112808Ssilby if ((chainlen > SIS_TX_LIST_CNT / 4) || 1923112808Ssilby ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1924121262Ssilby m = m_defrag(*m_head, M_DONTWAIT); 1925112808Ssilby if (m == NULL) 1926112808Ssilby return (ENOBUFS); 1927121262Ssilby *m_head = m; 1928112808Ssilby } 1929112808Ssilby 1930112808Ssilby /* 193150974Swpaul * Start packing the mbufs in this chain into 193250974Swpaul * the fragment pointers. Stop when we run out 193350974Swpaul * of fragments or hit the end of the mbuf chain. 193450974Swpaul */ 193550974Swpaul cur = frag = *txidx; 193650974Swpaul 1937121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) { 193850974Swpaul if (m->m_len != 0) { 193951042Swpaul if ((SIS_TX_LIST_CNT - 194050974Swpaul (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 194150974Swpaul return(ENOBUFS); 194281713Swpaul f = &sc->sis_ldata.sis_tx_list[frag]; 194350974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 194481713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 194581713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 194681713Swpaul mtod(m, void *), m->m_len, 194781713Swpaul sis_dma_map_desc_ptr, f, 0); 194881713Swpaul bus_dmamap_sync(sc->sis_tag, 194981713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 195050974Swpaul if (cnt != 0) 195150974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 195250974Swpaul cur = frag; 195350974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 195450974Swpaul cnt++; 195550974Swpaul } 195650974Swpaul } 195750974Swpaul 195850974Swpaul if (m != NULL) 195950974Swpaul return(ENOBUFS); 196050974Swpaul 1961121262Ssilby sc->sis_ldata.sis_tx_list[cur].sis_mbuf = *m_head; 196281713Swpaul sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 196381713Swpaul sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 196450974Swpaul sc->sis_cdata.sis_tx_cnt += cnt; 196550974Swpaul *txidx = frag; 196650974Swpaul 196750974Swpaul return(0); 196850974Swpaul} 196950974Swpaul 197050974Swpaul/* 197150974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 197250974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 197350974Swpaul * copy of the pointers since the transmit list fragment pointers are 197450974Swpaul * physical addresses. 197550974Swpaul */ 197650974Swpaul 1977102334Salfredstatic void 1978102334Salfredsis_start(ifp) 197950974Swpaul struct ifnet *ifp; 198050974Swpaul{ 198150974Swpaul struct sis_softc *sc; 198250974Swpaul struct mbuf *m_head = NULL; 198350974Swpaul u_int32_t idx; 198450974Swpaul 198550974Swpaul sc = ifp->if_softc; 198667087Swpaul SIS_LOCK(sc); 198750974Swpaul 198867087Swpaul if (!sc->sis_link) { 198967087Swpaul SIS_UNLOCK(sc); 199064963Swpaul return; 199167087Swpaul } 199264963Swpaul 199350974Swpaul idx = sc->sis_cdata.sis_tx_prod; 199450974Swpaul 199567087Swpaul if (ifp->if_flags & IFF_OACTIVE) { 199667087Swpaul SIS_UNLOCK(sc); 199750974Swpaul return; 199867087Swpaul } 199950974Swpaul 200081713Swpaul while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 200150974Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 200250974Swpaul if (m_head == NULL) 200350974Swpaul break; 200450974Swpaul 2005121262Ssilby if (sis_encap(sc, &m_head, &idx)) { 200650974Swpaul IF_PREPEND(&ifp->if_snd, m_head); 200750974Swpaul ifp->if_flags |= IFF_OACTIVE; 200850974Swpaul break; 200950974Swpaul } 201050974Swpaul 201150974Swpaul /* 201250974Swpaul * If there's a BPF listener, bounce a copy of this frame 201350974Swpaul * to him. 201450974Swpaul */ 2015106936Ssam BPF_MTAP(ifp, m_head); 201651583Swpaul 201750974Swpaul } 201850974Swpaul 201950974Swpaul /* Transmit */ 202050974Swpaul sc->sis_cdata.sis_tx_prod = idx; 202150974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 202250974Swpaul 202350974Swpaul /* 202450974Swpaul * Set a timeout in case the chip goes out to lunch. 202550974Swpaul */ 202650974Swpaul ifp->if_timer = 5; 202750974Swpaul 202867087Swpaul SIS_UNLOCK(sc); 202967087Swpaul 203050974Swpaul return; 203150974Swpaul} 203250974Swpaul 2033102334Salfredstatic void 2034102334Salfredsis_init(xsc) 203550974Swpaul void *xsc; 203650974Swpaul{ 203750974Swpaul struct sis_softc *sc = xsc; 203850974Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 203950974Swpaul struct mii_data *mii; 204050974Swpaul 204167087Swpaul SIS_LOCK(sc); 204250974Swpaul 204350974Swpaul /* 204450974Swpaul * Cancel pending I/O and free all RX/TX buffers. 204550974Swpaul */ 204650974Swpaul sis_stop(sc); 204750974Swpaul 2048119712Sphk#ifdef notyet 2049119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2050119712Sphk /* 2051119712Sphk * Configure 400usec of interrupt holdoff. This is based 2052119712Sphk * on emperical tests on a Soekris 4801. 2053119712Sphk */ 2054119712Sphk CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2055119712Sphk } 2056119712Sphk#endif 2057119712Sphk 205850974Swpaul mii = device_get_softc(sc->sis_miibus); 205950974Swpaul 206050974Swpaul /* Set MAC address */ 206162672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 206262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 206362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 206462672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 206562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 206662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 206762672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 206862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 206962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 207062672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 207162672Swpaul } else { 207262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 207362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 207462672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 207562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 207662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 207762672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 207862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 207962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 208062672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 208162672Swpaul } 208250974Swpaul 208350974Swpaul /* Init circular RX list. */ 208450974Swpaul if (sis_list_rx_init(sc) == ENOBUFS) { 208550974Swpaul printf("sis%d: initialization failed: no " 208650974Swpaul "memory for rx buffers\n", sc->sis_unit); 208750974Swpaul sis_stop(sc); 208867087Swpaul SIS_UNLOCK(sc); 208950974Swpaul return; 209050974Swpaul } 209150974Swpaul 209250974Swpaul /* 209350974Swpaul * Init tx descriptors. 209450974Swpaul */ 209550974Swpaul sis_list_tx_init(sc); 209650974Swpaul 209762672Swpaul /* 209862672Swpaul * For the NatSemi chip, we have to explicitly enable the 209962672Swpaul * reception of ARP frames, as well as turn on the 'perfect 210062672Swpaul * match' filter where we store the station address, otherwise 210162672Swpaul * we won't receive unicasts meant for this host. 210262672Swpaul */ 210362672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 210462672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 210562672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 210662672Swpaul } 210762672Swpaul 210850974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 210950974Swpaul if (ifp->if_flags & IFF_PROMISC) { 211050974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 211150974Swpaul } else { 211250974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 211350974Swpaul } 211450974Swpaul 211550974Swpaul /* 211650974Swpaul * Set the capture broadcast bit to capture broadcast frames. 211750974Swpaul */ 211850974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 211950974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 212050974Swpaul } else { 212150974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 212250974Swpaul } 212350974Swpaul 212450974Swpaul /* 212550974Swpaul * Load the multicast filter. 212650974Swpaul */ 212762672Swpaul if (sc->sis_type == SIS_TYPE_83815) 212862672Swpaul sis_setmulti_ns(sc); 212962672Swpaul else 213062672Swpaul sis_setmulti_sis(sc); 213150974Swpaul 213250974Swpaul /* Turn the receive filter on */ 213350974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 213450974Swpaul 213550974Swpaul /* 213650974Swpaul * Load the address of the RX and TX lists. 213750974Swpaul */ 213881713Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 213981713Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 214050974Swpaul 2141109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2142109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 2143109059Smbr * for TX/RX DMA should be no larger than 16 double words. 2144109059Smbr */ 2145109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2146109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2147109059Smbr } else { 2148109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2149109059Smbr } 215064963Swpaul 2151109059Smbr 215287390Sjhay /* Accept Long Packets for VLAN support */ 215387390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 215487390Sjhay 215550974Swpaul /* Set TX configuration */ 215664963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 215764963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 215864963Swpaul } else { 215964963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 216064963Swpaul } 216150974Swpaul 216264963Swpaul /* Set full/half duplex mode. */ 216364963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 216464963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 216564963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 216664963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 216764963Swpaul } else { 216864963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 216964963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 217064963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 217164963Swpaul } 217264963Swpaul 2173119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2174119130Ssam IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2175119130Ssam uint32_t reg; 2176119130Ssam 2177119130Ssam /* 2178119130Ssam * Some DP83815s experience problems when used with short 2179119130Ssam * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2180119130Ssam * sequence adjusts the DSP's signal attenuation to fix the 2181119130Ssam * problem. 2182119130Ssam */ 2183119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2184119130Ssam 2185119130Ssam reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2186119130Ssam CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2187119130Ssam DELAY(100); 2188119130Ssam reg = CSR_READ_4(sc, NS_PHY_TDATA); 2189119130Ssam if ((reg & 0x0080) == 0 || (reg & 0xff) >= 0xd8) { 2190119712Sphk device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2191119130Ssam CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2192119130Ssam SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2193119130Ssam } 2194119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2195119130Ssam } 2196119130Ssam 219750974Swpaul /* 219850974Swpaul * Enable interrupts. 219950974Swpaul */ 220050974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 220187902Sluigi#ifdef DEVICE_POLLING 220287902Sluigi /* 220387902Sluigi * ... only enable interrupts if we are not polling, make sure 220487902Sluigi * they are off otherwise. 220587902Sluigi */ 2206102052Ssobomax if (ifp->if_flags & IFF_POLLING) 220787902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 220887902Sluigi else 220987902Sluigi#endif /* DEVICE_POLLING */ 221050974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 221150974Swpaul 221250974Swpaul /* Enable receiver and transmitter. */ 221350974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 221450974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 221550974Swpaul 221664963Swpaul#ifdef notdef 221750974Swpaul mii_mediachg(mii); 221864963Swpaul#endif 221950974Swpaul 222064963Swpaul /* 222164963Swpaul * Page 75 of the DP83815 manual recommends the 222264963Swpaul * following register settings "for optimum 222364963Swpaul * performance." Note however that at least three 222464963Swpaul * of the registers are listed as "reserved" in 222564963Swpaul * the register map, so who knows what they do. 222664963Swpaul */ 222764963Swpaul if (sc->sis_type == SIS_TYPE_83815) { 222864963Swpaul CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 222964963Swpaul CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 223064963Swpaul CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 223164963Swpaul CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 223264963Swpaul CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 223364963Swpaul } 223464963Swpaul 223550974Swpaul ifp->if_flags |= IFF_RUNNING; 223650974Swpaul ifp->if_flags &= ~IFF_OACTIVE; 223750974Swpaul 2238117858Scognet if (!sc->in_tick) 2239119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 224050974Swpaul 224167087Swpaul SIS_UNLOCK(sc); 224267087Swpaul 224350974Swpaul return; 224450974Swpaul} 224550974Swpaul 224650974Swpaul/* 224750974Swpaul * Set media options. 224850974Swpaul */ 2249102334Salfredstatic int 2250102334Salfredsis_ifmedia_upd(ifp) 225150974Swpaul struct ifnet *ifp; 225250974Swpaul{ 225350974Swpaul struct sis_softc *sc; 225464963Swpaul struct mii_data *mii; 225550974Swpaul 225650974Swpaul sc = ifp->if_softc; 225750974Swpaul 225864963Swpaul mii = device_get_softc(sc->sis_miibus); 225964963Swpaul sc->sis_link = 0; 226064963Swpaul if (mii->mii_instance) { 226164963Swpaul struct mii_softc *miisc; 226272012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 226364963Swpaul mii_phy_reset(miisc); 226464963Swpaul } 226564963Swpaul mii_mediachg(mii); 226650974Swpaul 226750974Swpaul return(0); 226850974Swpaul} 226950974Swpaul 227050974Swpaul/* 227150974Swpaul * Report current media status. 227250974Swpaul */ 2273102334Salfredstatic void 2274102334Salfredsis_ifmedia_sts(ifp, ifmr) 227550974Swpaul struct ifnet *ifp; 227650974Swpaul struct ifmediareq *ifmr; 227750974Swpaul{ 227850974Swpaul struct sis_softc *sc; 227950974Swpaul struct mii_data *mii; 228050974Swpaul 228150974Swpaul sc = ifp->if_softc; 228250974Swpaul 228350974Swpaul mii = device_get_softc(sc->sis_miibus); 228450974Swpaul mii_pollstat(mii); 228550974Swpaul ifmr->ifm_active = mii->mii_media_active; 228650974Swpaul ifmr->ifm_status = mii->mii_media_status; 228750974Swpaul 228850974Swpaul return; 228950974Swpaul} 229050974Swpaul 2291102334Salfredstatic int 2292102334Salfredsis_ioctl(ifp, command, data) 229350974Swpaul struct ifnet *ifp; 229450974Swpaul u_long command; 229550974Swpaul caddr_t data; 229650974Swpaul{ 229750974Swpaul struct sis_softc *sc = ifp->if_softc; 229850974Swpaul struct ifreq *ifr = (struct ifreq *) data; 229950974Swpaul struct mii_data *mii; 230067087Swpaul int error = 0; 230150974Swpaul 230250974Swpaul switch(command) { 230350974Swpaul case SIOCSIFFLAGS: 230450974Swpaul if (ifp->if_flags & IFF_UP) { 230550974Swpaul sis_init(sc); 230650974Swpaul } else { 230750974Swpaul if (ifp->if_flags & IFF_RUNNING) 230850974Swpaul sis_stop(sc); 230950974Swpaul } 231050974Swpaul error = 0; 231150974Swpaul break; 231250974Swpaul case SIOCADDMULTI: 231350974Swpaul case SIOCDELMULTI: 231481713Swpaul SIS_LOCK(sc); 231562672Swpaul if (sc->sis_type == SIS_TYPE_83815) 231662672Swpaul sis_setmulti_ns(sc); 231762672Swpaul else 231862672Swpaul sis_setmulti_sis(sc); 231981713Swpaul SIS_UNLOCK(sc); 232050974Swpaul error = 0; 232150974Swpaul break; 232250974Swpaul case SIOCGIFMEDIA: 232350974Swpaul case SIOCSIFMEDIA: 232450974Swpaul mii = device_get_softc(sc->sis_miibus); 232581713Swpaul SIS_LOCK(sc); 232650974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 232781713Swpaul SIS_UNLOCK(sc); 232850974Swpaul break; 232950974Swpaul default: 2330106936Ssam error = ether_ioctl(ifp, command, data); 233150974Swpaul break; 233250974Swpaul } 233350974Swpaul 233450974Swpaul return(error); 233550974Swpaul} 233650974Swpaul 2337102334Salfredstatic void 2338102334Salfredsis_watchdog(ifp) 233950974Swpaul struct ifnet *ifp; 234050974Swpaul{ 234150974Swpaul struct sis_softc *sc; 234250974Swpaul 234350974Swpaul sc = ifp->if_softc; 234450974Swpaul 234567087Swpaul SIS_LOCK(sc); 234667087Swpaul 234750974Swpaul ifp->if_oerrors++; 234850974Swpaul printf("sis%d: watchdog timeout\n", sc->sis_unit); 234950974Swpaul 235050974Swpaul sis_stop(sc); 235150974Swpaul sis_reset(sc); 235250974Swpaul sis_init(sc); 235350974Swpaul 235450974Swpaul if (ifp->if_snd.ifq_head != NULL) 235550974Swpaul sis_start(ifp); 235650974Swpaul 235767087Swpaul SIS_UNLOCK(sc); 235867087Swpaul 235950974Swpaul return; 236050974Swpaul} 236150974Swpaul 236250974Swpaul/* 236350974Swpaul * Stop the adapter and free any mbufs allocated to the 236450974Swpaul * RX and TX lists. 236550974Swpaul */ 2366102334Salfredstatic void 2367102334Salfredsis_stop(sc) 236850974Swpaul struct sis_softc *sc; 236950974Swpaul{ 237050974Swpaul register int i; 237150974Swpaul struct ifnet *ifp; 237250974Swpaul 237367087Swpaul SIS_LOCK(sc); 237450974Swpaul ifp = &sc->arpcom.ac_if; 237550974Swpaul ifp->if_timer = 0; 237650974Swpaul 2377119785Ssam callout_stop(&sc->sis_stat_ch); 237887472Speter 237987472Speter ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 238087902Sluigi#ifdef DEVICE_POLLING 238187902Sluigi ether_poll_deregister(ifp); 238287902Sluigi#endif 238350974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 238450974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 238550974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 238650974Swpaul DELAY(1000); 238750974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 238850974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 238950974Swpaul 239064963Swpaul sc->sis_link = 0; 239164963Swpaul 239250974Swpaul /* 239350974Swpaul * Free data in the RX lists. 239450974Swpaul */ 239550974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 239681713Swpaul if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 239781713Swpaul bus_dmamap_unload(sc->sis_tag, 239881713Swpaul sc->sis_ldata.sis_rx_list[i].sis_map); 239981713Swpaul bus_dmamap_destroy(sc->sis_tag, 240081713Swpaul sc->sis_ldata.sis_rx_list[i].sis_map); 240181713Swpaul m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 240281713Swpaul sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 240350974Swpaul } 240450974Swpaul } 240581713Swpaul bzero(sc->sis_ldata.sis_rx_list, 240681713Swpaul sizeof(sc->sis_ldata.sis_rx_list)); 240750974Swpaul 240850974Swpaul /* 240950974Swpaul * Free the TX list buffers. 241050974Swpaul */ 241150974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 241281713Swpaul if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 241381713Swpaul bus_dmamap_unload(sc->sis_tag, 241481713Swpaul sc->sis_ldata.sis_tx_list[i].sis_map); 241581713Swpaul bus_dmamap_destroy(sc->sis_tag, 241681713Swpaul sc->sis_ldata.sis_tx_list[i].sis_map); 241781713Swpaul m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 241881713Swpaul sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 241950974Swpaul } 242050974Swpaul } 242150974Swpaul 242281713Swpaul bzero(sc->sis_ldata.sis_tx_list, 242381713Swpaul sizeof(sc->sis_ldata.sis_tx_list)); 242450974Swpaul 242567087Swpaul SIS_UNLOCK(sc); 242667087Swpaul 242750974Swpaul return; 242850974Swpaul} 242950974Swpaul 243050974Swpaul/* 243150974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 243250974Swpaul * get confused by errant DMAs when rebooting. 243350974Swpaul */ 2434102334Salfredstatic void 2435102334Salfredsis_shutdown(dev) 243650974Swpaul device_t dev; 243750974Swpaul{ 243850974Swpaul struct sis_softc *sc; 243950974Swpaul 244050974Swpaul sc = device_get_softc(dev); 244167087Swpaul SIS_LOCK(sc); 244250974Swpaul sis_reset(sc); 244350974Swpaul sis_stop(sc); 244467087Swpaul SIS_UNLOCK(sc); 244550974Swpaul 244650974Swpaul return; 244750974Swpaul} 2448