if_sis.c revision 101340
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 101340 2002-08-04 21:52:05Z luigi $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67#include <sys/sysctl.h> 68 69#include <net/if.h> 70#include <net/if_arp.h> 71#include <net/ethernet.h> 72#include <net/if_dl.h> 73#include <net/if_media.h> 74#include <net/if_types.h> 75#include <net/if_vlan_var.h> 76 77#include <net/bpf.h> 78 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <pci/pcireg.h> 90#include <pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98/* "controller miibus0" required. See GENERIC if you get errors here. */ 99#include "miibus_if.h" 100 101#ifndef lint 102static const char rcsid[] = 103 "$FreeBSD: head/sys/pci/if_sis.c 101340 2002-08-04 21:52:05Z luigi $"; 104#endif 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114}; 115 116static int sis_probe (device_t); 117static int sis_attach (device_t); 118static int sis_detach (device_t); 119 120static int sis_newbuf (struct sis_softc *, 121 struct sis_desc *, struct mbuf *); 122static int sis_encap (struct sis_softc *, 123 struct mbuf *, u_int32_t *); 124static void sis_rxeof (struct sis_softc *); 125static void sis_rxeoc (struct sis_softc *); 126static void sis_txeof (struct sis_softc *); 127static void sis_intr (void *); 128static void sis_tick (void *); 129static void sis_start (struct ifnet *); 130static int sis_ioctl (struct ifnet *, u_long, caddr_t); 131static void sis_init (void *); 132static void sis_stop (struct sis_softc *); 133static void sis_watchdog (struct ifnet *); 134static void sis_shutdown (device_t); 135static int sis_ifmedia_upd (struct ifnet *); 136static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 137 138static u_int16_t sis_reverse (u_int16_t); 139static void sis_delay (struct sis_softc *); 140static void sis_eeprom_idle (struct sis_softc *); 141static void sis_eeprom_putbyte (struct sis_softc *, int); 142static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 143static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 144#ifdef __i386__ 145static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 146 int, int); 147static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 148static device_t sis_find_bridge (device_t); 149#endif 150 151static int sis_miibus_readreg (device_t, int, int); 152static int sis_miibus_writereg (device_t, int, int, int); 153static void sis_miibus_statchg (device_t); 154 155static void sis_setmulti_sis (struct sis_softc *); 156static void sis_setmulti_ns (struct sis_softc *); 157static u_int32_t sis_crc (struct sis_softc *, caddr_t); 158static void sis_reset (struct sis_softc *); 159static int sis_list_rx_init (struct sis_softc *); 160static int sis_list_tx_init (struct sis_softc *); 161 162static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 163static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 164static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 165#ifdef SIS_USEIOSPACE 166#define SIS_RES SYS_RES_IOPORT 167#define SIS_RID SIS_PCI_LOIO 168#else 169#define SIS_RES SYS_RES_MEMORY 170#define SIS_RID SIS_PCI_LOMEM 171#endif 172 173static device_method_t sis_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, sis_probe), 176 DEVMETHOD(device_attach, sis_attach), 177 DEVMETHOD(device_detach, sis_detach), 178 DEVMETHOD(device_shutdown, sis_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 186 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 187 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 188 189 { 0, 0 } 190}; 191 192static driver_t sis_driver = { 193 "sis", 194 sis_methods, 195 sizeof(struct sis_softc) 196}; 197 198static devclass_t sis_devclass; 199 200DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 201DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 202 203#define SIS_SETBIT(sc, reg, x) \ 204 CSR_WRITE_4(sc, reg, \ 205 CSR_READ_4(sc, reg) | (x)) 206 207#define SIS_CLRBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) & ~(x)) 210 211#define SIO_SET(x) \ 212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 213 214#define SIO_CLR(x) \ 215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 216 217static void 218sis_dma_map_desc_next(arg, segs, nseg, error) 219 void *arg; 220 bus_dma_segment_t *segs; 221 int nseg, error; 222{ 223 struct sis_desc *r; 224 225 r = arg; 226 r->sis_next = segs->ds_addr; 227 228 return; 229} 230 231static void 232sis_dma_map_desc_ptr(arg, segs, nseg, error) 233 void *arg; 234 bus_dma_segment_t *segs; 235 int nseg, error; 236{ 237 struct sis_desc *r; 238 239 r = arg; 240 r->sis_ptr = segs->ds_addr; 241 242 return; 243} 244 245static void 246sis_dma_map_ring(arg, segs, nseg, error) 247 void *arg; 248 bus_dma_segment_t *segs; 249 int nseg, error; 250{ 251 u_int32_t *p; 252 253 p = arg; 254 *p = segs->ds_addr; 255 256 return; 257} 258 259/* 260 * Routine to reverse the bits in a word. Stolen almost 261 * verbatim from /usr/games/fortune. 262 */ 263static u_int16_t sis_reverse(n) 264 u_int16_t n; 265{ 266 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 267 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 268 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 269 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 270 271 return(n); 272} 273 274static void sis_delay(sc) 275 struct sis_softc *sc; 276{ 277 int idx; 278 279 for (idx = (300 / 33) + 1; idx > 0; idx--) 280 CSR_READ_4(sc, SIS_CSR); 281 282 return; 283} 284 285static void sis_eeprom_idle(sc) 286 struct sis_softc *sc; 287{ 288 register int i; 289 290 SIO_SET(SIS_EECTL_CSEL); 291 sis_delay(sc); 292 SIO_SET(SIS_EECTL_CLK); 293 sis_delay(sc); 294 295 for (i = 0; i < 25; i++) { 296 SIO_CLR(SIS_EECTL_CLK); 297 sis_delay(sc); 298 SIO_SET(SIS_EECTL_CLK); 299 sis_delay(sc); 300 } 301 302 SIO_CLR(SIS_EECTL_CLK); 303 sis_delay(sc); 304 SIO_CLR(SIS_EECTL_CSEL); 305 sis_delay(sc); 306 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 307 308 return; 309} 310 311/* 312 * Send a read command and address to the EEPROM, check for ACK. 313 */ 314static void sis_eeprom_putbyte(sc, addr) 315 struct sis_softc *sc; 316 int addr; 317{ 318 register int d, i; 319 320 d = addr | SIS_EECMD_READ; 321 322 /* 323 * Feed in each bit and stobe the clock. 324 */ 325 for (i = 0x400; i; i >>= 1) { 326 if (d & i) { 327 SIO_SET(SIS_EECTL_DIN); 328 } else { 329 SIO_CLR(SIS_EECTL_DIN); 330 } 331 sis_delay(sc); 332 SIO_SET(SIS_EECTL_CLK); 333 sis_delay(sc); 334 SIO_CLR(SIS_EECTL_CLK); 335 sis_delay(sc); 336 } 337 338 return; 339} 340 341/* 342 * Read a word of data stored in the EEPROM at address 'addr.' 343 */ 344static void sis_eeprom_getword(sc, addr, dest) 345 struct sis_softc *sc; 346 int addr; 347 u_int16_t *dest; 348{ 349 register int i; 350 u_int16_t word = 0; 351 352 /* Force EEPROM to idle state. */ 353 sis_eeprom_idle(sc); 354 355 /* Enter EEPROM access mode. */ 356 sis_delay(sc); 357 SIO_CLR(SIS_EECTL_CLK); 358 sis_delay(sc); 359 SIO_SET(SIS_EECTL_CSEL); 360 sis_delay(sc); 361 362 /* 363 * Send address of word we want to read. 364 */ 365 sis_eeprom_putbyte(sc, addr); 366 367 /* 368 * Start reading bits from EEPROM. 369 */ 370 for (i = 0x8000; i; i >>= 1) { 371 SIO_SET(SIS_EECTL_CLK); 372 sis_delay(sc); 373 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 374 word |= i; 375 sis_delay(sc); 376 SIO_CLR(SIS_EECTL_CLK); 377 sis_delay(sc); 378 } 379 380 /* Turn off EEPROM access mode. */ 381 sis_eeprom_idle(sc); 382 383 *dest = word; 384 385 return; 386} 387 388/* 389 * Read a sequence of words from the EEPROM. 390 */ 391static void sis_read_eeprom(sc, dest, off, cnt, swap) 392 struct sis_softc *sc; 393 caddr_t dest; 394 int off; 395 int cnt; 396 int swap; 397{ 398 int i; 399 u_int16_t word = 0, *ptr; 400 401 for (i = 0; i < cnt; i++) { 402 sis_eeprom_getword(sc, off + i, &word); 403 ptr = (u_int16_t *)(dest + (i * 2)); 404 if (swap) 405 *ptr = ntohs(word); 406 else 407 *ptr = word; 408 } 409 410 return; 411} 412 413#ifdef __i386__ 414static device_t sis_find_bridge(dev) 415 device_t dev; 416{ 417 devclass_t pci_devclass; 418 device_t *pci_devices; 419 int pci_count = 0; 420 device_t *pci_children; 421 int pci_childcount = 0; 422 device_t *busp, *childp; 423 device_t child = NULL; 424 int i, j; 425 426 if ((pci_devclass = devclass_find("pci")) == NULL) 427 return(NULL); 428 429 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 430 431 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 432 pci_childcount = 0; 433 device_get_children(*busp, &pci_children, &pci_childcount); 434 for (j = 0, childp = pci_children; 435 j < pci_childcount; j++, childp++) { 436 if (pci_get_vendor(*childp) == SIS_VENDORID && 437 pci_get_device(*childp) == 0x0008) { 438 child = *childp; 439 goto done; 440 } 441 } 442 } 443 444done: 445 free(pci_devices, M_TEMP); 446 free(pci_children, M_TEMP); 447 return(child); 448} 449 450static void sis_read_cmos(sc, dev, dest, off, cnt) 451 struct sis_softc *sc; 452 device_t dev; 453 caddr_t dest; 454 int off; 455 int cnt; 456{ 457 device_t bridge; 458 u_int8_t reg; 459 int i; 460 bus_space_tag_t btag; 461 462 bridge = sis_find_bridge(dev); 463 if (bridge == NULL) 464 return; 465 reg = pci_read_config(bridge, 0x48, 1); 466 pci_write_config(bridge, 0x48, reg|0x40, 1); 467 468 /* XXX */ 469 btag = I386_BUS_SPACE_IO; 470 471 for (i = 0; i < cnt; i++) { 472 bus_space_write_1(btag, 0x0, 0x70, i + off); 473 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 474 } 475 476 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 477 return; 478} 479 480static void sis_read_mac(sc, dev, dest) 481 struct sis_softc *sc; 482 device_t dev; 483 caddr_t dest; 484{ 485 u_int32_t filtsave, csrsave; 486 487 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 488 csrsave = CSR_READ_4(sc, SIS_CSR); 489 490 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 491 CSR_WRITE_4(sc, SIS_CSR, 0); 492 493 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 494 495 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 496 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 497 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 498 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 499 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 500 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 501 502 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 503 CSR_WRITE_4(sc, SIS_CSR, csrsave); 504 return; 505} 506#endif 507 508static int sis_miibus_readreg(dev, phy, reg) 509 device_t dev; 510 int phy, reg; 511{ 512 struct sis_softc *sc; 513 int i, val = 0; 514 515 sc = device_get_softc(dev); 516 517 if (sc->sis_type == SIS_TYPE_83815) { 518 if (phy != 0) 519 return(0); 520 /* 521 * The NatSemi chip can take a while after 522 * a reset to come ready, during which the BMSR 523 * returns a value of 0. This is *never* supposed 524 * to happen: some of the BMSR bits are meant to 525 * be hardwired in the on position, and this can 526 * confuse the miibus code a bit during the probe 527 * and attach phase. So we make an effort to check 528 * for this condition and wait for it to clear. 529 */ 530 if (!CSR_READ_4(sc, NS_BMSR)) 531 DELAY(1000); 532 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 533 return(val); 534 } 535 536 if (sc->sis_type == SIS_TYPE_900 && 537 sc->sis_rev < SIS_REV_635 && phy != 0) 538 return(0); 539 540 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 541 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 542 543 for (i = 0; i < SIS_TIMEOUT; i++) { 544 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 545 break; 546 } 547 548 if (i == SIS_TIMEOUT) { 549 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 550 return(0); 551 } 552 553 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 554 555 if (val == 0xFFFF) 556 return(0); 557 558 return(val); 559} 560 561static int sis_miibus_writereg(dev, phy, reg, data) 562 device_t dev; 563 int phy, reg, data; 564{ 565 struct sis_softc *sc; 566 int i; 567 568 sc = device_get_softc(dev); 569 570 if (sc->sis_type == SIS_TYPE_83815) { 571 if (phy != 0) 572 return(0); 573 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 574 return(0); 575 } 576 577 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 578 return(0); 579 580 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 581 (reg << 6) | SIS_PHYOP_WRITE); 582 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 583 584 for (i = 0; i < SIS_TIMEOUT; i++) { 585 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 586 break; 587 } 588 589 if (i == SIS_TIMEOUT) 590 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 591 592 return(0); 593} 594 595static void sis_miibus_statchg(dev) 596 device_t dev; 597{ 598 struct sis_softc *sc; 599 600 sc = device_get_softc(dev); 601 sis_init(sc); 602 603 return; 604} 605 606static u_int32_t sis_crc(sc, addr) 607 struct sis_softc *sc; 608 caddr_t addr; 609{ 610 u_int32_t crc, carry; 611 int i, j; 612 u_int8_t c; 613 614 /* Compute CRC for the address value. */ 615 crc = 0xFFFFFFFF; /* initial value */ 616 617 for (i = 0; i < 6; i++) { 618 c = *(addr + i); 619 for (j = 0; j < 8; j++) { 620 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 621 crc <<= 1; 622 c >>= 1; 623 if (carry) 624 crc = (crc ^ 0x04c11db6) | carry; 625 } 626 } 627 628 /* 629 * return the filter bit position 630 * 631 * The NatSemi chip has a 512-bit filter, which is 632 * different than the SiS, so we special-case it. 633 */ 634 if (sc->sis_type == SIS_TYPE_83815) 635 return((crc >> 23) & 0x1FF); 636 637 return((crc >> 25) & 0x0000007F); 638} 639 640static void sis_setmulti_ns(sc) 641 struct sis_softc *sc; 642{ 643 struct ifnet *ifp; 644 struct ifmultiaddr *ifma; 645 u_int32_t h = 0, i, filtsave; 646 int bit, index; 647 648 ifp = &sc->arpcom.ac_if; 649 650 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 651 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 652 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 653 return; 654 } 655 656 /* 657 * We have to explicitly enable the multicast hash table 658 * on the NatSemi chip if we want to use it, which we do. 659 */ 660 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 661 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 662 663 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 664 665 /* first, zot all the existing hash bits */ 666 for (i = 0; i < 32; i++) { 667 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 668 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 669 } 670 671 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 672 if (ifma->ifma_addr->sa_family != AF_LINK) 673 continue; 674 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 675 index = h >> 3; 676 bit = h & 0x1F; 677 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 678 if (bit > 0xF) 679 bit -= 0x10; 680 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 681 } 682 683 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 684 685 return; 686} 687 688static void sis_setmulti_sis(sc) 689 struct sis_softc *sc; 690{ 691 struct ifnet *ifp; 692 struct ifmultiaddr *ifma; 693 u_int32_t h = 0, i, filtsave; 694 695 ifp = &sc->arpcom.ac_if; 696 697 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 698 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 699 return; 700 } 701 702 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 703 704 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 705 706 /* first, zot all the existing hash bits */ 707 for (i = 0; i < 8; i++) { 708 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 709 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 710 } 711 712 /* now program new ones */ 713 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 714 if (ifma->ifma_addr->sa_family != AF_LINK) 715 continue; 716 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 717 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 718 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 719 } 720 721 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 722 723 return; 724} 725 726static void sis_reset(sc) 727 struct sis_softc *sc; 728{ 729 register int i; 730 731 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 732 733 for (i = 0; i < SIS_TIMEOUT; i++) { 734 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 735 break; 736 } 737 738 if (i == SIS_TIMEOUT) 739 printf("sis%d: reset never completed\n", sc->sis_unit); 740 741 /* Wait a little while for the chip to get its brains in order. */ 742 DELAY(1000); 743 744 /* 745 * If this is a NetSemi chip, make sure to clear 746 * PME mode. 747 */ 748 if (sc->sis_type == SIS_TYPE_83815) { 749 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 750 CSR_WRITE_4(sc, NS_CLKRUN, 0); 751 } 752 753 return; 754} 755 756/* 757 * Probe for an SiS chip. Check the PCI vendor and device 758 * IDs against our list and return a device name if we find a match. 759 */ 760static int sis_probe(dev) 761 device_t dev; 762{ 763 struct sis_type *t; 764 765 t = sis_devs; 766 767 while(t->sis_name != NULL) { 768 if ((pci_get_vendor(dev) == t->sis_vid) && 769 (pci_get_device(dev) == t->sis_did)) { 770 device_set_desc(dev, t->sis_name); 771 return(0); 772 } 773 t++; 774 } 775 776 return(ENXIO); 777} 778 779/* 780 * Attach the interface. Allocate softc structures, do ifmedia 781 * setup and ethernet/BPF attach. 782 */ 783static int sis_attach(dev) 784 device_t dev; 785{ 786 u_char eaddr[ETHER_ADDR_LEN]; 787 u_int32_t command; 788 struct sis_softc *sc; 789 struct ifnet *ifp; 790 int unit, error = 0, rid; 791 792 sc = device_get_softc(dev); 793 unit = device_get_unit(dev); 794 bzero(sc, sizeof(struct sis_softc)); 795 796 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 797 MTX_DEF | MTX_RECURSE); 798 SIS_LOCK(sc); 799 800 if (pci_get_device(dev) == SIS_DEVICEID_900) 801 sc->sis_type = SIS_TYPE_900; 802 if (pci_get_device(dev) == SIS_DEVICEID_7016) 803 sc->sis_type = SIS_TYPE_7016; 804 if (pci_get_vendor(dev) == NS_VENDORID) 805 sc->sis_type = SIS_TYPE_83815; 806 807 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 808 809 /* 810 * Handle power management nonsense. 811 */ 812 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 813 u_int32_t iobase, membase, irq; 814 815 /* Save important PCI config data. */ 816 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 817 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 818 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 819 820 /* Reset the power state. */ 821 printf("sis%d: chip is in D%d power mode " 822 "-- setting to D0\n", unit, 823 pci_get_powerstate(dev)); 824 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 825 826 /* Restore PCI config data. */ 827 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 828 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 829 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 830 } 831 832 /* 833 * Map control/status registers. 834 */ 835 pci_enable_busmaster(dev); 836 pci_enable_io(dev, SYS_RES_IOPORT); 837 pci_enable_io(dev, SYS_RES_MEMORY); 838 command = pci_read_config(dev, PCIR_COMMAND, 4); 839 840#ifdef SIS_USEIOSPACE 841 if (!(command & PCIM_CMD_PORTEN)) { 842 printf("sis%d: failed to enable I/O ports!\n", unit); 843 error = ENXIO;; 844 goto fail; 845 } 846#else 847 if (!(command & PCIM_CMD_MEMEN)) { 848 printf("sis%d: failed to enable memory mapping!\n", unit); 849 error = ENXIO;; 850 goto fail; 851 } 852#endif 853 854 rid = SIS_RID; 855 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 856 0, ~0, 1, RF_ACTIVE); 857 858 if (sc->sis_res == NULL) { 859 printf("sis%d: couldn't map ports/memory\n", unit); 860 error = ENXIO; 861 goto fail; 862 } 863 864 sc->sis_btag = rman_get_bustag(sc->sis_res); 865 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 866 867 /* Allocate interrupt */ 868 rid = 0; 869 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 870 RF_SHAREABLE | RF_ACTIVE); 871 872 if (sc->sis_irq == NULL) { 873 printf("sis%d: couldn't map interrupt\n", unit); 874 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 875 error = ENXIO; 876 goto fail; 877 } 878 879 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 880 sis_intr, sc, &sc->sis_intrhand); 881 882 if (error) { 883 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 884 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 885 printf("sis%d: couldn't set up irq\n", unit); 886 goto fail; 887 } 888 889 /* Reset the adapter. */ 890 sis_reset(sc); 891 892 /* 893 * Get station address from the EEPROM. 894 */ 895 switch (pci_get_vendor(dev)) { 896 case NS_VENDORID: 897 /* 898 * Reading the MAC address out of the EEPROM on 899 * the NatSemi chip takes a bit more work than 900 * you'd expect. The address spans 4 16-bit words, 901 * with the first word containing only a single bit. 902 * You have to shift everything over one bit to 903 * get it aligned properly. Also, the bits are 904 * stored backwards (the LSB is really the MSB, 905 * and so on) so you have to reverse them in order 906 * to get the MAC address into the form we want. 907 * Why? Who the hell knows. 908 */ 909 { 910 u_int16_t tmp[4]; 911 912 sis_read_eeprom(sc, (caddr_t)&tmp, 913 NS_EE_NODEADDR, 4, 0); 914 915 /* Shift everything over one bit. */ 916 tmp[3] = tmp[3] >> 1; 917 tmp[3] |= tmp[2] << 15; 918 tmp[2] = tmp[2] >> 1; 919 tmp[2] |= tmp[1] << 15; 920 tmp[1] = tmp[1] >> 1; 921 tmp[1] |= tmp[0] << 15; 922 923 /* Now reverse all the bits. */ 924 tmp[3] = sis_reverse(tmp[3]); 925 tmp[2] = sis_reverse(tmp[2]); 926 tmp[1] = sis_reverse(tmp[1]); 927 928 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 929 } 930 break; 931 case SIS_VENDORID: 932 default: 933#ifdef __i386__ 934 /* 935 * If this is a SiS 630E chipset with an embedded 936 * SiS 900 controller, we have to read the MAC address 937 * from the APC CMOS RAM. Our method for doing this 938 * is very ugly since we have to reach out and grab 939 * ahold of hardware for which we cannot properly 940 * allocate resources. This code is only compiled on 941 * the i386 architecture since the SiS 630E chipset 942 * is for x86 motherboards only. Note that there are 943 * a lot of magic numbers in this hack. These are 944 * taken from SiS's Linux driver. I'd like to replace 945 * them with proper symbolic definitions, but that 946 * requires some datasheets that I don't have access 947 * to at the moment. 948 */ 949 if (sc->sis_rev == SIS_REV_630S || 950 sc->sis_rev == SIS_REV_630E || 951 sc->sis_rev == SIS_REV_630EA1) 952 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 953 954 else if (sc->sis_rev == SIS_REV_635 || 955 sc->sis_rev == SIS_REV_630ET) 956 sis_read_mac(sc, dev, (caddr_t)&eaddr); 957 else 958#endif 959 sis_read_eeprom(sc, (caddr_t)&eaddr, 960 SIS_EE_NODEADDR, 3, 0); 961 break; 962 } 963 964 /* 965 * A SiS chip was detected. Inform the world. 966 */ 967 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 968 969 sc->sis_unit = unit; 970 callout_handle_init(&sc->sis_stat_ch); 971 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 972 973 /* 974 * Allocate the parent bus DMA tag appropriate for PCI. 975 */ 976#define SIS_NSEG_NEW 32 977 error = bus_dma_tag_create(NULL, /* parent */ 978 1, 0, /* alignment, boundary */ 979 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 980 BUS_SPACE_MAXADDR, /* highaddr */ 981 NULL, NULL, /* filter, filterarg */ 982 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 983 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 984 BUS_DMA_ALLOCNOW, /* flags */ 985 &sc->sis_parent_tag); 986 987 /* 988 * Now allocate a tag for the DMA descriptor lists. 989 * All of our lists are allocated as a contiguous block 990 * of memory. 991 */ 992 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 993 1, 0, /* alignment, boundary */ 994 BUS_SPACE_MAXADDR, /* lowaddr */ 995 BUS_SPACE_MAXADDR, /* highaddr */ 996 NULL, NULL, /* filter, filterarg */ 997 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 998 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 999 0, /* flags */ 1000 &sc->sis_ldata.sis_rx_tag); 1001 1002 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1003 1, 0, /* alignment, boundary */ 1004 BUS_SPACE_MAXADDR, /* lowaddr */ 1005 BUS_SPACE_MAXADDR, /* highaddr */ 1006 NULL, NULL, /* filter, filterarg */ 1007 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1008 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1009 0, /* flags */ 1010 &sc->sis_ldata.sis_tx_tag); 1011 1012 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1013 1, 0, /* alignment, boundary */ 1014 BUS_SPACE_MAXADDR, /* lowaddr */ 1015 BUS_SPACE_MAXADDR, /* highaddr */ 1016 NULL, NULL, /* filter, filterarg */ 1017 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1018 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1019 0, /* flags */ 1020 &sc->sis_tag); 1021 1022 /* 1023 * Now allocate a chunk of DMA-able memory based on the 1024 * tag we just created. 1025 */ 1026 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1027 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1028 &sc->sis_ldata.sis_tx_dmamap); 1029 1030 if (error) { 1031 printf("sis%d: no memory for list buffers!\n", unit); 1032 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1033 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1034 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1035 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1036 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1037 error = ENXIO; 1038 goto fail; 1039 } 1040 1041 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1042 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1043 &sc->sis_ldata.sis_rx_dmamap); 1044 1045 if (error) { 1046 printf("sis%d: no memory for list buffers!\n", unit); 1047 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1049 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1050 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1051 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1052 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1053 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1054 error = ENXIO; 1055 goto fail; 1056 } 1057 1058 1059 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1060 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1061 1062 /* 1063 * Obtain the physical addresses of the RX and TX 1064 * rings which we'll need later in the init routine. 1065 */ 1066 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1067 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1068 sizeof(struct sis_desc), sis_dma_map_ring, 1069 &sc->sis_cdata.sis_tx_paddr, 0); 1070 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1071 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1072 sizeof(struct sis_desc), sis_dma_map_ring, 1073 &sc->sis_cdata.sis_rx_paddr, 0); 1074 1075 ifp = &sc->arpcom.ac_if; 1076 ifp->if_softc = sc; 1077 ifp->if_unit = unit; 1078 ifp->if_name = "sis"; 1079 ifp->if_mtu = ETHERMTU; 1080 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1081 ifp->if_ioctl = sis_ioctl; 1082 ifp->if_output = ether_output; 1083 ifp->if_start = sis_start; 1084 ifp->if_watchdog = sis_watchdog; 1085 ifp->if_init = sis_init; 1086 ifp->if_baudrate = 10000000; 1087 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1088 1089 /* 1090 * Do MII setup. 1091 */ 1092 if (mii_phy_probe(dev, &sc->sis_miibus, 1093 sis_ifmedia_upd, sis_ifmedia_sts)) { 1094 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1095 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1096 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1097 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1098 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1099 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1100 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1101 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1102 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1103 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1104 error = ENXIO; 1105 goto fail; 1106 } 1107 1108 /* 1109 * Call MI attach routine. 1110 */ 1111 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1112 1113 /* 1114 * Tell the upper layer(s) we support long frames. 1115 */ 1116 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1117 1118 callout_handle_init(&sc->sis_stat_ch); 1119 SIS_UNLOCK(sc); 1120 return(0); 1121 1122fail: 1123 SIS_UNLOCK(sc); 1124 mtx_destroy(&sc->sis_mtx); 1125 return(error); 1126} 1127 1128static int sis_detach(dev) 1129 device_t dev; 1130{ 1131 struct sis_softc *sc; 1132 struct ifnet *ifp; 1133 1134 1135 sc = device_get_softc(dev); 1136 SIS_LOCK(sc); 1137 ifp = &sc->arpcom.ac_if; 1138 1139 sis_reset(sc); 1140 sis_stop(sc); 1141 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1142 1143 bus_generic_detach(dev); 1144 device_delete_child(dev, sc->sis_miibus); 1145 1146 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1147 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1148 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1149 1150 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1151 sc->sis_ldata.sis_rx_dmamap); 1152 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1153 sc->sis_ldata.sis_tx_dmamap); 1154 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1155 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1156 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1157 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1158 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1159 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1160 bus_dma_tag_destroy(sc->sis_parent_tag); 1161 1162 SIS_UNLOCK(sc); 1163 mtx_destroy(&sc->sis_mtx); 1164 1165 return(0); 1166} 1167 1168/* 1169 * Initialize the transmit descriptors. 1170 */ 1171static int sis_list_tx_init(sc) 1172 struct sis_softc *sc; 1173{ 1174 struct sis_list_data *ld; 1175 struct sis_ring_data *cd; 1176 int i, nexti; 1177 1178 cd = &sc->sis_cdata; 1179 ld = &sc->sis_ldata; 1180 1181 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1182 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1183 ld->sis_tx_list[i].sis_nextdesc = 1184 &ld->sis_tx_list[nexti]; 1185 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1186 sc->sis_ldata.sis_tx_dmamap, 1187 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1188 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1189 ld->sis_tx_list[i].sis_mbuf = NULL; 1190 ld->sis_tx_list[i].sis_ptr = 0; 1191 ld->sis_tx_list[i].sis_ctl = 0; 1192 } 1193 1194 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1195 1196 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1197 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1198 1199 return(0); 1200} 1201 1202/* 1203 * Initialize the RX descriptors and allocate mbufs for them. Note that 1204 * we arrange the descriptors in a closed ring, so that the last descriptor 1205 * points back to the first. 1206 */ 1207static int sis_list_rx_init(sc) 1208 struct sis_softc *sc; 1209{ 1210 struct sis_list_data *ld; 1211 struct sis_ring_data *cd; 1212 int i,nexti; 1213 1214 ld = &sc->sis_ldata; 1215 cd = &sc->sis_cdata; 1216 1217 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1218 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1219 return(ENOBUFS); 1220 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1221 ld->sis_rx_list[i].sis_nextdesc = 1222 &ld->sis_rx_list[nexti]; 1223 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1224 sc->sis_ldata.sis_rx_dmamap, 1225 &ld->sis_rx_list[nexti], 1226 sizeof(struct sis_desc), sis_dma_map_desc_next, 1227 &ld->sis_rx_list[i], 0); 1228 } 1229 1230 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1231 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1232 1233 cd->sis_rx_prod = 0; 1234 1235 return(0); 1236} 1237 1238/* 1239 * Initialize an RX descriptor and attach an MBUF cluster. 1240 */ 1241static int sis_newbuf(sc, c, m) 1242 struct sis_softc *sc; 1243 struct sis_desc *c; 1244 struct mbuf *m; 1245{ 1246 1247 if (c == NULL) 1248 return(EINVAL); 1249 1250 if (m == NULL) { 1251 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1252 if (m == NULL) 1253 return(ENOBUFS); 1254 } else 1255 m->m_data = m->m_ext.ext_buf; 1256 m->m_len = m->m_pkthdr.len = MCLBYTES; 1257 1258 m_adj(m, sizeof(u_int64_t)); 1259 1260 c->sis_mbuf = m; 1261 c->sis_ctl = SIS_RXLEN; 1262 1263 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1264 bus_dmamap_load(sc->sis_tag, c->sis_map, 1265 mtod(m, void *), m->m_len, 1266 sis_dma_map_desc_ptr, c, 0); 1267 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1268 1269 return(0); 1270} 1271 1272/* 1273 * A frame has been uploaded: pass the resulting mbuf chain up to 1274 * the higher level protocols. 1275 */ 1276static void sis_rxeof(sc) 1277 struct sis_softc *sc; 1278{ 1279 struct ether_header *eh; 1280 struct mbuf *m; 1281 struct ifnet *ifp; 1282 struct sis_desc *cur_rx; 1283 int i, total_len = 0; 1284 u_int32_t rxstat; 1285 1286 ifp = &sc->arpcom.ac_if; 1287 i = sc->sis_cdata.sis_rx_prod; 1288 1289 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1290 1291#ifdef DEVICE_POLLING 1292 if (ifp->if_ipending & IFF_POLLING) { 1293 if (sc->rxcycles <= 0) 1294 break; 1295 sc->rxcycles--; 1296 } 1297#endif /* DEVICE_POLLING */ 1298 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1299 rxstat = cur_rx->sis_rxstat; 1300 bus_dmamap_sync(sc->sis_tag, 1301 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1302 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1303 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1304 m = cur_rx->sis_mbuf; 1305 cur_rx->sis_mbuf = NULL; 1306 total_len = SIS_RXBYTES(cur_rx); 1307 SIS_INC(i, SIS_RX_LIST_CNT); 1308 1309 /* 1310 * If an error occurs, update stats, clear the 1311 * status word and leave the mbuf cluster in place: 1312 * it should simply get re-used next time this descriptor 1313 * comes up in the ring. 1314 */ 1315 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1316 ifp->if_ierrors++; 1317 if (rxstat & SIS_RXSTAT_COLL) 1318 ifp->if_collisions++; 1319 sis_newbuf(sc, cur_rx, m); 1320 continue; 1321 } 1322 1323 /* No errors; receive the packet. */ 1324#ifdef __i386__ 1325 /* 1326 * On the x86 we do not have alignment problems, so try to 1327 * allocate a new buffer for the receive ring, and pass up 1328 * the one where the packet is already, saving the expensive 1329 * copy done in m_devget(). 1330 * If we are on an architecture with alignment problems, or 1331 * if the allocation fails, then use m_devget and leave the 1332 * existing buffer in the receive ring. 1333 */ 1334 if (sis_newbuf(sc, cur_rx, NULL) == 0) { 1335 m->m_pkthdr.rcvif = ifp; 1336 m->m_pkthdr.len = m->m_len = total_len; 1337 } else 1338#endif 1339 { 1340 struct mbuf *m0; 1341 m0 = m_devget(mtod(m, char *), total_len, 1342 ETHER_ALIGN, ifp, NULL); 1343 sis_newbuf(sc, cur_rx, m); 1344 if (m0 == NULL) { 1345 ifp->if_ierrors++; 1346 continue; 1347 } 1348 m = m0; 1349 } 1350 1351 ifp->if_ipackets++; 1352 eh = mtod(m, struct ether_header *); 1353 1354 /* Remove header from mbuf and pass it on. */ 1355 m_adj(m, sizeof(struct ether_header)); 1356 ether_input(ifp, eh, m); 1357 } 1358 1359 sc->sis_cdata.sis_rx_prod = i; 1360 1361 return; 1362} 1363 1364void sis_rxeoc(sc) 1365 struct sis_softc *sc; 1366{ 1367 sis_rxeof(sc); 1368 sis_init(sc); 1369 return; 1370} 1371 1372/* 1373 * A frame was downloaded to the chip. It's safe for us to clean up 1374 * the list buffers. 1375 */ 1376 1377static void sis_txeof(sc) 1378 struct sis_softc *sc; 1379{ 1380 struct ifnet *ifp; 1381 u_int32_t idx; 1382 1383 ifp = &sc->arpcom.ac_if; 1384 1385 /* 1386 * Go through our tx list and free mbufs for those 1387 * frames that have been transmitted. 1388 */ 1389 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1390 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1391 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1392 1393 if (SIS_OWNDESC(cur_tx)) 1394 break; 1395 1396 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1397 continue; 1398 1399 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1400 ifp->if_oerrors++; 1401 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1402 ifp->if_collisions++; 1403 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1404 ifp->if_collisions++; 1405 } 1406 1407 ifp->if_collisions += 1408 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1409 1410 ifp->if_opackets++; 1411 if (cur_tx->sis_mbuf != NULL) { 1412 m_freem(cur_tx->sis_mbuf); 1413 cur_tx->sis_mbuf = NULL; 1414 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1415 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1416 } 1417 } 1418 1419 if (idx != sc->sis_cdata.sis_tx_cons) { 1420 /* we freed up some buffers */ 1421 sc->sis_cdata.sis_tx_cons = idx; 1422 ifp->if_flags &= ~IFF_OACTIVE; 1423 } 1424 1425 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1426 1427 return; 1428} 1429 1430static void sis_tick(xsc) 1431 void *xsc; 1432{ 1433 struct sis_softc *sc; 1434 struct mii_data *mii; 1435 struct ifnet *ifp; 1436 1437 sc = xsc; 1438 SIS_LOCK(sc); 1439 ifp = &sc->arpcom.ac_if; 1440 1441 mii = device_get_softc(sc->sis_miibus); 1442 mii_tick(mii); 1443 1444 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1445 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1446 sc->sis_link++; 1447 if (ifp->if_snd.ifq_head != NULL) 1448 sis_start(ifp); 1449 } 1450 1451 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1452 1453 SIS_UNLOCK(sc); 1454 1455 return; 1456} 1457 1458#ifdef DEVICE_POLLING 1459static poll_handler_t sis_poll; 1460 1461static void 1462sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1463{ 1464 struct sis_softc *sc = ifp->if_softc; 1465 1466 SIS_LOCK(sc); 1467 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1468 CSR_WRITE_4(sc, SIS_IER, 1); 1469 goto done; 1470 } 1471 1472 /* 1473 * On the sis, reading the status register also clears it. 1474 * So before returning to intr mode we must make sure that all 1475 * possible pending sources of interrupts have been served. 1476 * In practice this means run to completion the *eof routines, 1477 * and then call the interrupt routine 1478 */ 1479 sc->rxcycles = count; 1480 sis_rxeof(sc); 1481 sis_txeof(sc); 1482 if (ifp->if_snd.ifq_head != NULL) 1483 sis_start(ifp); 1484 1485 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1486 u_int32_t status; 1487 1488 /* Reading the ISR register clears all interrupts. */ 1489 status = CSR_READ_4(sc, SIS_ISR); 1490 1491 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1492 sis_rxeoc(sc); 1493 1494 if (status & (SIS_ISR_RX_IDLE)) 1495 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1496 1497 if (status & SIS_ISR_SYSERR) { 1498 sis_reset(sc); 1499 sis_init(sc); 1500 } 1501 } 1502done: 1503 SIS_UNLOCK(sc); 1504 return; 1505} 1506#endif /* DEVICE_POLLING */ 1507 1508static void sis_intr(arg) 1509 void *arg; 1510{ 1511 struct sis_softc *sc; 1512 struct ifnet *ifp; 1513 u_int32_t status; 1514 1515 sc = arg; 1516 ifp = &sc->arpcom.ac_if; 1517 1518 SIS_LOCK(sc); 1519#ifdef DEVICE_POLLING 1520 if (ifp->if_ipending & IFF_POLLING) 1521 goto done; 1522 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1523 CSR_WRITE_4(sc, SIS_IER, 0); 1524 goto done; 1525 } 1526#endif /* DEVICE_POLLING */ 1527 1528 /* Supress unwanted interrupts */ 1529 if (!(ifp->if_flags & IFF_UP)) { 1530 sis_stop(sc); 1531 goto done; 1532 } 1533 1534 /* Disable interrupts. */ 1535 CSR_WRITE_4(sc, SIS_IER, 0); 1536 1537 for (;;) { 1538 /* Reading the ISR register clears all interrupts. */ 1539 status = CSR_READ_4(sc, SIS_ISR); 1540 1541 if ((status & SIS_INTRS) == 0) 1542 break; 1543 1544 if (status & 1545 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1546 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1547 sis_txeof(sc); 1548 1549 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1550 sis_rxeof(sc); 1551 1552 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1553 sis_rxeoc(sc); 1554 1555 if (status & (SIS_ISR_RX_IDLE)) 1556 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1557 1558 if (status & SIS_ISR_SYSERR) { 1559 sis_reset(sc); 1560 sis_init(sc); 1561 } 1562 } 1563 1564 /* Re-enable interrupts. */ 1565 CSR_WRITE_4(sc, SIS_IER, 1); 1566 1567 if (ifp->if_snd.ifq_head != NULL) 1568 sis_start(ifp); 1569done: 1570 SIS_UNLOCK(sc); 1571 1572 return; 1573} 1574 1575/* 1576 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1577 * pointers to the fragment pointers. 1578 */ 1579static int sis_encap(sc, m_head, txidx) 1580 struct sis_softc *sc; 1581 struct mbuf *m_head; 1582 u_int32_t *txidx; 1583{ 1584 struct sis_desc *f = NULL; 1585 struct mbuf *m; 1586 int frag, cur, cnt = 0; 1587 1588 /* 1589 * Start packing the mbufs in this chain into 1590 * the fragment pointers. Stop when we run out 1591 * of fragments or hit the end of the mbuf chain. 1592 */ 1593 m = m_head; 1594 cur = frag = *txidx; 1595 1596 for (m = m_head; m != NULL; m = m->m_next) { 1597 if (m->m_len != 0) { 1598 if ((SIS_TX_LIST_CNT - 1599 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1600 return(ENOBUFS); 1601 f = &sc->sis_ldata.sis_tx_list[frag]; 1602 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1603 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1604 bus_dmamap_load(sc->sis_tag, f->sis_map, 1605 mtod(m, void *), m->m_len, 1606 sis_dma_map_desc_ptr, f, 0); 1607 bus_dmamap_sync(sc->sis_tag, 1608 f->sis_map, BUS_DMASYNC_PREREAD); 1609 if (cnt != 0) 1610 f->sis_ctl |= SIS_CMDSTS_OWN; 1611 cur = frag; 1612 SIS_INC(frag, SIS_TX_LIST_CNT); 1613 cnt++; 1614 } 1615 } 1616 1617 if (m != NULL) 1618 return(ENOBUFS); 1619 1620 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1621 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1622 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1623 sc->sis_cdata.sis_tx_cnt += cnt; 1624 *txidx = frag; 1625 1626 return(0); 1627} 1628 1629/* 1630 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1631 * to the mbuf data regions directly in the transmit lists. We also save a 1632 * copy of the pointers since the transmit list fragment pointers are 1633 * physical addresses. 1634 */ 1635 1636static void sis_start(ifp) 1637 struct ifnet *ifp; 1638{ 1639 struct sis_softc *sc; 1640 struct mbuf *m_head = NULL; 1641 u_int32_t idx; 1642 1643 sc = ifp->if_softc; 1644 SIS_LOCK(sc); 1645 1646 if (!sc->sis_link) { 1647 SIS_UNLOCK(sc); 1648 return; 1649 } 1650 1651 idx = sc->sis_cdata.sis_tx_prod; 1652 1653 if (ifp->if_flags & IFF_OACTIVE) { 1654 SIS_UNLOCK(sc); 1655 return; 1656 } 1657 1658 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1659 IF_DEQUEUE(&ifp->if_snd, m_head); 1660 if (m_head == NULL) 1661 break; 1662 1663 if (sis_encap(sc, m_head, &idx)) { 1664 IF_PREPEND(&ifp->if_snd, m_head); 1665 ifp->if_flags |= IFF_OACTIVE; 1666 break; 1667 } 1668 1669 /* 1670 * If there's a BPF listener, bounce a copy of this frame 1671 * to him. 1672 */ 1673 if (ifp->if_bpf) 1674 bpf_mtap(ifp, m_head); 1675 1676 } 1677 1678 /* Transmit */ 1679 sc->sis_cdata.sis_tx_prod = idx; 1680 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1681 1682 /* 1683 * Set a timeout in case the chip goes out to lunch. 1684 */ 1685 ifp->if_timer = 5; 1686 1687 SIS_UNLOCK(sc); 1688 1689 return; 1690} 1691 1692static void sis_init(xsc) 1693 void *xsc; 1694{ 1695 struct sis_softc *sc = xsc; 1696 struct ifnet *ifp = &sc->arpcom.ac_if; 1697 struct mii_data *mii; 1698 1699 SIS_LOCK(sc); 1700 1701 /* 1702 * Cancel pending I/O and free all RX/TX buffers. 1703 */ 1704 sis_stop(sc); 1705 1706 mii = device_get_softc(sc->sis_miibus); 1707 1708 /* Set MAC address */ 1709 if (sc->sis_type == SIS_TYPE_83815) { 1710 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1711 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1712 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1713 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1714 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1715 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1716 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1717 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1718 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1719 } else { 1720 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1721 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1722 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1723 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1724 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1725 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1726 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1727 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1728 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1729 } 1730 1731 /* Init circular RX list. */ 1732 if (sis_list_rx_init(sc) == ENOBUFS) { 1733 printf("sis%d: initialization failed: no " 1734 "memory for rx buffers\n", sc->sis_unit); 1735 sis_stop(sc); 1736 SIS_UNLOCK(sc); 1737 return; 1738 } 1739 1740 /* 1741 * Init tx descriptors. 1742 */ 1743 sis_list_tx_init(sc); 1744 1745 /* 1746 * For the NatSemi chip, we have to explicitly enable the 1747 * reception of ARP frames, as well as turn on the 'perfect 1748 * match' filter where we store the station address, otherwise 1749 * we won't receive unicasts meant for this host. 1750 */ 1751 if (sc->sis_type == SIS_TYPE_83815) { 1752 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1753 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1754 } 1755 1756 /* If we want promiscuous mode, set the allframes bit. */ 1757 if (ifp->if_flags & IFF_PROMISC) { 1758 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1759 } else { 1760 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1761 } 1762 1763 /* 1764 * Set the capture broadcast bit to capture broadcast frames. 1765 */ 1766 if (ifp->if_flags & IFF_BROADCAST) { 1767 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1768 } else { 1769 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1770 } 1771 1772 /* 1773 * Load the multicast filter. 1774 */ 1775 if (sc->sis_type == SIS_TYPE_83815) 1776 sis_setmulti_ns(sc); 1777 else 1778 sis_setmulti_sis(sc); 1779 1780 /* Turn the receive filter on */ 1781 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1782 1783 /* 1784 * Load the address of the RX and TX lists. 1785 */ 1786 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1787 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1788 1789 /* Set RX configuration */ 1790 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1791 1792 /* Accept Long Packets for VLAN support */ 1793 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1794 1795 /* Set TX configuration */ 1796 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1797 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1798 } else { 1799 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1800 } 1801 1802 /* Set full/half duplex mode. */ 1803 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1804 SIS_SETBIT(sc, SIS_TX_CFG, 1805 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1806 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1807 } else { 1808 SIS_CLRBIT(sc, SIS_TX_CFG, 1809 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1810 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1811 } 1812 1813 /* 1814 * Enable interrupts. 1815 */ 1816 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1817#ifdef DEVICE_POLLING 1818 /* 1819 * ... only enable interrupts if we are not polling, make sure 1820 * they are off otherwise. 1821 */ 1822 if (ifp->if_ipending & IFF_POLLING) 1823 CSR_WRITE_4(sc, SIS_IER, 0); 1824 else 1825#endif /* DEVICE_POLLING */ 1826 CSR_WRITE_4(sc, SIS_IER, 1); 1827 1828 /* Enable receiver and transmitter. */ 1829 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1830 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1831 1832#ifdef notdef 1833 mii_mediachg(mii); 1834#endif 1835 1836 /* 1837 * Page 75 of the DP83815 manual recommends the 1838 * following register settings "for optimum 1839 * performance." Note however that at least three 1840 * of the registers are listed as "reserved" in 1841 * the register map, so who knows what they do. 1842 */ 1843 if (sc->sis_type == SIS_TYPE_83815) { 1844 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1845 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1846 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1847 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1848 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1849 } 1850 1851 ifp->if_flags |= IFF_RUNNING; 1852 ifp->if_flags &= ~IFF_OACTIVE; 1853 1854 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1855 1856 SIS_UNLOCK(sc); 1857 1858 return; 1859} 1860 1861/* 1862 * Set media options. 1863 */ 1864static int sis_ifmedia_upd(ifp) 1865 struct ifnet *ifp; 1866{ 1867 struct sis_softc *sc; 1868 struct mii_data *mii; 1869 1870 sc = ifp->if_softc; 1871 1872 mii = device_get_softc(sc->sis_miibus); 1873 sc->sis_link = 0; 1874 if (mii->mii_instance) { 1875 struct mii_softc *miisc; 1876 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1877 mii_phy_reset(miisc); 1878 } 1879 mii_mediachg(mii); 1880 1881 return(0); 1882} 1883 1884/* 1885 * Report current media status. 1886 */ 1887static void sis_ifmedia_sts(ifp, ifmr) 1888 struct ifnet *ifp; 1889 struct ifmediareq *ifmr; 1890{ 1891 struct sis_softc *sc; 1892 struct mii_data *mii; 1893 1894 sc = ifp->if_softc; 1895 1896 mii = device_get_softc(sc->sis_miibus); 1897 mii_pollstat(mii); 1898 ifmr->ifm_active = mii->mii_media_active; 1899 ifmr->ifm_status = mii->mii_media_status; 1900 1901 return; 1902} 1903 1904static int sis_ioctl(ifp, command, data) 1905 struct ifnet *ifp; 1906 u_long command; 1907 caddr_t data; 1908{ 1909 struct sis_softc *sc = ifp->if_softc; 1910 struct ifreq *ifr = (struct ifreq *) data; 1911 struct mii_data *mii; 1912 int error = 0; 1913 1914 switch(command) { 1915 case SIOCSIFADDR: 1916 case SIOCGIFADDR: 1917 case SIOCSIFMTU: 1918 error = ether_ioctl(ifp, command, data); 1919 break; 1920 case SIOCSIFFLAGS: 1921 if (ifp->if_flags & IFF_UP) { 1922 sis_init(sc); 1923 } else { 1924 if (ifp->if_flags & IFF_RUNNING) 1925 sis_stop(sc); 1926 } 1927 error = 0; 1928 break; 1929 case SIOCADDMULTI: 1930 case SIOCDELMULTI: 1931 SIS_LOCK(sc); 1932 if (sc->sis_type == SIS_TYPE_83815) 1933 sis_setmulti_ns(sc); 1934 else 1935 sis_setmulti_sis(sc); 1936 SIS_UNLOCK(sc); 1937 error = 0; 1938 break; 1939 case SIOCGIFMEDIA: 1940 case SIOCSIFMEDIA: 1941 mii = device_get_softc(sc->sis_miibus); 1942 SIS_LOCK(sc); 1943 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1944 SIS_UNLOCK(sc); 1945 break; 1946 default: 1947 error = EINVAL; 1948 break; 1949 } 1950 1951 return(error); 1952} 1953 1954static void sis_watchdog(ifp) 1955 struct ifnet *ifp; 1956{ 1957 struct sis_softc *sc; 1958 1959 sc = ifp->if_softc; 1960 1961 SIS_LOCK(sc); 1962 1963 ifp->if_oerrors++; 1964 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1965 1966 sis_stop(sc); 1967 sis_reset(sc); 1968 sis_init(sc); 1969 1970 if (ifp->if_snd.ifq_head != NULL) 1971 sis_start(ifp); 1972 1973 SIS_UNLOCK(sc); 1974 1975 return; 1976} 1977 1978/* 1979 * Stop the adapter and free any mbufs allocated to the 1980 * RX and TX lists. 1981 */ 1982static void sis_stop(sc) 1983 struct sis_softc *sc; 1984{ 1985 register int i; 1986 struct ifnet *ifp; 1987 1988 SIS_LOCK(sc); 1989 ifp = &sc->arpcom.ac_if; 1990 ifp->if_timer = 0; 1991 1992 untimeout(sis_tick, sc, sc->sis_stat_ch); 1993 1994 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1995#ifdef DEVICE_POLLING 1996 ether_poll_deregister(ifp); 1997#endif 1998 CSR_WRITE_4(sc, SIS_IER, 0); 1999 CSR_WRITE_4(sc, SIS_IMR, 0); 2000 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2001 DELAY(1000); 2002 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2003 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2004 2005 sc->sis_link = 0; 2006 2007 /* 2008 * Free data in the RX lists. 2009 */ 2010 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2011 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2012 bus_dmamap_unload(sc->sis_tag, 2013 sc->sis_ldata.sis_rx_list[i].sis_map); 2014 bus_dmamap_destroy(sc->sis_tag, 2015 sc->sis_ldata.sis_rx_list[i].sis_map); 2016 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2017 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2018 } 2019 } 2020 bzero(sc->sis_ldata.sis_rx_list, 2021 sizeof(sc->sis_ldata.sis_rx_list)); 2022 2023 /* 2024 * Free the TX list buffers. 2025 */ 2026 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2027 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2028 bus_dmamap_unload(sc->sis_tag, 2029 sc->sis_ldata.sis_tx_list[i].sis_map); 2030 bus_dmamap_destroy(sc->sis_tag, 2031 sc->sis_ldata.sis_tx_list[i].sis_map); 2032 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2033 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2034 } 2035 } 2036 2037 bzero(sc->sis_ldata.sis_tx_list, 2038 sizeof(sc->sis_ldata.sis_tx_list)); 2039 2040 SIS_UNLOCK(sc); 2041 2042 return; 2043} 2044 2045/* 2046 * Stop all chip I/O so that the kernel's probe routines don't 2047 * get confused by errant DMAs when rebooting. 2048 */ 2049static void sis_shutdown(dev) 2050 device_t dev; 2051{ 2052 struct sis_softc *sc; 2053 2054 sc = device_get_softc(dev); 2055 SIS_LOCK(sc); 2056 sis_reset(sc); 2057 sis_stop(sc); 2058 SIS_UNLOCK(sc); 2059 2060 return; 2061} 2062