1250661Sdavidcs/* 2250661Sdavidcs * Copyright (c) 2013-2014 Qlogic Corporation 3250661Sdavidcs * All rights reserved. 4250661Sdavidcs * 5250661Sdavidcs * Redistribution and use in source and binary forms, with or without 6250661Sdavidcs * modification, are permitted provided that the following conditions 7250661Sdavidcs * are met: 8250661Sdavidcs * 9250661Sdavidcs * 1. Redistributions of source code must retain the above copyright 10250661Sdavidcs * notice, this list of conditions and the following disclaimer. 11250661Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12250661Sdavidcs * notice, this list of conditions and the following disclaimer in the 13250661Sdavidcs * documentation and/or other materials provided with the distribution. 14250661Sdavidcs * 15250661Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16250661Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17250661Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18250661Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19250661Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20250661Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21250661Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22250661Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23250661Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24250661Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25250661Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26250661Sdavidcs * 27250661Sdavidcs * $FreeBSD$ 28250661Sdavidcs */ 29250661Sdavidcs 30250661Sdavidcs/* 31250661Sdavidcs * File: ql_def.h 32250661Sdavidcs * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 33250661Sdavidcs */ 34250661Sdavidcs 35250661Sdavidcs#ifndef _QL_DEF_H_ 36250661Sdavidcs#define _QL_DEF_H_ 37250661Sdavidcs 38250661Sdavidcs#define BIT_0 (0x1 << 0) 39250661Sdavidcs#define BIT_1 (0x1 << 1) 40250661Sdavidcs#define BIT_2 (0x1 << 2) 41250661Sdavidcs#define BIT_3 (0x1 << 3) 42250661Sdavidcs#define BIT_4 (0x1 << 4) 43250661Sdavidcs#define BIT_5 (0x1 << 5) 44250661Sdavidcs#define BIT_6 (0x1 << 6) 45250661Sdavidcs#define BIT_7 (0x1 << 7) 46250661Sdavidcs#define BIT_8 (0x1 << 8) 47250661Sdavidcs#define BIT_9 (0x1 << 9) 48250661Sdavidcs#define BIT_10 (0x1 << 10) 49250661Sdavidcs#define BIT_11 (0x1 << 11) 50250661Sdavidcs#define BIT_12 (0x1 << 12) 51250661Sdavidcs#define BIT_13 (0x1 << 13) 52250661Sdavidcs#define BIT_14 (0x1 << 14) 53250661Sdavidcs#define BIT_15 (0x1 << 15) 54250661Sdavidcs#define BIT_16 (0x1 << 16) 55250661Sdavidcs#define BIT_17 (0x1 << 17) 56250661Sdavidcs#define BIT_18 (0x1 << 18) 57250661Sdavidcs#define BIT_19 (0x1 << 19) 58250661Sdavidcs#define BIT_20 (0x1 << 20) 59250661Sdavidcs#define BIT_21 (0x1 << 21) 60250661Sdavidcs#define BIT_22 (0x1 << 22) 61250661Sdavidcs#define BIT_23 (0x1 << 23) 62250661Sdavidcs#define BIT_24 (0x1 << 24) 63250661Sdavidcs#define BIT_25 (0x1 << 25) 64250661Sdavidcs#define BIT_26 (0x1 << 26) 65250661Sdavidcs#define BIT_27 (0x1 << 27) 66250661Sdavidcs#define BIT_28 (0x1 << 28) 67250661Sdavidcs#define BIT_29 (0x1 << 29) 68250661Sdavidcs#define BIT_30 (0x1 << 30) 69250661Sdavidcs#define BIT_31 (0x1 << 31) 70250661Sdavidcs 71250661Sdavidcsstruct qla_rx_buf { 72250661Sdavidcs struct mbuf *m_head; 73250661Sdavidcs bus_dmamap_t map; 74250661Sdavidcs bus_addr_t paddr; 75250661Sdavidcs uint32_t handle; 76250661Sdavidcs void *next; 77250661Sdavidcs}; 78250661Sdavidcstypedef struct qla_rx_buf qla_rx_buf_t; 79250661Sdavidcs 80250661Sdavidcsstruct qla_rx_ring { 81250661Sdavidcs qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS]; 82250661Sdavidcs}; 83250661Sdavidcstypedef struct qla_rx_ring qla_rx_ring_t; 84250661Sdavidcs 85250661Sdavidcsstruct qla_tx_buf { 86250661Sdavidcs struct mbuf *m_head; 87250661Sdavidcs bus_dmamap_t map; 88250661Sdavidcs}; 89250661Sdavidcstypedef struct qla_tx_buf qla_tx_buf_t; 90250661Sdavidcs 91250661Sdavidcs#define QLA_MAX_SEGMENTS 62 /* maximum # of segs in a sg list */ 92250661Sdavidcs#define QLA_MAX_MTU 9000 93250661Sdavidcs#define QLA_STD_FRAME_SIZE 1514 94250661Sdavidcs#define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22) 95250661Sdavidcs 96250661Sdavidcs/* Number of MSIX/MSI Vectors required */ 97250661Sdavidcs 98250661Sdavidcsstruct qla_ivec { 99250661Sdavidcs uint32_t sds_idx; 100250661Sdavidcs void *ha; 101250661Sdavidcs struct resource *irq; 102250661Sdavidcs void *handle; 103250661Sdavidcs int irq_rid; 104250661Sdavidcs}; 105250661Sdavidcs 106250661Sdavidcstypedef struct qla_ivec qla_ivec_t; 107250661Sdavidcs 108250661Sdavidcs#define QLA_WATCHDOG_CALLOUT_TICKS 1 109250661Sdavidcs 110250661Sdavidcstypedef struct _qla_tx_ring { 111250661Sdavidcs qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS]; 112250661Sdavidcs uint64_t count; 113250661Sdavidcs} qla_tx_ring_t; 114250661Sdavidcs 115250661Sdavidcs/* 116250661Sdavidcs * Adapter structure contains the hardware independant information of the 117250661Sdavidcs * pci function. 118250661Sdavidcs */ 119250661Sdavidcsstruct qla_host { 120250661Sdavidcs volatile struct { 121250661Sdavidcs volatile uint32_t 122250661Sdavidcs qla_callout_init :1, 123250661Sdavidcs qla_watchdog_active :1, 124250661Sdavidcs qla_watchdog_exit :1, 125250661Sdavidcs qla_watchdog_pause :1, 126250661Sdavidcs lro_init :1, 127250661Sdavidcs stop_rcv :1, 128250661Sdavidcs parent_tag :1, 129250661Sdavidcs lock_init :1; 130250661Sdavidcs } flags; 131250661Sdavidcs 132250661Sdavidcs volatile uint32_t qla_watchdog_exited; 133250661Sdavidcs volatile uint32_t qla_watchdog_paused; 134250661Sdavidcs volatile uint32_t qla_initiate_recovery; 135250661Sdavidcs 136250661Sdavidcs device_t pci_dev; 137250661Sdavidcs 138250661Sdavidcs uint16_t watchdog_ticks; 139250661Sdavidcs uint8_t pci_func; 140250661Sdavidcs uint8_t resvd; 141250661Sdavidcs 142250661Sdavidcs /* ioctl related */ 143250661Sdavidcs struct cdev *ioctl_dev; 144250661Sdavidcs 145250661Sdavidcs /* register mapping */ 146250661Sdavidcs struct resource *pci_reg; 147250661Sdavidcs int reg_rid; 148250661Sdavidcs struct resource *pci_reg1; 149250661Sdavidcs int reg_rid1; 150250661Sdavidcs 151250661Sdavidcs /* interrupts */ 152250661Sdavidcs struct resource *mbx_irq; 153250661Sdavidcs void *mbx_handle; 154250661Sdavidcs int mbx_irq_rid; 155250661Sdavidcs 156250661Sdavidcs int msix_count; 157250661Sdavidcs 158250661Sdavidcs qla_ivec_t irq_vec[MAX_SDS_RINGS]; 159250661Sdavidcs 160250661Sdavidcs /* parent dma tag */ 161250661Sdavidcs bus_dma_tag_t parent_tag; 162250661Sdavidcs 163250661Sdavidcs /* interface to o.s */ 164250661Sdavidcs struct ifnet *ifp; 165250661Sdavidcs 166250661Sdavidcs struct ifmedia media; 167250661Sdavidcs uint16_t max_frame_size; 168250661Sdavidcs uint16_t rsrvd0; 169250661Sdavidcs int if_flags; 170250661Sdavidcs 171250661Sdavidcs /* hardware access lock */ 172250661Sdavidcs 173250661Sdavidcs struct mtx hw_lock; 174250661Sdavidcs volatile uint32_t hw_lock_held; 175250661Sdavidcs 176250661Sdavidcs /* transmit and receive buffers */ 177250661Sdavidcs uint32_t txr_idx; /* index of the current tx ring */ 178250661Sdavidcs qla_tx_ring_t tx_ring[NUM_TX_RINGS]; 179250661Sdavidcs 180250661Sdavidcs bus_dma_tag_t tx_tag; 181250661Sdavidcs struct task tx_task; 182250661Sdavidcs struct taskqueue *tx_tq; 183250661Sdavidcs struct callout tx_callout; 184250661Sdavidcs struct mtx tx_lock; 185250661Sdavidcs 186250661Sdavidcs qla_rx_ring_t rx_ring[MAX_RDS_RINGS]; 187250661Sdavidcs bus_dma_tag_t rx_tag; 188250661Sdavidcs uint32_t std_replenish; 189250661Sdavidcs 190250661Sdavidcs qla_rx_buf_t *rxb_free; 191250661Sdavidcs uint32_t rxb_free_count; 192250661Sdavidcs volatile uint32_t posting; 193250661Sdavidcs 194250661Sdavidcs /* stats */ 195250661Sdavidcs uint32_t err_m_getcl; 196250661Sdavidcs uint32_t err_m_getjcl; 197250661Sdavidcs uint32_t err_tx_dmamap_create; 198250661Sdavidcs uint32_t err_tx_dmamap_load; 199250661Sdavidcs uint32_t err_tx_defrag; 200250661Sdavidcs 201250661Sdavidcs uint64_t rx_frames; 202250661Sdavidcs uint64_t rx_bytes; 203250661Sdavidcs 204250661Sdavidcs uint64_t lro_pkt_count; 205250661Sdavidcs uint64_t lro_bytes; 206250661Sdavidcs 207250661Sdavidcs uint64_t ipv4_lro; 208250661Sdavidcs uint64_t ipv6_lro; 209250661Sdavidcs 210250661Sdavidcs uint64_t tx_frames; 211250661Sdavidcs uint64_t tx_bytes; 212250661Sdavidcs uint64_t tx_tso_frames; 213250661Sdavidcs uint64_t hw_vlan_tx_frames; 214250661Sdavidcs 215250661Sdavidcs uint32_t fw_ver_major; 216250661Sdavidcs uint32_t fw_ver_minor; 217250661Sdavidcs uint32_t fw_ver_sub; 218250661Sdavidcs uint32_t fw_ver_build; 219250661Sdavidcs 220250661Sdavidcs /* hardware specific */ 221250661Sdavidcs qla_hw_t hw; 222250661Sdavidcs 223250661Sdavidcs /* debug stuff */ 224250661Sdavidcs volatile const char *qla_lock; 225250661Sdavidcs volatile const char *qla_unlock; 226250661Sdavidcs uint32_t dbg_level; 227250661Sdavidcs 228250661Sdavidcs uint8_t fw_ver_str[32]; 229250661Sdavidcs 230250661Sdavidcs /* Error Injection Related */ 231250661Sdavidcs uint32_t err_inject; 232250661Sdavidcs struct task err_task; 233250661Sdavidcs struct taskqueue *err_tq; 234250661Sdavidcs 235250661Sdavidcs /* Peer Device */ 236250661Sdavidcs device_t peer_dev; 237250661Sdavidcs 238250661Sdavidcs volatile uint32_t msg_from_peer; 239250661Sdavidcs#define QL_PEER_MSG_RESET 0x01 240250661Sdavidcs#define QL_PEER_MSG_ACK 0x02 241250661Sdavidcs 242250661Sdavidcs}; 243250661Sdavidcstypedef struct qla_host qla_host_t; 244250661Sdavidcs 245250661Sdavidcs/* note that align has to be a power of 2 */ 246250661Sdavidcs#define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1); 247250661Sdavidcs#define QL_MIN(x, y) ((x < y) ? x : y) 248250661Sdavidcs 249250661Sdavidcs#define QL_RUNNING(ifp) \ 250250661Sdavidcs ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \ 251250661Sdavidcs IFF_DRV_RUNNING) 252250661Sdavidcs 253250661Sdavidcs/* Return 0, if identical, else 1 */ 254250661Sdavidcs#define QL_MAC_CMP(mac1, mac2) \ 255250661Sdavidcs ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \ 256250661Sdavidcs (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1) 257250661Sdavidcs 258250661Sdavidcs#endif /* #ifndef _QL_DEF_H_ */ 259