1139749Simp/*- 2158124Smarcel * Copyright (c) 2006 Marcel Moolenaar 3158124Smarcel * All rights reserved. 490731Sjhay * 590731Sjhay * Redistribution and use in source and binary forms, with or without 690731Sjhay * modification, are permitted provided that the following conditions 790731Sjhay * are met: 8158124Smarcel * 990731Sjhay * 1. Redistributions of source code must retain the above copyright 1090731Sjhay * notice, this list of conditions and the following disclaimer. 1190731Sjhay * 2. Redistributions in binary form must reproduce the above copyright 1290731Sjhay * notice, this list of conditions and the following disclaimer in the 1390731Sjhay * documentation and/or other materials provided with the distribution. 1490731Sjhay * 1590731Sjhay * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1690731Sjhay * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1790731Sjhay * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1890731Sjhay * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1990731Sjhay * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2090731Sjhay * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2190731Sjhay * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2290731Sjhay * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2390731Sjhay * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2490731Sjhay * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2590731Sjhay */ 2690731Sjhay 2790731Sjhay#include <sys/cdefs.h> 2890731Sjhay__FBSDID("$FreeBSD$"); 2990731Sjhay 3090731Sjhay/* 3190731Sjhay * PCI "universal" communications card driver configuration data (used to 3290731Sjhay * match/attach the cards). 3390731Sjhay */ 3490731Sjhay 3590731Sjhay#include <sys/param.h> 36158124Smarcel#include <sys/systm.h> 37158124Smarcel#include <sys/kernel.h> 38158124Smarcel#include <sys/bus.h> 3990731Sjhay 40158124Smarcel#include <machine/resource.h> 41159545Simp#include <machine/bus.h> 42158124Smarcel#include <sys/rman.h> 43158124Smarcel 4490731Sjhay#include <dev/pci/pcivar.h> 4590731Sjhay 46158124Smarcel#include <dev/puc/puc_bus.h> 47158124Smarcel#include <dev/puc/puc_cfg.h> 48160030Sobrien#include <dev/puc/puc_bfe.h> 4990731Sjhay 50158124Smarcelstatic puc_config_f puc_config_amc; 51158124Smarcelstatic puc_config_f puc_config_diva; 52222660Sjhbstatic puc_config_f puc_config_exar; 53248340Srstonestatic puc_config_f puc_config_exar_pcie; 54158124Smarcelstatic puc_config_f puc_config_icbook; 55227457Seadlerstatic puc_config_f puc_config_moxa; 56251715Smariusstatic puc_config_f puc_config_oxford_pci954; 57222760Sjhbstatic puc_config_f puc_config_oxford_pcie; 58158124Smarcelstatic puc_config_f puc_config_quatech; 59158124Smarcelstatic puc_config_f puc_config_syba; 60158124Smarcelstatic puc_config_f puc_config_siig; 61264761Smariusstatic puc_config_f puc_config_sunix; 62158124Smarcelstatic puc_config_f puc_config_timedia; 63158124Smarcelstatic puc_config_f puc_config_titan; 64119814Smarcel 65158124Smarcelconst struct puc_cfg puc_pci_devices[] = { 6698376Sobrien 67158124Smarcel { 0x0009, 0x7168, 0xffff, 0, 68158124Smarcel "Sunix SUN1889", 69158124Smarcel DEFAULT_RCLK * 8, 70158124Smarcel PUC_PORT_2S, 0x10, 0, 8, 71128380Sbde }, 72128380Sbde 73158124Smarcel { 0x103c, 0x1048, 0x103c, 0x1049, 74158124Smarcel "HP Diva Serial [GSP] Multiport UART - Tosca Console", 75158124Smarcel DEFAULT_RCLK, 76158124Smarcel PUC_PORT_3S, 0x10, 0, -1, 77158124Smarcel .config_function = puc_config_diva 78119814Smarcel }, 79119814Smarcel 80158124Smarcel { 0x103c, 0x1048, 0x103c, 0x104a, 81158124Smarcel "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 82158124Smarcel DEFAULT_RCLK, 83158124Smarcel PUC_PORT_2S, 0x10, 0, -1, 84158124Smarcel .config_function = puc_config_diva 8598376Sobrien }, 8698376Sobrien 87158124Smarcel { 0x103c, 0x1048, 0x103c, 0x104b, 88158124Smarcel "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 89158124Smarcel DEFAULT_RCLK, 90158124Smarcel PUC_PORT_4S, 0x10, 0, -1, 91158124Smarcel .config_function = puc_config_diva 9298376Sobrien }, 9398376Sobrien 94158124Smarcel { 0x103c, 0x1048, 0x103c, 0x1223, 95158124Smarcel "HP Diva Serial [GSP] Multiport UART - Superdome Console", 96158124Smarcel DEFAULT_RCLK, 97158124Smarcel PUC_PORT_3S, 0x10, 0, -1, 98158124Smarcel .config_function = puc_config_diva 9998376Sobrien }, 100158124Smarcel 101158124Smarcel { 0x103c, 0x1048, 0x103c, 0x1226, 102158124Smarcel "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 103158124Smarcel DEFAULT_RCLK, 104158124Smarcel PUC_PORT_3S, 0x10, 0, -1, 105158124Smarcel .config_function = puc_config_diva 10698376Sobrien }, 10798376Sobrien 108158124Smarcel { 0x103c, 0x1048, 0x103c, 0x1282, 109158124Smarcel "HP Diva Serial [GSP] Multiport UART - Everest SP2", 110158124Smarcel DEFAULT_RCLK, 111158124Smarcel PUC_PORT_3S, 0x10, 0, -1, 112158124Smarcel .config_function = puc_config_diva 11398376Sobrien }, 114158124Smarcel 115158124Smarcel { 0x10b5, 0x1076, 0x10b5, 0x1076, 116158124Smarcel "VScom PCI-800", 117158124Smarcel DEFAULT_RCLK * 8, 118158124Smarcel PUC_PORT_8S, 0x18, 0, 8, 11998376Sobrien }, 12098376Sobrien 121158124Smarcel { 0x10b5, 0x1077, 0x10b5, 0x1077, 122158124Smarcel "VScom PCI-400", 123158124Smarcel DEFAULT_RCLK * 8, 124158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 12598376Sobrien }, 12698376Sobrien 127158124Smarcel { 0x10b5, 0x1103, 0x10b5, 0x1103, 128158124Smarcel "VScom PCI-200", 129158124Smarcel DEFAULT_RCLK * 8, 130158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 13198374Sobrien }, 13298376Sobrien 13390731Sjhay /* 134158124Smarcel * Boca Research Turbo Serial 658 (8 serial port) card. 135158124Smarcel * Appears to be the same as Chase Research PLC PCI-FAST8 136158124Smarcel * and Perle PCI-FAST8 Multi-Port serial cards. 13790731Sjhay */ 138158124Smarcel { 0x10b5, 0x9050, 0x12e0, 0x0021, 139158124Smarcel "Boca Research Turbo Serial 658", 140158124Smarcel DEFAULT_RCLK * 4, 141158124Smarcel PUC_PORT_8S, 0x18, 0, 8, 142158124Smarcel }, 14390731Sjhay 144158124Smarcel { 0x10b5, 0x9050, 0x12e0, 0x0031, 145158124Smarcel "Boca Research Turbo Serial 654", 146158124Smarcel DEFAULT_RCLK * 4, 147158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 148158124Smarcel }, 149158124Smarcel 15090731Sjhay /* 151158124Smarcel * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 15290731Sjhay * a seemingly-lame EEPROM setup that puts the Dolphin IDs 15390731Sjhay * into the subsystem fields, and claims that it's a 15490731Sjhay * network/misc (0x02/0x80) device. 15590731Sjhay */ 156158124Smarcel { 0x10b5, 0x9050, 0xd84d, 0x6808, 157158124Smarcel "Dolphin Peripherals 4035", 158158124Smarcel DEFAULT_RCLK, 159158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 16090731Sjhay }, 16190731Sjhay 16290731Sjhay /* 163158124Smarcel * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 16490731Sjhay * a seemingly-lame EEPROM setup that puts the Dolphin IDs 16590731Sjhay * into the subsystem fields, and claims that it's a 16690731Sjhay * network/misc (0x02/0x80) device. 16790731Sjhay */ 168158124Smarcel { 0x10b5, 0x9050, 0xd84d, 0x6810, 169158124Smarcel "Dolphin Peripherals 4014", 170158124Smarcel 0, 171158124Smarcel PUC_PORT_2P, 0x20, 4, 0, 17290731Sjhay }, 17390731Sjhay 174158124Smarcel { 0x10e8, 0x818e, 0xffff, 0, 175158124Smarcel "Applied Micro Circuits 8 Port UART", 176200230Smarcel DEFAULT_RCLK, 177200230Smarcel PUC_PORT_8S, 0x14, -1, -1, 178158124Smarcel .config_function = puc_config_amc 179200230Smarcel }, 180158124Smarcel 181158124Smarcel { 0x11fe, 0x8010, 0xffff, 0, 182158124Smarcel "Comtrol RocketPort 550/8 RJ11 part A", 183158124Smarcel DEFAULT_RCLK * 4, 184158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 18590731Sjhay }, 18690731Sjhay 187158124Smarcel { 0x11fe, 0x8011, 0xffff, 0, 188158124Smarcel "Comtrol RocketPort 550/8 RJ11 part B", 189158124Smarcel DEFAULT_RCLK * 4, 190158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 191158124Smarcel }, 19290731Sjhay 193158124Smarcel { 0x11fe, 0x8012, 0xffff, 0, 194158124Smarcel "Comtrol RocketPort 550/8 Octa part A", 195158124Smarcel DEFAULT_RCLK * 4, 196158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 197158124Smarcel }, 19890731Sjhay 199158124Smarcel { 0x11fe, 0x8013, 0xffff, 0, 200158124Smarcel "Comtrol RocketPort 550/8 Octa part B", 201158124Smarcel DEFAULT_RCLK * 4, 202158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 203158124Smarcel }, 204158124Smarcel 205158124Smarcel { 0x11fe, 0x8014, 0xffff, 0, 206158124Smarcel "Comtrol RocketPort 550/4 RJ45", 207158124Smarcel DEFAULT_RCLK * 4, 208158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 209158124Smarcel }, 210158124Smarcel 211158124Smarcel { 0x11fe, 0x8015, 0xffff, 0, 212158124Smarcel "Comtrol RocketPort 550/Quad", 213158124Smarcel DEFAULT_RCLK * 4, 214158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 215158124Smarcel }, 216158124Smarcel 217158124Smarcel { 0x11fe, 0x8016, 0xffff, 0, 218158124Smarcel "Comtrol RocketPort 550/16 part A", 219158124Smarcel DEFAULT_RCLK * 4, 220158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 221158124Smarcel }, 222158124Smarcel 223158124Smarcel { 0x11fe, 0x8017, 0xffff, 0, 224158124Smarcel "Comtrol RocketPort 550/16 part B", 225158124Smarcel DEFAULT_RCLK * 4, 226158124Smarcel PUC_PORT_12S, 0x10, 0, 8, 227158124Smarcel }, 228158124Smarcel 229158124Smarcel { 0x11fe, 0x8018, 0xffff, 0, 230158124Smarcel "Comtrol RocketPort 550/8 part A", 231158124Smarcel DEFAULT_RCLK * 4, 232158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 233158124Smarcel }, 234158124Smarcel 235158124Smarcel { 0x11fe, 0x8019, 0xffff, 0, 236158124Smarcel "Comtrol RocketPort 550/8 part B", 237158124Smarcel DEFAULT_RCLK * 4, 238158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 239158124Smarcel }, 240158124Smarcel 24190731Sjhay /* 242193305Srwatson * IBM SurePOS 300 Series (481033H) serial ports 243193305Srwatson * Details can be found on the IBM RSS websites 244193305Srwatson */ 245193305Srwatson 246193305Srwatson { 0x1014, 0x0297, 0xffff, 0, 247193305Srwatson "IBM SurePOS 300 Series (481033H) serial ports", 248193305Srwatson DEFAULT_RCLK, 249193305Srwatson PUC_PORT_4S, 0x10, 4, 0 250193305Srwatson }, 251193305Srwatson 252193305Srwatson /* 25390731Sjhay * SIIG Boards. 25490731Sjhay * 25590731Sjhay * SIIG provides documentation for their boards at: 256158124Smarcel * <URL:http://www.siig.com/downloads.asp> 25790731Sjhay */ 25890731Sjhay 259158124Smarcel { 0x131f, 0x1010, 0xffff, 0, 260158124Smarcel "SIIG Cyber I/O PCI 16C550 (10x family)", 261158124Smarcel DEFAULT_RCLK, 262158124Smarcel PUC_PORT_1S1P, 0x18, 4, 0, 263158124Smarcel }, 26490731Sjhay 265158124Smarcel { 0x131f, 0x1011, 0xffff, 0, 266158124Smarcel "SIIG Cyber I/O PCI 16C650 (10x family)", 267158124Smarcel DEFAULT_RCLK, 268158124Smarcel PUC_PORT_1S1P, 0x18, 4, 0, 26990731Sjhay }, 27090731Sjhay 271158124Smarcel { 0x131f, 0x1012, 0xffff, 0, 272158124Smarcel "SIIG Cyber I/O PCI 16C850 (10x family)", 273158124Smarcel DEFAULT_RCLK, 274158124Smarcel PUC_PORT_1S1P, 0x18, 4, 0, 27590731Sjhay }, 27690731Sjhay 277158124Smarcel { 0x131f, 0x1021, 0xffff, 0, 278158124Smarcel "SIIG Cyber Parallel Dual PCI (10x family)", 279158124Smarcel 0, 280158124Smarcel PUC_PORT_2P, 0x18, 8, 0, 28190731Sjhay }, 28290731Sjhay 283158124Smarcel { 0x131f, 0x1030, 0xffff, 0, 284158124Smarcel "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 285158124Smarcel DEFAULT_RCLK, 286158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 28790731Sjhay }, 28890731Sjhay 289158124Smarcel { 0x131f, 0x1031, 0xffff, 0, 290158124Smarcel "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 291158124Smarcel DEFAULT_RCLK, 292158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 29390731Sjhay }, 29490731Sjhay 295158124Smarcel { 0x131f, 0x1032, 0xffff, 0, 296158124Smarcel "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 297158124Smarcel DEFAULT_RCLK, 298158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 29990731Sjhay }, 30090731Sjhay 301158124Smarcel { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 302158124Smarcel "SIIG Cyber 2S1P PCI 16C550 (10x family)", 303158124Smarcel DEFAULT_RCLK, 304158124Smarcel PUC_PORT_2S1P, 0x18, 4, 0, 30590731Sjhay }, 30690731Sjhay 307158124Smarcel { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 308158124Smarcel "SIIG Cyber 2S1P PCI 16C650 (10x family)", 309158124Smarcel DEFAULT_RCLK, 310158124Smarcel PUC_PORT_2S1P, 0x18, 4, 0, 31190731Sjhay }, 31290731Sjhay 313158124Smarcel { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 314158124Smarcel "SIIG Cyber 2S1P PCI 16C850 (10x family)", 315158124Smarcel DEFAULT_RCLK, 316158124Smarcel PUC_PORT_2S1P, 0x18, 4, 0, 31790731Sjhay }, 31890731Sjhay 319158124Smarcel { 0x131f, 0x1050, 0xffff, 0, 320158124Smarcel "SIIG Cyber 4S PCI 16C550 (10x family)", 321158124Smarcel DEFAULT_RCLK, 322158124Smarcel PUC_PORT_4S, 0x18, 4, 0, 32390731Sjhay }, 32490731Sjhay 325158124Smarcel { 0x131f, 0x1051, 0xffff, 0, 326158124Smarcel "SIIG Cyber 4S PCI 16C650 (10x family)", 327158124Smarcel DEFAULT_RCLK, 328158124Smarcel PUC_PORT_4S, 0x18, 4, 0, 32990731Sjhay }, 33090731Sjhay 331158124Smarcel { 0x131f, 0x1052, 0xffff, 0, 332158124Smarcel "SIIG Cyber 4S PCI 16C850 (10x family)", 333158124Smarcel DEFAULT_RCLK, 334158124Smarcel PUC_PORT_4S, 0x18, 4, 0, 33590731Sjhay }, 33690731Sjhay 337158124Smarcel { 0x131f, 0x2010, 0xffff, 0, 338158124Smarcel "SIIG Cyber I/O PCI 16C550 (20x family)", 339158124Smarcel DEFAULT_RCLK, 340158124Smarcel PUC_PORT_1S1P, 0x10, 4, 0, 34190731Sjhay }, 34290731Sjhay 343158124Smarcel { 0x131f, 0x2011, 0xffff, 0, 344158124Smarcel "SIIG Cyber I/O PCI 16C650 (20x family)", 345158124Smarcel DEFAULT_RCLK, 346158124Smarcel PUC_PORT_1S1P, 0x10, 4, 0, 34790731Sjhay }, 34890731Sjhay 349158124Smarcel { 0x131f, 0x2012, 0xffff, 0, 350158124Smarcel "SIIG Cyber I/O PCI 16C850 (20x family)", 351158124Smarcel DEFAULT_RCLK, 352158124Smarcel PUC_PORT_1S1P, 0x10, 4, 0, 35390731Sjhay }, 35490731Sjhay 355158124Smarcel { 0x131f, 0x2021, 0xffff, 0, 356158124Smarcel "SIIG Cyber Parallel Dual PCI (20x family)", 357158124Smarcel 0, 358158124Smarcel PUC_PORT_2P, 0x10, 8, 0, 35990731Sjhay }, 36090731Sjhay 361158124Smarcel { 0x131f, 0x2030, 0xffff, 0, 362158124Smarcel "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 363158124Smarcel DEFAULT_RCLK, 364158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 36590731Sjhay }, 36690731Sjhay 367158124Smarcel { 0x131f, 0x2031, 0xffff, 0, 368158124Smarcel "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 369158124Smarcel DEFAULT_RCLK, 370158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 371158124Smarcel }, 37290731Sjhay 373158124Smarcel { 0x131f, 0x2032, 0xffff, 0, 374158124Smarcel "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 375158124Smarcel DEFAULT_RCLK, 376158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 37790731Sjhay }, 37890731Sjhay 379158124Smarcel { 0x131f, 0x2040, 0xffff, 0, 380158124Smarcel "SIIG Cyber 2P1S PCI 16C550 (20x family)", 381158124Smarcel DEFAULT_RCLK, 382158124Smarcel PUC_PORT_1S2P, 0x10, -1, 0, 383158124Smarcel .config_function = puc_config_siig 38490731Sjhay }, 38590731Sjhay 386158124Smarcel { 0x131f, 0x2041, 0xffff, 0, 387158124Smarcel "SIIG Cyber 2P1S PCI 16C650 (20x family)", 388158124Smarcel DEFAULT_RCLK, 389158124Smarcel PUC_PORT_1S2P, 0x10, -1, 0, 390158124Smarcel .config_function = puc_config_siig 39190731Sjhay }, 39290731Sjhay 393158124Smarcel { 0x131f, 0x2042, 0xffff, 0, 394158124Smarcel "SIIG Cyber 2P1S PCI 16C850 (20x family)", 395158124Smarcel DEFAULT_RCLK, 396158124Smarcel PUC_PORT_1S2P, 0x10, -1, 0, 397158124Smarcel .config_function = puc_config_siig 39890731Sjhay }, 39990731Sjhay 400158124Smarcel { 0x131f, 0x2050, 0xffff, 0, 401158124Smarcel "SIIG Cyber 4S PCI 16C550 (20x family)", 402158124Smarcel DEFAULT_RCLK, 403158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 40490731Sjhay }, 40590731Sjhay 406158124Smarcel { 0x131f, 0x2051, 0xffff, 0, 407158124Smarcel "SIIG Cyber 4S PCI 16C650 (20x family)", 408158124Smarcel DEFAULT_RCLK, 409158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 41090731Sjhay }, 41190731Sjhay 412158124Smarcel { 0x131f, 0x2052, 0xffff, 0, 413158124Smarcel "SIIG Cyber 4S PCI 16C850 (20x family)", 414158124Smarcel DEFAULT_RCLK, 415158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 41690731Sjhay }, 41790731Sjhay 418158124Smarcel { 0x131f, 0x2060, 0xffff, 0, 419158124Smarcel "SIIG Cyber 2S1P PCI 16C550 (20x family)", 420158124Smarcel DEFAULT_RCLK, 421158124Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 42290731Sjhay }, 42390731Sjhay 424158124Smarcel { 0x131f, 0x2061, 0xffff, 0, 425158124Smarcel "SIIG Cyber 2S1P PCI 16C650 (20x family)", 426158124Smarcel DEFAULT_RCLK, 427158124Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 42890731Sjhay }, 42990731Sjhay 430158124Smarcel { 0x131f, 0x2062, 0xffff, 0, 431158124Smarcel "SIIG Cyber 2S1P PCI 16C850 (20x family)", 432158124Smarcel DEFAULT_RCLK, 433158124Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 43490731Sjhay }, 43590731Sjhay 436158124Smarcel { 0x131f, 0x2081, 0xffff, 0, 437158124Smarcel "SIIG PS8000 8S PCI 16C650 (20x family)", 438158124Smarcel DEFAULT_RCLK, 439158124Smarcel PUC_PORT_8S, 0x10, -1, -1, 440158124Smarcel .config_function = puc_config_siig 44190731Sjhay }, 44290731Sjhay 443158124Smarcel { 0x135c, 0x0010, 0xffff, 0, 444158124Smarcel "Quatech QSC-100", 445158124Smarcel -3, /* max 8x clock rate */ 446158124Smarcel PUC_PORT_4S, 0x14, 0, 8, 447158124Smarcel .config_function = puc_config_quatech 44890731Sjhay }, 44990731Sjhay 450158124Smarcel { 0x135c, 0x0020, 0xffff, 0, 451158124Smarcel "Quatech DSC-100", 452158124Smarcel -1, /* max 2x clock rate */ 453158124Smarcel PUC_PORT_2S, 0x14, 0, 8, 454158124Smarcel .config_function = puc_config_quatech 45590731Sjhay }, 45690731Sjhay 457158124Smarcel { 0x135c, 0x0030, 0xffff, 0, 458158124Smarcel "Quatech DSC-200/300", 459158124Smarcel -1, /* max 2x clock rate */ 460158124Smarcel PUC_PORT_2S, 0x14, 0, 8, 461158124Smarcel .config_function = puc_config_quatech 46290731Sjhay }, 46390731Sjhay 464158124Smarcel { 0x135c, 0x0040, 0xffff, 0, 465158124Smarcel "Quatech QSC-200/300", 466158124Smarcel -3, /* max 8x clock rate */ 467158124Smarcel PUC_PORT_4S, 0x14, 0, 8, 468158124Smarcel .config_function = puc_config_quatech 46990731Sjhay }, 47090731Sjhay 471158124Smarcel { 0x135c, 0x0050, 0xffff, 0, 472158124Smarcel "Quatech ESC-100D", 473158124Smarcel -3, /* max 8x clock rate */ 474158124Smarcel PUC_PORT_8S, 0x14, 0, 8, 475158124Smarcel .config_function = puc_config_quatech 47690731Sjhay }, 47790731Sjhay 478158124Smarcel { 0x135c, 0x0060, 0xffff, 0, 479158124Smarcel "Quatech ESC-100M", 480158124Smarcel -3, /* max 8x clock rate */ 481158124Smarcel PUC_PORT_8S, 0x14, 0, 8, 482158124Smarcel .config_function = puc_config_quatech 48390731Sjhay }, 48490731Sjhay 485158124Smarcel { 0x135c, 0x0170, 0xffff, 0, 486158124Smarcel "Quatech QSCLP-100", 487158124Smarcel -1, /* max 2x clock rate */ 488158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 489158124Smarcel .config_function = puc_config_quatech 49090731Sjhay }, 49190731Sjhay 492158124Smarcel { 0x135c, 0x0180, 0xffff, 0, 493158124Smarcel "Quatech DSCLP-100", 494158124Smarcel -1, /* max 3x clock rate */ 495158124Smarcel PUC_PORT_2S, 0x18, 0, 8, 496158124Smarcel .config_function = puc_config_quatech 49790731Sjhay }, 49890731Sjhay 499158124Smarcel { 0x135c, 0x01b0, 0xffff, 0, 500158124Smarcel "Quatech DSCLP-200/300", 501158124Smarcel -1, /* max 2x clock rate */ 502158124Smarcel PUC_PORT_2S, 0x18, 0, 8, 503158124Smarcel .config_function = puc_config_quatech 50490731Sjhay }, 50590731Sjhay 506158124Smarcel { 0x135c, 0x01e0, 0xffff, 0, 507158124Smarcel "Quatech ESCLP-100", 508158124Smarcel -3, /* max 8x clock rate */ 509158124Smarcel PUC_PORT_8S, 0x10, 0, 8, 510158124Smarcel .config_function = puc_config_quatech 511102259Sjhay }, 512102259Sjhay 513237350Sfjoe { 0x1393, 0x1024, 0xffff, 0, 514237350Sfjoe "Moxa Technologies, Smartio CP-102E/PCIe", 515237350Sfjoe DEFAULT_RCLK * 8, 516238933Sfjoe PUC_PORT_2S, 0x14, 0, -1, 517251713Smarius .config_function = puc_config_moxa 518237350Sfjoe }, 519237350Sfjoe 520237350Sfjoe { 0x1393, 0x1025, 0xffff, 0, 521237350Sfjoe "Moxa Technologies, Smartio CP-102EL/PCIe", 522237350Sfjoe DEFAULT_RCLK * 8, 523238933Sfjoe PUC_PORT_2S, 0x14, 0, -1, 524251713Smarius .config_function = puc_config_moxa 525237350Sfjoe }, 526237350Sfjoe 527158124Smarcel { 0x1393, 0x1040, 0xffff, 0, 528158124Smarcel "Moxa Technologies, Smartio C104H/PCI", 529158124Smarcel DEFAULT_RCLK * 8, 530158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 53190731Sjhay }, 53290731Sjhay 533158124Smarcel { 0x1393, 0x1041, 0xffff, 0, 534158124Smarcel "Moxa Technologies, Smartio CP-104UL/PCI", 535158124Smarcel DEFAULT_RCLK * 8, 536158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 53790731Sjhay }, 538158124Smarcel 539227457Seadler { 0x1393, 0x1042, 0xffff, 0, 540227457Seadler "Moxa Technologies, Smartio CP-104JU/PCI", 541227457Seadler DEFAULT_RCLK * 8, 542227457Seadler PUC_PORT_4S, 0x18, 0, 8, 543227457Seadler }, 544227457Seadler 545175245Smaxim { 0x1393, 0x1043, 0xffff, 0, 546175245Smaxim "Moxa Technologies, Smartio CP-104EL/PCIe", 547175245Smaxim DEFAULT_RCLK * 8, 548175245Smaxim PUC_PORT_4S, 0x18, 0, 8, 549175245Smaxim }, 550175245Smaxim 551227457Seadler { 0x1393, 0x1045, 0xffff, 0, 552227457Seadler "Moxa Technologies, Smartio CP-104EL-A/PCIe", 553227457Seadler DEFAULT_RCLK * 8, 554227457Seadler PUC_PORT_4S, 0x14, 0, -1, 555251713Smarius .config_function = puc_config_moxa 556227457Seadler }, 557227457Seadler 558224898Sjhb { 0x1393, 0x1120, 0xffff, 0, 559224898Sjhb "Moxa Technologies, CP-112UL", 560224898Sjhb DEFAULT_RCLK * 8, 561224898Sjhb PUC_PORT_2S, 0x18, 0, 8, 562224898Sjhb }, 563224898Sjhb 564158124Smarcel { 0x1393, 0x1141, 0xffff, 0, 565158124Smarcel "Moxa Technologies, Industio CP-114", 566158124Smarcel DEFAULT_RCLK * 8, 567158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 56890731Sjhay }, 569158124Smarcel 570237350Sfjoe { 0x1393, 0x1144, 0xffff, 0, 571237350Sfjoe "Moxa Technologies, Smartio CP-114EL/PCIe", 572237350Sfjoe DEFAULT_RCLK * 8, 573237350Sfjoe PUC_PORT_4S, 0x14, 0, -1, 574251713Smarius .config_function = puc_config_moxa 575237350Sfjoe }, 576237350Sfjoe 577237350Sfjoe { 0x1393, 0x1182, 0xffff, 0, 578237350Sfjoe "Moxa Technologies, Smartio CP-118EL-A/PCIe", 579237350Sfjoe DEFAULT_RCLK * 8, 580238933Sfjoe PUC_PORT_8S, 0x14, 0, -1, 581251713Smarius .config_function = puc_config_moxa 582237350Sfjoe }, 583237350Sfjoe 584158124Smarcel { 0x1393, 0x1680, 0xffff, 0, 585158124Smarcel "Moxa Technologies, C168H/PCI", 586158124Smarcel DEFAULT_RCLK * 8, 587158124Smarcel PUC_PORT_8S, 0x18, 0, 8, 58890731Sjhay }, 58990731Sjhay 590158124Smarcel { 0x1393, 0x1681, 0xffff, 0, 591158124Smarcel "Moxa Technologies, C168U/PCI", 592158124Smarcel DEFAULT_RCLK * 8, 593158124Smarcel PUC_PORT_8S, 0x18, 0, 8, 594118357Sbde }, 595118357Sbde 596187766Sstas { 0x1393, 0x1682, 0xffff, 0, 597187766Sstas "Moxa Technologies, CP-168EL/PCIe", 598187766Sstas DEFAULT_RCLK * 8, 599187766Sstas PUC_PORT_8S, 0x18, 0, 8, 600187766Sstas }, 601187766Sstas 602237350Sfjoe { 0x1393, 0x1683, 0xffff, 0, 603237350Sfjoe "Moxa Technologies, Smartio CP-168EL-A/PCIe", 604237350Sfjoe DEFAULT_RCLK * 8, 605238933Sfjoe PUC_PORT_8S, 0x14, 0, -1, 606251713Smarius .config_function = puc_config_moxa 607237350Sfjoe }, 608237350Sfjoe 609222660Sjhb { 0x13a8, 0x0152, 0xffff, 0, 610222660Sjhb "Exar XR17C/D152", 611222660Sjhb DEFAULT_RCLK * 8, 612222660Sjhb PUC_PORT_2S, 0x10, 0, -1, 613222660Sjhb .config_function = puc_config_exar 614222660Sjhb }, 615222660Sjhb 616222660Sjhb { 0x13a8, 0x0154, 0xffff, 0, 617222660Sjhb "Exar XR17C154", 618222660Sjhb DEFAULT_RCLK * 8, 619222660Sjhb PUC_PORT_4S, 0x10, 0, -1, 620222660Sjhb .config_function = puc_config_exar 621222660Sjhb }, 622222660Sjhb 623158124Smarcel { 0x13a8, 0x0158, 0xffff, 0, 624222660Sjhb "Exar XR17C158", 625158124Smarcel DEFAULT_RCLK * 8, 626158124Smarcel PUC_PORT_8S, 0x10, 0, -1, 627222660Sjhb .config_function = puc_config_exar 62890731Sjhay }, 62990731Sjhay 630216513Semaste { 0x13a8, 0x0258, 0xffff, 0, 631216513Semaste "Exar XR17V258IV", 632216513Semaste DEFAULT_RCLK * 8, 633216513Semaste PUC_PORT_8S, 0x10, 0, -1, 634248472Srstone .config_function = puc_config_exar 635216513Semaste }, 636216513Semaste 637248340Srstone /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 638248340Srstone { 0x13a8, 0x0358, 0xffff, 0, 639248340Srstone "Exar XR17V358", 640248340Srstone 125000000, 641248340Srstone PUC_PORT_8S, 0x10, 0, -1, 642248340Srstone .config_function = puc_config_exar_pcie 643248340Srstone }, 644248340Srstone 645242814Seadler { 0x13fe, 0x1600, 0x1602, 0x0002, 646242814Seadler "Advantech PCI-1602", 647242814Seadler DEFAULT_RCLK * 8, 648242814Seadler PUC_PORT_2S, 0x10, 0, 8, 649242814Seadler }, 650242814Seadler 651158124Smarcel { 0x1407, 0x0100, 0xffff, 0, 652158124Smarcel "Lava Computers Dual Serial", 653158124Smarcel DEFAULT_RCLK, 654158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 65590731Sjhay }, 65690731Sjhay 657158124Smarcel { 0x1407, 0x0101, 0xffff, 0, 658158124Smarcel "Lava Computers Quatro A", 659158124Smarcel DEFAULT_RCLK, 660158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 66190731Sjhay }, 66290731Sjhay 663158124Smarcel { 0x1407, 0x0102, 0xffff, 0, 664158124Smarcel "Lava Computers Quatro B", 665158124Smarcel DEFAULT_RCLK, 666158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 66790731Sjhay }, 66890731Sjhay 669158124Smarcel { 0x1407, 0x0120, 0xffff, 0, 670158124Smarcel "Lava Computers Quattro-PCI A", 671158124Smarcel DEFAULT_RCLK, 672158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 67395394Sjhay }, 67495394Sjhay 675158124Smarcel { 0x1407, 0x0121, 0xffff, 0, 676158124Smarcel "Lava Computers Quattro-PCI B", 677158124Smarcel DEFAULT_RCLK, 678158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 67990731Sjhay }, 68090731Sjhay 681158124Smarcel { 0x1407, 0x0180, 0xffff, 0, 682158124Smarcel "Lava Computers Octo A", 683158124Smarcel DEFAULT_RCLK, 684158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 68590731Sjhay }, 68690731Sjhay 687158124Smarcel { 0x1407, 0x0181, 0xffff, 0, 688158124Smarcel "Lava Computers Octo B", 689158124Smarcel DEFAULT_RCLK, 690158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 69190731Sjhay }, 69290731Sjhay 693188511Skevlo { 0x1409, 0x7268, 0xffff, 0, 694188511Skevlo "Sunix SUN1888", 695188511Skevlo 0, 696188511Skevlo PUC_PORT_2P, 0x10, 0, 8, 697188511Skevlo }, 698188511Skevlo 699158124Smarcel { 0x1409, 0x7168, 0xffff, 0, 700158124Smarcel NULL, 701158124Smarcel DEFAULT_RCLK * 8, 702158124Smarcel PUC_PORT_NONSTANDARD, 0x10, -1, -1, 703158124Smarcel .config_function = puc_config_timedia 70490731Sjhay }, 70590731Sjhay 70690731Sjhay /* 70790731Sjhay * Boards with an Oxford Semiconductor chip. 70890731Sjhay * 70990731Sjhay * Oxford Semiconductor provides documentation for their chip at: 710221182Sjhb * <URL:http://www.plxtech.com/products/uart/> 71190731Sjhay * 71290731Sjhay * As sold by Kouwell <URL:http://www.kouwell.com/>. 71390731Sjhay * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 71490731Sjhay */ 715226404Seadler { 716251713Smarius 0x1415, 0x9501, 0x10fc, 0xc070, 717251713Smarius "I-O DATA RSA-PCI2/R", 718251713Smarius DEFAULT_RCLK * 8, 719251713Smarius PUC_PORT_2S, 0x10, 0, 8, 720226404Seadler }, 72190731Sjhay 722184258Sdes { 0x1415, 0x9501, 0x131f, 0x2050, 723184258Sdes "SIIG Cyber 4 PCI 16550", 724184258Sdes DEFAULT_RCLK * 10, 725184258Sdes PUC_PORT_4S, 0x10, 0, 8, 726184258Sdes }, 727184258Sdes 728162007Smarcel { 0x1415, 0x9501, 0x131f, 0x2051, 729162007Smarcel "SIIG Cyber 4S PCI 16C650 (20x family)", 730162007Smarcel DEFAULT_RCLK * 10, 731162007Smarcel PUC_PORT_4S, 0x10, 0, 8, 732162007Smarcel }, 733162007Smarcel 734221731Sjhb { 0x1415, 0x9501, 0x131f, 0x2052, 735221731Sjhb "SIIG Quartet Serial 850", 736221731Sjhb DEFAULT_RCLK * 10, 737221731Sjhb PUC_PORT_4S, 0x10, 0, 8, 738221731Sjhb }, 739221731Sjhb 740221326Sjhb { 0x1415, 0x9501, 0x14db, 0x2150, 741221326Sjhb "Kuroutoshikou SERIAL4P-LPPCI2", 742221326Sjhb DEFAULT_RCLK * 10, 743221326Sjhb PUC_PORT_4S, 0x10, 0, 8, 744221326Sjhb }, 745221326Sjhb 746158124Smarcel { 0x1415, 0x9501, 0xffff, 0, 747183817Sdes "Oxford Semiconductor OX16PCI954 UARTs", 748251715Smarius 0, 749158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 750251715Smarius .config_function = puc_config_oxford_pci954 751145391Simp }, 752145391Simp 753222093Sjhb { 0x1415, 0x950a, 0x131f, 0x2030, 754222093Sjhb "SIIG Cyber 2S PCIe", 755222093Sjhb DEFAULT_RCLK * 10, 756222093Sjhb PUC_PORT_2S, 0x10, 0, 8, 757222093Sjhb }, 758222093Sjhb 759239076Seadler { 0x1415, 0x950a, 0x131f, 0x2032, 760239076Seadler "SIIG Cyber Serial Dual PCI 16C850", 761239076Seadler DEFAULT_RCLK * 10, 762239076Seadler PUC_PORT_4S, 0x10, 0, 8, 763239076Seadler }, 764239076Seadler 765158124Smarcel { 0x1415, 0x950a, 0xffff, 0, 766183817Sdes "Oxford Semiconductor OX16PCI954 UARTs", 767183817Sdes DEFAULT_RCLK, 768158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 76990731Sjhay }, 77090731Sjhay 771158124Smarcel { 0x1415, 0x9511, 0xffff, 0, 772158124Smarcel "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 773158124Smarcel DEFAULT_RCLK, 774158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 775121488Sambrisko }, 776121488Sambrisko 777158124Smarcel { 0x1415, 0x9521, 0xffff, 0, 778158124Smarcel "Oxford Semiconductor OX16PCI952 UARTs", 779158124Smarcel DEFAULT_RCLK, 780158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 78190731Sjhay }, 78290731Sjhay 783186520Srik { 0x1415, 0x9538, 0xffff, 0, 784186520Srik "Oxford Semiconductor OX16PCI958 UARTs", 785247571Smarius DEFAULT_RCLK, 786186520Srik PUC_PORT_8S, 0x18, 0, 8, 787186520Srik }, 788186520Srik 789208350Sjhb /* 790208350Sjhb * Perle boards use Oxford Semiconductor chips, but they store the 791208350Sjhb * Oxford Semiconductor device ID as a subvendor device ID and use 792208350Sjhb * their own device IDs. 793208350Sjhb */ 794208350Sjhb 795208350Sjhb { 0x155f, 0x0331, 0xffff, 0, 796239048Seadler "Perle Ultraport4 Express", 797239048Seadler DEFAULT_RCLK * 8, 798239048Seadler PUC_PORT_4S, 0x10, 0, 8, 799239048Seadler }, 800239048Seadler 801239048Seadler { 0x155f, 0xB012, 0xffff, 0, 802239048Seadler "Perle Speed2 LE", 803239048Seadler DEFAULT_RCLK * 8, 804239048Seadler PUC_PORT_2S, 0x10, 0, 8, 805239048Seadler }, 806239048Seadler 807239048Seadler { 0x155f, 0xB022, 0xffff, 0, 808239048Seadler "Perle Speed2 LE", 809239048Seadler DEFAULT_RCLK * 8, 810239048Seadler PUC_PORT_2S, 0x10, 0, 8, 811239048Seadler }, 812239048Seadler 813239048Seadler { 0x155f, 0xB004, 0xffff, 0, 814208350Sjhb "Perle Speed4 LE", 815208350Sjhb DEFAULT_RCLK * 8, 816208350Sjhb PUC_PORT_4S, 0x10, 0, 8, 817208350Sjhb }, 818208350Sjhb 819239048Seadler { 0x155f, 0xB008, 0xffff, 0, 820239048Seadler "Perle Speed8 LE", 821239048Seadler DEFAULT_RCLK * 8, 822239048Seadler PUC_PORT_8S, 0x10, 0, 8, 823239048Seadler }, 824239048Seadler 825239048Seadler 826221182Sjhb /* 827221182Sjhb * Oxford Semiconductor PCI Express Expresso family 828221182Sjhb * 829221182Sjhb * Found in many 'native' PCI Express serial boards such as: 830221182Sjhb * 831221182Sjhb * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 832221182Sjhb * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 833221182Sjhb * 834221182Sjhb * Lindy 51189 (4 port) 835221182Sjhb * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 836251713Smarius * 837221182Sjhb * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 838221182Sjhb * <URL:http://www.startech.com> 839221182Sjhb */ 840221182Sjhb 841225878Sae { 0x1415, 0xc138, 0xffff, 0, 842225878Sae "Oxford Semiconductor OXPCIe952 UARTs", 843225878Sae DEFAULT_RCLK * 0x22, 844225878Sae PUC_PORT_NONSTANDARD, 0x10, 0, -1, 845225878Sae .config_function = puc_config_oxford_pcie 846225878Sae }, 847225878Sae 848221182Sjhb { 0x1415, 0xc158, 0xffff, 0, 849221182Sjhb "Oxford Semiconductor OXPCIe952 UARTs", 850221182Sjhb DEFAULT_RCLK * 0x22, 851221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 852221182Sjhb .config_function = puc_config_oxford_pcie 853221182Sjhb }, 854221182Sjhb 855221182Sjhb { 0x1415, 0xc15d, 0xffff, 0, 856221182Sjhb "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 857221182Sjhb DEFAULT_RCLK * 0x22, 858221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 859221182Sjhb .config_function = puc_config_oxford_pcie 860221182Sjhb }, 861221182Sjhb 862221182Sjhb { 0x1415, 0xc208, 0xffff, 0, 863221182Sjhb "Oxford Semiconductor OXPCIe954 UARTs", 864221182Sjhb DEFAULT_RCLK * 0x22, 865221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 866221182Sjhb .config_function = puc_config_oxford_pcie 867221182Sjhb }, 868221182Sjhb 869221182Sjhb { 0x1415, 0xc20d, 0xffff, 0, 870221182Sjhb "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 871221182Sjhb DEFAULT_RCLK * 0x22, 872221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 873221182Sjhb .config_function = puc_config_oxford_pcie 874221182Sjhb }, 875221182Sjhb 876221182Sjhb { 0x1415, 0xc308, 0xffff, 0, 877221182Sjhb "Oxford Semiconductor OXPCIe958 UARTs", 878221182Sjhb DEFAULT_RCLK * 0x22, 879221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 880221182Sjhb .config_function = puc_config_oxford_pcie 881221182Sjhb }, 882221182Sjhb 883221182Sjhb { 0x1415, 0xc30d, 0xffff, 0, 884221182Sjhb "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 885221182Sjhb DEFAULT_RCLK * 0x22, 886221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 887221182Sjhb .config_function = puc_config_oxford_pcie 888221182Sjhb }, 889221182Sjhb 890181974Sthompsa { 0x14d2, 0x8010, 0xffff, 0, 891181974Sthompsa "VScom PCI-100L", 892181974Sthompsa DEFAULT_RCLK * 8, 893181974Sthompsa PUC_PORT_1S, 0x14, 0, 0, 894181974Sthompsa }, 895181974Sthompsa 896158124Smarcel { 0x14d2, 0x8020, 0xffff, 0, 897158124Smarcel "VScom PCI-200L", 898158124Smarcel DEFAULT_RCLK * 8, 899158124Smarcel PUC_PORT_2S, 0x14, 4, 0, 900128354Scperciva }, 901128354Scperciva 902158124Smarcel { 0x14d2, 0x8028, 0xffff, 0, 903158124Smarcel "VScom 200Li", 904158124Smarcel DEFAULT_RCLK, 905158124Smarcel PUC_PORT_2S, 0x20, 0, 8, 906145391Simp }, 907145391Simp 908158124Smarcel /* 909158124Smarcel * VScom (Titan?) PCI-800L. More modern variant of the 910158124Smarcel * PCI-800. Uses 6 discrete 16550 UARTs, plus another 911158124Smarcel * two of them obviously implemented as macro cells in 912158124Smarcel * the ASIC. This causes the weird port access pattern 913158124Smarcel * below, where two of the IO port ranges each access 914158124Smarcel * one of the ASIC UARTs, and a block of IO addresses 915158124Smarcel * access the external UARTs. 916158124Smarcel */ 917158124Smarcel { 0x14d2, 0x8080, 0xffff, 0, 918158124Smarcel "Titan VScom PCI-800L", 919158124Smarcel DEFAULT_RCLK * 8, 920158124Smarcel PUC_PORT_8S, 0x14, -1, -1, 921158124Smarcel .config_function = puc_config_titan 92290731Sjhay }, 92390731Sjhay 92490731Sjhay /* 925158124Smarcel * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 926158124Smarcel * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 927158124Smarcel * device ID 3 and PCI device 1 device ID 4. 92890731Sjhay */ 929158124Smarcel { 0x14d2, 0xa003, 0xffff, 0, 930158124Smarcel "Titan PCI-800H", 931158124Smarcel DEFAULT_RCLK * 8, 932158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 93390731Sjhay }, 934247571Smarius 935158124Smarcel { 0x14d2, 0xa004, 0xffff, 0, 936158124Smarcel "Titan PCI-800H", 937158124Smarcel DEFAULT_RCLK * 8, 938158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 93990731Sjhay }, 94090731Sjhay 941158124Smarcel { 0x14d2, 0xa005, 0xffff, 0, 942158124Smarcel "Titan PCI-200H", 943158124Smarcel DEFAULT_RCLK * 8, 944158124Smarcel PUC_PORT_2S, 0x10, 0, 8, 945113006Sphk }, 946113006Sphk 947158124Smarcel { 0x14d2, 0xe020, 0xffff, 0, 948158124Smarcel "Titan VScom PCI-200HV2", 949158124Smarcel DEFAULT_RCLK * 8, 950158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 951123360Sobrien }, 952123360Sobrien 953227535Seadler { 0x14d2, 0xa007, 0xffff, 0, 954227535Seadler "Titan VScom PCIex-800H", 955227535Seadler DEFAULT_RCLK * 8, 956227535Seadler PUC_PORT_4S, 0x10, 0, 8, 957227535Seadler }, 958227535Seadler 959227535Seadler { 0x14d2, 0xa008, 0xffff, 0, 960227535Seadler "Titan VScom PCIex-800H", 961227535Seadler DEFAULT_RCLK * 8, 962227535Seadler PUC_PORT_4S, 0x10, 0, 8, 963227535Seadler }, 964227535Seadler 965158124Smarcel { 0x14db, 0x2130, 0xffff, 0, 966158124Smarcel "Avlab Technology, PCI IO 2S", 967158124Smarcel DEFAULT_RCLK, 968158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 96990731Sjhay }, 97090731Sjhay 971158124Smarcel { 0x14db, 0x2150, 0xffff, 0, 972158124Smarcel "Avlab Low Profile PCI 4 Serial", 973158124Smarcel DEFAULT_RCLK, 974158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 97590731Sjhay }, 97690731Sjhay 977181973Sthompsa { 0x14db, 0x2152, 0xffff, 0, 978181973Sthompsa "Avlab Low Profile PCI 4 Serial", 979181973Sthompsa DEFAULT_RCLK, 980181973Sthompsa PUC_PORT_4S, 0x10, 4, 0, 981181973Sthompsa }, 982181973Sthompsa 983158124Smarcel { 0x1592, 0x0781, 0xffff, 0, 984158124Smarcel "Syba Tech Ltd. PCI-4S2P-550-ECP", 985158124Smarcel DEFAULT_RCLK, 986158124Smarcel PUC_PORT_4S1P, 0x10, 0, -1, 987158124Smarcel .config_function = puc_config_syba 988118902Spb }, 989118902Spb 990264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0002, 991264761Smarius "Sunix SER5xxxx 2-port serial", 992236736Sjhay DEFAULT_RCLK * 8, 993236736Sjhay PUC_PORT_2S, 0x10, 0, 8, 994236736Sjhay }, 995236736Sjhay 996264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0004, 997264761Smarius "Sunix SER5xxxx 4-port serial", 998264761Smarius DEFAULT_RCLK * 8, 999264761Smarius PUC_PORT_4S, 0x10, 0, 8, 1000264761Smarius }, 1001264761Smarius 1002264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0008, 1003264761Smarius "Sunix SER5xxxx 8-port serial", 1004264761Smarius DEFAULT_RCLK * 8, 1005264761Smarius PUC_PORT_8S, -1, -1, -1, 1006264761Smarius .config_function = puc_config_sunix 1007264761Smarius }, 1008264761Smarius 1009264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0101, 1010264761Smarius "Sunix MIO5xxxx 1-port serial and 1284 Printer port", 1011264761Smarius DEFAULT_RCLK * 8, 1012264761Smarius PUC_PORT_1S1P, -1, -1, -1, 1013264761Smarius .config_function = puc_config_sunix 1014264761Smarius }, 1015264761Smarius 1016264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0102, 1017264761Smarius "Sunix MIO5xxxx 2-port serial and 1284 Printer port", 1018264761Smarius DEFAULT_RCLK * 8, 1019264761Smarius PUC_PORT_2S1P, -1, -1, -1, 1020264761Smarius .config_function = puc_config_sunix 1021264761Smarius }, 1022264761Smarius 1023264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0104, 1024264761Smarius "Sunix MIO5xxxx 4-port serial and 1284 Printer port", 1025264761Smarius DEFAULT_RCLK * 8, 1026264761Smarius PUC_PORT_4S1P, -1, -1, -1, 1027264761Smarius .config_function = puc_config_sunix 1028264761Smarius }, 1029264761Smarius 1030251713Smarius { 0x5372, 0x6873, 0xffff, 0, 1031251713Smarius "Sun 1040 PCI Quad Serial", 1032251713Smarius DEFAULT_RCLK, 1033251713Smarius PUC_PORT_4S, 0x10, 4, 0, 1034236282Seadler }, 1035236282Seadler 1036158124Smarcel { 0x6666, 0x0001, 0xffff, 0, 1037158124Smarcel "Decision Computer Inc, PCCOM 4-port serial", 1038158124Smarcel DEFAULT_RCLK, 1039158124Smarcel PUC_PORT_4S, 0x1c, 0, 8, 104091757Sjhay }, 104191757Sjhay 1042181975Sthompsa { 0x6666, 0x0002, 0xffff, 0, 1043181975Sthompsa "Decision Computer Inc, PCCOM 8-port serial", 1044181975Sthompsa DEFAULT_RCLK, 1045181975Sthompsa PUC_PORT_8S, 0x1c, 0, 8, 1046181975Sthompsa }, 1047181975Sthompsa 1048158124Smarcel { 0x6666, 0x0004, 0xffff, 0, 1049158124Smarcel "PCCOM dual port RS232/422/485", 1050158124Smarcel DEFAULT_RCLK, 1051158124Smarcel PUC_PORT_2S, 0x1c, 0, 8, 1052102261Sjhay }, 1053102261Sjhay 1054158124Smarcel { 0x9710, 0x9815, 0xffff, 0, 1055251713Smarius "NetMos NM9815 Dual 1284 Printer port", 1056158124Smarcel 0, 1057158124Smarcel PUC_PORT_2P, 0x10, 8, 0, 1058251713Smarius }, 105993330Smurray 1060189407Sjhb /* 1061264761Smarius * This is more specific than the generic NM9835 entry, and is placed 1062264761Smarius * here to _prevent_ puc(4) from claiming this single port card. 1063189407Sjhb * 1064189407Sjhb * uart(4) will claim this device. 1065189407Sjhb */ 1066189407Sjhb { 0x9710, 0x9835, 0x1000, 1, 1067189407Sjhb "NetMos NM9835 based 1-port serial", 1068189407Sjhb DEFAULT_RCLK, 1069189407Sjhb PUC_PORT_1S, 0x10, 4, 0, 1070189407Sjhb }, 1071189407Sjhb 1072194522Snp { 0x9710, 0x9835, 0x1000, 2, 1073194522Snp "NetMos NM9835 based 2-port serial", 1074194522Snp DEFAULT_RCLK, 1075194522Snp PUC_PORT_2S, 0x10, 4, 0, 1076194522Snp }, 1077194522Snp 1078158124Smarcel { 0x9710, 0x9835, 0xffff, 0, 1079158124Smarcel "NetMos NM9835 Dual UART and 1284 Printer port", 1080158124Smarcel DEFAULT_RCLK, 1081158124Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 108293533Sjhay }, 108393533Sjhay 1084158124Smarcel { 0x9710, 0x9845, 0x1000, 0x0006, 1085158124Smarcel "NetMos NM9845 6 Port UART", 1086158124Smarcel DEFAULT_RCLK, 1087158124Smarcel PUC_PORT_6S, 0x10, 4, 0, 1088128602Ssobomax }, 1089128602Ssobomax 1090158124Smarcel { 0x9710, 0x9845, 0xffff, 0, 1091158124Smarcel "NetMos NM9845 Quad UART and 1284 Printer port", 1092158124Smarcel DEFAULT_RCLK, 1093158124Smarcel PUC_PORT_4S1P, 0x10, 4, 0, 1094128602Ssobomax }, 1095128602Ssobomax 1096200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3002, 1097200230Smarcel "NetMos NM9865 Dual UART", 1098200230Smarcel DEFAULT_RCLK, 1099200230Smarcel PUC_PORT_2S, 0x10, 4, 0, 1100200230Smarcel }, 1101200230Smarcel 1102200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3003, 1103200230Smarcel "NetMos NM9865 Triple UART", 1104200230Smarcel DEFAULT_RCLK, 1105200230Smarcel PUC_PORT_3S, 0x10, 4, 0, 1106200230Smarcel }, 1107200230Smarcel 1108200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3004, 1109200230Smarcel "NetMos NM9865 Quad UART", 1110200230Smarcel DEFAULT_RCLK, 1111247571Smarius PUC_PORT_4S, 0x10, 4, 0, 1112200230Smarcel }, 1113200230Smarcel 1114200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3011, 1115200230Smarcel "NetMos NM9865 Single UART and 1284 Printer port", 1116200230Smarcel DEFAULT_RCLK, 1117200230Smarcel PUC_PORT_1S1P, 0x10, 4, 0, 1118200230Smarcel }, 1119200230Smarcel 1120200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3012, 1121200230Smarcel "NetMos NM9865 Dual UART and 1284 Printer port", 1122200230Smarcel DEFAULT_RCLK, 1123200230Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 1124200230Smarcel }, 1125200230Smarcel 1126200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3020, 1127200230Smarcel "NetMos NM9865 Dual 1284 Printer port", 1128200230Smarcel DEFAULT_RCLK, 1129200230Smarcel PUC_PORT_2P, 0x10, 4, 0, 1130200230Smarcel }, 1131200230Smarcel 1132158124Smarcel { 0xb00c, 0x021c, 0xffff, 0, 1133158124Smarcel "IC Book Labs Gunboat x4 Lite", 1134158124Smarcel DEFAULT_RCLK, 1135158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 1136158124Smarcel .config_function = puc_config_icbook 1137128602Ssobomax }, 1138128602Ssobomax 1139158124Smarcel { 0xb00c, 0x031c, 0xffff, 0, 1140158124Smarcel "IC Book Labs Gunboat x4 Pro", 1141158124Smarcel DEFAULT_RCLK, 1142158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 1143158124Smarcel .config_function = puc_config_icbook 1144128602Ssobomax }, 1145128602Ssobomax 1146158124Smarcel { 0xb00c, 0x041c, 0xffff, 0, 1147158124Smarcel "IC Book Labs Ironclad x8 Lite", 1148158124Smarcel DEFAULT_RCLK, 1149158124Smarcel PUC_PORT_8S, 0x10, 0, 8, 1150158124Smarcel .config_function = puc_config_icbook 1151114344Ssobomax }, 1152114344Ssobomax 1153158124Smarcel { 0xb00c, 0x051c, 0xffff, 0, 1154158124Smarcel "IC Book Labs Ironclad x8 Pro", 1155158124Smarcel DEFAULT_RCLK, 1156158124Smarcel PUC_PORT_8S, 0x10, 0, 8, 1157158124Smarcel .config_function = puc_config_icbook 1158114344Ssobomax }, 1159114344Ssobomax 1160158124Smarcel { 0xb00c, 0x081c, 0xffff, 0, 1161158124Smarcel "IC Book Labs Dreadnought x16 Pro", 1162158124Smarcel DEFAULT_RCLK * 8, 1163158124Smarcel PUC_PORT_16S, 0x10, 0, 8, 1164158124Smarcel .config_function = puc_config_icbook 1165108346Ssobomax }, 1166108346Ssobomax 1167158124Smarcel { 0xb00c, 0x091c, 0xffff, 0, 1168158124Smarcel "IC Book Labs Dreadnought x16 Lite", 1169158124Smarcel DEFAULT_RCLK, 1170158124Smarcel PUC_PORT_16S, 0x10, 0, 8, 1171158124Smarcel .config_function = puc_config_icbook 1172112154Ssobomax }, 1173112154Ssobomax 1174158124Smarcel { 0xb00c, 0x0a1c, 0xffff, 0, 1175158124Smarcel "IC Book Labs Gunboat x2 Low Profile", 1176158124Smarcel DEFAULT_RCLK, 1177158124Smarcel PUC_PORT_2S, 0x10, 0, 8, 1178129337Srik }, 1179129337Srik 1180158124Smarcel { 0xb00c, 0x0b1c, 0xffff, 0, 1181158124Smarcel "IC Book Labs Gunboat x4 Low Profile", 1182158124Smarcel DEFAULT_RCLK, 1183158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 1184158124Smarcel .config_function = puc_config_icbook 1185139728Swilko }, 1186139728Swilko 1187158124Smarcel { 0xffff, 0, 0xffff, 0, NULL, 0 } 1188158124Smarcel}; 1189139728Swilko 1190158124Smarcelstatic int 1191158124Smarcelpuc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1192158124Smarcel intptr_t *res) 1193158124Smarcel{ 1194158124Smarcel switch (cmd) { 1195158124Smarcel case PUC_CFG_GET_OFS: 1196158124Smarcel *res = 8 * (port & 1); 1197158124Smarcel return (0); 1198158124Smarcel case PUC_CFG_GET_RID: 1199158124Smarcel *res = 0x14 + (port >> 1) * 4; 1200158124Smarcel return (0); 1201158124Smarcel default: 1202158124Smarcel break; 1203158124Smarcel } 1204158124Smarcel return (ENXIO); 1205158124Smarcel} 1206140513Sbms 1207158124Smarcelstatic int 1208222660Sjhbpuc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1209158124Smarcel intptr_t *res) 1210158124Smarcel{ 1211222660Sjhb const struct puc_cfg *cfg = sc->sc_cfg; 1212222660Sjhb 1213158124Smarcel if (cmd == PUC_CFG_GET_OFS) { 1214222660Sjhb if (cfg->subdevice == 0x1282) /* Everest SP */ 1215222660Sjhb port <<= 1; 1216222660Sjhb else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1217222660Sjhb port = (port == 3) ? 4 : port; 1218222660Sjhb *res = port * 8 + ((port > 2) ? 0x18 : 0); 1219158124Smarcel return (0); 1220158124Smarcel } 1221158124Smarcel return (ENXIO); 1222158124Smarcel} 1223140882Sbms 1224158124Smarcelstatic int 1225222660Sjhbpuc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1226158124Smarcel intptr_t *res) 1227158124Smarcel{ 1228158124Smarcel if (cmd == PUC_CFG_GET_OFS) { 1229222660Sjhb *res = port * 0x200; 1230158124Smarcel return (0); 1231158124Smarcel } 1232158124Smarcel return (ENXIO); 1233158124Smarcel} 1234158124Smarcel 1235158124Smarcelstatic int 1236248340Srstonepuc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1237248340Srstone intptr_t *res) 1238248340Srstone{ 1239248340Srstone if (cmd == PUC_CFG_GET_OFS) { 1240248340Srstone *res = port * 0x400; 1241248340Srstone return (0); 1242248340Srstone } 1243248340Srstone return (ENXIO); 1244248340Srstone} 1245248340Srstone 1246248340Srstonestatic int 1247158124Smarcelpuc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1248158124Smarcel intptr_t *res) 1249158124Smarcel{ 1250158124Smarcel if (cmd == PUC_CFG_GET_ILR) { 1251158124Smarcel *res = PUC_ILR_DIGI; 1252158124Smarcel return (0); 1253158124Smarcel } 1254158124Smarcel return (ENXIO); 1255158124Smarcel} 1256158124Smarcel 1257158124Smarcelstatic int 1258227457Seadlerpuc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1259227457Seadler intptr_t *res) 1260227457Seadler{ 1261237350Sfjoe if (cmd == PUC_CFG_GET_OFS) { 1262238933Sfjoe const struct puc_cfg *cfg = sc->sc_cfg; 1263238933Sfjoe 1264238933Sfjoe if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144)) 1265238933Sfjoe port = 7; 1266238933Sfjoe *res = port * 0x200; 1267238933Sfjoe 1268227457Seadler return 0; 1269227457Seadler } 1270227457Seadler return (ENXIO); 1271227457Seadler} 1272227457Seadler 1273227457Seadlerstatic int 1274158124Smarcelpuc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1275158124Smarcel intptr_t *res) 1276158124Smarcel{ 1277158124Smarcel const struct puc_cfg *cfg = sc->sc_cfg; 1278158124Smarcel struct puc_bar *bar; 1279158124Smarcel uint8_t v0, v1; 1280158124Smarcel 1281158124Smarcel switch (cmd) { 1282158124Smarcel case PUC_CFG_SETUP: 1283158124Smarcel /* 1284158124Smarcel * Check if the scratchpad register is enabled or if the 1285158124Smarcel * interrupt status and options registers are active. 1286158124Smarcel */ 1287158124Smarcel bar = puc_get_bar(sc, cfg->rid); 1288158124Smarcel if (bar == NULL) 1289158124Smarcel return (ENXIO); 1290158124Smarcel /* Set DLAB in the LCR register of UART 0. */ 1291158124Smarcel bus_write_1(bar->b_res, 3, 0x80); 1292158124Smarcel /* Write 0 to the SPR register of UART 0. */ 1293158124Smarcel bus_write_1(bar->b_res, 7, 0); 1294158124Smarcel /* Read back the contents of the SPR register of UART 0. */ 1295158124Smarcel v0 = bus_read_1(bar->b_res, 7); 1296158124Smarcel /* Write a specific value to the SPR register of UART 0. */ 1297158124Smarcel bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1298158124Smarcel /* Read back the contents of the SPR register of UART 0. */ 1299158124Smarcel v1 = bus_read_1(bar->b_res, 7); 1300158124Smarcel /* Clear DLAB in the LCR register of UART 0. */ 1301158124Smarcel bus_write_1(bar->b_res, 3, 0); 1302158124Smarcel /* Save the two values read-back from the SPR register. */ 1303158124Smarcel sc->sc_cfg_data = (v0 << 8) | v1; 1304158124Smarcel if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1305158124Smarcel /* 1306158124Smarcel * The SPR register echoed the two values written 1307158124Smarcel * by us. This means that the SPAD jumper is set. 1308158124Smarcel */ 1309158124Smarcel device_printf(sc->sc_dev, "warning: extra features " 1310158124Smarcel "not usable -- SPAD compatibility enabled\n"); 1311158124Smarcel return (0); 1312158124Smarcel } 1313158124Smarcel if (v0 != 0) { 1314158124Smarcel /* 1315158124Smarcel * The first value doesn't match. This can only mean 1316158124Smarcel * that the SPAD jumper is not set and that a non- 1317158124Smarcel * standard fixed clock multiplier jumper is set. 1318158124Smarcel */ 1319158124Smarcel if (bootverbose) 1320158124Smarcel device_printf(sc->sc_dev, "fixed clock rate " 1321158124Smarcel "multiplier of %d\n", 1 << v0); 1322158124Smarcel if (v0 < -cfg->clock) 1323158124Smarcel device_printf(sc->sc_dev, "warning: " 1324158124Smarcel "suboptimal fixed clock rate multiplier " 1325158124Smarcel "setting\n"); 1326158124Smarcel return (0); 1327158124Smarcel } 1328158124Smarcel /* 1329158124Smarcel * The first value matched, but the second didn't. We know 1330158124Smarcel * that the SPAD jumper is not set. We also know that the 1331158124Smarcel * clock rate multiplier is software controlled *and* that 1332158124Smarcel * we just programmed it to the maximum allowed. 1333158124Smarcel */ 1334158124Smarcel if (bootverbose) 1335158124Smarcel device_printf(sc->sc_dev, "clock rate multiplier of " 1336158124Smarcel "%d selected\n", 1 << -cfg->clock); 1337158124Smarcel return (0); 1338158124Smarcel case PUC_CFG_GET_CLOCK: 1339158124Smarcel v0 = (sc->sc_cfg_data >> 8) & 0xff; 1340158124Smarcel v1 = sc->sc_cfg_data & 0xff; 1341158124Smarcel if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1342158124Smarcel /* 1343158124Smarcel * XXX With the SPAD jumper applied, there's no 1344158124Smarcel * easy way of knowing if there's also a clock 1345158124Smarcel * rate multiplier jumper installed. Let's hope 1346158124Smarcel * not... 1347158124Smarcel */ 1348158124Smarcel *res = DEFAULT_RCLK; 1349158124Smarcel } else if (v0 == 0) { 1350158124Smarcel /* 1351158124Smarcel * No clock rate multiplier jumper installed, 1352158124Smarcel * so we programmed the board with the maximum 1353158124Smarcel * multiplier allowed as given to us in the 1354158124Smarcel * clock field of the config record (negated). 1355158124Smarcel */ 1356158124Smarcel *res = DEFAULT_RCLK << -cfg->clock; 1357158124Smarcel } else 1358158124Smarcel *res = DEFAULT_RCLK << v0; 1359158124Smarcel return (0); 1360158124Smarcel case PUC_CFG_GET_ILR: 1361158124Smarcel v0 = (sc->sc_cfg_data >> 8) & 0xff; 1362158124Smarcel v1 = sc->sc_cfg_data & 0xff; 1363158124Smarcel *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1364158124Smarcel ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1365158124Smarcel return (0); 1366158124Smarcel default: 1367158124Smarcel break; 1368158124Smarcel } 1369158124Smarcel return (ENXIO); 1370158124Smarcel} 1371158124Smarcel 1372158124Smarcelstatic int 1373158124Smarcelpuc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1374158124Smarcel intptr_t *res) 1375158124Smarcel{ 1376158124Smarcel static int base[] = { 0x251, 0x3f0, 0 }; 1377158124Smarcel const struct puc_cfg *cfg = sc->sc_cfg; 1378158124Smarcel struct puc_bar *bar; 1379158124Smarcel int efir, idx, ofs; 1380158124Smarcel uint8_t v; 1381158124Smarcel 1382158124Smarcel switch (cmd) { 1383158124Smarcel case PUC_CFG_SETUP: 1384158124Smarcel bar = puc_get_bar(sc, cfg->rid); 1385158124Smarcel if (bar == NULL) 1386158124Smarcel return (ENXIO); 1387158124Smarcel 1388158124Smarcel /* configure both W83877TFs */ 1389158124Smarcel bus_write_1(bar->b_res, 0x250, 0x89); 1390158124Smarcel bus_write_1(bar->b_res, 0x3f0, 0x87); 1391158124Smarcel bus_write_1(bar->b_res, 0x3f0, 0x87); 1392158124Smarcel idx = 0; 1393158124Smarcel while (base[idx] != 0) { 1394158124Smarcel efir = base[idx]; 1395158124Smarcel bus_write_1(bar->b_res, efir, 0x09); 1396158124Smarcel v = bus_read_1(bar->b_res, efir + 1); 1397158124Smarcel if ((v & 0x0f) != 0x0c) 1398158124Smarcel return (ENXIO); 1399158124Smarcel bus_write_1(bar->b_res, efir, 0x16); 1400158124Smarcel v = bus_read_1(bar->b_res, efir + 1); 1401158124Smarcel bus_write_1(bar->b_res, efir, 0x16); 1402158124Smarcel bus_write_1(bar->b_res, efir + 1, v | 0x04); 1403158124Smarcel bus_write_1(bar->b_res, efir, 0x16); 1404158124Smarcel bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1405158124Smarcel ofs = base[idx] & 0x300; 1406158124Smarcel bus_write_1(bar->b_res, efir, 0x23); 1407158124Smarcel bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1408158124Smarcel bus_write_1(bar->b_res, efir, 0x24); 1409158124Smarcel bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1410158124Smarcel bus_write_1(bar->b_res, efir, 0x25); 1411158124Smarcel bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1412158124Smarcel bus_write_1(bar->b_res, efir, 0x17); 1413158124Smarcel bus_write_1(bar->b_res, efir + 1, 0x03); 1414158124Smarcel bus_write_1(bar->b_res, efir, 0x28); 1415158124Smarcel bus_write_1(bar->b_res, efir + 1, 0x43); 1416158124Smarcel idx++; 1417158124Smarcel } 1418158124Smarcel bus_write_1(bar->b_res, 0x250, 0xaa); 1419158124Smarcel bus_write_1(bar->b_res, 0x3f0, 0xaa); 1420158124Smarcel return (0); 1421158124Smarcel case PUC_CFG_GET_OFS: 1422158124Smarcel switch (port) { 1423158124Smarcel case 0: 1424158124Smarcel *res = 0x2f8; 1425158124Smarcel return (0); 1426158124Smarcel case 1: 1427158124Smarcel *res = 0x2e8; 1428158124Smarcel return (0); 1429158124Smarcel case 2: 1430158124Smarcel *res = 0x3f8; 1431158124Smarcel return (0); 1432158124Smarcel case 3: 1433158124Smarcel *res = 0x3e8; 1434158124Smarcel return (0); 1435158124Smarcel case 4: 1436158124Smarcel *res = 0x278; 1437158124Smarcel return (0); 1438158124Smarcel } 1439158124Smarcel break; 1440158124Smarcel default: 1441158124Smarcel break; 1442158124Smarcel } 1443158124Smarcel return (ENXIO); 1444158124Smarcel} 1445158124Smarcel 1446158124Smarcelstatic int 1447158124Smarcelpuc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1448158124Smarcel intptr_t *res) 1449158124Smarcel{ 1450158124Smarcel const struct puc_cfg *cfg = sc->sc_cfg; 1451158124Smarcel 1452158124Smarcel switch (cmd) { 1453158124Smarcel case PUC_CFG_GET_OFS: 1454158124Smarcel if (cfg->ports == PUC_PORT_8S) { 1455158124Smarcel *res = (port > 4) ? 8 * (port - 4) : 0; 1456158124Smarcel return (0); 1457158124Smarcel } 1458158124Smarcel break; 1459158124Smarcel case PUC_CFG_GET_RID: 1460158124Smarcel if (cfg->ports == PUC_PORT_8S) { 1461158124Smarcel *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1462158124Smarcel return (0); 1463158124Smarcel } 1464158124Smarcel if (cfg->ports == PUC_PORT_2S1P) { 1465158124Smarcel switch (port) { 1466158124Smarcel case 0: *res = 0x10; return (0); 1467158124Smarcel case 1: *res = 0x14; return (0); 1468158124Smarcel case 2: *res = 0x1c; return (0); 1469158124Smarcel } 1470158124Smarcel } 1471158124Smarcel break; 1472158124Smarcel default: 1473158124Smarcel break; 1474158124Smarcel } 1475158124Smarcel return (ENXIO); 1476158124Smarcel} 1477158124Smarcel 1478158124Smarcelstatic int 1479158124Smarcelpuc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1480158124Smarcel intptr_t *res) 1481158124Smarcel{ 1482247571Smarius static const uint16_t dual[] = { 1483158124Smarcel 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1484251713Smarius 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1485251713Smarius 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1486158124Smarcel 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1487158124Smarcel 0xD079, 0 1488158124Smarcel }; 1489247571Smarius static const uint16_t quad[] = { 1490251713Smarius 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1491251713Smarius 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1492158124Smarcel 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1493158124Smarcel 0xB157, 0 1494158124Smarcel }; 1495247571Smarius static const uint16_t octa[] = { 1496251713Smarius 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1497158124Smarcel 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1498158124Smarcel }; 1499247571Smarius static const struct { 1500158124Smarcel int ports; 1501247571Smarius const uint16_t *ids; 1502158124Smarcel } subdevs[] = { 1503158124Smarcel { 2, dual }, 1504158124Smarcel { 4, quad }, 1505158124Smarcel { 8, octa }, 1506158124Smarcel { 0, NULL } 1507158124Smarcel }; 1508158124Smarcel static char desc[64]; 1509158124Smarcel int dev, id; 1510158124Smarcel uint16_t subdev; 1511158124Smarcel 1512158124Smarcel switch (cmd) { 1513222328Sjhb case PUC_CFG_GET_CLOCK: 1514222328Sjhb if (port < 2) 1515222328Sjhb *res = DEFAULT_RCLK * 8; 1516222328Sjhb else 1517222328Sjhb *res = DEFAULT_RCLK; 1518222328Sjhb return (0); 1519158124Smarcel case PUC_CFG_GET_DESC: 1520158124Smarcel snprintf(desc, sizeof(desc), 1521158124Smarcel "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1522158124Smarcel *res = (intptr_t)desc; 1523158124Smarcel return (0); 1524158124Smarcel case PUC_CFG_GET_NPORTS: 1525158124Smarcel subdev = pci_get_subdevice(sc->sc_dev); 1526158124Smarcel dev = 0; 1527158124Smarcel while (subdevs[dev].ports != 0) { 1528158124Smarcel id = 0; 1529158124Smarcel while (subdevs[dev].ids[id] != 0) { 1530158124Smarcel if (subdev == subdevs[dev].ids[id]) { 1531158124Smarcel sc->sc_cfg_data = subdevs[dev].ports; 1532158124Smarcel *res = sc->sc_cfg_data; 1533158124Smarcel return (0); 1534158124Smarcel } 1535158124Smarcel id++; 1536158124Smarcel } 1537158124Smarcel dev++; 1538158124Smarcel } 1539158124Smarcel return (ENXIO); 1540158124Smarcel case PUC_CFG_GET_OFS: 1541158124Smarcel *res = (port == 1 || port == 3) ? 8 : 0; 1542158124Smarcel return (0); 1543158124Smarcel case PUC_CFG_GET_RID: 1544179050Smarcel *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1545158124Smarcel return (0); 1546158124Smarcel case PUC_CFG_GET_TYPE: 1547158124Smarcel *res = PUC_TYPE_SERIAL; 1548158124Smarcel return (0); 1549158124Smarcel default: 1550158124Smarcel break; 1551158124Smarcel } 1552158124Smarcel return (ENXIO); 1553158124Smarcel} 1554158124Smarcel 1555158124Smarcelstatic int 1556251715Smariuspuc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1557251715Smarius int port __unused, intptr_t *res) 1558251715Smarius{ 1559251715Smarius 1560251715Smarius switch (cmd) { 1561251715Smarius case PUC_CFG_GET_CLOCK: 1562251715Smarius /* 1563251715Smarius * OXu16PCI954 use a 14.7456 MHz clock by default while 1564251715Smarius * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one. 1565251715Smarius */ 1566251715Smarius if (pci_get_revid(sc->sc_dev) == 1) 1567251715Smarius *res = DEFAULT_RCLK * 8; 1568251715Smarius else 1569251715Smarius *res = DEFAULT_RCLK; 1570251715Smarius return (0); 1571251715Smarius default: 1572251715Smarius break; 1573251715Smarius } 1574251715Smarius return (ENXIO); 1575251715Smarius} 1576251715Smarius 1577251715Smariusstatic int 1578221182Sjhbpuc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1579221182Sjhb intptr_t *res) 1580221182Sjhb{ 1581221182Sjhb const struct puc_cfg *cfg = sc->sc_cfg; 1582221182Sjhb int idx; 1583221182Sjhb struct puc_bar *bar; 1584221182Sjhb uint8_t value; 1585221182Sjhb 1586221182Sjhb switch (cmd) { 1587221182Sjhb case PUC_CFG_SETUP: 1588221182Sjhb device_printf(sc->sc_dev, "%d UARTs detected\n", 1589221182Sjhb sc->sc_nports); 1590221182Sjhb 1591221182Sjhb /* Set UARTs to enhanced mode */ 1592221182Sjhb bar = puc_get_bar(sc, cfg->rid); 1593221182Sjhb if (bar == NULL) 1594221182Sjhb return (ENXIO); 1595221182Sjhb for (idx = 0; idx < sc->sc_nports; idx++) { 1596222760Sjhb value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1597222760Sjhb 0x92); 1598221182Sjhb bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1599222760Sjhb value | 0x10); 1600221182Sjhb } 1601221182Sjhb return (0); 1602221182Sjhb case PUC_CFG_GET_LEN: 1603221182Sjhb *res = 0x200; 1604221182Sjhb return (0); 1605221182Sjhb case PUC_CFG_GET_NPORTS: 1606221182Sjhb /* 1607221182Sjhb * Check if we are being called from puc_bfe_attach() 1608221182Sjhb * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1609221182Sjhb * puc_get_bar(), so we return a value of 16. This has cosmetic 1610221182Sjhb * side-effects at worst; in PUC_CFG_GET_DESC, 1611221182Sjhb * (int)sc->sc_cfg_data will not contain the true number of 1612221182Sjhb * ports in PUC_CFG_GET_DESC, but we are not implementing that 1613221182Sjhb * call for this device family anyway. 1614221182Sjhb * 1615221182Sjhb * The check is for initialisation of sc->sc_bar[idx], which is 1616221182Sjhb * only done in puc_bfe_attach(). 1617221182Sjhb */ 1618221182Sjhb idx = 0; 1619221182Sjhb do { 1620221182Sjhb if (sc->sc_bar[idx++].b_rid != -1) { 1621221182Sjhb sc->sc_cfg_data = 16; 1622221182Sjhb *res = sc->sc_cfg_data; 1623221182Sjhb return (0); 1624221182Sjhb } 1625221182Sjhb } while (idx < PUC_PCI_BARS); 1626221182Sjhb 1627221182Sjhb bar = puc_get_bar(sc, cfg->rid); 1628221182Sjhb if (bar == NULL) 1629221182Sjhb return (ENXIO); 1630221182Sjhb 1631221182Sjhb value = bus_read_1(bar->b_res, 0x04); 1632221182Sjhb if (value == 0) 1633221182Sjhb return (ENXIO); 1634221182Sjhb 1635221182Sjhb sc->sc_cfg_data = value; 1636221182Sjhb *res = sc->sc_cfg_data; 1637221182Sjhb return (0); 1638221182Sjhb case PUC_CFG_GET_OFS: 1639221182Sjhb *res = 0x1000 + (port << 9); 1640221182Sjhb return (0); 1641221182Sjhb case PUC_CFG_GET_TYPE: 1642221182Sjhb *res = PUC_TYPE_SERIAL; 1643221182Sjhb return (0); 1644221182Sjhb default: 1645221182Sjhb break; 1646221182Sjhb } 1647221182Sjhb return (ENXIO); 1648221182Sjhb} 1649221182Sjhb 1650221182Sjhbstatic int 1651264761Smariuspuc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1652264761Smarius intptr_t *res) 1653264761Smarius{ 1654264761Smarius int error; 1655264761Smarius 1656264761Smarius switch (cmd) { 1657264761Smarius case PUC_CFG_GET_OFS: 1658264761Smarius error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1659264761Smarius if (error != 0) 1660264761Smarius return (error); 1661264761Smarius *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; 1662264761Smarius return (0); 1663264761Smarius case PUC_CFG_GET_RID: 1664264761Smarius error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1665264761Smarius if (error != 0) 1666264761Smarius return (error); 1667264761Smarius *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; 1668264761Smarius return (0); 1669264761Smarius default: 1670264761Smarius break; 1671264761Smarius } 1672264761Smarius return (ENXIO); 1673264761Smarius} 1674264761Smarius 1675264761Smariusstatic int 1676158124Smarcelpuc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1677158124Smarcel intptr_t *res) 1678158124Smarcel{ 1679158124Smarcel switch (cmd) { 1680158124Smarcel case PUC_CFG_GET_OFS: 1681158124Smarcel *res = (port < 3) ? 0 : (port - 2) << 3; 1682158124Smarcel return (0); 1683158124Smarcel case PUC_CFG_GET_RID: 1684158124Smarcel *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1685158124Smarcel return (0); 1686158124Smarcel default: 1687158124Smarcel break; 1688158124Smarcel } 1689158124Smarcel return (ENXIO); 1690158124Smarcel} 1691