ppcreg.h revision 42475 
1/*-
2 * Copyright (c) 1997 Nicolas Souchu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 *	$Id: ppcreg.h,v 1.5 1998/10/31 11:37:09 nsouch Exp $
27 *
28 */
29#ifndef __PPCREG_H
30#define __PPCREG_H
31
32/*
33 * Parallel Port Chipset type.
34 */
35#define SMC_LIKE	0
36#define SMC_37C665GT	1
37#define SMC_37C666GT	2
38#define NS_PC87332	3
39#define NS_PC87306	4
40#define INTEL_820191AA	5	/* XXX not implemented */
41#define GENERIC		6
42#define WINB_W83877F	7
43#define WINB_W83877AF	8
44#define WINB_UNKNOWN	9
45#define NS_PC87334	10
46
47/*
48 * Generic structure to hold parallel port chipset info.
49 */
50struct ppc_data {
51
52	int ppc_unit;
53	int ppc_type;
54
55	int ppc_mode;		/* chipset current mode */
56	int ppc_avm;		/* chipset available modes */
57
58#define PPC_IRQ_NONE		0x0
59#define PPC_IRQ_nACK		0x1
60#define PPC_IRQ_DMA		0x2
61#define PPC_IRQ_FIFO		0x4
62#define PPC_IRQ_nFAULT		0x8
63	int ppc_irqstat;	/* remind irq settings */
64
65#define PPC_DMA_INIT		0x01
66#define PPC_DMA_STARTED		0x02
67#define PPC_DMA_COMPLETE	0x03
68#define PPC_DMA_INTERRUPTED	0x04
69#define PPC_DMA_ERROR		0x05
70	int ppc_dmastat;	/* dma state */
71	int ppc_dmachan;	/* dma channel */
72	int ppc_dmaflags;	/* dma transfer flags */
73	caddr_t ppc_dmaddr;	/* buffer address */
74	u_int ppc_dmacnt;	/* count of bytes sent with dma */
75
76#define PPC_PWORD_MASK	0x30
77#define PPC_PWORD_16	0x00
78#define PPC_PWORD_8	0x10
79#define PPC_PWORD_32	0x20
80	char ppc_pword;		/* PWord size */
81	short ppc_fifo;		/* FIFO threshold */
82
83	short ppc_wthr;		/* writeIntrThresold */
84	short ppc_rthr;		/* readIntrThresold */
85
86#define ppc_base ppc_link.base
87#define ppc_epp ppc_link.epp_protocol
88#define ppc_irq ppc_link.id_irq
89#define ppc_subm ppc_link.submicroseq
90#define ppc_ptr ppc_link.ptr
91#define ppc_accum ppc_link.accum
92
93	unsigned char ppc_flags;
94
95	struct ppb_link ppc_link;
96};
97
98/*
99 * Parallel Port Chipset registers.
100 */
101#define PPC_SPP_DTR	0	/* SPP data register */
102#define PPC_ECP_A_FIFO	0	/* ECP Address fifo register */
103#define PPC_SPP_STR	1	/* SPP status register */
104#define PPC_SPP_CTR	2	/* SPP control register */
105#define PPC_EPP_DATA	4	/* EPP data register (8, 16 or 32 bit) */
106#define PPC_ECP_D_FIFO	0x400	/* ECP Data fifo register */
107#define PPC_ECP_CNFGA	0x400	/* Configuration register A */
108#define PPC_ECP_CNFGB	0x401	/* Configuration register B */
109#define PPC_ECP_ECR	0x402	/* ECP extended control register */
110
111#define PPC_FIFO_EMPTY	0x1	/* ecr register - bit 0 */
112#define PPC_FIFO_FULL	0x2	/* ecr register - bit 1 */
113#define PPC_SERVICE_INTR 0x4	/* ecr register - bit 2 */
114#define PPC_ENABLE_DMA	0x8	/* ecr register - bit 3 */
115#define PPC_nFAULT_INTR	0x10	/* ecr register - bit 4 */
116#define PPC_ECR_STD	0x0
117#define PPC_ECR_PS2	0x20
118#define PPC_ECR_FIFO	0x40
119#define PPC_ECR_ECP	0x60
120#define PPC_ECR_EPP	0x80
121
122#define PPC_DISABLE_INTR	(PPC_SERVICE_INTR | PPC_nFAULT_INTR)
123#define PPC_ECR_RESET		(PPC_ECR_PS2 | PPC_DISABLE_INTR)
124
125#define r_dtr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_DTR))
126#define r_str(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_STR))
127#define r_ctr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_CTR))
128#define r_epp(ppc) ((char)inb((ppc)->ppc_base + PPC_EPP_DATA))
129#define r_cnfgA(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_CNFGA))
130#define r_cnfgB(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_CNFGB))
131#define r_ecr(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_ECR))
132#define r_fifo(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_D_FIFO))
133
134#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte)
135#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte)
136#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte)
137#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte)
138#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte)
139#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_D_FIFO, byte)
140
141/*
142 * Register defines for the PC873xx parts
143 */
144
145#define PC873_FER	0x00
146#define PC873_PPENABLE	(1<<0)
147#define PC873_FAR	0x01
148#define PC873_PTR	0x02
149#define PC873_CFGLOCK	(1<<6)
150#define PC873_EPPRDIR	(1<<7)
151#define PC873_EXTENDED	(1<<7)
152#define PC873_LPTBIRQ7	(1<<3)
153#define PC873_FCR	0x03
154#define PC873_ZWS	(1<<5)
155#define PC873_ZWSPWDN	(1<<6)
156#define PC873_PCR	0x04
157#define PC873_EPPEN	(1<<0)
158#define PC873_EPP19	(1<<1)
159#define PC873_ECPEN	(1<<2)
160#define PC873_ECPCLK	(1<<3)
161#define PC873_PMC	0x06
162#define PC873_TUP	0x07
163#define PC873_SID	0x08
164#define PC873_PNP0	0x1b
165#define PC873_PNP1	0x1c
166#define PC873_LPTBA	0x19
167
168/*
169 * Register defines for the SMC FDC37C66xGT parts
170 */
171
172/* Init codes */
173#define SMC665_iCODE	0x55
174#define SMC666_iCODE	0x44
175
176/* Base configuration ports */
177#define SMC66x_CSR	0x3F0
178#define SMC666_CSR	0x370		/* hard-configured value for 666 */
179
180/* Bits */
181#define SMC_CR1_ADDR	0x3		/* bit 0 and 1 */
182#define SMC_CR1_MODE	(1<<3)		/* bit 3 */
183#define SMC_CR4_EMODE	0x3		/* bits 0 and 1 */
184#define SMC_CR4_EPPTYPE	(1<<6)		/* bit 6 */
185
186/* Extended modes */
187#define SMC_SPP		0x0		/* SPP */
188#define SMC_EPPSPP	0x1		/* EPP and SPP */
189#define SMC_ECP		0x2 		/* ECP */
190#define SMC_ECPEPP	0x3		/* ECP and EPP */
191
192/*
193 * Register defines for the Winbond W83877F parts
194 */
195
196#define WINB_W83877F_ID		0xa
197#define WINB_W83877AF_ID	0xb
198
199/* Configuration bits */
200#define WINB_HEFERE	(1<<5)		/* CROC bit 5 */
201#define WINB_HEFRAS	(1<<0)		/* CR16 bit 0 */
202
203#define WINB_PNPCVS	(1<<2)		/* CR16 bit 2 */
204#define WINB_CHIPID	0xf		/* CR9 bits 0-3 */
205
206#define WINB_PRTMODS0	(1<<2)		/* CR0 bit 2 */
207#define WINB_PRTMODS1	(1<<3)		/* CR0 bit 3 */
208#define WINB_PRTMODS2	(1<<7)		/* CR9 bit 7 */
209
210/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
211#define WINB_W83757	0x0
212#define WINB_EXTFDC	0x4
213#define WINB_EXTADP	0x8
214#define WINB_EXT2FDD	0xc
215#define WINB_JOYSTICK	0x80
216
217#define WINB_PARALLEL	0x80
218#define WINB_EPP_SPP	0x4
219#define WINB_ECP	0x8
220#define WINB_ECP_EPP	0xc
221
222#endif
223