ppcreg.h revision 40784
1/*- 2 * Copyright (c) 1997 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: ppcreg.h,v 1.4 1998/09/13 18:26:44 nsouch Exp $ 27 * 28 */ 29#ifndef __PPCREG_H 30#define __PPCREG_H 31 32/* 33 * Parallel Port Chipset type. 34 */ 35#define SMC_LIKE 0 36#define SMC_37C665GT 1 37#define SMC_37C666GT 2 38#define NS_PC87332 3 39#define NS_PC87306 4 40#define INTEL_820191AA 5 /* XXX not implemented */ 41#define GENERIC 6 42#define WINB_W83877F 7 43#define WINB_W83877AF 8 44#define WINB_UNKNOWN 9 45#define NS_PC87334 10 46 47/* 48 * Generic structure to hold parallel port chipset info. 49 */ 50struct ppc_data { 51 52 int ppc_unit; 53 int ppc_type; 54 55 int ppc_mode; /* chipset current mode */ 56 int ppc_avm; /* chipset available modes */ 57 58#define ppc_base ppc_link.base 59#define ppc_epp ppc_link.epp_protocol 60#define ppc_irq ppc_link.id_irq 61#define ppc_subm ppc_link.submicroseq 62#define ppc_ptr ppc_link.ptr 63#define ppc_accum ppc_link.accum 64 65 unsigned char ppc_flags; 66 67 struct ppb_link ppc_link; 68}; 69 70/* 71 * Parallel Port Chipset registers. 72 */ 73#define PPC_SPP_DTR 0 /* SPP data register */ 74#define PPC_SPP_STR 1 /* SPP status register */ 75#define PPC_SPP_CTR 2 /* SPP control register */ 76#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ 77#define PPC_ECP_FIFO 0x400 /* ECP fifo register */ 78#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 79 80#define r_dtr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_DTR)) 81#define r_str(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_STR)) 82#define r_ctr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_CTR)) 83#define r_epp(ppc) ((char)inb((ppc)->ppc_base + PPC_EPP_DATA)) 84#define r_ecr(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_ECR)) 85#define r_fifo(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_FIFO)) 86 87#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte) 88#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte) 89#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte) 90#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte) 91#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte) 92#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_FIFO, byte) 93 94/* 95 * Register defines for the PC873xx parts 96 */ 97 98#define PC873_FER 0x00 99#define PC873_PPENABLE (1<<0) 100#define PC873_FAR 0x01 101#define PC873_PTR 0x02 102#define PC873_CFGLOCK (1<<6) 103#define PC873_EPPRDIR (1<<7) 104#define PC873_EXTENDED (1<<7) 105#define PC873_LPTBIRQ7 (1<<3) 106#define PC873_FCR 0x03 107#define PC873_ZWS (1<<5) 108#define PC873_ZWSPWDN (1<<6) 109#define PC873_PCR 0x04 110#define PC873_EPPEN (1<<0) 111#define PC873_EPP19 (1<<1) 112#define PC873_ECPEN (1<<2) 113#define PC873_ECPCLK (1<<3) 114#define PC873_PMC 0x06 115#define PC873_TUP 0x07 116#define PC873_SID 0x08 117#define PC873_PNP0 0x1b 118#define PC873_PNP1 0x1c 119#define PC873_LPTBA 0x19 120 121/* 122 * Register defines for the SMC FDC37C66xGT parts 123 */ 124 125/* Init codes */ 126#define SMC665_iCODE 0x55 127#define SMC666_iCODE 0x44 128 129/* Base configuration ports */ 130#define SMC66x_CSR 0x3F0 131#define SMC666_CSR 0x370 /* hard-configured value for 666 */ 132 133/* Bits */ 134#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */ 135#define SMC_CR1_MODE (1<<3) /* bit 3 */ 136#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */ 137#define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */ 138 139/* Extended modes */ 140#define SMC_SPP 0x0 /* SPP */ 141#define SMC_EPPSPP 0x1 /* EPP and SPP */ 142#define SMC_ECP 0x2 /* ECP */ 143#define SMC_ECPEPP 0x3 /* ECP and EPP */ 144 145/* 146 * Register defines for the Winbond W83877F parts 147 */ 148 149#define WINB_W83877F_ID 0xa 150#define WINB_W83877AF_ID 0xb 151 152/* Configuration bits */ 153#define WINB_HEFERE (1<<5) /* CROC bit 5 */ 154#define WINB_HEFRAS (1<<0) /* CR16 bit 0 */ 155 156#define WINB_PNPCVS (1<<2) /* CR16 bit 2 */ 157#define WINB_CHIPID 0xf /* CR9 bits 0-3 */ 158 159#define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */ 160#define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */ 161#define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */ 162 163/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */ 164#define WINB_W83757 0x0 165#define WINB_EXTFDC 0x4 166#define WINB_EXTADP 0x8 167#define WINB_EXT2FDD 0xc 168#define WINB_JOYSTICK 0x80 169 170#define WINB_PARALLEL 0x80 171#define WINB_EPP_SPP 0x4 172#define WINB_ECP 0x8 173#define WINB_ECP_EPP 0xc 174 175#endif 176